74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 03 -- 14 March 2008 Product data sheet 1. General description The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. 2. Features n n n n Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specified from -40 C to +85 C and from -40 C to +125 C 3. Applications n Parallel-to-serial data conversion 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 4. Ordering information Table 1. Ordering information Type number Package 74HC165N Temperature range Name Description Version -40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 -40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 -40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm 74HCT165N 74HC165D 74HCT165D 74HC165DB 74HCT165DB 74HC165PW 74HCT165PW 74HC165BQ 74HCT165BQ SOT763-1 5. Functional diagram 1 SRG8 C2[LOAD] G1[SHIFT] 15 10 11 12 13 14 3 4 5 6 1 1 2 1 C3/ DS D0 10 D1 11 D2 12 D3 3D 2D 2D 13 D4 14 D5 D6 Q7 D7 Q7 9 3 7 4 5 PL 9 6 CP CE 2 mna986 mna985 Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC_HCT165_3 Product data sheet 7 15 (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 2 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 11 12 13 14 3 4 5 6 D0 D1 D2 D3 D4 D5 D6 D7 1 PL 10 DS 2 CP 15 CE Q7 9 8-BIT SHIFT REGISTER PARALLEL-IN/SERIAL-OUT Q7 7 mna992 Fig 3. Functional diagram 6. Pinning information 6.1 Pinning 74HC165 74HCT165 PL terminal 1 index area 16 VCC 74HC165 74HCT165 1 16 VCC CP 2 15 CE CP 2 15 CE D4 3 14 D3 D4 3 14 D3 D5 4 13 D2 D5 4 13 D2 D6 5 12 D1 D7 6 Q7 7 6 11 D0 Q7 7 10 DS GND 8 9 Q7 GND(1) 11 D0 10 DS 9 D7 Q7 12 D1 8 5 GND D6 1 PL 001aah565 Transparent top view 001aah564 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 4. Pin configuration (DIP16, SO16 and (T)SSOP16) Fig 5. Pin configuration (DHVQFN16) 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 3 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 6.2 Pin description Table 2. Pin description Symbol Pin Description PL 1 asynchronous parallel load input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary output from the last stage GND 8 ground (0 V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn) CE 15 clock enable input (active LOW) VCC 16 positive supply voltage 7. Functional description Table 3. Function table[1] Operating modes Inputs PL parallel load serial shift hold "do nothing" [1] Qn registers CE CP DS D0 to D7 Q0 Outputs Q1 to Q6 Q7 Q7 L X X X L L L to L L H L X X X H H H to H H L H L l X L q0 to q5 q6 q6 H L h X H q0 to q5 q6 q6 H L l X L q0 to q5 q6 q6 H L h X H q0 to q5 q6 q6 H H X X X q0 q1 to q6 q7 q7 H X H X X q0 q1 to q6 q7 q7 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don't care; = LOW-to-HIGH clock transition. 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 4 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register CP CE DS PL D0 D1 D2 D3 D4 D5 D6 D7 Q7 Q7 inhibit serial shift mna993 load Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +7 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - 20 mA IO output current -0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 C 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 5 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Ptot total power dissipation Tamb = -40 C to +125 C [1] Min Max Unit DIP16 package [2] - 750 mW SO16 package [3] - 500 mW (T)SSOP16 package [4] - 500 mW DHVQFN16 package [5] - 500 mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 C. [3] Ptot derates linearly with 8 mW/K above 70 C. [4] Ptot derates linearly with 5.5 mW/K above 60 C. [5] Ptot derates linearly with 4.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC165 74HCT165 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature t/V input transition rise and fall rate VCC supply voltage VI -40 - +125 -40 - +125 VCC = 2.0 V - - 625 - - - ns/V C VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions -40 C to +85 C -40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V 74HC165 VIH VIL HIGH-level input voltage LOW-level input voltage 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 6 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL HIGH-level output voltage LOW-level output voltage 25 C Conditions -40 C to +85 C -40 C to +125 C Unit Min Typ Max Min Max Min Max IO = -20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 74HCT165 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 A 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A ICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V CI input capacitance Dn and DS inputs - 35 126 - 157.5 - 171.5 A CP CE, and PL inputs - 65 234 - 292.5 - 318.5 A - 3.5 - - - - - pF 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 7 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter 25 C Conditions Min -40 C to +85 C -40 C to +125 C Unit Typ Max Min Max Min Max 74HC165 tpd propagation delay [1] CP or CE to Q7, Q7; see Figure 7 VCC = 2.0 V - 52 165 - 205 - 250 ns VCC = 4.5 V - 19 33 - 41 - 50 ns VCC = 6.0 V - 15 28 - 35 - 43 ns VCC = 5.0 V; CL = 15 pF - 16 - - - - - ns VCC = 2.0 V - 50 165 - 205 - 250 ns VCC = 4.5 V - 18 33 - 41 - 50 ns VCC = 6.0 V - 14 28 - 35 - 43 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 2.0 V - 36 120 - 150 - 180 ns VCC = 4.5 V - 13 24 - 30 - 36 ns VCC = 6.0 V - 10 20 - 26 - 31 ns - 11 - - - - - ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 100 22 - 125 - 150 - ns VCC = 4.5 V 20 8 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns PL to Q7, Q7; see Figure 8 D7 to Q7, Q7; see Figure 9 VCC = 5.0 V; CL = 15 pF tt tW transition time pulse width Q7, Q7 output; see Figure 7 [2] CP input HIGH or LOW; see Figure 7 PL input LOW; see Figure 8 trec recovery time PL to CP, CE; see Figure 8 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 8 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics ...continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter 25 C Conditions Min tsu set-up time -40 C to +85 C -40 C to +125 C Unit Typ Max Min Max Min Max DS to CP, CE; see Figure 10 VCC = 2.0 V 80 11 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 5 6 - 5 - 5 - ns VCC = 4.5 V 5 2 - 5 - 5 - ns VCC = 6.0 V 5 2 - 5 - 5 - ns VCC = 2.0 V 5 -17 - 5 - 5 - ns VCC = 4.5 V 5 -6 - 5 - 5 - ns VCC = 6.0 V 5 -5 - 5 - 5 - ns VCC = 2.0 V 6 17 - 5 - 4 - MHz VCC = 4.5 V 30 51 - 24 - 20 - MHz VCC = 6.0 V 35 61 - 28 - 24 - MHz - 56 - - - - - MHz - 35 - - - - - pF CE to CP and CP to CE; see Figure 10 Dn to PL; see Figure 11 th hold time DS to CP, CE and Dn to PL; see Figure 10 CE to CP and CP to CE; see Figure 10 fmax maximum frequency CP input; see Figure 7 VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance per package; VI = GND to VCC [3] 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 9 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics ...continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter 25 C Conditions Min -40 C to +85 C -40 C to +125 C Unit Typ Max Min Max Min Max 74HCT165 tpd propagation delay [1] CE, CP to Q7, Q7; see Figure 7 VCC = 4.5 V - 17 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns VCC = 4.5 V - 20 40 - 50 - 60 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns PL to Q7, Q7; see Figure 8 D7 to Q7, Q7; see Figure 9 tt tW VCC = 4.5 V - 14 28 - 35 - 42 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns - 7 15 - 19 - 22 ns 16 6 - 20 - 24 - ns 20 9 - 25 - 30 - ns 20 8 - 25 - 30 - ns 20 2 - 25 - 30 - ns 20 7 - 25 - 30 - ns 20 10 - 25 - 30 - ns 7 -1 - 9 - 11 - ns 0 -7 - 0 - 0 - ns transition time Q7, Q7 output; see Figure 7 pulse width CP input; see Figure 7 VCC = 4.5 V VCC = 4.5 V [2] PL input; see Figure 8 VCC = 4.5 V trec recovery time PL to CP, CE; see Figure 8 VCC = 4.5 V tsu set-up time DS to CP, CE; see Figure 10 VCC = 4.5 V CE to CP and CP to CE; see Figure 10 VCC = 4.5 V Dn to PL; see Figure 11 VCC = 4.5 V th hold time DS to CP, CE and Dn to PL; see Figure 10 VCC = 4.5 V CE to CP and CP to CE; see Figure 10 VCC = 4.5 V fmax maximum frequency CP input; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 26 44 - 21 - 17 - MHz - 48 - - - - - MHz 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 10 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics ...continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter 25 C Conditions Min CPD power dissipation capacitance [3] per package; VI = GND to VCC - 1.5 V - Typ Max 35 [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. -40 C to +85 C -40 C to +125 C Unit - Min Max Min Max - - - - pF 12. Waveforms 1/fmax VI CP or CE input VM GND tW tPLH tPHL VOH VM Q7 or Q7 output VOL tTHL tTLH mna987 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 11 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register VI VM PL input GND tW trec VI CE, CP input VM GND tPHL VOH VM Q7 or Q7 output VOL mna988 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time VI VM D7 input GND tPLH tPHL VOH VM Q7 output VOL tPLH tPHL VOH VM Q7 output VOL mna989 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 12 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register (1) VI VM CP, CE input GND th th tsu tsu VI VM DS input GND tsu tW VI VM CP, CE input GND mna990 The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. (1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1. Fig 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE) VI Dn input VM VM GND tsu th tsu th VI PL input VM VM mna991 GND Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Measurement points Type Input Output VI VM VM 74HC165 VCC 0.5VCC 0.5VCC 74HCT165 3V 1.3 V 1.3 V 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 13 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC165 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT165 3V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 14 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 13. Package outline SOT38-4 (DIP16) 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 15 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 16 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 15. Package outline SOT338-1 (SSOP16) 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 17 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 16. Package outline SOT403-1 (TSSOP16) 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 18 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT763-1 (DHVQFN16) 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 19 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT165_3 20080314 Product data sheet - 74HC_HCT165_CNV_2 Modifications: 74HC_HCT165_CNV_2 * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * * Legal texts have been adapted to the new company name where appropriate. * Family data added, see Section 10 "Static characteristics" Package SOT763-1 (DHVQFN16) added to Section 4 "Ordering information" and Section 13 "Package outline". December 1990 Product specification 74HC_HCT165_3 Product data sheet - - (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 20 of 22 74HC165; 74HCT165 NXP Semiconductors 8-bit parallel-in/serial out shift register 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT165_3 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 03 -- 14 March 2008 21 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 March 2008 Document identifier: 74HC_HCT165_3