74HC/HCT74 flip-flops DUAL D-TYPE FLIP-FLOP WITH SET AND RESET; POSITIVE-EDGE TRIGGER FEATURES TYPICAL Output capability: standard SYMBOL PARAMETER CONDITIONS UNIT Icc category: flip-flops Hc HCT ENERAL DESCRIP propagation delay GEN TION PHL! nCP to nQ, nd 14 | 15 | ns The 74HC/HCT74 are high-speed tPLH n&p to nQ, nQ C, = 15 pF 15 18 ns Si-gate CMOS devices and are pin NRp tonda, nad Voc =5V 16 18 ns compatible with low power Schottky TTL {LSTTL). They are specified in fmax maximum clack frequency 76 59 MHz compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive- C input capacitance 3.5 | 3.5 | pF edge triggered, D-type flip-flops with power dissipation individual data (D) inputs, clock (CP) Cp . notes 1 and 2 24 29 pE inputs, set (Sp) arid reset (Rp-) inputs; D capacitance per flip-flop also complementary Q and Q outputs. GND = 0 V: Tamp = 25 C: te = ty = 6 ns The set and reset are asynchronous active LOW inputs and operate Notes independently of the clock input. . . . ae . Information y the data input is 1. Cpp is used to determine the dynamic power dissipation (Pp in uW): transferred to the QO output on the LOW- Pp = Cpp x Vcc? x fj + 5 (CL x Vcc? x fo} where: to-HIGH transition of the clock pulse. fj = input frequency in MHz CL = output load capacitance in pF The D inputs must be stable one set-up fo = output frequency in MHz VCC = supply voltage in V time prior to the LOW-to-HIGH clock E (CL x Voc? x fg) = sum of outputs ition f ictabl eration. transition for predictable op 2. For HC the condition is V| = GND to Vcc Schmitt-trigger action in the clock input For HCT the condition is Vj = GND to Vcc 1.5 V makes the circuit highly tolerant to slower clock rise and fall times. PACKAGE OUTLINES 14-tead DIL; plastic (SOT27). 14-lead mini-pack; plastic (S014; SOT108A), PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1,13 1Rp. 2Rp asynchronous reset-direct input (active LOW) 2,12 1D, 2D data inputs 3,11 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered) 4,10 18p, 25p asynchronous set-direct input (active LOW) 5,9 10, 20 true flip-flop outputs 6,8 10, 26 complement flip-flop outputs 7 GND ground (0 V) 14 Vcc positive supply voltage 1p L1] U ia] Yc aio s } 10 [2] 13] 27> 1351255 op 6 Py * 21D s Jon] ver [3] }2] 20 Tm, of 28 p Sp[4] 74 = [isjece 21 op ce 10 - 11 2CP - SEs 8 1a [5 | [10] 28 ates Us ci t ~ Rp 2a8 12 10[6] Pe} 2a ~_ 4! bh 8 _ on BM, GND 7] re] 20 7293117 1113 PZ9GATB.F 7293116 Fig, 1 Pin configuration. Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. September 1993 187 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.74HC/HCT74 flip-flops 7293118 Fig. 4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS Sp Rp cP D Q a L H Xx x H L H L x x L H L L Xx Xx H H INPUTS OUTPUTS $b Rp cp D On+4 Ont H H t L L H H H t H H L H = HIGH voltage level L = LOW voltage level x = dont care t = LOW-to-HIGH CP transition On+7 = state after the next LOW-to-HIGH CP transition ol al ol e- c c a 7Z93720.3 Fig. 5 Logic diagram (one flip-flop). 188 Printed From CAPS XPert Version 1.2P September 1993 This Material Copyrighted By Philips Semiconductors.Dual D-type flip-flop with set and reset; positive-edge trigger DC CHARACTERISTICS FOR 74HG For the DC characteristics see chapter HCMOS famiiy characteristics, section Family specifications. Output capab Icc category: AC CHARACTERISTICS FOR 74HC GND =0 V; +t, = tp = 6 ns: C, = 50 pF ility: standard flip-flops 74HC/HCT74 flip-flops Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +85 | -40to +125 Vv Min. j typ. | max. | min.{ max. | min. | max. . 47 | 475 220 265 2.0 tPHL/ propagation delay 17 | 35 44 53 | ns 45 | Fig. 6 *PLH nP to nQ, n 14 | 30 37 45 6.0 ; 50 | 200 250 300 2.0 tPHL/ propagation delay 18 | 40 50 60 | ns 45 | Fig.7 tPLH nsp tona, n 14 | 34 43 51 6.0 52 | 200 250 300 2.0 PHL! propagation delay 19 | 40 50 60 | ns 45 | Fig7 tPLH np to nQ, n 15 | 34 43 51 6.0 19 | 75 95 110 2.0 tTHL/ output transition time 7 15 19 22 ns 4.5 Fig. 6 'TLH 6 |13 16 19 6.0 0 tw ork ee 1) 2. oa on (| 45 Fig. 6 HIGH or LOW 14 | 6 17 20 6.0 + pulse width 80 | 19 100 120 2.0 tw Set OF reset Pulse WE 16 | 7 20 24 ns 45 | Fig.7 LOW 14/6 17 20 6.0 removal time a. 3 3 . ns ae Fig. 7 trem set or reset 5 1 7 8 6.0 , 60 |6 75 90 2.0 tu De ncP 12 |2 15 18 ns 4.5 | Fig. 6 nD ton 10 | 2 13 15 6.0 3 |-6 3 3 2.0 th hold time 3 | -2 3 3 ns 4.5 | Fig 6 ncP to nD 3 ~2 3 3 6.0 6.0 | 23 48 4.0 2.0 fmax maximum clock pulse 30 | 69 24 20 MHz | 4.5 | Fig. 6 frequency 35 | 82 28 24 6.0 Printed From CAPS XPert Version 1. aP This Material Copyrighted By Philips Semiconductors. September 1993 18974HC/HCT74 flip-flops DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: flip-flops Note to HCT types The value of additional quiescent supply current (Alce) for a unit load of 1 is given in the family specifications. To determine Alcc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT nbd 0.70 nRp 0.70 nSp 0.80 ncP 0.80 AC CHARACTERISTICS FOR 74HCT GND = 0 V; ty = tp = 6 ns; C_ = 50 pF Tamb (C) TEST CONDITIONS , 74HCT SYMBOL | PARAMETER UNIT | Voc} WAVEFORMS +25 40 to +85 | 40to +125 Vv min. | typ. | max. | min.| max. {| min. | max. tPHL/ | Propagation delay 1 a4 53 | ns | 45 | Fig.6 tPLH ncP to nd, nO 8 | 35 tPHL/ _|_ Propagation delay 23 | 40 50 eo | ns | 45 | Fig.7 tpLH nSp tond, nG tpHi/ |_ Propagation delay 24 | 40 50 60 | ns | 45 | Fig 7 tPLH nRp to na, nO tTHL/ output transition time 7 15 19 22 ns 4.5 Fig. 6 TLH clock pulse width 18 | 9 23 27 ns 45 | Fig.6 Ww HIGH or LOW 8 set or reset pulse width 16 9 20 24 ns 45 Fig, 7 w LOW t removal time 6 | 1 8 9 ns | 4.5 | Fig.? rem set or reset set-up time 12/5 15 18 ns 45 | Fig.6 tsu nD to nCP hold time Fic. 6 3 -3 3 3 ns 4.5 g. th nD to nCP maximum clock pulse 22 18 MHz | 45 Fig. 6 fmax frequency 27 | 54 190 September 1993 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 flip-flops AC WAVEFORMS - & / a 1), jae Te my | th bee + gg, ncP INPUT Veal) _ tw >| t _ . : PHL PLE Fig. 6 Waveforms showing the clock (nCP) to output (nQ, n&) propagation delays, the clock nQ OUTPUT pulse width, the nD to nCP set-up, the nCP tonD hold times, the output transition times and the wel le tri maximum clock pulse frequency. nd OUTPUT Note to Fig. 6 The shaded areas indicate when the input is ole pa permitted to change for predictable output 7299122.1 tpHL performance. aCcP INPUT Vai! | trem : nSp INPUT \ nAip INPUT 1Q OUTPUT | Fig. 7 Waveforms showing the set (nSp) and reset (nRp) input to output (nQ, nO) propagation delays, the set and reset pulse widths and the nRp to nCP removal time. n@ OUTPUT 7222176 Note to AC waveforms (1) HC : Vjy = 50%; V) = GND to Vcc. HCT: Vyy=1.3V; Vp =GND to3V. September 1993 191 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.