ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8432-101 is a general purpose, dual output Differential-to-3.3V LVPECL high frequency HiPerClockSTM synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8432-101 has a selectable TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS8432-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications. * Dual differential 3.3V LVPECL outputs ICS * Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK * TEST_CLK can accept the following input levels: LVCMOS or LVTTL * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK, nCLK or TEST_CLK maximum input frequency: 40MHz * Output frequency range: 25MHz to 700MHz * VCO range: 250MHz to 700MHz * Accepts any single-ended input signal on CLK input with resistor bias on nCLK input * Parallel interface for programming counter and output dividers * RMS period jitter: 5ps (maximum) * Cycle-to-cycle jitter: 25ps (maximum) * 3.3V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT nCLK nP_LOAD M0 1 M1 CLK nCLK M2 0 M3 M4 CLK_SEL TEST_CLK VCO_SEL VCO_SEL 32 31 30 29 28 27 26 25 PLL PHASE DETECTOR MR VCO /M 1 3 22 CLK_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR ICS8432-101 9 10 11 12 13 14 15 16 VEE nFOUT0 FOUT0 VCCO TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N1 8432DY-101 TEST_CLK M7 nFOUT1 CONFIGURATION INTERFACE LOGIC CLK 23 FOUT1 FOUT0 nFOUT0 FOUT1 nFOUT1 24 2 VCC /1 /2 /4 /8 1 M6 TEST S_LOAD S_DATA S_CLOCK nP_LOAD 0 M5 www.icst.com/products/hiperclocks.html 1 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION rial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: fVCO = fIN x M NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS8432-101 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the ICS8432-101. This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8 M 28. The frequency out is defined as follows: fOUT = fVCO = fIN x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-101 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a se- T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK T1 S_DATA t S_LOAD S t T0 * NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 H t nP_LOAD S PARALLEL LOADING M, N M0:M8, N0:N1 nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: 8432DY-101 The NULL timing slot must be observed. www.icst.com/products/hiperclocks.html 2 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 2, 3, 4 28, 29 30, 31, 32 M5 M6, M7, M8, M0, M1, M2, M3, M4 5, 6 Type Input Description Pullup Input M divider inputs. Data latched on LOW-to-HIGH transistion Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pulldown 7 nc Unused 8, 16 VEE Power 9 TEST Output Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. 10 VCC Power Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 23 TEST_CLK Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Clock select input. Selects between differential clock input or TEST_CLK input as the PLL reference source. When HIGH, selects CLK, nCLK inputs. When LOW, selects TEST_CLK input. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. 24 CLK Input Pulldown Non-inver ting differential clock input. 25 nCLK Input Pullup 26 nP_LOAD Input 27 VCO_SEL Input 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power 22 CLK_SEL Input Pullup Inver ting differential clock input. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterisitics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k 8432DY-101 www.icst.com/products/hiperclocks.html 3 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X L L Data Data X X X L Data Data L X X L H X X L Data L H X X L Data L H X X L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial inputs do not affect shift registers. H Data L H X X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 0 1 1 0 VCO Frequency (MHz) M Divide 200 8 0 0 0 0 0 1 225 9 0 0 0 0 0 1 250 10 0 0 0 0 0 1 0 275 11 0 0 0 0 0 1 0 1 1 * * * * * * * * * * * * * * * * * * * * * * 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 700 28 0 0 0 0 1 1 1 0 0 NOTE 1: These M divide values and the resulting frequencies correspond to differential input or TEST_CLK input frequency of 25MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N1 N0 0 0 N Divider Value 1 Output Frequency (MHz) Minimum Maximum 250 700 0 1 2 125 350 1 0 4 62.5 175 1 1 8 31.25 87.5 8432DY-101 www.icst.com/products/hiperclocks.html 4 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3. 3 3.465 V VCCA Analog Supply Voltage 3.135 3. 3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 mA ICCA Analog Supply Current 15 mA Maximum Units 2 VCC + 0.3 V 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V VCC = VIN = 3.465V 150 A VCC = VIN = 3.465V 5 A TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCO_SEL, CLK_SEL, MR, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK VCO_SEL, CLK_SEL, MR, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, CLK_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD Typical VCC = 3.465V, VIN = 0V -5 A M5, CLK_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 A 2.6 V VOH Output High Voltage TEST VCC = 3.135V, IOH = -36mA VOL Output Low Voltage TEST VCC = 3.135V, IOL = 36mA 8432DY-101 Minimum www.icst.com/products/hiperclocks.html 5 0.5 V REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions IIH Input High Current CLK Minimum Typical Maximum Units 150 A VCC = VIN = 3.465V nCLK VCC = VIN = 3.465V CLK VCC = 3.465V, VIN = 0V -5 A nCLK VCC = 3.465V, VIN = 0V -150 A IIL Input Low Current VPP Peak-to-Peak Input Voltage 5 0.15 VCMR Common Mode Input Voltage VEE + 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. A 1.3 V VCC - 0.85 V TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 1.0 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V Maximum Units Peak-to-Peak Output Voltage Swing VSWING NOTE 1: Outputs terminated with 50 to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions fIN Input Frequency Minimum Typical TEST_CLK; NOTE 1 10 40 MHz CLK, nCLK; NOTE 1 10 40 MHz S_CLOCK 40 MHz NOTE 1: For the differential input and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 25 M 70. Using the maximum frequency of 40MHz, valid values of M are 7 M 17. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Units FOUT Output Frequency 700 MHz tjit(cc) Cycle-to-Cycle Jitter ; NOTE 1 fVCO > 350MHz 25 ps tjit(per) Period Jitter, RMS fOUT > 100MHz 5 ps tsk(o) Output Skew; NOTE 1, 2 t R / tF Output Rise/Fall Time tS Setup Time tH Hold Time 31.25 Maximum 20% to 80% 200 15 ps 700 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle N>1 47 53 tPW Output Pulse Width N=1 tPERIOD/2 - 150 tPERIOD/2 + 150 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. 8432DY-101 www.icst.com/products/hiperclocks.html 6 1 % ps ms REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCO Qx VCC SCOPE nCLK LVPECL V V Cross Points PP CMR CLK nQx VEE V EE -1.3V 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL VOH nFOUTx VREF FOUTx tcycle n+1 1000 Cycles Mean Period (Trigger Edge) n t jit(cc) = tcycle n -tcycle n+1 Histogram Reference Point tcycle VOL 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements (First edge after trigger) PERIOD JITTER CYCLE-TO-CYCLE JITTER nFOUTx 80% 80% FOUTx VSW I N G Clock Outputs nFOUTy 20% 20% tR tF FOUTy tsk(o) OUTPUT SKEW OUTPUT RISE/FALL TIME nFOUTx FOUTx t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8432DY-101 www.icst.com/products/hiperclocks.html 7 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION STORAGE AREA NETWORKS A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common appli- cation frequencies as well as the ICS8432-101 configurations used to generate the appropriate frequency. Table 7. Common SANs Application Frequencies Clock Rate Reference Frequency to SERDES (MHz) Crystal Frequency (MHz) 1.25 GHz 125, 250, 156.25 25, 19.53125 FC1 1.0625 GHz FC2 2.1250 GHz 106.25, 53.125, 132.8125 16.6015625, 25 2.5 GHz 125, 250 25 Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Table 8. Configuration Details for SANs Applications Interconnect Technology CLK, nCLK Input (MHz) ICS8432-101 Output Frequency to SERDES (MHz) 25 125 0 0 0 0 1 0 1 0 25 250 0 0 0 0 1 0 1 25 156.25 0 0 0 0 1 1 19.53125 156.25 0 0 0 1 0 25 53.125 0 0 0 0 25 106.25 0 0 0 16.6015625 132.8125 0 0 25 125 0 25 250 0 ICS8432-101 M & N Settings M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 Gigabit Ethernet Fiber Channel 1 Fiber Channel 2 Infiniband POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8432-101 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 8432DY-101 3.3V VCC .01F 10 V CCA .01F 10 F FIGURE 2. POWER SUPPLY FILTERING www.icst.com/products/hiperclocks.html 8 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 FOUT 50 RTT = 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 4A. LVPECL OUTPUT TERMINATION 8432DY-101 125 84 FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8432DY-101 BY www.icst.com/products/hiperclocks.html 10 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The schematic of the ICS8432-101 layout example used in this layout guideline is shown in Figure 6A. The ICS8432-101 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. nCLK CLK 32 31 30 29 28 27 26 25 CLK REF_IN nCLK_SEL VDDA S_LOAD S_DATA S_CLOCK MR 10 24 23 22 21 20 19 18 17 C11 0.01u C16 10u XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR Termination A VCC VCC FOUT FOUTN VCC TEST 8432-101 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD nCLK M5 M6 M7 M8 N0 N1 nc VEE VCC TEST VDD FOUT1/2 nFOUT1/2 VCCO FOUT nFOUT VEE 1 2 3 4 5 6 7 8 R7 9 10 11 12 13 14 15 16 U1 R1 125 R3 125 Termination B (not shown in the layout) IN+ Zo = 50 Ohm IN+ IN- TL1 R2 50 Zo = 50 Ohm C14 0.1u INC15 0.1u TL2 R2 84 FIGURE 6A. SCHEMATIC 8432DY-101 R1 50 OF R3 50 RECOMMENDED LAYOUT www.icst.com/products/hiperclocks.html 11 R4 84 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. GROUNDING Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. * The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. * Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible. CLOCK TRACES AND TERMINATION * Make sure no other signal trace is routed between the clock trace pair. The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. GND U1 VCC PIN 1 C11 VIA C16 VCCA R7 Close to the input pins of the receiver R4 R3 TL1N TL1N C15 C14 TL1 TL1 R2 TL1, TL2 are 50 Ohm traces and equal length FIGURE 6B. PCB BOARD LAYOUT 8432DY-101 FOR ICS8432-101 www.icst.com/products/hiperclocks.html 12 R1 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8432-101. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8432-101 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 9 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.476W * 42.1C/W = 90C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 9. THERMAL RESISTANCE JA FOR 32-PIN LQFP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 55.9C/W 42.1C/W 500 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8432DY-101 www.icst.com/products/hiperclocks.html 13 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 7. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CCO * For logic high, VOUT = V OH_MAX (V CCO_MAX * -V OH_MAX =V OL_MAX CCO_MAX -V OL_MAX CCO_MAX - 1.0V ) = 1.0V For logic low, VOUT = V (V =V CCO_MAX - 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CCO_MAX - 2V))/R ] * (V ] * 1V = 20.0mW [(2V - 1V)/50 Pd_L = [(V OL_MAX - (V CCO_MAX CCO_MAX L - 2V))/R ] * (V ] * 1.7V = 10.2mW [(2V - 1.7V)/50 L CCO_MAX -V OH_MAX -V OL_MAX ) = [(2V - (V CCO_MAX ) = [(2V - (V CCO_MAX -V ))/R ] * (V OH_MAX -V OL_MAX CCO_MAX L ))/R ] * (V L CCO_MAX -V OH_MAX -V OL_MAX )= )= Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8432DY-101 www.icst.com/products/hiperclocks.html 14 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 10. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8432-101 is: 3712 8432DY-101 www.icst.com/products/hiperclocks.html 15 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FOR 32 LEAD LQFP TABLE 11. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL 32 N 1.60 A A1 MAXIMUM 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 0.80 BASIC e L 0.45 0 0.60 0.75 7 0.10 ccc Reference Document: JEDEC Publication 95, MS-026 8432DY-101 www.icst.com/products/hiperclocks.html 16 REV. B JUNE 1, 2005 ICS8432-101 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 12. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8432DY-101 ICS8432DY-101 32 Lead LQFP tray 0C to 70C ICS8432DY-101T ICS8432DY-101 32 Lead LQFP 1000 tape & reel 0C to 70C ICS8432DY-101LF TBD 32 Lead "Lead-Free" LQFP tray 0C to 70C ICS8432DY-101LFT TB D 32 Lead "Lead-Free" LQFP 1000 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8432DY-101 www.icst.com/products/hiperclocks.html 17 REV. B JUNE 1, 2005 Integrated Circuit Systems, Inc. ICS8432-101 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table T2 A A B B 8432DY-101 T3C T6 T6 T12 Page 1 3 5 10 2 1 2 4 6 9 1 2 6 17 Description of Change Features Section - added HCSL to input levels. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. Added Differential Clock Input Interface section. Test Output Table - changed last line from CMOS Fout/2 to CMOS Fout Changed VCO Frequency min. from 200MHz to 250MHz through data sheet. Updated Parallel & Serial Load Operations Diagram. Programmable Output Divider Function Table - changed minimum values. AC Table - changed FOUT min. from 25MHz to 31.25MHz. Updated LVPECL Output Termination Diagrams. Features Section - added Lead-Free bullet. Updated Fig. 1 Parallel & Serial Load Operations. AC Characteristics Table - deleted Note "Jitter performance using XTAL inputs". Ordering Information Table - added Lead-Free par t number. www.icst.com/products/hiperclocks.html 18 Date 7/8/03 7/23/03 9/5/03 6/1/05 REV. B JUNE 1, 2005