ICS8432DY-101T - Integrated Circuit Systems, Inc.

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

GENERAL DESCRIPTION

The ICS8432-101 is a general purpose, dual out-

put Differential-to-3.3V LVPECL high frequency

synthesizer and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS8432-101 has a selectable

TEST_CLK or CLK, nCLK inputs. The TEST_CLK input

accepts LVCMOS or LVTTL input levels and translates them

to 3.3V LVPECL levels. The CLK, nCLK pair can accept most

standard differential input levels. The VCO operates at a

frequency range of 250MHz to 700MHz. The VCO frequency

is programmed in steps equal to the value of the input differ-

ential or single ended reference frequency. The VCO and

output frequency can be programmed using the serial or

parallel interfaces to the configuration logic. The low phase

noise characteristics of the ICS8432-101 makes it an ideal

clock source for Gigabit Ethernet and SONET applications.

BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

•Dual differential 3.3V LVPECL outputs

•Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK

•TEST_CLK can accept the following input levels:

LVCMOS or LVTTL

•CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

•CLK, nCLK or TEST_CLK maximum input frequency: 40MHz

•Output frequency range: 25MHz to 700MHz

•VCO range: 250MHz to 700MHz

•Accepts any single-ended input signal on CLK input

with resistor bias on nCLK input

•Parallel interface for programming counter

and output dividers

•RMS period jitter: 5ps (maximum)

•Cycle-to-cycle jitter: 25ps (maximum)

•3.3V supply voltage

•0°C to 70°C ambient operating temperature

•Lead-Free package fully RoHS compliant

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

CLK

TEST_CLK

CLK_SEL

VCCA

S_LOAD

S_DATA

S_CLOCK

VEE

nFOUT0

FOUT0

VCCO

nFOUT1

FOUT1

VCC

TEST

nCLK

nP_LOAD

VCO_SEL

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

ICS8432-101

VCO_SEL

CLK_SEL

TEST_CLK

CLK

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

M0:M8

N0:N1

VCO

PLL

FOUT0

nFOUT0

FOUT1

nFOUT1

TEST

CONFIGURATION

INTERFACE

LOGIC

÷ M

PHASE DETECTOR

÷1

÷2

÷4

÷8

nCLK

HiPerClockS™

ICS

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

rial event occurs. As a result, the M and N bits can be hardwired

to set the M divider and N output divider to a specific default

state that will automatically occur during power-up. The TEST

output is LOW when operating in the parallel input mode. The

relationship between the VCO frequency, the input frequency

and the M divider is defined as follows:

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock for a

25MHz reference are defined as 8 ≤ M ≤ 28. The frequency

out is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the shift

S_LOAD transitions from LOW-to-HIGH. The M divide and N out-

put divide values are latched on the HIGH-to-LOW transition of

S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is

passed directly to the M divider and N output divider on each rising

edge of S_CLOCK. The serial mode can be used to

program the M and N bits and test bits T1 and T0. The internal reg-

isters T0 and T1 determine the state of the TEST output as follows:

Time

SERIAL LOADING

PARALLEL LOADING

M, N

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes op-

eration using a 25MHz clock input. Valid PLL loop divider val-

ues for different input frequencies are defined in the Input Fre-

quency Characteristics, Table 5, NOTE 1.

The ICS8432-101 features a fully integrated PLL and there-

fore requires no external components for setting the loop band-

width. A differential clock input is used as the input to the

ICS8432-101. This input is fed into the phase detector. A

25MHz clock input provides a 25MHz phase detector refer-

ence frequency. The VCO of the PLL operates over a range

of 250MHz to 700MHz. The output of the M divider is also

applied to the phase detector.

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjust-

ing the VCO control voltage. Note, that for some values of M

(either too high or too low), the PLL will not achieve lock. The

output of the VCO is scaled by a divider prior to being sent to

each of the LVPECL output buffers. The divider provides a

50% output duty cycle.

The programmable features of the ICS8432-101 support two

input modes to program the PLL M divider and N output divider.

The two input operational modes are parallel and serial.

Figure1

shows the timing diagram for each mode. In parallel mode, the

nP_LOAD input is initially LOW. The data on inputs M0 through

M8 and N0 and N1 is passed directly to the M divider and

N output divider. On the LOW-to-HIGH transition of the

nP_LOAD input, the data is latched and the M divider remains

loaded until the next LOW transition on nP_LOAD or until a se-

fVCO = fIN x M

T1 T0 TEST Output

0 0 LOW

0 1 S_Data, Shift Register Input

1 0 Output of M divider

1 1 CMOS Fout

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

*NOTE: The NULL timing slot must be observed.

T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

S_LOAD

fOUT = fVCO = fIN x M

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

15MtupnIpulluP

noitsisnartHGIH-ot-WOLnodehctalataD.stupniredividM

.slevelecafretniLT

TVL/SOMCVL.tupniDAOL_Pnfo

4,3,2

92,82

23,13,03

,8M,7M,6M

,1M,0M

4M,3M,2M

tupnInwodlluP

6,51N,0NtupnInwodlluP ,C3el

baTnidenifedsaeulavredividtuptuosenimreteD

.slevelecafretniLTTVL/SOMCVL.elbaTnoitcnuF

7cndesunU.tcennocoN

1,8V

rewoP.snipylppusevitageN

9TSETtuptuO tuptuO.noitarepofoedomlairesehtniEVITCAsihcihwtuptuotseT

.slevelecafre

tniLTTVL/SOMCVL.edomlellarapniWOLnevird

01V

rewoP.nipylppuseroC

21,111TUOFn,1TUOFtuptuO .slevelecafretniLCEPVLV3.3.rezisehtnysehtroftuptuolaitnereffiD

31V

OCC

rewoP.nipylppustuptuO

51,410TUOFn,0TUOFtuptuO .slevelecafretniLCEPVLV3.3.rezisehtnysehtroftuptuolaitnereff

71RMtupnInwodlluP

sredividlanretnieht,HGIHcigolnehW.teseRretsaMhgiHevitcA

detrevniehtdnawologotxTUOFstup

tuoeurtehtgnisuacteserera

sredividlanretnieht,WOLcigolnehW.hgihogotxTUOFnstuptuo

dedaoltceffatonseodRMf

onoitressA.delbaneerastuptuoehtdna

.slevelecafretniLTTVL/SOMCVL.seulavTdna,N,M

81KCOLC_StupnInwodlluP retsigertfihsehtotnitupniATAD_StatneserpatadlairesniskcolC

.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfoegdegnisir

ehtno

91ATAD_StupnInwodlluP egdegnisirehtnodelpmasataD.tupnilairesretsigertfihS

.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfo

02DAOL_StupnInwodlluP .sredividehtotniretsigertfihsmorfatadfonoitisnartslortnoC

.slevelecafretn

iLTTVL/SOMCVL

12V

ACC

rewoP.nipylppusgolanA

22LES_KLCtupnIpulluP

rotupnikcolclaitnereffidneewtebstceleS.tupnitceleskcolC

,HGIHnehW

.ecruosecnereferLLPehtsatupniKLC_TSET

.tupniKLC_TSETstceles,WOLnehW.stupniKLCn,KLCstceles

.slevelecafre

tniLTTVL/SOMCVL

32KLC_TSETtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolctseT

42KLCtupnInwodlluP.tupnikcol

claitnereffidgnitrevni-noN

52KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI

62DAOL_PntupnInwodlluP

si0M:8Mtatn

eserpatadnehwsenimreteD.tupnidaollellaraP

ehtstes0N:1Ntatneserpatadnehwdna,redividMotnidedaol

.slevelec

afretniLTTVL/SOMCVL.eulavredividtuptuoN

72LES_OCVtupnIpulluP .edomssapybroLLPnisirezisehtnysrehtehwsenimre

teD

.slevelecafretniLTTVL/SOMCVL

:ETON

pulluP

dna

nwodlluP

.seulavlacipytrof,scitisiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE

TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE

TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE

stupnI snoitidnoC

RMDAOL_PnMNDAOL_SKCOLC_SATAD_S

HX XXX X X .WOLstuptuosecroF.teseR

LL ataDataDX X X

ehtotyltceriddessapstupniNdnaMn

oataD

tuptuoTSET.redividtuptuoNdnaredividM

.WOLdecrof

L↑ataDataDL X X dedaolsniamerdnasretsigertupniotnidehctal

siataD

.sruccotnevelairesalitnuronoitisnartWOLtxenlitnu

LH XXL ↑ataD noatadhtiwdedaolsiretsigertfihS.edomtupni

laireS

.KCOLC_SfoegdegnisirhcaenoATAD_S

LH XX↑LataD ehtotdessaperaretsigertfihsehtfostnetnoC

.redividtuptuoNdn

aredividM

LH XX↓LataD.dehctaleraseulavredividtuptuoNdnaredividM

LH XXL X X .sretsigertfihstceffatonodstupnilairesrolella

raP

LH XXH ↑ataD.dekcolcsitisaredividMotyltceriddessapATAD_S

WOL=L:ETON

HGIH=H

eract'noD=X

↑noitisnartegdegnisiR=

↓noitisnartegdegnillaF=

stupnI eulaVrediviDN )zHM(ycneuqerFtuptuO

1N0NmuminiMmumixaM

00 1 052007

01 2 521053

10 4 5.26571

11 8 52.135.78

ycneuqerFOCV

)zHM( ediviDM 6528214623618421

8M7M6M5M4M3M2M1M0M

002 8 00000 1000

522 9 00000 100 1

05201 0 0 0 0 0 10 10

57211 00000 1011

• • •••••••••

05662 0 0 0 0 1 10 10

57672 000011011

00782 0000 11100

ycneuqerftupniKLC_TSETrotupnilai

tnereffidotdnopserrocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON

.zHM52fo

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ACC

egatloVylppuSgolanA 531.33.3564.3V

OCC

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP 021Am

ACC

tnerruCylppuSgolanA 51Am

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tupnI

egatloVhgiH

,RM,LES_KLC,LES_OCV

,ATAD_S,DAOL_S

,DAOL_Pn,KCOLC_S

1N:0N,8M:0M

3.0+V

KLC_TSET2V

3.0+V

tupnI

egatloVwoL

,RM,LES_KLC,LES_OCV

,ATAD_S,DAOL_S

,DAOL_Pn,KCOLC_S

1N:0N,8M:0M

3.0-8.0V

KLC_TSET3.0-3.1V

tupnI

tnerruChgiH

,RM,1N,0N,8M-6M,4M-0M

,KLC_TSET,KCOLC_S

DAOL_Pn,DAOL_S,ATAD_S

V564.3=051Aµ

LES_OCV,LES_KLC,5MV

V564.3=5Aµ

tupnI

tnerruCwoL

,RM,1N,0N,8M-6M,4M-0M

,KLC_TSET,KCOLC_S

DAOL_Pn,DAOL_S,ATAD_S

,V564.3=

V0= 5-Aµ

LES_OCV,LES_KLC,5M V

,V564.3=

V0= 051-Aµ

tuptuO

egatloVhgiH TSET V

,V531.3=

Am63-= 6.2V

tuptuO

egatloVwoL TSET V

,V531.3=

Am63= 5.0V

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5 V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ycneuqerFtupnI

1ETON;KLC_TSET0104zHM

1ETON;KLCn,KLC0104zHM

KCOLC_S 04zHM

nihtiwetarepootOCVehtroftesebtsumeulavMe

ht,egnarycneuqerfKLC_TSETdnatupnilaitnereffidehtroF:1ETON

52eraMfoseulavdilav,zHM01foycneuqerftupnimuminimehtgnisU.egnarzHM007otzHM052eht ≤M≤.07

7eraMfoseulavdilav,zHM04foycneuqerfmumixamehtgnisU ≤M≤.71

TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

OCC

4.1-V

OCC

0.1-V

1ETON;egatloVwoLtuptuOV

OCC

0.2-V

OCC

7.1-V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

OCC

.V2-

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tnerruChgiHtupnI KLCV

V564.3=051Aµ

KLCnV

V564.3=5Aµ

tnerruCwoLtupnI KLCV

V,V564.3=

V0=5-Aµ

KLCnV

V,V564.3=

V0=051-Aµ

egatloVtupnIkaeP-ot-kaeP51.03.1V

RMC

egatloVtupnIedoMnommoCV

5.0+V

58.0-V

VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON

.V3.0+

VsadenifedsiegatlovedomnommoC:2ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO52.13007zHM

)cc(tij1ETON;rettiJelcyC-ot-elcyCzHM053>OCVf52sp

)rep(tijSMR,rettiJdoirePzHM001>TUOf5sp

)o(ks2,1ETON;wekStuptuO 51sp

emiTllaF/esiRtuptuO%08ot%02002007sp

emiTputeS

DAOL_PnotN,M5sn

KCOLC_SotATAD_S5sn

DAOL_SotKCOLC_S5sn

emiTdloH

DAOL_PnotN,M5sn

KCOLC_SotATAD_S5sn

DAOL_SotKCOLC_S5sn

cdoelcyCytuDtuptuO1>N7435%

htdiWesluPtuptuO1=Nt

PDOIRE

051-2/t

PDOIRE

051+2/sp

KCOL

emiTkcoLLLP 1sm

.noitcesnoitamrofnItnemerusaeMretemaraPeeS

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretem

arapsihT:1ETON

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

.stni

opssorclaitnereffidtuptuoehttaderusaeM

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

PARAMETER MEASUREMENT INFORMATION

3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL

CYCLE-TO-CYCLE JITTER

PERIOD JITTER

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

OUTPUT SKEW OUTPUT RISE/FALL TIME

CMR

Cross Points

VEE

nCLK

VCC

CLK

SCOPE

nQx

LVPECL

-1.3V ± 0.165V

REF

Mean Period

(First edge after trigger)

Reference Point

(Trigger Edge)

1σ contains 68.26% of all measurements

2σ contains 95.4% of all measurements

3σ contains 99.73% of all measurements

4σ contains 99.99366% of all measurements

6σ contains (100-1.973x10

-7

)% of all measurements

Histogram

tsk(o)

nFOUTx

FOUTx

nFOUTy

FOUTy

Clock

Outputs 20%

80% 80%

20%

SWING

PERIOD

odc = x 100%

FOUTx

nFOUTx

➤

nFOUTx

FOUTx

jit(cc) =

cycle n –

cycle n+1

1000 Cycles

cycle n

cycle n+1

VCC,

VCCO

V EE

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

STORAGE AREA NETWORKS

A variety of technologies are used for interconnection of the

elements within a SAN. The tables below list the common appli-

Table 7. Common SANs Application Frequencies

Table 8. Configuration Details for SANs Applications

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8432-101 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VCC, VCCA, and VCCO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 2

illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each VCCA pin.

POWER SUPPLY FILTERING T ECHNIQUES

FIGURE 2. POWER SUPPLY FILTERING

10Ω

VCCA

10 μF

.01μF

3.3V

.01μF

VCC

ygolonhceTtcennocretnIetaRkcolC SEDRESotycneuqerFecnerefeR

)zHM(

ycneuqerFlatsyrC

)zHM(

tenrehtEtibagiGzHG52

.152.651,052,52152135.91,52

lennahCerbiF zHG5260.11CF

zHG0521.22CF 5218.231,521.35,52.60152,5265106.61

dnabin

ifnIzHG5.2052,52152

tcennocretnI

ygolonhceT

tupnIKLCn,KLC

)zHM(

101-2348SCI

ycneuqerFtuptuO

SEDRESot

)zHM(

101-2348SCI

sgnitteSN&M

8M7M6M5M4M3M2M1M0M1N0N

tenrehtEtibagiG

52521 0000 10 10010

52052 0000 10 10001

5252.651 00001100 110

52135.9152.651 000 10000010

1lennahCrebiF

52521.35 00001000 111

5252.601 00001000 110

2lennahCrebiF5265106

.615218.231 000 10000010

dnabinifnI

52521 0000 10 10010

52052 0000 10 10001

cation frequencies as well as the ICS8432-101 configurations

used to generate the appropriate frequency.

8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005

Integrated

Circuit

Systems, Inc.

ICS8432-101

700MHZ,

DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

- 2V

50Ω50Ω

RTT

= 50Ω

FOUT FIN

RTT = Z

((V

+ V

) / (V

– 2)) – 2

3.3V

125Ω125Ω

84Ω84Ω

= 50Ω

FOUT FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, termi-

nating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION

designed to drive 50Ω transmission lines. Matched impedance

techniques should be used to maximize operating frequency

and minimize signal distortion.

Figures 4A and 4B

show two

different layouts which are recommended only as guidelines.

Other suitable clock layouts may exist and it would be rec-

ommended that the board designers simulate to guarantee

compatibility across all printed circuit and clock component

process variations.

TERMINATION FOR LVPECL OUTPUTS

Figure 3

shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VCC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u R2

Single Ended Clock Input CLK

nCLK

VCC

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FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 5A to 5E show inter-

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in

Figure 5A,

the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS R1

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Zo = 50 Ohm

125

HiPerClockS

CLK

nCLK

3.3V

100 - 200

3.3V

100 - 200

Input

R5,R6 locate near the driver pin.

Zo = 50 Ohm

125

LVPECL C1

Zo = 50 Ohm

100

3.3V

LVDS_Driver

Zo = 50 Ohm

Receiver

CLK

nCLK

3.3V

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DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

LAYOUT GUIDELINE

The schematic of the ICS8432-101 layout example used in

this layout guideline is shown in

Figure 6A.

The ICS8432-101

recommended PCB board layout for this example is shown in

Figure 6B

. This layout example is used as a general guideline.

FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT

C16

10u

Termination A

8432-101

VEE

TEST

VDD

FOUT1/2

nFOUT1/2

VCCO

FOUT

nFOUT

VEE

S_CLOCK

S_DATA

S_LOAD

VDDA

nCLK_SEL

REF_IN

CLK

VCO_SEL

nP_LOAD

nCLK

125

VCCA

TL2

Zo = 50 Ohm

TEST

IN-

VCC

S_CLOCK

VCC

125

C11

0.01u

XTAL_SEL

S_LOAD

TL1

Zo = 50 Ohm

IN+

FOUT

S_DATA

C15

0.1u

nCLK

CLK

VCC

IN+

Termination B

(not shown in

the layout)

FOUTN

C14

0.1u

VCC

The layout in the actual system will depend on the selected

component types, the density of the components, the density

of the traces, and the stack up of the P.C. board.

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GND

Close to the input

pins of the

receiver

VCCA

TL1

C14

PIN 1

TL1N

TL1

VCC

C11 C16

C15

TL1, TL2 are 50 Ohm traces and

equal length

TL1N

VIA

The following component footprints are used in this layout

example: All the resistors and capacitors are size 0603.

POWER AND GROUNDING

Place the decoupling capacitors C14 and C15 as close as pos-

sible to the power pins. If space allows, placing the decoupling

capacitor at the component side is preferred. This can reduce

unwanted inductance between the decoupling capacitor and the

power pin generated by the via.

Maximize the pad size of the power (ground) at the decoupling

capacitor. Maximize the number of vias between power (ground)

and the pads. This can reduce the inductance between the power

(ground) plane and the component power (ground) pins.

If VCCA shares the same power supply with VCC, insert the RC

filter R7, C11, and C16 in between. Place this RC filter as close

to the VCCA as possible.

CLOCK TRACES AND TERMINATION

The component placements, locations and orientations should be

arranged to achieve the best clock signal quality. Poor clock signal

quality can degrade the system performance or cause system fail-

ure. In the synchronous high-speed digital system, the clock signal

is less tolerable to poor signal quality than other signals. Any ring-

ing on the rising or falling edge or excessive ring back can cause

system failure. The trace shape and the trace delay might be re-

stricted by the available space on the board and the component

location. While routing the traces, the clock signal traces should be

routed first and should be locked prior to routing other signal traces.

• The traces with 50Ω transmission lines TL1 and TL2 at

FOUT and nFOUT should have equal delay and run ad-

jacent to each other. Avoid sharp angles on the clock trace.

Sharp angle turns cause the characteristic impedance to

change on the transmission lines.

• Keep the clock trace on same layer. Whenever possible,

avoid any vias on the clock traces. Any via on the trace

can affect the trace characteristic impedance and hence

degrade signal quality.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow more space between the clock trace

and the other signal trace.

• Make sure no other signal trace is routed between the

clock trace pair.

The matching termination resistors R1, R2, R3 and R4 should

be located as close to the receiver input pins as possible. Other

termination schemes can also be used but are not shown in this

example.

FIGURE 6B. PCB BOARD LAYOUT FOR ICS8432-101

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POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8432-101.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8432-101 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW

•Power (outputs)MAX = 30.2mW/Loaded Output pair

If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW

Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.476W * 42.1°C/W = 90°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 9. THERMAL RESISTANCE θθ

θθ

θJA FOR 32-PIN LQFP, FORCED CONVECTION

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DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in

Figure 7.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V

CCO

- 2V.

• For logic high, VOUT = VOH_MAX = VCCO_MAX – 1.0V

CCO_MAX - VOH_MAX

) = 1.0V

• For logic low, VOUT = VOL_MAX = VCCO_MAX

– 1.7V

CCO_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCCO_MAX

- 2V))/R

] * (VCCO_MAX

- VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX

))/R

] * (VCCO_MAX

- VOH_MAX) =

[(2V - 1V)/50ΩΩ

ΩΩ

Ω] * 1V = 20.0mW

Pd_L = [(VOL_MAX

– (VCCO_MAX

- 2V))/R

] * (VCCO_MAX

- VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX

))/R

] * (VCCO_MAX

- VOL_MAX) =

[(2V - 1.7V)/50ΩΩ

ΩΩ

Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

VOUT

VCCO

VCCO - 2V

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RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8432-101 is: 3712

TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

LOBMYS

ABB

MUMINIMLANIMONMUMIXAM

N23

A06.1

1A 50.051.0

2A 53.104.154.1

b03.

073.054.0

c90.002.0

DCISAB00.9

1D CISAB00.7

2D 06.5

ECISAB00.9

1E CISAB00.7

2E 06.5

eCISAB08.0

L54.006.057.0

θθ

θθ 0

ccc 01.0

TABLE 11. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-026

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TABLE 12. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

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101-YD2348SCI101-YD2348SCIPFQLdaeL23yartC°07otC°0

01-YD2348SCI101-YD2348SCIPFQLdaeL23leer&epat0001C°07otC°0

FL101-YD2348SCIDBTPFQL"eerF-daeL"daeL23yartC°07otC°0

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The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

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