DAC8043A1FS - Analog Devices Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

DAC8043A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/461-3113 © Analog Devices, Inc., 2006

12-Bit Serial Input

Multiplying D/A Converter

FUNCTIONAL BLOCK DIAGRAM

12-BIT SHIFT

DAC REG

DAC

DAC8043A

VDD

VREF

CLK

SRI

GND

IOUT

RFB

FEATURES

Compact SOIC, and TSSOP Packages

True 12-Bit Accuracy

5 V Operation @ <10 ␮A

Fast 3-Wire Serial Input

Fast 1 ␮s Settling Time

2.4 MHz 4-Quadrant Multiply BW

Pin-for-Pin Upgrade for DAC8043

Standard and Rotated Pinout

APPLICATIONS

Ideal for PLC Applications in Industrial Control

Programmable Amplifiers and Attenuators

Digitally Controlled Calibration and Filters

Motion Control Systems

GENERAL DESCRIPTION

The DAC8043A is an improved high accuracy 12-bit multiply-

ing digital-to-analog converter in space-saving 8-lead packages.

Featuring serial input, double buffering and excellent analog

performance, the DAC8043A is ideal for applications where PC

board space is at a premium. Improved linearity and gain error

performance permit reduced parts count through the elimina-

tion of trimming components. Separate input clock and load

DAC control lines allow full user control of data loading and

analog output.

The circuit consists of a 12-bit serial-in/parallel-out shift regis-

ter, a 12-bit DAC register, a 12-bit CMOS DAC and control

logic. Serial data is clocked into the input register on the rising

edge of the CLOCK pulse. When the new data word has been

clocked in, it is loaded into the DAC register with the LD input

pin. Data in the DAC register is converted to an output current

by the D/A converter.

Consuming only 10 µA from a single 5 V power supply, the

DAC8043A is the ideal low power, small size, high performance

solution to many application problems.

The DAC8043A is specified over the extended industrial

(–40°C to +85°C) temperature range. DAC8043A is available

in a PDIP package, and the low profile 1.75 mm height SOIC-8

surface mount packages. The DAC8043AFRU is available for

ultra-compact applications in a thin 1.1 mm TSSOP-8 package.

CODE

INL – LSB

0.1

–0.1

01024 2048 3072 4096

–0.5

0.5

0.4

0.3

0.2

–0.2

–0.3

–0.4

512 1536 2560 3584

TA = +25ⴗC, +85ⴗC, –40ⴗC

VDD = +5V

VREF = –10V

Figure 1. Integral Nonlinearity Error vs. Code

REV. B

–2–

DAC8043A–SPECIFICATIONS

Parameter Symbol Condition E Grade F Grade Unit

STATIC PERFORMANCE

Resolution N 12 12 Bits

Relative Accuracy INL ±0.5 ±1.0 LSB max

Differential Nonlinearity DNL All Grades Monotonic to 12 Bits ±0.5 ±1.0 LSB max

Gain Error

FSE

= 25°C, Data = FFF

±1.0 ±2.0 LSB max

= –40°C, +85°C, Data = FFF

±2.0 ±2.0 LSB max

Gain Tempco

TCG

OUT

Pin Measured ±5±5ppm/°C max

Output Leakage Current I

LKG

Data = 000

, I

OUT

Pin Measured ±5±5nA max

= –40°C, +85°C, Data = 000

, I

OUT

Pin Measured ±25 ±25 nA max

Zero-Scale Error

ZSE

Data = 000

0.03 0.03 LSB max

= –40°C, +85°C, Data = 000

0.15 0.15 LSB max

REFERENCE INPUT

Input Resistance R

REF

Absolute Tempco < 50 ppm/°C7/15 7/15 kΩ min/max

Input Capacitance

REF

55pF typ

ANALOG OUTPUT

Output Capacitance

OUT

Data = 000

25 25 pF typ

Data = FFF

30 30 pF typ

DIGITAL INPUTS

Digital Input Low V

0.8 0.8 V max

Digital Input High V

2.4 2.4 V min

Input Leakage Current I

LOGIC

= 0 V to 5 V 0.001/±10.001/±1µA typ/max

Input Capacitance

LOGIC

= 0 V 10 10 pF max

INTERFACE TIMING

2, 4

Data Setup t

10 10 ns min

Data Hold t

55ns min

Clock Width High t

25 25 ns min

Clock Width Low t

25 25 ns min

Load Pulsewidth t

25 25 ns min

LSB CLK to LD DAC t

ASB

00ns min

AC CHARACTERISTICS

1, 2

Output Current Settling Time t

To ±0.01% of Full Scale, Ext Op Amp OP42 1 1 µs max

DAC Glitch Q Data = 000

to FFF

to 000

, V

REF

= 0 V 20 20 nVs max

Feedthrough (V

OUT

REF

)FT V

REF

= 20 V p-p, Data = 000

, f = 10 kHz 1 1 mV p-p

Total Harmonic Distortion THD V

REF

= 6 V rms, Data = FFF

, f = 1 kHz –85 –85 dB typ

Output Noise Density

10 Hz to 100 kHz Between R

and I

OUT

17 17 nV/√Hz max

Multiplying Bandwidth BW –3 dB, V

OUT

REF

, V

REF

= 100 mV rms, Data = FFF

2.4 2.4 MHz typ

SUPPLY CHARACTERISTICS

Power Supply Range V

DD RANGE

4.5/5.5 4.5/5.5 V min/max

Positive Supply Current I

LOGIC

= 0 V or V

10 10 µA max

Power Dissipation P

DISS

LOGIC

= 0 V or V

50 50 µW max

Power Supply Sensitivity PSS ∆V

= ±5% 0.002 0.002 %/% max

NOTES

Using internal feedback resistor R

, see Figure 19 test circuit with V

REF

= 10 V.

These parameters are guaranteed by design and not subject to production testing.

Calculated from worst case R

REF

: I

ZSE

(LSB) = (R

REF

× I

LKG

× 4096)/V

REF

All input control signals are specified with t

= t

= 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Calculation from e

= √4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

(@ VDD = 5 V, VREF = 10 V, –40ⴗC < TA < +85ⴗC, unless otherwise noted.)

REV. B

DAC8043A

–3–

ABSOLUTE MAXIMUM RATINGS*

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, V

+ 0.3 V

OUT

to GND . . . . . . . . . . . . . . . . . . . –0.3 V, V

+ 0.3 V

OUT

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA

Package Power Dissipation . . . . . . . . . . . . . (T

max – T

)/θ

Thermal Resistance θ

8-Lead PDIP Package (N-8) . . . . . . . . . . . . . . . . . 103°C/W

8-Lead SOIC Package (R-8) . . . . . . . . . . . . . . . . . 158°C/W

8-Lead TSSOP Package (RU-8) . . . . . . . . . . . . . . 240°C/W

Maximum Junction Temperature (T

max) . . . . . . . . . 150°C

Operating Temperature Range . . . . . . . . . . – 40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

PIN FUNCTION DESCRIPTIONS

#(*) Name Function

1(7) V

REF

DAC Reference Input Pin. Establishes DAC full-

scale voltage. Constant input resistance versus

code.

2 (8) R

Internal Matching Feedback Resistor. Connect

to external op amp output.

3 (1) I

OUT

DAC Current Output, full-scale output 1 LSB

less than reference input voltage –V

REF

4 (2) GND Analog and Digital Ground.

5 (3) LD Load Strobe, Level-Sensitive Digital Input.

Transfers shift-register data to DAC register

while active low. See truth table for operation.

6 (4) SRI 12-Bit Serial Register Input, data loads directly

into the shift register MSB first. Extra leading

bits are ignored.

7 (5) CLK Clock Input, positive-edge clocks data into shift

8 (6) V

Positive Power Supply Input. Specified range of

operation 5 V ± 10%.

*Note Pin numbers in parenthesis represent the rotated pinout of the

DAC8043A1ES and DAC8043A1FS models.

DAC8043AE/F PIN CONFIGURATIONS

SOIC-8

DAC8043A

ES/FS

TSSOP-8

DAC8043A

FRU

TOP VIEW

(Not to Scale)

OUT

GND LD

REF

CLK

SRI

PDIP-8

DAC8043A

EP/FP

DAC8043A1E AND DAC8043A1F PIN CONFIGURATION

(Rotated Pinout)

TOP VIEW

(Not to Scale)

IOUT

GND

RFB

VREF

VDD

CLKSRI

SOIC-8

DAC8043A1ES

DAC8043A1FS

ORDERING GUIDE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

DAC8043A

–4–

SRI

CLK

SRI

CLK

OUT

DATA LOADED MSB(D11) FIRST DAC REGISTER LOAD

D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0D7

tLD1

tDS tDH

tCL

tCH

tLD

ⴞ1 LSB

ERROR BAND

Dxx

tASB

Figure 2. Timing Diagram

Table I. Control-Logic Truth Table

CLK LD Serial Shift Register Function DAC Register Function

uHShift-Register-Data Advanced One Bit Latched

H or L L No Effect Updated with Current Shift Register Contents

LuNo Effect Latched All 12 Bits

NOTES

u positive logic transition.

The DAC Register LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the

switches in the R-2R DAC ladder.

TOTAL UNADJUSTED ERROR – LSB

FREQUENCY

–1.0 1.0

–0.5 0.0 0.5

SS = 200 UNITS

= 25ⴗC

= 5V

REF

= 10V

Figure 3. Total Unadjusted Error Histogram

Typical Performance Characteristics

FULL SCALE TEMPCO – ppm/ⴗC

FREQUENCY

SS = 200 UNITS

TA = –40ⴗC TO +85ⴗC

VDD = 5V

VREF = 10V

Figure 4. Full-Scale Output Tempco Histogram

REV. B

DAC8043A

–5–

LOGIC INPUT VOLTAGE – Volts

SUPPLY CURRENT I

– mA

0.1

0.2

0.5

= 25ⴗC

= 5V

12 345

0.5 1.5 2.5 3.5 4.5

0.3

0.4

Figure 5. Supply Current vs. Logic Input Voltage

TEMPERATURE – ⴗC

– ␮A

0.01

0.001

–55

0.1

= 5V

LOGIC

= 0V OR V

–35 –15 5 25 45

65 85 105 125

Figure 6. Supply Current vs. Temperature

FREQUENCY – Hz

– ␮A

500

010k

1000

= 5V

REF

= 10V

= 25ⴗC

100k 1M 10M 100M1k

1500

2000

3000

3500

2500

CODE = F55H

CODE = 800H

CODE = FFFH

Figure 7. Supply Current vs. Clock Frequency

FREQUENCY – Hz

PSRR – dB

20 10k

⌬VDD = 5V ⴞ10%

100k 1M 10M

100

Figure 8. Power Supply Rejection vs. Frequency

CODE – Decimal

DNL – LSB

–0.5 1024 2048 3072 4096

–0.4

–0.3

–0.2

–0.1

0.2

0.4

0.5

VDD = 5V

VREF = 10V

SUPERIMPOSED: TA = –40ⴗC, +25ⴗC, +85ⴗC

512 1536 2560 3584

0.1

0.3

Figure 9. Linearity Error vs. Digital Code

OPAMP OFFSET VOS – ␮V

INL – LSB

–1000 01000 2000–2000

VDD = 5V

VREF = 10V

TA = 25ⴗC

–4

–2

Figure 10. Linearity Error vs. External Op Amp V

REV. B

DAC8043A

–6–

20mV

= 5V

REF

= 10V

CLK

= 2.5MHz

CODE: 7FF

TO 800

OUT

(10mV/DIV)

TIME – 200ns/DIV

(5V/DIV)

Figure 11. Midscale Transition Performance

= 5V

REF

= 10V

= 25ⴗC

CLK

(5V/DIV)

TIME – 1␮s/DIV

OUT

(5V/DIV)

Figure 12. Large Signal Settling Time

FREQUENCY – Hz

1k 10k 100k 1M 10M

ALL BITS ON

DATA BITS "ON"

(ALL OTHER DATA BITS "OFF")

B10

(MSB) B11

(LSB) B0

ATTENUATION – dB

108

100

ALL BITS OFF

Figure 13. Reference Multiplying Bandwidth vs. Fre-

quency and Code

|VREF| – Volts

INL – LSB

010

–0.5

–0.25

0.5

0.25

VDD = 5V

TA = 25ⴗC

Figure 14. Linearity Error vs. Reference Voltage

HOURS OF OPERATION AT 150ⴗC

NOMINAL CHANGE IN VOLTAGE – mV

1.0

CODE = 000H

CODE = FFFH

SAMPLE SIZE = 50

0.2

0.4

0.6

0.8

1.2

100 200 300 400 500 600

Figure 15. Long-Term Drift Accelerated by Burn-In

–95

0.0018

1k 10k 100k

THD – %

100

0.0032

0.0056

0.010

0.018

0.032

–90

–85

–80

–75

–70

VREF = 4V p-p

OUTPUT OP AMP: OP42

THD – dB

FREQUENCY – Hz

Figure 16. THD vs. Frequency

REV. B

DAC8043A

–7–

PARAMETER DEFINITIONS

INTEGRAL NONLINEARITY (INL)

This is the single most important DAC specification. ADI mea-

sures INL as the maximum deviation of the analog output (from

the ideal) from a straight line drawn between the end points. It

is expressed as a percent of full-scale range or in terms of LSBs.

Refer to Analog Devices Data Reference Manual for additional

digital-to-analog converter definitions.

INTERFACE LOGIC INFORMATION

The DAC8043A has been designed for ease of operation. The

timing diagram, Figure 2, illustrates the input register loading

sequence. Note that the most significant bit (MSB) is loaded

first. Once the 12-bit input register is full, the data is transferred

to the DAC register by taking LD momentarily low.

DIGITAL SECTION

The DAC8043A’s digital inputs, SRI, LD, and CLK, are TTL

compatible. The input voltage levels affect the amount of cur-

rent drawn from the supply; peak supply current occurs as the

digital input (VIN) passes through the transition region. See the

Supply Current vs. Logic Input Voltage graph located in the

typical performance characteristics curves. Maintaining the

digital input voltage levels as close as possible to the supplies,

VDD and GND, minimizes supply current consumption. The

DAC8043A’s digital inputs have been designed with ESD resis-

tance incorporated through careful layout and the inclusion of

input protection circuitry. Figure 17 shows the input protection

diodes and series resistor; this input structure is duplicated on

each digital input. High voltage static charges applied to the

inputs are shunted to the supply and ground rails through for-

ward biased diodes. These protection diodes were designed to

clamp the inputs to well below dangerous levels during static

discharge conditions.

VDD

LD, CLK, SRI

GND

5k⍀

Figure 17. Digital Input Protection

GENERAL CIRCUIT INFORMATION

The DAC8043A is a 12-bit multiplying D/A converter with a

very low temperature coefficient. It contains an R-2R resistor

ladder network, data input and control logic, and two data

registers.

The digital circuitry forms an interface in which serial data can

be loaded under microprocessor control into a 12-bit shift regis-

ter and then transferred, in parallel, to the 12-bit DAC register.

The analog portion of the DAC8043A contains an inverted

R-2R ladder network consisting of silicon-chrome, highly-stable

(50 ppm/°C) thin-film resistors, and twelve pairs of NMOS

current-steering switches, see Figure 18. These switches steer

binarily weighted currents into either I

OUT

or GND; this yields a

constant current in each ladder leg, regardless of digital input

code. This constant current results in a constant input resis-

tance at V

REF

equal to R. The V

REF

input may be driven by any

reference voltage or current, ac or dc that is within the limits

stated in the Absolute Maximum Ratings.

10k⍀

20k⍀

10k⍀

20k⍀

10k⍀

S12

20k⍀20k⍀

10k⍀

BIT 1 (MSB) BIT 2 BIT 3 BIT 12 (LSB)

FEEDBACK

REF

OUT

GND

DIGITAL INPUTS

(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")

*THESE SWITCHES PERMANENTLY "ON"

Figure 18. Simplified DAC Circuit

The twelve output current steering NMOS FET switches are in

series with each R-2R resistor.

To further ensure accuracy across the full temperature range,

permanently “ON” MOS switches were included in series with

the feedback resistor and the R-2R ladder’s terminating resistor.

Figure 18 shows the location of the series switches. During any

testing of the resistor ladder or R

FEEDBACK

(such as incoming

inspection), V

must be present to turn “ON” these series

switches.

DYNAMIC PERFORMANCE

OUTPUT IMPEDANCE

The DAC8043A’s output resistance, as in the case of the output

capacitance, varies with the digital input code. This resistance,

looking back into the I

OUT

terminal, may be between 10 kΩ (the

feedback resistor alone when all digital inputs are LOW) and

7.5 kΩ (the feedback resistor in parallel with approximate 30 kΩ

of the R-2R ladder network resistance when any single bit logic

is HIGH). Static accuracy and dynamic performance will be

affected by these variations.

APPLICATIONS INFORMATION

In most applications, linearity depends upon the potential of the

OUT

and GND pins being at the same voltage potential. The

DAC is connected to an external precision op amp inverting

input. The external amplifiers noninverting input should be tied

directly to ground without the usual bias current compensating

resistor. (See Figures 19 and 20.) The selected amplifier should

have a low input bias current and low drift over temperature.

The amplifiers input offset voltage should be nulled to less than

200 microvolts (less than 10% of 1 LSB). All grounded pins

should tie to a single common ground point to avoid ground loops.

The V

power supply should have a low noise level with

adequate bypassing. It is best to operate the DAC8043A from

the analog power supply and grounds.

UNIPOLAR 2-QUADRANT MULTIPLYING

The most straightforward application of the DAC8043A is in

the 2-quadrant multiplying configuration shown in Figure 19. If

the reference input signal is replaced with a fixed dc voltage

REV. B

DAC8043A

–8–

C00272–0–4/06 (B)

reference, the DAC output will provide a proportional dc voltage

output according to the transfer equation:

OUT

= –D/4096 × V

REF

where D is the decimal data loaded into the DAC register and

REF

is the externally applied reference voltage source.

REF

OUT

GND

OP77

ⴞ10V

OUT

DIGITAL INPUTS OMITTED FOR CLARITY

10pF

Figure 19. Unipolar (2-Quadrant) Operation

BIPOLAR 4-QUADRANT MULTIPLYING

Figure 20 shows a suggested circuit to achieve 4-quadrant mul-

tiplying operation. The summing amplifier multiplies V

OUT1

2, and offsets the output with the reference voltage so that a

midscale digital input code of 2048 places V

OUT2

at zero volts.

The negative full-scale voltage will be V

REF

when the DAC is

loaded with all zeros. The positive full-scale output will be

–(V

REF

– 1 LSB) when the DAC is loaded with all ones. Thus

the digital coding is offset binary. The voltage output transfer

equation for various input data and reference (or signal) values

follows:

OUT2

= (D/2048 – 1) × –V

REF

where D is the decimal data loaded into the DAC register and

REF

is the externally applied reference voltage source.

Precision resistors will be necessary to avoid ratio errors. Other-

wise trimming will be required to achieve full accuracy specifica-

tions available from the DAC8043A device. See the various

Analog Devices Digital Potentiometer products for automated

trimming solutions (e.g., the AD5204 for low voltage applica-

tions or the AD7376 for high voltage applications).

(0V TO –V

REF

)

REF

OUT

GND

ⴞ10V

OUT1

DIGITAL INPUTS OMITTED FOR CLARITY

OP213

10k⍀

OP213

OUT2

20k⍀20k⍀

10pF

Figure 20. Bipolar (4-Quadrant) Operation

8-Lead Standard Small Outline Package [SOIC_N]

(R-8)

S-Suffix

Dimensions shown in millimeters and (inches).

8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters).

8-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-8)

Dimensions shown in millimeters.

OUTLINE DIMENSIONS