SEMICONDUCTOR
5-22
HI5805
12-Bit, 5 MSPS A/D Converter
Description
The HI5805 is a monolithic, 12-bit, Analog-to-Digital
Conv erter fabricated in Harris’ HBC10 BiCMOS process. It is
designed for high speed, high resolution applications where
wide bandwidth and low power consumption are essential.
The HI5805 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5805 has excellent dynamic
perf ormance while consuming 300mW power at 5 MSPS.
The 100MHz full power input bandwidth is ideal for commu-
nication systems and document scanner applications. Data
output latches are provided which present valid data to the
output bus with a latency of 3 clock cycles. The digital out-
puts have a separate supply pin which can be powered from
a 3.0V to 5.0V supply.
Ordering Information
PART
NUMBER SAMPLE
RATE TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HI5805BIB 5 MSPS -40 to 85 28 Ld SOIC (W) M28.3
HI5805EVAL1 25 Evaluation Board
Features
• 5 MSPS Sampling Rate
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
• 100MHz Full Power Input Bandwidth
• Low Distortion
• Internal Voltage Reference
• TTL/CMOS Compatible Digital I/O
• 5V to 3.0V Digital Outputs
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Document Scanners
• Additional Reference Documents
- AN9214 Using Harris High Speed A/D Converters
January 1997
Pinout
HI5805 (SOIC)
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
DVCC1
VIN+
VDC
VROUT
VRIN
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D0
D2
D3
D4
DVCC2
DGND2
D6
D7
D8
D9
D1
D5
DGND1
DVCC1
DGND1
AVCC
AGND
AVCC
D10
D11
VIN-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 3984.3
5-23
Functional Block Diagram
Typical Applications Schematic
VDC
VIN+
VIN-
BIAS
4-BIT
FLASH
+
-
4-BIT
DAC
4-BIT
FLASH
STAGE 4
STAGE 3
STAGE 1
AVCC AGND DVCC1 DGND1
DIGITAL DELAY
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
4-BIT
FLASH
+
-
4-BIT
DAC
AND
DIGITAL ERROR CORRECTION
CLOCK
REF
DVCC2
DGND2
VROUT
CLK
VRIN
∑
X8
X8
S/H
∑
VRIN (12)
HI5805
VROUT (11)
VIN- (9)
CLK (1)
DGND1 (5)
DGND2 (21)
DGND1 (3)
AGND (13)
(14) AVCC
(22) DVCC2
(17) D9
(18) D8
(19) D7
(20) D6
(23) D5
(24) D4
(25) D3
(26) D2
(27) D1
(LSB) (28) D0
AS CLOSE TO PART AS POSSIBLE
10µF AND 0.1µF CAPS ARE PLACED
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BNC
CLOCK
VIN+
0.1µF10µF
0.1µF10µF
+
+
AGND (7)
VIN+ (8)
VIN-
DGND AGND
(2) DVCC1
(4) DVCC1
VDC (10)
(16) D10 D10
(MSB) (15) D11 D11
(6) AVCC
+5V
+5V
HI5805HI5805
5-24
Absolute Maximum Ratings Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND. . . . . . . . . . .+6.0V
DGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range, HI5805BIB . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
HI5805BIB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVCC = DVCC1 = DVCC2 = DVCC3 = +5.0V, FS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = -40oC to 85oC, Differential Analog Input, Unless Otherwise Specified
PARAMETER TEST CONDITION
HI5805BIB (-40oC TO 85oC)
UNITSMIN TYP MAX
ACCURACY
Resolution 12 - - Bits
Integral Linearity Error, INL fIN = DC - ±1±2 LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes) fIN = DC - ±0.5 ±1 LSB
Offset Error, VOS fIN = DC - 19 - LSB
Full Scale Error, FSE fIN = DC - 32 - LSB
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate No Missing Codes - 0.5 - MSPS
Maximum Conversion Rate No Missing Codes 5 - - MSPS
Effective Number of Bits, ENOB fIN = 1MHz - 11 - Bits
Signal to Noise and Distortion Ratio, SINAD fIN = 1MHz - 68 - dB
Signal to Noise Ratio, SNR fIN = 1MHz - 68 - dB
Total Harmonic Distortion, THD fIN = 1MHz - -80 - dBc
2nd Harmonic Distortion fIN = 1MHz - -86 dBc
3rd Harmonic Distortion fIN = 1MHz - -83 - dBc
Spurious Free Dynamic Range, SFDR fIN = 1MHz - 83 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - -68 - dBc
Transient Response - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive - 2 - Cycle
ANALOG INPUT
Maximum Peak-to-P eak Diff erential Analog Input Range
(VIN+ - VIN-) -±2.0 - V
Maximum Peak-to-Peak Single-Ended Analog Input Range - 4.0 - V
Analog Input Resistance, RIN (Notes 2, 3) 1 - - MΩ
Analog Input Capacitance, CIN -10-pF
Analog Input Bias Current, IB+ or IB- (Note 3) -10 - +10 µA
Differential Analog Input Bias Current IB DIFF = (IB+ - I B-) - ±0.5 - µA
Full Power Input Bandwidth (FPBW) - 100 - MHz
Analog Input Common Mode Voltage Range (V IN+ + V IN-)/2 Differential Mode (Note 2) 1 2.3 4 V
=RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------
=RMS Signal
RMS Noise
-------------------------------
HI5805HI5805
5-25
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT (Loaded) - 3.5 - V
Reference Output Current - - 1 mA
Reference Temperature Coefficient - 200 - ppm/oC
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN - 3.5 - V
Total Reference Resistance, RL- 7.8 - kΩ
Reference Current - 450 - µA
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC - 2.3 - V
Max Output Current (Not To Exceed) - - 1 mA
DIGITAL INPUTS (CLK)
Input Logic High Voltage, VIH 2.0 - - V
Input Logic Low Voltage, VIL - - 0.8 V
Input Logic High Current, IIH VCLK = 5V - - 10.0 µA
Input Logic Low Current, IIL VCLK = 0V - - 10.0 µA
Input Capacitance, CIN -7-pF
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, IOL VO = 0.4V (Note 2) 1.6 - - mA
DVCC3 = 3.0V, VO = 0.4V - 1.6 - mA
Output Logic Source Current, IOH VO = 2.4V (Note 2) -0.2 - - mA
DVCC3 = 3.0V, VO = 2.4V - -0.2 - mA
Output Capacitance, COUT -5-pF
TIMING CHARACTERISTICS
Aperture Delay, tAP -5-ns
Aperture Jitter, tAJ - 5 - ps (RMS)
Data Output Delay, tOD -8-ns
Data Output Hold, tH-8-ns
Data Latency, tLAT For a Valid Sample (Note 2) - - 3 Cycles
Clock Pulse Width (Low) 5MHz Clock 90 100 110 ns
Clock Pulse Width (High) 5MHz Clock 90 100 110 ns
POWER SUPPLY CHARACTERISTICS
Total Supply Current, ICC VIN+ = VIN- = VDC -6070mA
Analog Supply Current, AICC VIN+ = VIN- = VDC -46-mA
Digital Supply Current, DICC VIN+ = VIN- = VDC -13-mA
Output Supply Current, DICC1 VIN+ = VIN- = VDC -1-mA
Power Dissipation VIN+ = VIN- = VDC - 300 - mW
Offset Error PSRR, ∆VOS AVCC or DVCC = 5V ± 5% - 2 - LSB
Gain Error PSRR, ∆FSE AVCC or DVCC = 5V ± 5% - 30 - LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
Electrical Specifications AVCC = DVCC1 = DVCC2 = DVCC3 = +5.0V, FS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = -40oC to 85oC, Differential Analog Input, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITION
HI5805BIB (-40oC TO 85oC)
UNITSMIN TYP MAX
HI5805
5-26
Timing Waveforms
NOTES:
4. SN: N-th sampling period.
5. HN: N-th holding period.
6. BM,N: M-th stage digital output corresponding to N-th sampled in-
put.
7. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
FIGURE 2. INPUT-TO-OUTPUT TIMING
ANALOG
INPUT
CLOCK
INPUT
INPUT
S/H
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
DATA
OUTPUT
SN-1 HN-1 SNHNSN+1 HN+1 SN+2 HN+2 SN+3 HN+3 SN+4 HN+4 SN+5 HN+5 SN+6 HN+6
B1, N+7
B1, N+3
B1, N+2
B1, N+1
B1, N+1
B1, N
B1, N-1
B2, N-2
B3, N-2
B4, N-3
DN-3
B2, N-1
B3, N-1
B4, N-2
DN-2
tLAT
DN-1
B4, N-1
B2, N
B3, N
B2, N+1
B3, N+1
B4, N
DNDN+1
B4, N+1
B2, N+1 B2, N+2
B3, N+1
B4, N+1
DN+1
B3, N+2
B2, N+3
B3, N+3
B4, N+2
DN+2
tOD
tH
DATA N-1 DATA N
CLOCK
INPUT
DATA
OUTPUT 0.8V
2.0V
1.5V
tAP
ANALOG
INPUT
tAJ
1.5V
HI5805HI5805
5-27
Typical Performance Curves
10
INPUT FREQUENCY (MHz) 100
11
10
9
8
7
6
51
ENOB
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FS = 5 MSPS
TEMPERATURE = 25oC
FIGURE 4. SIGNAL T O NOISE AND DIST ORTION (SINAD) vs
INPUT FREQUENCY
10
INPUT FREQUENCY (MHz) 100
70
60
50
40
301
SINAD (dB)
FS = 5 MSPS
TEMPERATURE = 25oC
FIGURE 5. SIGNAL T O NOISE RATIO (SNR) vs INPUT
FREQUENCY
10
INPUT FREQUENCY (MHz) 100
70
60
50
40
301
SNR (dB)
FS = 5 MSPS
TEMPERATURE = 25oC
FIGURE 6. T O TAL HARMONIC DISTOR TION (THD) vs INPUT
FREQUENCY
10
INPUT FREQUENCY (MHz) 100
-40
-50
-60
-70
-801
THD (dBc)
FS = 5 MSPS
TEMPERATURE = 25oC
FIGURE 7. SPURIOUS FREE D YNAMIC RANGE (SFDR) vs
INPUT FREQUENCY
10
INPUT FREQUENCY (MHz) 100
80
70
60
50
401
SFDR (dB)
FS = 5 MSPS
TEMPERATURE = 25oC
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs CLOCK
DUTY CYCLE AND INPUT FREQUENCY
0.5
DUTY CYCLE (tCLK-LOW/tCLK)0.6
11
10
9
8
7
6
50.4
ENOB
FS = 5 MSPS
TEMPERATURE = 25oC
50MHz
20MHz
10MHz
5MHz
100MHz
2MHz
1MHz
HI5805HI5805
5-28
Typical Performance Curves
(Continued)
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE AND INPUT FREQUENCY
20
TEMPERATURE (oC) 80
11
10
9
8
7
6
5-40
ENOB
50MHz
20MHz
10MHz
5MHz
100MHz
2MHz
-20 0 40 60
FS = 5 MSPS
1MHz
FIGURE 10. INTERNAL V OLT A GE REFERENCE OUTPUT
(VROUT) vs TEMPERATURE AND LOAD
20
TEMPERATURE (oC) 80
3.525
3.515
3.505
3.495
3.485
3.475
-40
VROUT (V)
VREFNOM
-20 0 40 60
VREFLD
FIGURE 11. POWER DISSIPATION vs TEMPERATURE
20
TEMPERATURE (oC) 80
306
304
302
300
298
296
-40
POWER DISSIPATION (mW)
-20 0 40 60
FS = 5 MSPS
VIN+ = VIN- = VDC
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
20
TEMPERATURE (oC) 80
70
50
40
30
20
0
-40
CURRENT (mA)
-20 0 40 60
60
10
FS = 5 MSPS
VIN+ = VIN- = VDC
DICC3
DICC1/2
AICC
ITOT
FIGURE 13. 2048 POINT FFT SPECTRAL PLOT
-120
OUTPUT LEVEL (dB)
200 400 600 800 1000
-100
-80
-60
-40
-20
0
FREQUENCY BIN
FIN = 1MHz, FS = 5 MSPS
HI5805
5-29
Detailed Description
Theory of Operation
The HI5805 is a 12-bit fully differential sampling pipeline A/D
conver ter with digital error correction. Figure 14 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, f1 and f2,
derived from the master clock. During the sampling phase,
f1, the input signal is applied to the sampling capacitors, CS.
At the same time the holding capacitors, CH, are discharged
to analog ground. At the falling edge of f1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, f2, the two bottom plates of the sam-
pling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between CS and CH completing
one sample-and-hold cycle. The output is a fully-differential,
sampled-data representation of the analog input. The circuit
not only perfor ms the sample-and-hold function but will also
conver t a single-ended input to a fully-differential output for
the conver ter core. During the sampling phase, the VIN pins
see only the on-resistance of a switch and CS. The relatively
small values of these components result in a typical full
power input bandwidth of 100MHz for the converter.
As illustrated in the functional b loc k diag r am and the timing dia-
gram in Figure 1, three identical pipeline subconver ter stages,
each containing a four-bit flash converter, a four-bit digital-to-
analog conver ter and an amplifier with a voltage gain of 8, fol-
low the S/H circuit with the fourth stage being only a 4-bit flash
converter. Each converter stage in the pipeline will be sampling
in one phase and amplifying in the other clock phase. Each
individual sub-converter clock signal is offset by 180 degrees
from the previous stage clock signal, with the result that alter-
nate stages in the pipeline will perf orm the same operation.
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final 12-bit output for the converter.
Because of the pipeline nature of this conver ter, the data on
the bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each suc-
ceeding sample is output at the following clock pulse. The
output data is synchronized to the exter nal clock by a latch.
The digital outputs are in offset binary format (See Table 1).
Internal Reference Generator, VROUT and VRIN
The HI5805 has an internal reference generator, therefore,
no external reference voltage is required. VROUT must be
connected to VRIN when using the internal reference v oltage .
The HI5805 can be used with an external reference. The
conver ter requires only one external reference voltage con-
nected to the VRIN pin with VROUT left open.
The HI5805 is tested with VRIN equal to 3.5V. Inter nal to the
converter, two reference voltages of 1.3V and 3.3V are gen-
erated for a fully differential input signal range of ±2V.
In order to minimize overall converter noise, it is recom-
mended that adequate high frequency decoupling be pro-
vided at the reference voltage input pin, VRIN.
Pin Description
PIN
NO. NAME DESCRIPTION
1 CLK Input Clock
2DV
CC1 Digital Supply (5.0V)
3D
GND1 Digital Ground
4DV
CC1 Digital Supply (5.0V)
5D
GND1 Digital Ground
6AV
CC Analog Supply (5.0V)
7A
GND Analog Ground
8V
IN+ Positive Analog Input
9V
IN- Negative Analog Input
10 VDC DC Bias Voltage Output
11 VROUT Reference Voltage Output
12 VRIN Reference Voltage Input
13 AGND Analog Ground
14 AVCC Analog Supply (5.0V)
15 D11 Data Bit 11 Output (MSB)
16 D10 Data Bit 10 Output
17 D9 Data Bit 9 Output
18 D8 Data Bit 8 Output
19 D7 Data Bit 7 Output
20 D6 Data Bit 6 Output
21 DGND2 Digital Output Ground
22 DVCC2 Digital Output Supply (3.0V to 5.0V)
23 D5 Data Bit 5 Output
24 D4 Data Bit 4 Output
25 D3 Data Bit 3 Output
26 D2 Data Bit 2 Output
27 D1 Data Bit 1 Output
28 D0 Data Bit 0 Output (LSB)
CH
CS
CS
VIN+VOUT+
VOUT-
VIN-
φ1
φ1
φ2
φ1
φ1
CH
φ1φ1
+-
-+
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
HI5805HI5805
5-30
Analog Input, Differential Connection
The analog input to the HI5805 can be configured in various
ways depending on the signal source and the required level
of perf ormance. A fully diff erential connection (Figure 15) will
give the best performance for the converter.
Since the HI5805 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input
common mode voltage range of 1.0V to 4.0V. The perfor-
mance of the ADC does not change significantly with the
value of the analog input common mode voltage.
A 2.3V DC bias voltage source, VDC, half way between the
top and bottom internal reference voltages, is made avail-
able to the user to help simplify circuit design when using a
differential input. This low output impedance voltage source
is not designed to be a reference but makes an excellent
bias source and sta ys within the analog input common mode
voltage range over temperature.
The difference between the converter’s two internal voltage
references is 2V. For the AC coupled differential input,
(Figure 15), if VIN is a 2VP-P sinewave with -VIN being 180
degrees out of phase with VIN, then VIN+ is a 2VP-P sine-
wa ve riding on a DC bias voltage equal to VDC and VIN- is a
2VP-P sinewave riding on a DC bias voltage equal to VDC.
Consequently, the converter will be at positive full scale, all
1s digital data output code, when the VIN+ input is at
VDC+1V and the VIN- input is at VDC-1V (VIN+-VIN- = 2V).
Conversely, the ADC will be at negative full scale, all 0s
digital data output code, when the VIN+ input is equal to
VDC-1V and VIN- is at VDC+1V (VIN+-VIN- = -2V). From
this, the converter is seen to have a peak-to-peak differen-
tial analog input voltage range of ±2V.
The analog input can be DC coupled (Figure 16) as long as
the inputs are within the analog input common mode voltage
range (1.0V≤VDC≤4.0V).
The resistors, R, in Figure 16 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high fre-
quency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest fre-
quency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 17 may be used with a
single ended A C coupled input. Sufficient headroom must be
provided such that the input voltage never goes above +5V
or below AGND.
CODE CENTER
DESCRIPTION
DIFFERENTIAL
INPUT VOL T AGE†
(USING INTERNAL
REFERENCE)
OFFSET BINARY OUTPUT CODE
MSB LSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
+Full Scale(+FS) - 1/4 LSB +1.99976V 1 1111111111 1
+FS - 1 1/4 LSB 1.99878V 1 1111111111 0
+ 3/4 LSB 732.4µV 10000000000 0
- 1/4 LSB -244.1µV 01111111111 1
-FS + 1 3/4 LSB -1.99829V 0 0000000000 1
-Full Scale (-FS) + 3/4 LSB -1.99927V 0 0000000000 0
† The voltages listed above represent the ideal center of each offset binary output code shown.
VIN+
VDC
VIN-
HI5805
VIN
-VIN
FIGURE 15. AC COUPLED DIFFERENTIAL INPUT
VIN+
VDC
VIN-
HI5805
VIN
-VIN R
RC
VDC
VDC
FIGURE 16. DC COUPLED DIFFERENTIAL INPUT
HI5805
5-31
Again, the difference between the two internal voltage refer-
ences is 2V. If VIN is a 4VP-P sinewave, then VIN+ is a 4VP-P
sinew a v e riding on a positiv e v oltage equal to VDC. The con-
verter will be at positive full scale when VIN+ is at VDC + 2V
(VIN+ - VIN- = 2V) and will be at negative full scale when
VIN+ is equal to VDC - 2V (VIN+ - VIN- = -2V). In this case,
VDC could range between 2V and 3V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the VDC bias voltage output of the HI5805.
The single ended analog input can be DC coupled (Figure
18) as long as the input is within the analog input common
mode voltage range.
The resistor, R, in Figure 18 is not absolutely necessar y but
may be used as a load setting resistor. A capacitor, C, con-
nected from VIN+ to VIN- will help filter any high frequency
noise on the inputs, also improving performance. Values
around 20pF are sufficient and can be used on AC coupled
inputs as well. Note, however, that the value of capacitor C
chosen must take into account the highest frequency com-
ponent of the analog input signal.
A single ended source will give better overall system perfor-
mance if it is first conver ted to differential before driving the
HI5805.
Digital I/O and Clock Requirements
The HI5805 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5805 to be driven by CMOS logic.
The digital CMOS outputs have a separate digital supply.
This allows the digital outputs to operate from a 3.0V to 5.0V
supply. When driving CMOS logic, the digital outputs will
swing to the rails. When driving standard TTL loads, the
digital outputs will meet standard TTL level requirements
even with a 3.0V supply.
In order to ensure rated performance of the HI5805, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5805 will only be guaranteed at con-
version rates above 0.5 MSPS. This ensures proper perfor-
mance of the internal dynamic circuits.
Supply and Ground Considerations
The HI5805 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The par t should be mounted on a board that provides
separate low impedance connections for the analog and dig-
ital supplies and grounds. For best performance, the sup-
plies to the HI5805 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as possi-
ble to the converter. If the part is powered off a single supply
then the analog supply and ground pins should be isolated
by ferrite beads from the digital supply and ground pins.
Refer to the Application Note AN9214, “Using Harris High
Speed A/D Converters” for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSBs below positive full-scale with the offset error
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Rejection Ratio (PSRR)
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evalu-
ate the dynamic perfor mance of the HI5805. A low distortion
sine wave is applied to the input, it is coherently sampled,
and the output is stored in RAM. The data is then trans-
formed into the frequency domain with an FFT and analyzed
VIN+
VIN-
HI5805
VIN
VDC
FIGURE 17. AC COUPLED SINGLE ENDED INPUT
VIN+
VIN-
HI5805
VDC
R
C
VIN
VDC
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
HI5805HI5805
5-32
to evaluate the dynamic performance of the A/D. The sine
wave input to the part is -0.5dB down from full-scale for all
these tests. SNR and SINAD are quoted in dB. The distor-
tion numbers are quoted in dBc (decibels with respect to car-
rier) and DO NOT include any correction factors for
normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a speci-
fied input and sampling frequency. The noise is the RMS
sum of all of the spectral components except the fundamen-
tal and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
FS/2, excluding DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
where: VCORR = 0.5dB
VCORR adjusts the ENOB for the amount the input is below
fullscale.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic com-
ponents to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable har-
monic component to the RMS value of the fundamental
input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral compo-
nent in the spectrum below FS/2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate inter-
modulation products when two tones, f1 and f2, are present
at the inputs. The ratio of the measured signal to the distor-
tion terms is calculated. The ter ms included in the calcula-
tion are (f1+ f2), (f1- f2), (2f1), (2f2), (2f1+ f2), (2f1- f2), (f1+
2f2), (f1- 2f2). The ADC is tested with each tone 6dB below
full scale.
Transient Response
Transient response is measured by pro viding a fullscale tran-
sition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Over-Voltage Recovery
Over-voltage Recovery is measured by providing a fullscale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
The input sinewave has an amplitude which swings from -FS
to +FS. The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external sam-
ple command (the falling edge of the clock) and the time at
which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture Jitter is the RMS v ariation in the aperture dela y due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the pipe-
line nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 3
clock cycles.
ENOB = SINAD + VCORR-1.76()/6.02
HI5805
