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FEATURES
Provides bank switching for 16 banks of
memory
Bank switching is software-controlled by a
pattern recognition sequence on four address
inputs
Automatically sets all 16 banks off on
power-up
Bank switching logic allows only one bank on
at a time
Custom recognition patterns are available to
prevent unauthorized access
Full ±10% operating range
Low-power CMOS circuitry
Can be used to expand the address range of
microprocessors and decoders
Optional 16-pin SOIC surface mount package
PIN ASSIGNMENT
PIN DESCRIPTION
AW-AZ - Address Inputs
CEI - Chip Enable Input
CEO - Chip Enable Output
NC - No Connection
BS1,BS2, - Bank Select Outputs
BS3,BS4 - Bank Select Outputs
IPF - Power Fail Input
VCC - +5 Volts
GND - Ground
DESCRIPTION
The DS1222 BankSwitch Chip is a CMOS circuit designed to select one of 16 memory banks under
software control. Memory bank switching allows for an increase in memory capacit y without additional
address lines. Continuous blocks of memory are enabled by selecting proper memory bank through a
pattern recognition sequence on four address inputs. Custom patterns from Dallas Semiconductor can
provide security through uniqueness and prevent unauthorized access. By combining the DS1222 with
the DS1212 Nonvolatile Controller x16 Chip, up to 16 banks of static RAMs can be selected.
DS1222
BankSwitch Chip
www.dalsemi.com
DS1222 14-Pin DIP
(300-mil)
See Mech. Drawings
Section
CEI VCC
13
AW
AY
GND
CEO
BS1
BS2
BS3
BS4
NC
1
2
3
4
5
6
7
14
12
11
10
9
8
PFI
AX
AZ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC
CEO
NC
BS1
BS2
BS3
NC
BS4
CEI
NC
PFI
AW
AX
AY
AZ
GND
DS1222S 16-Pin SOIC
(300-mil)
See Mech. Drawings
Section
DS1222
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OPERATION - BANK SWITCHING
Initially, on power-up all four bank select outputs are low and the chip enable output (CEO ) is held high.
(Note: the power fail input [ IFP ] must be low prior to power-up to assure proper initialization.) Bank
switching is achieved by matching a pred efined pattern stored within the DS1222 with a 16-bit sequence
received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read
cycle of 1111 on address inputs AW through A Z should be executed to guarantee that pattern entry starts
with bit 0. Each set of address inputs is clocked into the DS1222 when CEI is driven low. All 16 inputs
must be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in
Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ.
However, address line AW defines the bank number to be enabled as per Table 2.
Switching to a selected bank of memor y occurs on the rising edge of CEI when the last set of bits is input
and a match has been established. After bank selection CEO always follows CEI with a maximum
propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 through
Bank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory
bank is selected.
ADDRESS BIT SEQUENCE Table 1
BIT SEQUENCE
ADDRESS
INPUTS 0123456789101112131415
AW10100011010xxxxx
AX0101110010100011
AY1010001101011100
AZ0101110010100011
X See Table 2
BANK SELECT CONTROL Table 2
AW Bit Sequence Outputs
Bank
Selected 11 12 13 14 15 BS1 BS2 BS3 BS4
*Banks Off0XXXXLowLowLowLow
Bank 0100 00LowLowLowLow
Bank 1100 01HighLowLowLow
Bank 2100 10LowHighLowLow
Bank 3100 11HighHighLowLow
Bank 4101 00LowLowHighLow
Bank 5101 01HighLowHighLow
Bank 6101 10LowHighHighLow
Bank 7 1 0 1 1 1 High High High Low
Bank 8110 00LowLowLowHigh
Bank 9110 01HighLowLowHigh
Bank 1011010LowHighLowHigh
Bank 1111011HighHighLowHigh
Bank 1211100LowLowLowHigh
Bank 13 1 1 1 0 1 High Low High High
Bank 14 1 1 1 1 0 Low High High High
Bank 15 1 1 1 1 1 High High High High
*CEO =VIH independent of CEI
DS1222
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ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temper ature -55°C to +125°C
∗ This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITI ONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage VCC 4.5 5.0 5.5 V 1
Logic 1 VIH 2.2 V CC +0.3 V 1
Logic 0 VIL -0.3 +0.8 V 1
DC ELECTRICAL CHARAC TERI STICS (0°C to 70°C; VCC = 5V ±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leaka ge Current IIL -1.0 +1.0 µA
I/O Leakage Current ILO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA 2
Output Current @ 0.4V IOL +4.0 mA 2
Operating Current ICC 15 mA
CAPACITANCE (TA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510pF
Input/Output Capacitance CI/O 510pF
AC ELECTRICAL CHARACT ERIST ICS (0°C to 70°C; VCC = 5V ±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Address Setup tAS 5ns
Address Hold tAH 50 ns
Read Recovery tRR 40 ns
Propagation Delay tPD 15 ns 2
Power Fail Input to First CEI tPF 50 ns
Chip Enable Low tCW 110 ns
NOTES:
1. All voltages are referenced to ground.
2. Measured with a load as shown in Figure 1.
DS1222
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OUTPUT LOAD Figure 1
TIMING DIAGR AM-ACCESS TO BANK SWITCH
