1
LTC1274/LTC1277
12-Bit, 10mW, 100ksps
ADCs with 1µA Shutdown
U
A
O
PPLICATITYPICAL
S
FEATURE
D
U
ESCRIPTIO
The LTC
®
1274/LTC1277 are 8µs sampling 12-bit A/D
converters which draw only 2mA (typ) from single 5V or
±5V supplies. These easy-to-use devices come complete
with a 2µs sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conversion
modes add to the flexibility of the ADCs.
Two power-down modes are available in the LTC1277. In
Nap mode, the LTC1277 draws only 180µA and the instant
wake-up from Nap mode allows the LTC1277 to be pow-
ered down even during brief inactive periods. In Sleep
mode only 1µA will be drawn. A REFRDY signal is used to
show the ADC is ready to sample after waking up from
Sleep mode. The LTC1274 also provides the Sleep mode
and REFRDY signal.
The A/D converters convert 0V to 4.096V unipolar inputs
from a single 5V supply or ±2.048V bipolar inputs from
±5V supplies.
The LTC1274 has a single-ended input and a 12-bit
parallel data format. The LTC1277 offers a differential
input and a 2-byte read format. The bipolar mode is
formatted as 2’s complement for the LTC1274 and offset
binary for the LTC1277.
■
Low Power Dissipation: 10mW
■
Sample Rate: 100ksps
■
Samples Inputs Beyond Nyquist, 72dB S/(N + D)
and 82dB THD at f
IN
= 100kHz
■
Single Supply 5V or ±5V Operation
■
Power Shutdown to 1µA in Sleep Mode
■
180µA Nap Mode (LTC1277) with Instant Wake-Up
■
Internal Reference Can Be Overdriven
■
Internal Synchronized Clock
■
0V to 4.096V or ±2.048V Input Ranges (1mV/LSB)
■
24-Lead SO Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
Supply Current vs Sample Rate with
Sleep and Nap Modes
SAMPLE RATE (Hz)
SUPPLY CURRENT (µA)
10000
1000
100
10
1
0.1 1k 100k
LTC1274/77 • TA02
101 10k100
WITHOUT SLEEP OR NAP
NAP = 5V
(SLEEP MODE)
NAP = REFRDY
(SLEEP MODE)
NAP MODE
C
REF
= 4.7µF
U
S
A
O
PPLICATI
■
Battery-Powered Portable Systems
■
High Speed Data Acquisition for PCs
■
Digital Signal Processing
■
Multiplexed Data Acquisition Systems
■
Audio and Telecom Processing
■
Spectrum Analysis
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A
IN+
A
IN–
V
REF
AGND
REFRDY
SLEEP
NAP
D7
D6
D5
D4
DGND
V
DD
V
SS
BUSY
CS
RD
CONVST
HBEN
V
LOGIC
D0/8
D1/9
D2/10
D3/11
LTC1277
0.1µF
+
10µF
ANALOG
DIFFERENTIAL INPUTS
(0V TO 4.096V)
2.42V
V
REF
OUTPUT
10µF0.1µF
5V
8-BIT
PARALLEL
BUS
µP
CONTROL
LINES
OPTIONAL 3V SUPPLY
TO INTERFACE WITH 3V
PROCESSOR
LTC1274/77 • TA01
+
Single 5V Supply, 10mW, 100kHz, 12-Bit ADC
2
LTC1274/LTC1277
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................ 7V
Negative Supply Voltage (V
SS
)
Bipolar Operation Only .......................... – 6V to GND
Total Supply Voltage (V
DD
to V
SS
)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation ................... – 0.3V to V
DD
+ 0.3V
Bipolar Operation............... V
SS
– 0.3V to V
DD
+ 0.3V
Digital Input Voltage (Note 4)
Unipolar Operation .............................. – 0.3V to 12V
Bipolar Operation.......................... V
SS
– 0.3V to 12V
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER
PART NUMBER
LTC1274CSW
LTC1274ISW
ORDER
PART NUMBER
LTC1277CSW
LTC1277ISW
Digital Output Voltage
Unipolar Operation ................... – 0.3V to V
DD
+ 0.3V
Bipolar Operation...................... – 0.3V to V
DD
+ 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
T
JMAX
= 110°C, θ
JA
= 130°C/W
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
A
IN
V
REF
AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
V
DD
V
SS
BUSY
CS
RD
CONVST
SLEEP
REFRDY
D0
D1
D2
D3
SW PACKAGE
24-LEAD PLASTIC SO WIDE
T
JMAX
= 110°C, θ
JA
= 130°C/W
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
A
IN+
A
IN–
V
REF
AGND
REFRDY
SLEEP
NAP
D7
D6
D5
D4
DGND
V
DD
V
SS
BUSY
CS
RD
CONVST
HBEN
V
LOGIC
D0/8
D1/9
D2/10
D3/11
(D11 = MSB)
SW PACKAGE
24-LEAD PLASTIC SO WIDE
Consult factory for Military grade parts.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●12 Bits
Integral Linearity Error (Note 7) ●±1 LSB
Differential Linearity Error ●±1 LSB
Unipolar Offset Error ±6 LSB
●±8 LSB
Bipolar Offset Error (Note 8) ±8 LSB
●±10 LSB
Gain Error ±20 LSB
Gain Error Tempco I
OUT(REF)
= 0 ●±10 ±45 ppm/°C
CCHARA TERISTICS
CO
U
VERTER
With Internal Reference (Notes 5, 6)
3
LTC1274/LTC1277
(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (Note 10) 4.75V ≤ V
DD
≤ 5.25V (Unipolar) ●0 to 4.096 V
4.75V ≤ V
DD
≤ 5.25V, –5.25V ≤ V
SS
≤ –2.45V (Bipolar) ●±2.048 V
I
IN
Analog Input Leakage Current CS = High ●±1µA
C
IN
Analog Input Capacitance Between Conversions (Sample Mode) 45 pF
During Conversions (Hold Mode) 5 pF
PUT
U
IA
A
U
LOG
ACCURACY
IC
DY
U
W
A
(Notes 5, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-Noise 50kHz Input Signal 73 dB
Plus Distortion Ratio 100kHz Input Signal ●70 72.5 dB
THD Total Harmonic Distortion 50kHz Input Signal – 84 dB
Up to 5th Harmonic 100kHz Input Signal ●–82 –76 dB
Peak Harmonic or 50kHz Input Signal – 84 dB
Spurious Noise 100kHz Input Signal ●–82 –76 dB
IMD Intermodulation Distortion fa = 96.95kHz, fb = 97.68kHz 2nd Order Terms – 78 dB
3rd Order Terms – 81 dB
Full Power Bandwidth 2 MHz
Full Linear Bandwidth 350 kHz
[S/(N + D) ≥ 68dB]
I TER AL REFERE CE CHARACTERISTICS
UUU
(Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0 2.400 2.420 2.440 V
V
REF
Output Tempco I
OUT
= 0 ●±10 ±45 ppm/°C
V
REF
Line Regulation 4.75V ≤ V
DD
≤ 5.25V 0.01 LSB/V
–5.25V ≤ V
SS
≤ –4.75V 0.01 LSB/V
V
REF
Load Regulation –5mA ≤ I
OUT
≤ 70µA 2 LSB/mA
(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 5pF
V
OH
High Level Output Voltage, All Logic Outputs V
DD
= 4.75V
I
O
= – 10µA 4.70 V
I
O
= –200µA●4.0 V
V
LOGIC
= 2.7V (LTC1277)
I
O
= – 10µA 2.65 V
I
O
= –200µA 2.60 V
V
OL
Low Level Output Voltage, V
DD
= 4.75V
All Logic Outputs I
O
= 160µA 0.05 V
I
O
= 1.6mA ●0.10 0.4 V
V
LOGIC
=2.7V (LTC1277)
I
O
= 160µA 0.05 V
I
O
= 1.6mA 0.10 V
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
4
LTC1274/LTC1277
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
OZ
High-Z Output Leakage D11 to D0/8 V
OUT
= 0V to V
DD
, CS High ●±10 µA
C
OZ
High-Z Output Capacitance D11 to D0/8 CS High (Note 10) ●15 pF
I
SOURCE
Output Source Current V
OUT
= 0V –10 mA
I
SINK
Output Sink Current V
OUT
= V
DD
10 mA
(Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
(Note 5)
POWER REQUIRE E TS
WU
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage (Notes 11, 12) Unipolar and Bipolar Mode 4.75 5.25 V
V
LOGIC
Logic Supply (Notes 11,12) Unipolar and Bipolar Mode (LTC1277) 2.7 to 5.25 V
V
SS
Negative Supply Voltage (Note 11) Bipolar Mode Only – 2.45 – 5.25 V
I
DD
Positive Supply Current f
SAMPLE
= 100ksps ●24 mA
NAP = 0V (LTC1277 Only) ●180 320 µA
SLEEP = 0V ●0.3 5 µA
I
SS
Negative Supply Current f
SAMPLE
= 100ksps, Bipolar Mode Only ●40 70 µA
SLEEP = 0V ●0.3 5 µA
P
DISS
Power Dissipation f
SAMPLE
= 100ksps ●10 20 mW
NAP = 0V (LTC1277 Only) ●0.9 1.8 mW
SLEEP = 0V (Unipolar/Bipolar) ●25/50 µW
(Note 5) See Figures 13 to 17.
TI I G CHARACTERISTICS
WU
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency (Note 11) ●100 ksps
t
CONV
Conversion Time ●68 µs
t
ACQ
Acquisition Time ●0.35 2 µs
t
1
CS↓ to RD↓ Setup Time (Note 10) ●0ns
t
2
CS↓ to CONVST↓ Setup Time (Note 10) ●30 ns
t
3
NAP↑ to CONVST↓ Wake-Up Time (LTC1277 Only) (Note 11) 620 ns
t
4
CONVST Low Time (Note 13) ●40 ns
t
5
CONVST↓ to BUSY↓ Delay C
L
= 100pF ●70 150 ns
t
6
Data Ready Before BUSY↑C
L
= 100pF ●20 65 ns
t
7
Delay Between Conversions (Note 11) ●0.35 2 µs
t
8
Wait Time RD↓ After BUSY↑(Note 10) ●–20 ns
t
9
Data Access Time After RD↓C
L
= 20pF (Note 10) 50 110 ns
●140 ns
C
L
= 100pF 65 125 ns
●170 ns
t
10
Bus Relinquish Time C
L
= 100pF 20 60 90 ns
●20 100 ns
t
11
RD Low Time (Note 10) ●t
9
ns
t
12
CONVST High Time (Notes 10, 13) ●40 ns
t
13
Aperture Delay of Sample-and-Hold 35 ns
t
14
SLEEP↑ to REFRDY↑ Wake-Up Time 10µF Bypass at V
REF
Pin 4.2 ms
4.7µF Bypass at V
REF
Pin 3.3 ms
t
15
HBEN↑ to High Byte Data Valid C
L
= 100pF (LTC1277 Only) ●35 100 ns
5
LTC1274/LTC1277
(Note 5) See Figures 13 to 17.
TI I G CHARACTERISTICS
WU
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
16
HBEN↓ to Low Byte Data Valid C
L
= 100pF (LTC1277 Only) ●45 100 ns
t
17
HBEN↑ to RD↓ Setup Time (Note 10) (LTC1277 Only) ●10 ns
t
18
RD↑ to HBEN↓ Setup Time (Note 10) (LTC1277 Only) ●10 ns
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together and V
LOGIC
is tied to V
DD
in LTC1277 (unless
otherwise noted).
Note 3: When these pin voltages are taken below V
SS
(ground for unipolar
mode) or above V
DD
, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below V
SS
(ground for
unipolar mode) or above V
DD
without latch-up.
Note 4: When these pin voltages are taken below V
SS
(ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below V
SS
(ground for unipolar mode)
without latch-up. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V (V
SS
= –5V for bipolar mode), V
LOGIC
= V
DD
(LTC1277),
f
SAMPLE
= 100ksps, t
r
= t
f
= 5ns unless otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: For LTC1274, bipolar offset is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 and
1111 1111 1111. For LTC1277, bipolar offset voltage is measured from
–0.5LSB when the output code flickers between 0111 1111 1111 and
1000 0000 0000.
Note 9: The AC tests apply to bipolar mode only and the S/(N + D) is 71dB
(typ) for unipolar mode at 100kHz input frequency.
Note 10: Guaranteed by design, not subject to test.
Note 11: Recommended operating conditions.
Note 12: A
IN
must not exceed V
DD
or fall below V
SS
by more than 50mV to
specified accuracy.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 400ns after conversion start (i.e., before the first bit decision) or
after BUSY rises (i.e., after the last bit test). See timing diagrams Modes
1a and 1b (Figures 13, 14).
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Integral Nonlinearity vs
Output Code
OUTPUT CODE
0
–1.00
INTEGRAL NONLINEARITY ERROR (LSB)
–0.50
0
0.50
1.00
512 1024 1536 2048
LT1274/77 • TPC01
2560 3072 3584 4096
f
SAMPLE
= 100kHz
INPUT FREQUENCY (Hz)
10k
EFFECTIVE NUMBER OF BITS (ENOBs)
12
11
10
9
8
7
6
5
4
3
2
1
0
S/(N + D)(dB)
74
68
62
56
50
100k 1M 2M
LTC1274/77 • TPC03
fSAMPLE = 100kHz
NYQUIST
FREQUENCY
OUTPUT CODE
0
–1.00
DIFFERENTIAL NONLINEARITY ERROR (LSB)
–0.50
0
0.50
1.00
512 1024 1536 2048
LT1274/77 • TPC02
2560 3072 3584 4096
f
SAMPLE
= 100kHz
Differential Nonlinearity vs
Output Code
ENOBs and S/(N + D) vs
Input Frequency
6
LTC1274/LTC1277
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
INPUT FREQUENCY (Hz)
10k
SIGNAL/(NOISE + DISTORTION)(dB)
100k 2M1M
LTC1274/77 • TPC04
80
70
60
50
40
30
20
10
0
V
IN
= –60dB
V
IN
= –20dB
V
IN
= 0dB
f
SAMPLE
= 100kHz
INPUT FREQUENCY (Hz)
10k
SIGNAL-TO-NOISE RATIO (dB)
100k 2M1M
LTC1274/77 • TPC05
80
70
60
50
40
30
20
10
0
f
SAMPLE
= 100kHz
Distortion vs Input Frequency
THD
INPUT FREQUENCY (Hz)
10k
DISTORTION (dB)
0
–20
–40
–60
–80
–100
–120
100k 1M 2M
LTC1274/77 • TPC06
3RD HARMONIC
2ND HARMONIC
f
SAMPLE
= 100kHz
INPUT FREQUENCY (Hz)
10k
SPURIOUS-FREE DYNAMIC RANGE (dB)
100k 2M1M
LTC1274/77 • TPC07
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
SAMPLE
= 100kHz
Spurious-Free Dynamic Range vs
Input Frequency Intermodulation Distortion Plot
S/(N + D) vs Input Frequency
and Amplitude
FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10 20 30 40
LTC1274/77 • TPC08
50
fb – fa
2fb – fa
2fa – fb
2fa
2fb
3fb
fa + 2fb
3fa 2fa
– fb
f
SAMPLE
= 100kHz
fa = 9.54kHz
fb = 9.79kHz
fb – fa
SOURCE RESISTANCE (Ω)
10
ACQUISITION TIME (µs)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100 1k 10k
LTC1274/75 • TPC10
T
A
= 25°C
Acquistion Time vs
Source Impedance
Intermodulation Distortion Plot
FREQUENCY (Hz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10k 20k 30k 40k
LTC1274/77 • TPC09
50k
2fb – fa
fb
fa
fb – fa
2fb
2fa – fb
2fa
3fb
2fb + fa
2fa + fb
fa + fb
3fa
fSAMPLE = 100kHz
fa = 96.948kHz
fb = 97.681kHz
7
LTC1274/LTC1277
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Reference Voltage vs
Load Current
LOAD CURRENT (mA)
–6
REFERENCE VOLTAGE (V)
2.435
2.430
2.425
2.420
2.415
2.410
2.405 –3 –1
LT1274/77 • TPC13
–5 –4 –2 0 1
Supply Current vs Temperature
TEMPERATURE (°C)
–55
SUPPLY CURRENT (mA)
3.0
2.5
2.0
1.5
1.0
0.5
025 75
LT1274/77 • TPC11
–25 0 50 100 125
fSAMPLE = 100kHz
Power Supply Feedthrough vs
Ripple Frequency
RIPPLE FREQUENCY (kHz)
1
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
10 100 1000
LTC1274/77 • TPC12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
fSAMPLE = 100kHz
AVDD (VRIPPLE = 1mV)
VSS (VRIPPLE = 10mV)
DGND (VRIPPLE = 0.1V)
Supply Current vs Sample Rate
With Sleep and Nap Modes
SAMPLE RATE (Hz)
SUPPLY CURRENT (µA)
10000
1000
100
10
1
0.1 1k 100k
LTC1274/77 • TPC15
101 10k100
WITHOUT SLEEP OR NAP
NAP = 5V
(SLEEP MODE)
NAP = REFRDY
(SLEEP MODE)
NAP MODE
CREF = 4.7µF
Wake-Up Time vs
CREF (Sleep Mode)
Supply Current vs
Supply Voltage
C
REF
(µF)
0
WAKE-UP TIME (ms)
10
9
8
7
6
5
4
3
2
1
040
LTC1274/77 • TPC16
10515253545
20 30 50
T
A
= 25°C
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
3.0
2.5
2.0
1.5
1.0
0.5
0
1234
LTC1274/77 • TPC14
56
fSAMPLE = 100kHz
PI FU CTIO S
UU U
LTC1274
A
IN
(Pin 1): Analog Input. 0V to 4.096V, unipolar (V
SS
=
0V) or ±2.048V, bipolar (V
SS
= –5V).
V
REF
(Pin 2): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic). V
REF
can be
overdriven positive with an external reference voltage.
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 4 to 11): Three-State Data Outputs. D11
is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
REFRDY (Pin 17): Reference Ready Signal. It goes high
when the reference has settled after SLEEP indicating that
the ADC is ready to sample.
SLEEP (Pin 18): SLEEP Mode Input. Tie this pin to low to
put the ADC in Sleep mode and save power (REFRDY will
go low). The device will draw 1µA in this mode.
CONVST (Pin 19): Conversion Start Signal. This active low
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be low.)
8
LTC1274/LTC1277
PI FU CTIO S
UU U
*The LTC1277 bipolar mode is in offset binary.
RD (Pin 20): Read Input. This enables the output drivers
when CS is low.
CS (Pin 21): The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 21): The BUSY output shows the converter
status. It is low when a conversion is in progress. The
rising Busy edge can be used to latch the conversion
result.
V
SS
(Pin 23): Negative 5V Supply. Negative 5V will select
bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
this pin to analog ground to select unipolar operation.
V
DD
(Pin 24): Positive 5V Supply. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
LTC1277
A
IN+
(Pin 1): Positive Analog Input. (A
IN+
– A
IN–
) = 0V to
4.096V, unipolar (V
SS
= 0V) or ±2.048V, bipolar (V
SS
= – 5V).
A
IN–
(Pin 2): Negative Analog Input. This pin needs to be
free of noise during conversion. For single-ended inputs
tie A
IN–
to analog ground.
V
REF
(Pin 3): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic). V
REF
can be
overdriven positive with an external reference voltage.
AGND (Pin 4): Analog Ground.
REFRDY (Pin 5): Reference Ready Signal. It goes high
when the reference has settled after SLEEP indicating that
the ADC is ready to sample.
SLEEP (Pin 6): SLEEP Mode Input. Tie this pin to low to put
the ADC in Sleep mode and save power (REFRDY will go
LOW). The device will draw 1µA in this mode.
NAP (Pin 7): NAP Mode Input. Pulling this pin low will shut
down all currents in the ADC except the reference. In this
mode the ADC draws 180µA. Wake-up from Nap mode is
about 620ns.
D7 to D4* (Pins 8 to 11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11 to D0/8* (Pins 13 to 16): Three-State Data Outputs.
D11 is the Most Significant Bit.
V
LOGIC
(Pin 17): 5V or 3V Digital Power Supply. This pin
allows a 5V or 3V logic interface with the processor. All
logic outputs (Data Bits, BUSY and REFRDY) will swing
between 0V and V
LOGIC
.
HBEN (Pin 18): High Byte Enable Input. The four Most
Significant Bits will appear at Pins 13 to 16 when this pin
is high. The LTC1277 uses straight binary for unipolar
mode and offset binary for bipolar mode.
CONVST (Pin 19): Conversion Start Signal. This active low
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be low).
RD (Pin 20): Read Input. This enables the output drivers
when CS is low.
CS (Pin 21): The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is low when a conversion is in progress.
V
SS
(Pin 23): Negative 5V Supply. Negative 5V will select
bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
this pin to analog ground to select unipolar operation.
V
DD
(Pin 24): 5V Positive Supply. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
Table 1. LTC1277 Two-Byte Read Data Bus Status
DATA
OUTPUTS D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
Low Byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
High Byte Low Low Low Low DB11 DB10 DB9 DB8
9
LTC1274/LTC1277
BLOCK DIAGRA S
W
LTC1274
12-BIT CAPACITIVE DAC
COMPARATOR
C
SAMPLE
•
•
•
D11
D0
BUSY
CONTROL LOGIC
CSCONVST RD
INTERNAL
CLOCK
SLEEP
ZEROING SWITCHES V
SS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
V
DD
A
IN
V
REF
REFRDY
AGND
DGND
12
LTC1274 • BD
SUCCESSIVE APPROXIMATION
REGISTER OUTPUT LATCHES
2.42V REF
LTC1277
12-BIT CAPACITIVE DAC
COMPARATOR
C
SAMPLE
•
•
•
•
•
D7
D1/9
D0/8
BUSY V
LOGIC
3V OR 5V
CONTROL LOGIC
CSCONVST RD
INTERNAL
CLOCK
SLEEPHBEN NAP
ZEROING SWITCHES V
SS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
V
DD
A
IN–
A
IN+
V
REF
REFRDY
AGND
DGND
12
LTC1277 • BD
SUCCESSIVE APPROXIMATION
REGISTER OUTPUT LATCHES
2.42V REF
TEST CIRCUITS
Load Circuits for Output Float DelayLoad Circuits for Access Timing
3k C
L
DBN
DGND
A) HIGH-Z TO V
OH
(t
9
)
AND V
OL
TO V
OH
(t
6
)
C
L
DBN
3k
5V
B) HIGH-Z TO V
OL
(t
9
)
AND V
OH
TO V
OL
(t
6
)
DGND
1274/77 • TC01
3k 10pF
DBN
DGND
A) VOH TO HIGH-Z
10pF
DBN
3k
5V
B) VOL TO HIGH-Z
DGND
1274/77 • TC02
10
LTC1274/LTC1277
TI I G DIAGRA S
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CS to RD Setup Timing CS to CONVST Setup Timing
t
1
CS
RD
LTC1274/77 • TD01
t
2
CS
CONVST
LTC1274/77 • TD02
NAP to CONVST Wake-Up Timing (LTC1277) SLEEP to REFRDY Wake-Up Timing
t
3
NAP
CONVST
LTC1274/77 • TD03
t
14
SLEEP
REFRDY
LTC1274/77 • TD04
APPLICATIONS INFORMATION
WUUU
CONVERSION DETAILS
The LTC1274/LTC1277 use a successive approximation
algorithm and an internal sample-and-hold circuit to con-
vert an analog signal to a 12-bit parallel output. The ADCs
are complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC out-
put is sequenced by the SAR from the most significant bit
(MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
(LTC1274) or A
IN+
(LTC1277) input con-
nects to the sample-and-hold capacitor during the acquire
phase, and the comparator offset is nulled by the feedback
switch. In this acquire phase, a minimum delay of 2µs will
provide enough time for the sample-and-hold capacitor to
acquire the analog signal. During the convert phase, the
comparator feedback switch opens, putting the comparator
into the compare mode. The input switch connects C
SAMPLE
to ground (LTC1274) or A
IN–
(LTC1277), injecting the
analog input charge onto the summing junction. This input
charge is successively compared with the binary-weighted
charges supplied by the capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the DAC output balances the A
IN
(LTC1274) or
A
IN+
– A
IN–
(LTC1277) input charge. The SAR contents (a 12-
bit data word) which represent the A
IN
(LTC1274) or
A
IN+
– A
IN–
(LTC1277) are loaded into the 12-bit output latches.
V
DAC
1274 • F01
+
–
CDAC
DAC
SAMPLE
HOLD
CSAMPLE
S
A
R
12-BIT
LATCH
COMPAR-
ATOR
SAMPLE
SI
AIN
Figure 1. LTC1274 AIN Input
DYNAMIC PERFORMANCE
The LTC1274/LTC1277 have excellent high speed sam-
pling capability. FFT (Fast Fourier Transform) test tech-
niques are used to test the ADCs’ frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
11
LTC1274/LTC1277
APPLICATIONS INFORMATION
WUUU
using an FFT algorithm, the ADCs’ spectral content can be
examined for frequencies outside the fundamental. Figures
2a and 2b show typical LTC1274 FFT plots.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is band
limited to frequencies above DC and below half the sam-
pling frequency. Figure 2a shows a typical spectral content
with a 100kHz sampling rate and a 48.85kHz input. The
dynamic performance is excellent for input frequencies well
beyond Nyquist as shown in Figure 2b and Figure 3.
INPUT FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10 20 30 40
LTC1274/77 • F02a
50
f
SAMPLE
= 100kHz
f
IN
= 48.85kHz
Figure 2a. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 50kHz Input Frequency
INPUT FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10 20 30 40
LTC1274/77 • F02b
50
f
SAMPLE
= 100kHz
f
IN
= 97.68kHz
Figure 2b. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 100kHz Input Frequency
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 100kHz, the LTC1274/LTC1277 maintain very
good ENOBs over 300kHz. Refer to Figure 3.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamen-
tal itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling
frequency. THD is expressed as:
THD = 20log√V22 + V32 + V42 ... + VN2
V1
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics. THD versus input fre-
INPUT FREQUENCY (Hz)
10k
EFFECTIVE NUMBER OF BITS (ENOBs)
12
11
10
9
8
7
6
5
4
3
2
1
0
S/(N + D)(dB)
74
68
62
56
50
100k 1M 2M
LTC1274/77 • F03
fSAMPLE = 100kHz
NYQUIST
FREQUENCY
Figure 3. ENOBs and S/(N + D) vs Input Frequency
12
LTC1274/LTC1277
APPLICATIONS INFORMATION
WUUU
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1274/LTC1277 have been designed to optimize input
bandwidth, allowing ADCs to undersample input signals
with frequencies above the converter’s Nyquist frequency.
The noise floor stays very low at high frequencies;
S/(N + D) becomes dominated by distortion at frequencies
far beyond Nyquist.
Driving the Analog Input
The analog input of the LTC1274/LTC1277 is easy to
drive. It draws only one small current spike while charg-
ing the sample-and-hold capacitor at the end of conver-
sion. During conversion the analog input draws only a
small leakage current. The only requirement is that the
amplifier driving the analog input must settle after the
small current spike before the next conversion starts.
Any op amp that settles in 2µs to small current transients
will allow maximum speed operation. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions. Suitable devices capable of
driving the ADC A
IN
input include the LT
®
1006, LT1007,
LT1220, LT1223 and LT1224 op amps.
quency is shown in Figure 4. The ADCs have good distor-
tion performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can pro-
duce intermodulation distortion (IMD) in addition to THD.
IMD is the change in one sinusoidal input caused by the
presence of another sinusoidal input at a different frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of the
2nd order IMD products can be expressed by the following
formula:
IMD (fa ± fb) = 20log Amplitude at (fa ± fb)
Amplitude at fa
Figure 5 shows the IMD performance at a 97kHz input.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.
Figure 4. Distortion vs Input Frequency Figure 5. Intermodulation Distortion
FREQUENCY (Hz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10k 20k 30k 40k
LTC1274/77 • F05
50k
2fb – fa
fb
fa
fb – fa
2fb
2fa – fb
2fa
3fb
2fb + fa
2fa + fb
fa + fb
3fa
f
SAMPLE
= 100kHz
fa = 96.948kHz
fb = 97.681kHz
THD
INPUT FREQUENCY (Hz)
10k
DISTORTION (dB)
0
–20
–40
–60
–80
–100
–120
100k 1M 2M
LTC1274/77 • F04
3RD HARMONIC
2ND HARMONIC
fSAMPLE = 100kHz
13
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3V to keep the input span within the 5V supply in unipolar
mode. In bipolar mode the reference should be driven to
no more than 5V, the positive supply voltage of the chip.
Figure 6 shows an LT1006 op amp driving the Reference
pin. In unipolar mode, the reference can be driven up to
2.95V at which point it will provide a 0V to 5V input span.
For the bipolar mode, the reference can be driven up to 5V
at which point it will provide a ±4.23V input span. Figure
7 shows a typical reference, the LT1019A-2.5 connected
to the LTC1274. This will provide an improved drift (equal
to the maximum 5ppm/°C of the LT1019A-2.5) and a
±2.115V (bipolar) or 4.231V (unipolar) full scale.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1274/LTC1277, a printed cir-
cuit board is required. Layout for the printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC. The analog input
should be screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the V
DD
and V
REF
pins as shown in
LTC1277 A
IN+
/A
IN–
Input Settling
The input capacitor for the LTC1277 is switched onto the
A
IN+
input during the sample phase. The voltage on the
A
IN+
input must settle completely within the sample
period. At the end of the sample phase the input capacitor
switches to the A
IN–
input and the conversion starts.
During the conversion the A
IN+
input voltage is effec-
tively “held” by the sample-and-hold and will not affect
the conversion result. It is critical that the A
IN–
input
voltage be free of noise and settles completely during the
conversion.
Internal Reference
The ADCs have an on-chip, temperature compensated,
curvature corrected bandgap reference which is factory
trimmed to 2.42V. It is internally connected to the DAC and
is available at Pin 2 (LTC1274) or Pin 3 (LTC1277) to
provide up to 1mA current to an external load.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with a
0.1µF ceramic).
The V
REF
pin can be driven with a DAC or other means to
provide input span adjustment. The V
REF
pin must be
driven to at least 2.45V to prevent conflict with the internal
reference. The reference should be driven to no more than
Figure 6. Driving the VREF with the LT1006 Op Amp
VREF(OUT) ≥ 2.45V
3Ω
INPUT RANGE:
±0.846VREF(OUT)
IN BIPOLAR MODE
0 TO 1.69VREF(OUT) IN
UNIPOLAR MODE
5V
–
+
LT1006
LTC1274
AIN
AGND
VREF
10µF
LTC1274/77 • F06
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1274 with the LT1019A-2.5
3Ω
INPUT RANGE:
±2.115V (±0.846 × V
REF
)
IN BIPOLAR AND
0V TO 4.231V (1.69V
REF(OUT)
)
IN UNIPOLAR MODE LTC1274
A
IN
AGND
V
REF
10µF
LTC1274/77 • F07
LT1019A-2.5
V
IN
GND
V
OUT
5V
5V
14
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Figure 8. For bipolar mode, a 0.1µF ceramic provides
adequate bypassing for the V
SS
pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
Input signal leads to A
IN
and signal return leads from
AGND (Pin 3 for LTC1274, Pin 4 for LTC1277) should be
kept as short as possible to minimize input noise cou-
pling. In applications where this is not possible a shielded
cable between source and ADC is recommended.
Also, since any potential difference in grounds between
the signal source and the ADC appears as an error voltage
in series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at AGND or as close as possible to the ADC.
DGND (Pin 12) and all other analog grounds should be
connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continu-
ously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be elimi-
nated by forcing the microprocessor into a Wait state
during conversion or by using three-state buffers to
isolate the ADC data bus. Figure 9 is a typical application
circuit for the LTC1274.
Figure 8. Power Supply Grounding Practice
Figure 9. LTC1274 Typical Circuit
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AIN
VREF
AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
VDD
VSS
BUSY
CS
RD
CONVST
SLEEP
REFRDY
D0
D1
D2
D3
LTC1274
0.1µF
+
10µF
ANALOG INPUT
(0V TO 4.095V)
2.42V
VREF OUTPUT 10µF0.1µF
5V
12-BIT
PARALLEL
BUS
µP
CONTROL
LINES
CONVERSION START INPUT
SLEEP MODE INPUT
REFERENCE READY SIGNAL
LTC1274/77 • F09
+
LTC1274/77 • F08
A
IN
AGND V
REF
AV
DD
DV
DD
DGND
LTC1274 DIGITAL
SYSTEM
0.1µF
+
–
ANALOG GROUND PLANE
GROUND CONNECTION
TO DIGITAL CIRCUITRY
ANALOG
INPUT
CIRCUITRY
3 2 24 17 12
1
0.1µF10µF10µF
15
LTC1274/LTC1277
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DIGITAL INTERFACE
The ADCs are designed to interface with microproces-
sors as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
A separate CONVST is used to initiate a conversion.
Figures 10a to 10c are the input/output characteristics of
the ADCs. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB…FS – 1.5LSV). The output code is scaled such
that 1.0LSB = FS/4096 = 4.096V/4096 = 1.0mV.
Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important, then
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 11b can be used. For zero
offset error, apply 0.50mV (i.e., 0.5LSB) at the input and
adjust the offset trim until the LTC1274/LTC1277 output
code flickers between 0000 0000 0000 and 0000 0000
0001. For zero full-scale error, apply an analog input of
4.0945V (i.e., FS – 1.5LSB or last code transition) at the
input and adjust R5 until the ADC output code flickers
between 1111 1111 1110 and 1111 1111 1111.
Bipolar Offset and Full-Scale Error Adjustments
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset must be
INPUT VOLTAGE (V)
0V
OUTPUT CODE
–1
LSB
LTC1274/77 • F10c
111...111
111...110
100...001
100...000
000...000
000...001
011...110
1
LSB
BIPOLAR
ZERO
011...111
FS/2 – 1LSB–FS/2
1LSB = = = 1mV
4.096V
4096
FS
4096
Figure 10c. LTC1277 Bipolar Transfer Characteristics
(Offset Binary)
Figure 10a. LTC1274/LTC1277 Unipolar
Transfer Characteristics
Figure 10b. LTC1274 Bipolar Transfer
Characteristics (2’s Complement)
INPUT VOLTAGE (V)
0V
OUTPUT CODE
FS – 1LSB
LTC1274/77 F10a
111...111
111...110
111...101
111...100
000...000
000...001
000...010
000...011
1
LSB
UNIPOLAR
ZERO
1LSB = FS
4096
4.096V
4096
= = 1mV
INPUT VOLTAGE (V)
0V
OUTPUT CODE
–1
LSB
LTC1274/77 • F10b
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
1LSB = = = 1mV
4.096V
4096
FS
4096
16
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LTC1274
LTC1277
A
IN
(LTC1274)
A
IN+
(LTC1277)
AGND
A
IN–
(LTC1277)
LTC1274/77 F11a
R4
100Ω
FULL-SCALE
ADJUST
R3
10k
R2
10k
R1
50Ω
V1
–
+
A1
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
LTC1274/77 F11b
R2
10k R4
100k
R1
10k
10k
5V
R9
20Ω
ANALOG
INPUT
0V TO
4.096V
R3
100k
5V
R8
10k
OFFSET
ADJUST
R6
400Ω
R5
4.3k
FULL-SCALE
ADJUST
R7
100k
–
+
LTC1274
LTC1277
AIN (LTC1274)
AIN
+
(LTC1277)
AIN
–
(LTC1277)
Figure 11a. Full-Scale Adjust Circuit
Figure 11b. LTC1274/LTC1277 Unipolar Offset and
Full-Scale Adjust Circuit
Figure 11c. LTC1274/LTC1277 Bipolar Offset and
Full-Scale Adjust Circuit
adjusted before full-scale error. Bipolar offset error ad-
justment is achieved by trimming the offset adjust while
the input voltage is 0.5LSB below ground. This is done by
applying an input voltage of –0.50mV (–0.5LSB) to the
input in Figure 11c and adjusting the R8 until the ADC’s
output code flickers between 0000 0000 0000 and 1111
1111 1111 in LTC1274 or between 0111 1111 1111 and
1000 0000 0000 in LTC1277. For full-scale adjustment, an
input voltage of 2.0465V (FS – 1.5LSBs) is applied to the
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111 in LTC1274
or between 1111 1111 1110 and 1111 1111 1111 in
LTC1277.
Internal Clock
The A/D converters have an internal clock that eliminates
the need of synchronization between the external clock
and the CS and RD signals found in other ADCs. The
internal clock is factory trimmed to achieve a typical
conversion time of 6µs. No external adjustments are
required and with the maximum acquisition time of 2µs
throughput performance of 100ksps is assured.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs in the LTC1274: CS, CONVST and
RD. For the LTC1277 there are four digital inputs: CS,
CONVST, RD and HBEN. Figure 12 shows the logic
structure associated with these inputs for LTC1277. A
falling edge on CONVST will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output and this
is low while conversion is in progress. The High Byte
Enable input (HBEN) in the LTC1277 is to multiplex the 12
bits of conversion data onto the lower D7 to D0/8
outputs.
Figures 13 through 17 show several different modes of
operation. In modes 1a and 1b (Figures 13 and 17) CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
LTC1274/77 F11c
R2
10k R4
100k
R1
10k
ANALOG
INPUT
R3
100k
5V
R8
20k
OFFSET
ADJUST
R6
200Ω
R5
4.3k
FULL-SCALE
ADJUST
R7
100k
–
+
–5V
LTC1274
LTC1277
A
IN
(LTC1274)
A
IN
+
(LTC1277)
A
IN
–
(LTC1277)
17
LTC1274/LTC1277
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the
previous conversion result. After the conversion is com-
plete, the processor can read the new result and initiate
another conversion.
The narrow logic pulse on CONVST ensures that CONVST
doesn’t return high during the conversion (see Note 13
following the Timing Characteristics table).
In Mode 2 (Figure 15) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
both are in three-state until read by the MPU with the RD
signal. Mode 2 can be used for operation with a shared
MPU databus.
In slow memory and ROM modes (Figures 16 and 17) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
DATA (N – 1)
DB11 TO DB0
DATA (N – 1)
DB7 TO DB0
CONVST
BUSY
LTC1274/77 • F13
t
16
t
15
t
4
t
5
t
6
CS = RD = 0
HBEN (LTC1277)
DATA N
DB11 TO DB0
DATA N
DB7 TO DB0
DATA N
DB11 TO DB8
DATA N
DB7 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA (N + 1)
DB7 TO DB0
LTC1274 DATA
LTC1277 DATA
t
7
t
CONV
(SAMPLE N) (SAMPLE N + 1)
(CONVST = )
Figure 13. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
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CONVERSION
START (RISING
EDGE TRIGGER)
1274/77 • F12
BUSY
FLIP
FLOP
CLEAR
QD
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
CS
RD
CONVST
NAP
SLEEP
Figure 12. Internal Logic for Control Inputs CS, RD, CONVST, NAP and SLEEP (LTC1277)
18
LTC1274/LTC1277
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Figure 15. Mode 2. CONVST Starts a Conversion. Data is Read by RD
CONVST
BUSY
RD
LTC1274/77 • F15
t
17
t
4
t
5
t
11
t
16
CS = 0
HBEN (LTC1277)
DATA N
DB11 TO DB0
DATA N
DB11 TO DB8
DATA N
DB7 TO DB0
LTC1274 DATA
LTC1277 DATA
t
8
t
9
t
CONV
t
12
(SAMPLE N) (SAMPLE N + 1)
t
10
t
7
Figure 14. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
DATA (N – 1)
DB11 TO DB0
CONVST
BUSY
LTC1274/77 • F14
t12
t16
t5t5
CS = RD = 0
HBEN (LTC1277)
DATA N
DB11 TO DB0
DATA (N – 1)
DB11 TO DB8
DATA (N – 1)
DB7 TO DB0
DATA N
DB7 TO DB0
DATA N
DB7 TO DB0
DATA (N + 1)
DB7 TO DB0
DATA N
DB11 TO DB8
DATA (N – 1)
DB7 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1274 DATA
LTC1277 DATA
t7
tCONV
(SAMPLE N)
t6
t15
(SAMPLE N + 1)
19
LTC1274/LTC1277
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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The LTC1277 has an additional Nap mode. When NAP
(Pin 7) is tied low, all the power is off except the internal
reference which is still active and provides 2.42V output
voltage to the other circuitry. In this mode the ADC draws
0.9mW instead of 10mW (for minimum power, the logic
inputs must be within 600mV from the supply rails). The
wake-up time from the power shutdown to active state is
620ns. The typical performance graph on the front page of
this data sheet shows that the power will be reduced
greatly by using the Sleep and Nap modes.
Power Shutdown
The LTC1274/LTC1277 provide shutdown features that
will save power when the ADC is in inactive periods. Both
ADCs have a Sleep mode. To power down the ADCs,
SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to
be driver low.
When in Sleep mode, the LTC1274/LTC1277
will not start a conversion even though the CONVST goes
low. The parts draw 1µA. After release from the Sleep
mode, the ADCs need 3ms (4.7µF bypass capacitor on
V
REF
pin) to wake up and a REFRDY signal will go to high
to indicate the ADC is ready to do conversions.
RD = CONVST
BUSY
LTC1274/77 • F16
t15
t18
CS = 0
HBEN (LTC1277)
DATA N
DB11 TO DB0
DATA N
DB7 TO DB0
DATA (N – 1)
DB7 TO DB0
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB8
LTC1274 DATA
LTC1277 DATA
t5
t9t6
t10
t7
(SAMPLE N)
DATA (N + 1)
DB7 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB8
(SAMPLE N + 1)
DATA (N + 1)
DB11 TO DB0
DATA N
DB11 TO DB0
tCONV
Figure 16. Slow Memory Mode
RD = CONVST
BUSY
LTC1274/77 • F17
t
15
CS = 0
HBEN (LTC1277)
DATA (N – 1)
DB11 TO DB0
DATA (N – 1)
DB7 TO DB0
DATA (N – 1)
DB11 TO DB8
LTC1274 DATA
LTC1277 DATA
t
5
t
18
t
9
t
10
t
7
(SAMPLE N)
DATA N
DB7 TO DB0
DATA N
DB11 TO DB8
(SAMPLE N + 1)
DATA N
DB11 TO DB0
t
CONV
Figure 17. ROM Mode Timing
20
LTC1274/LTC1277
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX
: (408) 434-0507
●
TELEX
: 499-3977
© LINEAR TECHNOLOGY CORPORATION 1995
LT/GP 1195 10K • PRINTED IN USA
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1272 12-Bit, 3µs, 250kHz Sampling A/D Converter Single 5V, Sampling 7572 Upgrade
LTC1273/75/76 12-Bit, 300ksps Sampling A/D Converters with Reference Complete with Clock, Reference
LTC1278 12-Bit, 500ksps Sampling A/D Converter with Shutdown 70dB SINAD at Nyquist, Low Power
LTC1279 12-Bit, 600ksps Sampling A/D Converter with Shutdown 70dB SINAD at Nyquist, Low Power
LTC1282 12-Bit, 140ksps Sampling A/D Converter with Reference 3V or ±3V ADC with Reference, Clock
LTC1409 12-Bit, 800ksps Sampling A/D Converter with Shutdown Fast, Complete Low Power ADC, 80mV
LTC1410 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown Fast, Complete Wideband ADC, 160mV
In the Sleep mode, the comparator of the ADC will start
consuming power after the rising edge of SLEEP as shown
in Figure 18a. If REFRDY is tied to NAP, the comparator will
be powered up after REFRDY’s rising edge. Hence more
power will be saved as in Figure 18b.
REFRDY
COMPARATOR
STATUS ON OFF ON
LTC1274/77 • F18a
SLEEP
3ms
(C
REF
= 4.7µF)
NAP = REFRDY
COMPARATOR
STATUS ON OFF ON
LTC1274/77 • F18b
SLEEP
3ms
(CREF = 4.7µF)
Figure 18a. Power Saved in Sleep Mode (NAP = HIGH) Figure 18b. Power Saved in Sleep Mode (NAP = REFRDY)
SW Package
24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
NOTE 1
0.598 – 0.614*
(15.190 – 15.600)
22 21 20 19 18 17 16 15
12345678
0.394 – 0.419
(10.007 – 10.643)
910
1314
11 12
2324
0.037 – 0.045
(0.940 – 1.143)
0.004 – 0.012
(0.102 – 0.305)
0.093 – 0.104
(2.362 – 2.642)
0.050
(1.270)
TYP 0.014 – 0.019
(0.356 – 0.482)
0° – 8° TYP
NOTE 1
0.009 – 0.013
(0.229 – 0.330)
0.016 – 0.050
(0.406 – 1.270)
0.291 – 0.299**
(7.391 – 7.595)
× 45°
0.010 – 0.029
(0.254 – 0.737)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
