10-Bit, 200 MSPS/250 MSPS
1.8 V Analog-to-Digital Converter
AD9601
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 59.4 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = 81 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
DNL = 0.2 LSB typical
INL = 0.2 LSB typical
CMOS outputs
Single data port at up to 250 MHz
Demultiplexed dual port at up to 2 × 125 MHz
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
274 mW @ 200 MSPS
322 mW @ 250 MSPS
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
AGNDPWDNRBIAS AVDD (1.8V)
VIN+
VIN–
CML
TRACK-AND-HOLD
REFERENCE
ADC
10-BIT
CORE
OUTPUT
STAGING
LVDS
CLK+
CLK–
CLOCK
MANAGEMENT
SERIAL PORT
RESET SCLK SDIO CSB
DCO–
DCO+
OVRB
OVRA
Dx9 TO Dx0
DRGND
DRVDD
10 10
AD9601
07100-001
Figure 1.
GENERAL DESCRIPTION
The AD9601 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary func-
tions, including a track-and-hold (T/H) and voltage reference,
are included on the chip to provide a complete signal
conversion solution.
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
CMOS compatible and support either twos complement, offset
binary format, or Gray code. A data clock output is available for
proper output data timing.
Fabricated on an advanced CMOS process, the AD9601 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 59.4 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 322 mW @ 250 MSPS.
3. Ease of Use—CMOS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, power-
down, gain adjust, and output test pattern generation.
5. Pin-Compatible Family—12-bit pin-compatible family
offered as the AD9626.
AD9601
Rev. 0 | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Equivalent Circuits......................................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 16
Analog Input and Voltage Reference ....................................... 16
Clock Input Considerations...................................................... 17
Power Dissipation and Power-Down Mode ........................... 18
Digital Outputs........................................................................... 18
Timing—Single Port Mode....................................................... 19
Timing—Interleaved Mode....................................................... 19
Layout Considerations................................................................... 20
Power and Ground Recommendations................................... 20
CML ............................................................................................. 20
RBIAS........................................................................................... 20
AD9601 Configuration Using the SPI..................................... 20
Hardware Interface..................................................................... 21
Configuration Without the SPI ................................................ 21
Memory Map .................................................................................. 23
Reading the Memory Map Table.............................................. 23
Reserved Locations .................................................................... 23
Default Values............................................................................. 23
Logic Levels................................................................................. 23
Evaluation Board ............................................................................ 25
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
11/07—Revision 0: Initial Version
AD9601
Rev. 0 | Page 3 of 32
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled,
unless otherwise noted.
Table 1.
AD9601-200 AD9601-250
Parameter1Temp Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error 25°C 4.0 4.0 mV
Full −12 +12 −12 +12 mV
Gain Error 25°C 1.4 1.4 % FS
Full −2.1 +4.5 −2.1 +4.5 % FS
Differential Nonlinearity (DNL) 25°C 0.2 0.2 LSB
Full −0.5 +0.5 −0.5 +0.5 LSB
Integral Nonlinearity (INL) 25°C 0.2 0.2 LSB
Full −0.5 +0.5 −0.5 +0.5 LSB
TEMPERATURE DRIFT
Offset Error Full 8 8 µV/°C
Gain Error Full 0.021 0.021 %/°C
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range2Full 0.98 1.25 1.5 0.98 1.25 1.5 V p-p
Input Common-Mode Voltage Full 1.4 1.4 V
Input Resistance (Differential) Full 4.3 4.3 kΩ
Input Capacitance 25°C 2 2 pF
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Currents
IAVDD 3Full 133 142 157 167 mA
IDRVDD3/Single Port Mode4Full 19 20 22 24 mA
IDRVDD3/Interleaved Mode5Full 16 18 mA
Power Dissipation3Full mW
Single Port Mode4Full 274 291 322 344 mW
Interleaved Mode5Full 268 315 mW
Power-Down Mode Supply Currents
IAVDD Full 40 40 µA
IDRVDD Full 170 170 22 µA
Standby Mode Supply Currents
IAVDD Full 19 19 mA
IDRVDD Full 170 170 22 µA
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.
4 Single data rate mode; this is the default mode of the AD9601.
5 Interleaved mode; user-programmable feature. See the Memory Map section.
AD9601
Rev. 0 | Page 4 of 32
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. 1
Table 2.
AD9601-200 AD9601-250
Parameter2 Temp Min Typ Max Min Typ Max Unit
SNR
fIN = 10 MHz 25°C 59.5 59.4 dB
Full 58.5 57.8 dB
fIN = 70 MHz 25°C 59.3 59.4 dB
SINAD
fIN = 10 MHz 25°C 59.5 59.4 dB
Full 58.5 57.7 dB
fIN = 70 MHz 25°C 59.3 59.4 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25°C 9.6 9.7 Bits
fIN = 70 MHz 25°C 9.6 9.7 Bits
WORST HARMONIC (SECOND OR THIRD)
fIN = 10 MHz 25°C 84 84 dBc
Full 77 72 dBc
fIN = 70 MHz 25°C 78 81 dBc
WORST OTHER (SFDR EXCLUDING SECOND AND THIRD)
fIN = 10 MHz 25°C 88 86 dBc
Full 80 75 dBc
fIN = 70 MHz 25°C 87 85 dBc
TWO-TONE IMD
170.2 MHz/171.3 MHz @ −7 dBFS 25°C 81 81 dBFS
ANALOG INPUT BANDWIDTH 25°C 700 700 MHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
AD9601
Rev. 0 | Page 5 of 32
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
AD9601-200 AD9601-250
Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK INPUTS
Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 1.2 1.2 V
Differential Input Voltage Full 0.2 6 0.2 6 V p-p
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V
Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD V
High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 V
Input Resistance (Differential) Full 16 20 24 16 20 24 kΩ
Input Capacitance Full 4 4 pF
LOGIC INPUTS
Logic 1 Voltage Full 0.8 × VDD 0.8 × VDD V
Logic 0 Voltage Full 0.2 × AVDD 0.2 × AVDD V
Logic 1 Input Current (SDIO) Full 0 0 µA
Logic 0 Input Current (SDIO) Full −60 −60 µA
Logic 1 Input Current
(SCLK, PDWN, CSB, RESET)
Full 55 50 µA
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Full 0 0 µA
Input Capacitance 25°C 4 4 pF
LOGIC OUTPUTS
High Level Output Voltage Full DRVDD − 0.05 DRVDD − 0.05 V
Low Level Output Voltage Full GND + 0.05 GND + 0.05 V
Output Coding Twos complement, Gray code, or offset binary (default)
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
AD9601
Rev. 0 | Page 6 of 32
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4.
AD9601-200 AD9601-250
Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 200 250
MSPS
Minimum Conversion Rate Full
40
40 MSPS
CLK+ Pulse Width High (tCH) Full 2.15 2.4 1.8 2.0 ns
CLK+ Pulse Width Low (tCL) Full 2.15 2.4 1.8 2.0 ns
Output, Single Data Port Mode1
Data Propagation Delay (tPD) 25°C 3.7 3.7 ns
DCO Propagation Delay (tCPD) 25°C 3.4 3.4 ns
Data to DCO Skew (tSKEW) Full 0 0.3 0.55 0 0.3 0.55 ns
Latency Full 6 6 Cycles
Output, Interleaved Mode2
Data Propagation Delay (tPDA, tPDB) 25°C 3.5 3.5 ns
DCO Propagation Delay (tCPDA, tCPDB) 25°C 3.0 3.0 ns
Data to DCO Skew (tSKEWA, tSKEWB ) Full 0 0.5 1.1 0 0.5 1.1 ns
Latency Full 6 6 Cycles
Standby Recovery 25°C 250 250 ns
Power-Down Recovery 50 50 µs
Aperture Delay (tA) 25°C 0.1 0.1 ns
Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms
1 See Figure 2.
2 See Figure 3.
AD9601
Rev. 0 | Page 7 of 32
TIMING DIAGRAMS
CLK+
DCO+
N
CLK–
DAX N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7
DCO–
N + 5 N + 6 N + 7
N + 8
N + 4
N + 3
N + 2
N + 1
t
A
t
PD
t
SKEW
t
CPD
t
CLK
= 1/
f
CLK
07100-042
Figure 2. Single Port Mode
CLK+
DCO–
N
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
N + 1
N + 2
N – 7
CLK–
DCO+
DAX
DBX
N + 1
N + 8
N + 7
N + 6
N + 5
N + 4
N + 3
N + 2
t
CPDA
t
SKEWB
t
PDB
t
CPDB
t
PDA
t
SKEWA
t
A
t
CLK
= 1/
f
CLK
07100-043
Figure 3. Interleaved Mode
AD9601
Rev. 0 | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
ELECTRICAL
AVDD to AGND −0.3 V to +2.0 V
DRVDD to DRGND −0.3 V to +2.0 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −2.0 V to +2.0 V
Dx0 Through Dx9 to DRGND −0.3 V to DRVDD + 0.3 V
DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V
OVRA/OVRB to DGND −0.3 V to DRVDD + 0.3 V
CLK+ to AGND −0.3 V to +3.6 V
CLK− to AGND −0.3 V to +3.6 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V
PDWN to AGND −0.3 V to +3.6 V
CSB to AGND −0.3 V to +3.6 V
SCLK/DFS to AGND −0.3 V to +3.6 V
ENVIRONMENTAL
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering, 10 sec)
300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 6.
Package Type θJA θJC Unit
56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, and through holes, ground, and power planes
reduces the θJA.
ESD CAUTION
AD9601
Rev. 0 | Page 9 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1DA4
2DA5
3DA6
4DA7
5DA8
6(MSB) DA9
7DRVDD
8DRGND
9OVRA
10NIC
11NIC
12(LSB) DB0
13DB1
14DB2
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
15
DB3
16
DB4
17
DB5
19
DB7
21
(MSB) DB9
20
DB8
22
OVRB
23
DRGND
24
DRVDD
25
SDIO/DCS
26
SCLK/DFS
27
CSB
28
RESET
18
DB6
45 CLK–
46 AVDD
47 DRVDD
48 DRGND
49 DCO–
50 DCO+
51 NIC
52 NIC
53 DA0 (LSB)
54 DA1
44 CLK+
43 AVDD
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9601
55 DA2
56 DA3
07100-002
Figure 4. Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No. Mnemonic Description
30, 32, 33, 34, 37, 38, 39,
41, 42, 43, 46
AVDD 1.8 V Analog Supply.
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
0 AGND1Analog Ground.
8, 23, 48 DRGND1Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 RBIAS
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)
Nominally 0.5 V.
28 RESET CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer
Select (External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
53 DA0 (LSB) Output Port A Output Bit 0 (LSB).
54 DA1 Output Port A Output Bit 1.
55 DA2 Output Port A Output Bit 2.
56 DA3 Output Port A Output Bit 3.
1 DA4 Output Port A Output Bit 4.
2 DA5 Output Port A Output Bit 5.
3 DA6 Output Port A Output Bit 6.
AD9601
Rev. 0 | Page 10 of 32
Pin No. Mnemonic Description
4 DA7 Output Port A Output Bit 7.
5 DA8 Output Port A Output Bit 8.
6 DA9 (MSB) Output Port A Output Bit 9 (MSB).
10, 11, 51, 52 NIC Not internally connected.
9 OVRA Output Port A Overrange Output Bit.
12 DB0 (LSB) Output Port B Output Bit 0 (LSB).
13 DB1 Output Port B Output Bit 1.
14 DB2 Output Port B Output Bit 2.
15 DB3 Output Port B Output Bit 3.
16 DB4 Output Port B Output Bit 4.
17 DB5 Output Port B Output Bit 5.
18 DB6 Output Port B Output Bit 6.
19 DB7 Output Port B Output Bit 7.
20 DB8 Output Port B Output Bit 8.
21 DB9 (MSB) Output Port B Output Bit 9 (MSB).
22 OVRB Output Port B Overrange Output Bit.
1 AGND and DRGND should be tied to a common quiet ground plane.
AD9601
Rev. 0 | Page 11 of 32
EQUIVALENT CIRCUITS
1.2V
10kΩ10kΩ
CLK+ CLK–
AVDD
07100-003
Figure 5. Clock Inputs
V
IN+
AVDD
BUF
VIN–
AVDD
BUF
2kΩ
2kΩ
BUF
AVDD
V
CML
~1.4V
0
7100-004
Figure 6. Analog Inputs (VCML = ~1.4 V)
SCLK/DFS
RESET
PDWN
1kΩ
30kΩ
07100-005
Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit
C
SB 1kΩ
26kΩ
AVDD
07100-006
Figure 8. Equivalent CSB Input Circuit
0
7100-044
DR
V
DD
DRGND
Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−)
SDIO/DCS
1kΩ
DRVDD
07100-007
Figure 10. Equivalent SDIO/DCS Input Circuit
AD9601
Rev. 0 | Page 12 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless
otherwise noted.
0
–140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
10010 20 30 40 50 60 70 80 90
200MSPS
10.3MHz @ –1.0dBFS
SNR: 59.48dB
ENOB: 9.58 BITS
SFDR: 83.79dBc
07100-020
Figure 11. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz
0
–140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
10010 20 30 40 50 60 70 80 90
200MSPS
70.3MHz @ –1.0dBFS
SNR: 59.3dB
ENOB: 9.7 BITS
SFDR: 78dBc
07100-021
Figure 12. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz
0
–140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
10010 20 30 40 50 60 70 80 90
200MSPS
170.3MHz @ –1.0dBFS
SNR: 59.35dB
ENOB: 9.7 BITS
SFDR: 83dBc
07100-022
Figure 13. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz
70k
0
BIN
NUMBER OF HITS
60k
50k
40k
30k
20k
10k
N – 1N – 2 N N + 1
07100-023
Figure 14. AD9601-200 Grounded Input Histogram; 200 MSPS
90
50
0 500
ANALOG INPUT FREQUENCY (MHz)
SNR/SFDR (dB)
85
80
75
70
65
60
55
50 100 150 200 250 300 350 400 450
SFDR (+85°C)
SFDR (+25°C)
SFDR (–40°C)
SNR (–40°C)
SNR (+25°C)
SNR (+85°C)
07100-024
Figure 15. AD9601-200 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 200 MSPS
0
90 0
AMPLITUDE (–dBFS)
SNR/SFDR (dB)
90
80
70
60
50
40
30
20
10
80 70 60 50 40 30 20 10
SNR (dB)
SFDR (dBc)
SNR (dBFS)
SFDR (dBFS)
07100-025
Figure 16. AD9601-200 SNR/SFDR vs. Input Amplitude; 170.3 MHz
AD9601
Rev. 0 | Page 13 of 32
OUTPUT CODE
INL (LSB)
1.0
–1.0
01
024
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
128 256 384 512 640 768 896
07100-026
Figure 17. AD9601-200 INL; 200 MSPS
400
0
5 245
SAMPLE RATE (MSPS)
CURRENT (mA)
350
300
250
200
150
100
50
25 45 65 85 105 125 145 165 185 205 225
TOTAL POWER (mW)
IAVDD (mA)
IDVDD (mA)
07100-027
Figure 18. AD9601-200 Power Supply Current vs. Sample Rate
1.0
–1.0
01
024
07100-028
90
50
0 500
ANALOG INPUT FREQUENCY (MHz)
SNR/SFDR (dB)
OUTPUT CODE
DNL (LSB)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
128 256 384 512 640 768 896
Figure 19. AD9601-200 DNL; 200 MSPS
85
80
75
70
65
60
55
SFDR (+25°C)
SFDR (–40°C)
SFDR (+85°C)
SNR (+85°C) SNR (+25°C) SNR (–40°C)
07100-029
50 100 150 200 250 300 350 400 450
Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs.
Temperature
0
–140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
20 40 60 80 100 120
250MSPS
10.3MHz @ –1.0dBFS
SNR: 59.4dB
ENOB: 9.7 BITS
SFDR: 84dBc
07100-030
Figure 21. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz
0
–140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
20 40 60 80 100 120
250MSPS
70.3MHz @ –1.0dBFS
SNR: 59.4dB
ENOB: 9.7 BITS
SFDR: 81dBc
07100-031
Figure 22. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz
AD9601
Rev. 0 | Page 14 of 32
0
–140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
20 40 60 80 100 120
250MSPS
170.3MHz @ –1.0dBFS
SNR: 59.1dB
ENOB: 9.60 BITS
SFDR: 73dBc
07100-032
Figure 23. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz
70k
0
BIN
NUMBER OF HITS
60k
50k
40k
30k
20k
10k
N – 2 N – 1 N N + 1 N + 2
07100-033
Figure 24. AD9601-250 Grounded Input Histogram; 250 MSPS
90
50
0 500
ANALOG INPUT FREQUENCY (MHz)
SNR/SFDR (dB)
85
80
75
70
65
60
55
50 100 150 200 250 300 350 400 450
SFDR (+85°C)
SFDR (+25°C)
SFDR (–40°C)
SNR (+85°C) SNR (–40°C)
SNR (+25°C)
07100-034
Figure 25. AD9601-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 250 MSPS
100
0
90 0
AMPLITUDE (–dBFS)
SNR/SFDR (dB)
90
80
70
60
50
40
30
20
10
80 70 60 50 40 30 20 10
SNR (dB)SFDR (dBc)
SNR (dBFS)
SFDR (dBFS)
07100-035
Figure 26. AD9601-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz
1.0
–1.0
01
OUTPUT CODE
INL (LSB)
024
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
128 256 384 512 640 768 896
07100-036
Figure 27. AD9601-250 DNL; 250 MSPS
400
0
5 245
SAMPLE RATE (MSPS)
CURRENT (mA)
350
300
250
200
150
100
50
25 45 65 85 105 125 145 165 185 205 225
TOTAL POWER (mW)
IAVDD (mA)
IDVDD (mA)
07100-037
Figure 28. AD9601 Power Supply Current vs. Sample Rate
AD9601
Rev. 0 | Page 15 of 32
1.0
–1.0
0
OUTPUT CODE
DNL (LSB)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
128 256 384 512 640 768 896
07100-038
Figure 29. AD9601-250 DNL; 250 MSPS
90
0
SAMPLE RATE (MSPS)
SNR/SFDR (dB)
80
70
60
50
40
30
20
10
SFDR
SNR
12575 175 225 275
07100-039
Figure 30. SNR/SFDR vs. Sample Rate;
AD9626-250 , 170.3 MHz @ −1 dBFS
2.5
2.0
1.5
1.0
0.5
0
–0.5
–60 120100806040200–20–40
GAIN (%FS)
TEMPERATURE (°C)
AD9601-210
AD9601-250
AD9601-170
07100-040
Figure 31. Gain vs. Temperature
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–40 –30 –20 –10 0 908070605040302010
OFFSET (mV)
TEMPERATURE (°C)
AD9601-170
AD9601-210
AD9601-250
07100-041
Figure 32. Offset vs. Temperature
AD9601
Rev. 0 | Page 16 of 32
THEORY OF OPERATION
The AD9601 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 10-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled. The output-staging block aligns the data, carries
out the error correction, and passes the data to the output
buffers. The output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. During power-
down, the output buffers go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9601 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+
and VIN− should be matched such that common-mode settling
errors are symmetrical. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially.
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 1.4 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. See the AD9601 Configuration Using
the SPI section for more details.
Differential Input Configurations
Optimum performance is achieved while driving the AD9601
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
VIN+
VIN–
AVDD
CML
AD8138
523Ω
499Ω
499Ω
499Ω
33Ω
33Ω
49.9Ω1V p-p
0.1µF
20pF
AD9601
0
7100-008
Figure 33. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9601. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few millihertz, and excessive signal power
can also cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
VIN+
VIN–
15Ω
15Ω
50Ω1.25V p-p
0.1µF
2pF
AD9601
07100-009
Figure 34. Differential Transformer-Coupled Configuration
As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the AD8352 differential
driver can be used (see Figure 35).
AD9601
AD8352
0Ω
R
0Ω
C
D
R
D
R
G
0.1µF
0.1µF
0.1µF
VIN+
VIN– CML
C
0.1µF
0.1µF
16
1
2
3
4
5
11
R
0.1µF
0.1µF
10
8, 13
14
V
CC
200Ω
200Ω
A
NALOG INPUT
A
NALOG INPUT
07100-010
Figure 35. Differential Input Configuration Using the AD8352
AD9601
Rev. 0 | Page 17 of 32
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9601 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 36 shows one preferred method for clocking the AD9601.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9601 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9601 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
0.1µF
0.1µF
0.1µF0.1µF
CLOCK
INPUT 50Ω100Ω
CLK–
CLK+
ADC
AD9601
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
07100-011
Figure 36. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 37. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50Ω*50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9601
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
07100-012
Figure 37. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50Ω*50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9601
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
07100-013
Figure 38. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 39). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1µF
0.1µF
0.1µF
39kΩ
CMOS DRIVER
50Ω*
OPTIONAL
100Ω
0.1µF
CLK
CLK
*50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9601
A
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
07100-014
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
CMOS DRIVER
CLK
CLK
*50Ω RESISTOR IS OPTIONAL.
0.1µF
CLK–
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
ADC
AD9601
CLOCK
INPUT
50Ω*
OPTIONAL
100Ω
07100-015
Figure 40. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic per-
formance characteristics. The AD9601 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9601. When the DCS is on, noise
and distortion performance are nearly flat for a wide range of
duty cycles. However, some applications may require the DCS
function to be off. If so, keep in mind that the dynamic range
performance can be affected when operated in this mode. See the
AD9601 Configuration Using the SPI section for more details
on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
AD9601
Rev. 0 | Page 18 of 32
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR for a full-scale input signal
at a given input frequency (fA) due only to aperture jitter (tJ) can
be calculated by
SNR Degradation = 20 × log10[1/2 × π × fA × tJ]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 41).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9601.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
SNR (dB)
07100-016
Figure 41. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS Input Signal
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 28, the power dissipated by the AD9601 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
By asserting PDWN (Pin 29) high, the AD9601 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9601 into its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 20 MHz, the
AD9601 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9601 resumes normal
operation after allowing for the pipeline latency.
DIGITAL OUTPUTS
Digital Outputs and Timing
The off-chip drivers on the AD9601 are CMOS-compatible
output levels. The outputs are biased from a separate supply
(DRVDD), allowing isolation from the analog supply and easy
interface to external logic. The outputs are CMOS devices that
swing from ground to DRVDD (with no dc load). It is recom-
mended to minimize the capacitive load the ADC drives by
keeping the output traces short (<1 inch, for a total CLOAD < 5 pF).
When operating in CMOS mode, it is also recommended to
place low value (20 Ω) series damping resistors on the data lines
to reduce switching transient effects on performance.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11 .
If it is desired to change the output data format to twos comple-
ment, see the AD9601 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9601. The DCO+/DCO− signal is used to clock the
output data and is equal to the sampling clock (CLK) rate in
single port mode, and one-half the clock rate in interleaved
output mode. See the timing diagrams shown in Figure 2 and
Figure 3 for more information.
Out-of-Range
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OVRA/OVRB is a digital
output that is updated along with the data output corresponding
to the particular sampled input voltage. Thus, OVRA/OVRB
has the same pipeline latency as the digital data. OVRA/OVRB
is low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 42. OVRA/OVRB remains high until
the analog input returns to within the input range and another
conversion is completed. By logically AND-ing OVRA/OVRB
with the MSB and its complement, overrange high or under-
range low conditions can be detected.
1
0
0
0
0
1
O
VRA/OVRB
DATA OUTPUTS
OVRA/
OVRB
+FS – 1 LSB
+FS – 1/2 LSB
+FS–FS
–FS + 1/2 LSB
–FS – 1/2 LSB
1111
1111
1111
0000
0000
0000
1111
1111
1111
0000
0000
0000
1111
1111
1110
0001
0000
0000
07100-017
Figure 42. OVRA/OVRB Relation to Input Voltage and Output Data
AD9601
Rev. 0 | Page 19 of 32
TIMING—SINGLE PORT MODE
In single port mode, the CMOS output data is available from
Data Port A (DA0 to DA9). The outputs for Port B (DB0 to
DB9) are unused, and are high impedance in this mode.
The Port A outputs and the differential output data clock
(DCO+/DCO−) switch nearly simultaneously during the rising
edge of DCO+. In this mode, it is recommended to use the
rising edge of DCO− to capture the data from Port A. The setup
and hold time depends on the input sample clock period, and is
approximately 1/fCLK ± tSKEW.
TIMING—INTERLEAVED MODE
In interleaved mode, the output data of the AD9601 is de-
multiplexed onto two data port buses, Port A (DA0 to DA9) and
Port B (DB0 to DB9). The output data and differential data
capture clock switch at one-half the rate of the sample clock
input (CLK+/CLK−), increasing the setup and hold time for the
external data capture circuit relative to single port mode (see
Figure 3, interleaved mode timing diagram). The two ports
switch on alternating sample clock cycles, with the data for
Port A being valid during the rising edge of DCO+, and the
data for Port B being valid during the rising edge of DCO−. The
pipeline latency for both ports is six sample clock cycles. Due to
the random nature of the ÷2 circuit that generates the timing
for the output stage in interleaved mode, the first data sample
during power-up can be assigned to either Data Port A or Port
B. The user cannot control the polarity of the output data clock
relative to the input sample clock. In this mode, it is recom-
mended to use the rising edge of DCO+ to capture the data
from Port A, and the rising edge of DCO− to capture the data
from Port B. In both cases, the setup and hold time depends on
the input sample clock period, and both are approximately
2/fS ± tSKEW.
fS/2 Spurious
Because the AD9601 output data rate is at one-half the sampling
frequency in interleaved output mode, there is significant fS/2
energy in the outputs of the part, and there is significant energy
in the ADC output spectrum at fS/2. Care must be taken to be
certain that this fS/2 energy does not couple into either the clock
circuit or the analog inputs of the AD9601. When fS/2 energy is
coupled in this fashion, it appears as a spurious tone reflected
around fS/4, 3fS/4, 5fS/4, and so on. For example, in a 125 MSPS
sampling application with a 90 MHz single-tone analog input,
this energy generates a tone at 97.5 MHz.
[(3 × 125 MSPS/4 − 90 MHz) + 3 × 125 MSPS/4]
Depending on the relationship of the IF frequency to the center
of the Nyquist zone, this spurious tone may or may not be in the
user’s band of interest. Some residual fS/2 energy is present in
the AD9601, and the level of this spur is typically below the
level of the harmonics at clock rates. Figure 20 shows a plot of
the fS/2 spur level vs. the analog input frequency for the
AD9601-250. For the specifications provided in Table 2, the fS/2
spur effect is not a factor, as the device is specified in single port
output mode.
AD9601
Rev. 0 | Page 20 of 32
LAYOUT CONSIDERATIONS
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9601, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V nominal). If only a
single 1.8 V supply is available, it is routed to AVDD first, then
tapped off and isolated with a ferrite bead or filter choke with
decoupling capacitors proceeding connection to DRVDD. The
user can employ several different decoupling capacitors to cover
both high and low frequencies. These should be located close to
the point of entry at the PC board level and close to the parts
with minimal trace length.
A single PC board ground plane is sufficient when using the
AD9601. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9601. An
exposed, continuous copper plane on the PCB should mate to
the AD9601 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie
point between the ADC and PCB. See Figure 43 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.
SILKSCREEN PARTITION
PIN 1 INDICATOR
07100-018
Figure 43. Typical PCB Layout
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 45.
RBIAS
The AD9601 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
AD9601 CONFIGURATION USING THE SPI
The AD9601 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or read back) serially in
one-byte words. Each byte can be further divided down into
fields, which are documented in the Memory Map section.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 8).
Table 8. Serial Port Pins
Mnemonic Function
SCLK SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB CSB (Chip Select Bar) is an active low control that
gates the read and write cycles.
RESET Master Device Reset. When asserted, device
assumes default settings. Active low.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 44
and Table 10.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see Interfacing to High Speed ADCs via SPI at
www.analog.com.
AD9601
Rev. 0 | Page 21 of 32
HARDWARE INTERFACE
The pins described in Table 8 comprise the physical interface
between the user’s programming device and the serial port of
the AD9601. All serial pins are inputs, which is an open-drain
output and should be tied to an external pull-up or pull-down
resistor (suggested value of 10 kΩ).
This interface is flexible enough to be controlled by either
PROMS or PIC microcontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power-
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9601.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode, the SPI CSB chip select should be connected to
ground, which disables the serial port interface.
Table 9. Mode Selection
Mnemonic
External
Voltage Configuration
AVDD Duty cycle stabilizer enabled SPI SDIO/DCS
AGND Duty cycle stabilizer disabled
AVDD Twos complement enabled SPI SCLK/DFS
AGND Offset binary enabled
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
tStDH
tHI tCLK
tLO
tDS tH
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
07100-019
Figure 44. Serial Port Interface Timing Diagram
AD9601
Rev. 0 | Page 22 of 32
Table 10. Serial Timing Definitions
Parameter Timing (minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS5 Setup time between CSB and SCLK
tH2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 1 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 44)
tDIS_SDIO 5 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 44)
Table 11. Output Data Format
Input (V) Condition (V)
Offset Binary Output Mode
D11 to D0
Twos Complement Mode
D11 to D0
Gray Code Mode
(SPI Accessible)
D11 to D0 OR
VIN+ − VIN− < 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1
VIN+ − VIN− = 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0
VIN+ − VIN− = 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0
VIN+ − VIN− = 0.62 1111 1111 1111 1111 1111 1111 0000 0000 0000 0
VIN+ − VIN− > 0.62 + 0.5 LSB 1111 1111 1111 1111 1111 1111 0000 0000 0000 1
AD9601
Rev. 0 | Page 23 of 32
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and program register map
(Address 0x08 to Address 0x2A).
The Addr (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, clock, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the Interfacing
to High Speed ADCs via SPI user manual at www.analog.com.
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 12. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 12. Memory Map Register
Addr
(Hex) Parameter Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00 chip_port_config 0 LSB
first
Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles
should be
mirrored by the
user so that LSB
or MSB first mode
registers correctly,
regardless of shift
mode.
01 chip_id 8-bit chip ID, Bits[7:0]
AD9601 = 0x36
Read-
only
Default is unique
chip ID, different
for each device.
This is a read-
only register.
02 chip_grade 0 0 0 Speed grade:
01 = 200 MSPS
10 = 250 MSPS
X X X Read-
only
Child ID used to
differentiate
graded devices.
Transfer Register
FF device_update 0 0 0 0 0 0 0 SW
transfer
0x00 Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08 modes 0 0 PDWN:
0 = full
(default)
1 =
standby
0 0 Internal power-down mode:
000 = normal (power-up, default)
001 = full power-down
010 = standby
011 = normal (power-up)
Note: external PDWN pin overrides
this setting
0x00 Determines
various generic
modes of chip
operation.
AD9601
Rev. 0 | Page 24 of 32
Addr
(Hex) Parameter Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default Notes/
Comments
09 clock 0 0 0 0 0 0 0 Duty cycle
stabilizer:
0 =
disabled
1 =
enabled
(default)
0x01
OD test_io Reset
PN23 gen:
1 = on
0 = off
(default)
Reset
PN9 gen:
1 = on
0 = off
(default)
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
0x00 When set, the
test data is
placed on the
output pins in
place of normal
data.
OF ain_config 0 0 0 0 0 Analog
input
disable:
1 = on
0 = off
(default)
CML
enable:
1 = on
0 = off
(default)
0 0x00
14 output_mode 0 0 Interleave
output
mode:
1 =
enabled
0 =
disabled
(default)
Output
enable:
0 =
enable
(default)
1 =
disable
0 Output
invert:
1 = on
0 = off
(default)
Data format select:
00 = offset binary
(default)
01 = twos
complement
10 = Gray code
0x00
16 output_phase Output
clock
polarity
1 =
inverted
0 =
normal
(default)
0 0 0 0x03
17 flex_output_delay Output
delay
enable:
0 =
enable
1 =
disable
Output clock delay:
00000 = 0.1 ns
00001 = 0.2 ns
00010 = 0.3 ns
…
11101 = 3.0 ns
11110 = 3.1 ns
11111 = 3.2 ns
0x00
18 flex_vref Input voltage range setting:
10000 = 0.98 V
10001 =1.00 V
10010 = 1.02 V
10011 =1.04 V
…
11111 = 1.23 V
00000 = 1.25 V
00001 = 1.27 V
…
01110 = 1.48 V
01111 = 1.50 V
0x00
AD9601
Rev. 0 | Page 25 of 32
EVALUATION BOARD
ADT1-1WT
PRI SEC
nc
ETC1-1-13
PRI SEC
IN OUT
EVQ-Q2
ETC1-1-13
PRI SEC
0.1UF
VOLT_CONTROL
VCLK
TRI_STATE
GND
NC
OUTPUT
A1
A10
A2
A3
A4
A5
A6
A7
A8
A9
B1
B10
B2
B3
B4
B5
B6
B7
B8
B9
C1
C10
C2
C3
C4
C5
C6
C7
C8
C9
D1
D10
D2
D3
D4
D5
D6
D7
D8
D9
GNDAB1
GNDAB10
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
GNDAB9
GNDCD1
GNDCD10
GNDCD2
GNDCD3
GNDCD4
GNDCD5
GNDCD6
GNDCD7
GNDCD8
GNDCD9
HEADERM1469169_1
A1
A10
A2
A3
A4
A5
A6
A7
A8
A9
B1
B10
B2
B3
B4
B5
B6
B7
B8
B9
C1
C10
C2
C3
C4
C5
C6
C7
C8
C9
D1
D10
D2
D3
D4
D5
D6
D7
D8
D9
GNDAB1
GNDAB10
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
GNDAB9
GNDCD1
GNDCD10
GNDCD2
GNDCD3
GNDCD4
GNDCD5
GNDCD6
GNDCD7
GNDCD8
GNDCD9
HEADERM1469169_1
AIN
AINB
AVDD_CLK
AVDD_CLK1
AVDD_FL
AVDD_FL1
AVDD_PIPE
AVDD_PIPE1
AVDD_PIPE2
AVDD_PIPE3
AVDD_PIPE4
AVDD_PIPE5
AVDD_REF
CLK
CLKB
CML
D0
D0B
D1
D10
D10B
D11
D11B
D1B
D2
D2B
D3
D3B
D4
D4B
D5B
D6
D6B
D7
D7B
D8
D8B
D9
D9B
DCO
DCOB
DGND
DGND1 DGND2
DOR
DORB
DVDD
DVDD1 DVDD2
PAD
PDN
RBIAS
RESETB
SPCSB
SPSCLK/DFS
SPSDIO/DCS
D5
PRI SEC
nc
50_OHMS
50_OHMS
Alternate Options
DNP
optional
ENCODE
CR2 TO MAKE LAYOUT AND PARASI TIC LOADI NG SYMMETRICAL
ANALOG
Input
CVHD_956 Crystek Cry st al
U6
OPT IO NAL ENCODE CIRCUI TS
D1
D1B
D0
D0B
DCOB
DCO
D2B
D2
9
10
12
13
14
15
2
3
4
5
6
7
8
116
11
RN3
9
10
12
13
14
152
3
4
5
6
7
8
116
11
RN2
9
10
12
13
14
15
2
3
4
5
6
7
8
116
11
D9B
D9
D10B
D10
D11B
D11
DORB
D10B
DORB
DOR
D10
9
10
12
13
14
152
3
4
5
6
7
8
116
11
CMLX
12
34
56
T3
ADT1-1WT
35
36
43
46
42
41
39
38
37
34
33
32
30
44
45
40
52
51
54
18
17
20
19
53
56
55
2
1
4
3
5
10
9
12
11
14
13
16
15
50
49
8
23 48
22
21
7
24 47
57
29
31
28
27
26
25
6
U4
AD9601_CSP
C17 DNP
R9
DNP
AMPOUT-
AMPOUT+
TOUT
TOUTB
0.1UF
C21
GND
00
R90
00
R89
00
R8 R1
50
D1B
D1
GND
10K
R12
L8
0
L9
0
R6
36
R5
36
R7
33
DNP
R4
R16
33
CSB1_CHA
1
10
2
3
4
5
6
7
8
9
11
20
12
13
14
15
16
17
18
19
31
40
32
33
34
35
36
37
38
39
41
50
42
43
44
45
46
47
48
49
21
30
22
23
24
25
26
27
28
29
51
60
52
53
54
55
56
57
58
59
SDO_CHA
SDI_CHA
SCLK_CH
A
1
10
2
3
4
5
6
7
8
9
11
20
12
13
14
15
16
17
18
19
31
40
32
33
34
35
36
37
38
39
41
50
42
43
44
45
46
47
48
49
21
30
22
23
24
25
26
27
28
29
51
60
52
53
54
55
56
57
58
59
P7
CONNECT S T O J2
P17
GND
P5
P9
GND
0.1UF
C75
R17
0 DNP
VOLT_CONTROL
C74
0.1UF
GND
1
6
2
3
5
4
E20
C61
0.1UF
E19
0
R87
XTALINPUT
50
R3
C15
R86
10K
R85
10K
J3
J4
J2
R13
1K R10
1K
1
3
2
CR3
1
3
2
CR2
CSB
GND
VSPI E10
E5 E4
DNP
R15
E7
E6
1
34
2
5
T6
12
SW3
C22
0.1UF
C20
DNP
0.1UF
C23
DNP
R14
R11
1K
E9
L1
10NH
0.1UF
C19
0.1UF
C18
E8
0.1UF
C16
1
34
2
5
T5
12
34
56
T2
E3
E2
E1
P4
P3
P2
P1
CML
GND
GND
CLKCT CLKCT
GND
AVDD
CML CML
SDIO_ODM
SCLK_DTP
TOUTBTINB
TOUTGND GND
VSPI
GND
GND
GND
VSPI
GND
E33
E32 E31
CSB_DUT
VSPI
CSB
GND
DRVDD
DRVDD
DRVDD
GND
GND
GND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
E18 GND
VCLK
GND
GND
GND
VCLK
XTALINPUT
VCLK
GND
GND
GND
GND
GND P16
P10
GND
GND
GND
D8B
D6B
D4B
D2B
D0B
D0
D2
D4
D6
D8
D11B
D9B
D7B
D5B
D3B
D3
D5
D7
D9
D11
DCOBDCO
GND
CLK CLK
GND
TINB
CML
CML
GND
GND
GND
GND
GND
GND
DOR
D8B
D8
D7B
D7
D6B
D6
D5
D5B
D4B
D4
D3B
D3
P11
CONNECT S T O J1
RN1
50_OHMS
RN4
50_OHMS
07100-045
Figure 45. AD9601 Evaluation Board Schematic Page 1
AD9601
Rev. 0 | Page 26 of 32
+
+
+
+
IN
OUT
OUT1
ADP3338
U9
GND
IN
OUT
OUT1
ADP3338
U12
GND
IN
OUT
ADP3338
U11
GND
IN
OUT
OUT1
ADP3338
U10
GND
+
+
PJ-102A
+5.0V
1.8V
1.8V
3.3V
1.8V 1.8V 3.3V
+5V
POWER O P TION S
123
P8
VIN
VCLK
VSPIEXT1
L6
FERRITE
L2
FERRITE
VSPIEXTX
OUT1
VSPIEXTX
DRVDDX1
DRVDDX
VSPI
DRVDD1
L3
FERRITE
L5
FERRITE
AVDD1 L4
FERRITE
AVDDX
L7
FERRITE
VAMP1
VAMPX
0
R88
C11
10UF
AVDD1
VSPIEXT1
VAMP1
DRVDD1
GND
100PF
C73
0.1UF
C72
0.1UF
C69
VCLK
C54
10UF
0.1UF
C650.1UF
C68
0.1UF
C59
VSPI
GND
0.1UF
C39
0.1UF
C63
0.1UF
C62
0.1UF
C27
EGND
DRVDD
GND
3
4
2
1
3
4
2
1
3
4
2
1
3
4
2
1
0.1UF
C33
0.1UF
C31
C8
10UF
C9
10UF
GND
GND
GND
VIN
GND
U7
VAMPX
C12
10UF 0.1UF
C34
EGND
3
21
4
T1
U8
R2
499
0.1UF
C32
0.1UF
C30
0.1UF
C29
0.1UF
C28
0.1UF
C26
0.1UF
C25
0.1UF
C24
GND
VSPIEXTX
VIN
VIN
GND
GND
GND
GND
GND
DRVDDX1
GND
AVDDX
C14
10UF
0.1UF
C58
0.1UF
C57
0.1UF
C56
GND
VAMP
0.1UF
C60
0.1UF
C36
0.1UF
C35
VSPIEXT
0.1UF
C64
0.1UF
C13
0.1UF
C66
0.1UF
C67
GND
0.1UF
C70
0.1UF
C71
GND
AVDD
GND
C6
1UF
C5
1UF
C7
1UF
C10
1UF
C1
1UF
C3
1UF
C2
1UF
C4
1UF
GND
GND
GND
GND
21345678
P6
VAMP
DRVDD
VSPIEXT
AVDD
L12
FERRITE
L13
FERRITE
L14
FERRITE
L15
FERRITE
H4
MTHOLE6
H3
MTHOLE6
H2
MTHOLE6
H1
MTHOLE6
GND
GND
EGND
EGND
VIN
GND
0
7100-046
Figure 46. AD9601 Evaluation Board Schematic Page 2
AD9601
Rev. 0 | Page 27 of 32
ADT1-1WT
PRI SEC
nc
VOP
VON
VIP
VIN
VCMENB
AD8352
VCC
GND
GND
GND
VCC
RGN
RDN
RGP
RDP
ETC1-1-13
PRI SEC
Operational Amplifier
AD9515 Logic Setup
GND C37.1UF GND
C46.1UF
1
34
2
5
T7
00
R46
00
R41
00
R91
DNP
C76
DNP
L10
L11
DNP
10K
R42
00
R36
9
12
67
15
4
1
3
2
8
13
5
16 14
10
11
Z1
C44
DNP
C45
DNP
P13
SMBMST
P12
SMBMST
1
2
34
5
6
T4
C47
.1UF
00
R47
E14
5
R45
00
R44
10K
R43
C43
DNP
E13
E12
DNP
R40
C42
.1UF 5
R39
R38
25
C41
DNP
R37
25
C40
DNP
DNP
R35
DNP
R34 R33
49.9
00
R94
TINB1 TOUT2
TINB1
TINB2 TOUTB2
TOUTB2
TINB2
TOUT2
GND
AMPOUT-
AMPOUT+
CML
GND
GND VAMP
GND
GND
VAMP
GND
GND
GND
VAMP
GND
GND
0.1UF
SMBMST
SMBMST
DNC; 2 7, 28
CLK
CLKB
GND
GND_PAD
OUT0
OUT0B
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SYNCB
VREF
RSET
OUT1
OUT1B
AD9515
AD9515(Opt_Clk Circuit)
2
3
5
6
7
8
9
10
11
12
13
14
15
16
25
18
19
22
23
31
32
33
U1
VCLK; 1, 4, 17, 20, 21, 24, 26, 29, 30
P14
P15
0.1UF
C53
R62
4.12K
E17
E16
R61
240 R60
240
R59
100
0.1UF
C52
0.1UF
C51
0.1UF
C50
R58
100
R57
00
R56
00 R55
00
R54
10K
R53
00 R52
00
00
R51
DNP
R50
DNP
R49
C49
DNP
C48
50
R48 E15
GND
S9
S3
S1
S0
S8
VCLK
GND
GND GND
GND GND
GND
CLK
CLK
S10
S7
S5
S6
S4
S2
00
R84
00
R83
00
R82
00
R81
00
R80
00
R79
00
R78
00
R77
00
R76
00
R75
00
R74
00
R73
00
R72
00
R71
00
R70
00
R69
00
R68
00
R67
00
R66
00
R65
00
R64
00
R63
VCLK
S6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
S10
S9
VCLK
S8
S7
S5
S4
S3
S2
S1
S0
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
07100-047
Figure 47. AD9601 Evaluation Board Schematic Page 3
AD9601
Rev. 0 | Page 28 of 32
SPI CIRCUITRY
Y2
Y1
VCCGND
A2
A1
NC7WZ16
Y2
Y1
VCCGND
A2
A1
NC7WZ07
4
5
3
2
16
U5
4
5
3
2
16
U3
1K
R27
10K
R26
1K
R25 1K
R24
10K
R19
10K
R18
CSB1_CHA
SDO_CHA
SDIO_ODM
CSB_DU
T
GND
GND
SCLK_DTP
GND
GND
VSPI
VSPI
VSPI
VSPIEXT
VSPIEXT
SDI_CHA
SCLK_CHA
07100-048
Figure 48. AD9601 Evaluation Board Schematic Page 4
Table 13. Bill of Materials
Qty
Reference
Designator Package Description Vendor Part Number
1 PCB PCB, AD9230 customer evaluation board, Rev. G Moog AD9230revG
7 C1, C3, C4, C5,
C6, C7, C10
603 Capacitor, 1 F, 0603, X5R, ceramic, 6.3 V, 10% Panasonic ECJ-1VB0J105K
6 C8, C9, C11,
C12, C14, C55
6032-28 Capacitor, 10 F, tantalum, 16 V, 10% Kemet T491C106K016AS
1 C17 402 Capacitor, 2.0 pF, 50 V, ceramic, 0402, SMD Murata GRM1555C1H2R0GZ01D
7 C27, C32, C33,
C62, C63, C64,
C71
402 Capacitor, 0.33 F, ceramic, X5R, 10 V, 10% Murata GRM155R61A334KE15D
6 C28, C29, C30,
C31, C65, C70
402 Capacitor, 120 pF, ceramic, C0G, 25 V, 5% Murata GRM1555C1H121JA01J
10 C21, C22, C23,
C24, C25, C26,
C34, C35, C36,
C39
402 Capacitor, 0.1 F, ceramic, X5R, 10 V, 10% Murata GRM155R71C104KA88D
1 CR4 603 LED green, SMT, 0603, SS-TYPE Panasonic LNJ314G8TRA
1 CR2 Mini 3P Diode, 30 V, 20 mA Agilent HSMS2812
1 F1 1210 Fuse, 6.0 V, 2.2 A trip current resettable fuse Tyco/Raychem NANOSMDC110F-2
15 E1, E2, E3, E4,
E5, E7, E8, E9,
E10, E12, E13,
E14, E31, E32,
E33
Connector, header, 0.1" Samtec TSW-150-08-G-S
2 J2, J3 SMA end
launch
Connector, SMA PCB coax end launch, Johnson
142
Johnson 142-0701-851
10 L2, L3, L4, L5,
L7, L12, L13,
L14, L15, R88
1206 Ferrite bead, BLM, 3 A, 50 Ω @ 100 MHz Murata BLM31PG500SN1L
1 P8 Power jack, male, 2.1 mm power jack dc CUI Inc CP-102A-ND
1 R1 201 Resistor, 100 Ω, 0201, 1/20 W, 1% NIC Components NRC02F1000TRF
1 R2 603 Resistor, 499 Ω, 0603, 1/10 W, 1% NIC Components NRC06F4990TRF
AD9601
Rev. 0 | Page 29 of 32
Qty
Reference
Designator Package Description Vendor Part Number
2 R5, R6 402 Resistor, 36 Ω, 0402, 1/16 W, 1% Panasonic ERJ-2GEJ360X
2 R7, R16 402 Resistor, 15 Ω, 0402, 1/16 W, 5% Panasonic ERJ-2RKF15R0X
6 R10, R11, R13,
R24, R25, R27
402 Resistor, 1 kΩ, 0402, 1/16 W, 1% NIC Components NRC04F1001TRF
4 R12, R18, R19,
R26,
402 Resistor, 10 kΩ, 0402, 1/16 W, 5% NIC Components NRC04J103TRF
7 R15, C16, C18,
C19, C20, R89,
R90
402 Resistor, 0 Ω, 0402, 1/16 W, 5% NIC Components NRC04ZOTRF
4 RN1, RN2, RN3,
RN4
0402x8 Resistor array, SMT 0402; 0 Ω, ¼ W, 5%,
RESNEXB-2HV
Panasonic EXB2HV050JV
3 L1, L8, L9 603 Resistor, 0 Ω, 0603, 1/10 W, 5% NIC Components NRC06ZOTRF
1 P9, P10 805 Resistor, 0 Ω, 0805, 1/8 W, 1% NIC Components NRC10ZOTRF
1 SW3 EVQ-
Q2F03W
Switch, light touch SMD Panasonic P12937SCT-ND
1 T1 2020 Ferrite bead, 5 A, 50 V, 190 Ω @ 100 MHz Murata DLW5BSN191SQ2L
2 T2,T3 CD542 Transformer, 0.5 W, 30 mA Mini-Circuits ADT1-1WT+
1 U3 6-SC70 IC, buffer, inverter, UHS dual SC70-6 Fairchild NC7WZ16P6X
1 U5 6-SC70 IC, buffer, inverter, UHS dual OD out SC70-6 Fairchild NC7WZ07P6X
1 U7 DO-214AA Diode, 50 V, 2 A Micro Commercial S2A-TPMSTR-ND
1 U8 DO-214AB Diode, 30 V, 3 A (SMC) Micro Commercial SK33-TPMSCT-ND
1 U11 SOT-223 Voltage regulator, 3.3 V, 1.5 A Analog Devices ADP3339AKCZ-3.3
2 U9, U12 SOT-223 Voltage regulator, 1.8 V, 1.5 A Analog Devices ADP3339AKCZ-1.8
1 U4 LFCSP56 AD9230 12-bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V ADC, LFCSP-56
Analog Devices AD9230BCPZ-xxx
2 P7, P11 HM-Zd PCB Connector, 2-Pr, 10-column, high speed, HM-Zd,
PCB-mounted
Tyco 6469169-1
Do not install the following:
0 C2, C54 TAJD Capacitor, tantalum, SMT 6032, 10 F, 16 V, 10% Kemet T491C106K016AS
0 C15, C37, C38,
C40, C41, C61,
C42, C43, C44,
C45, C46, C47,
C48, C49, C50,
C51, C52, C53,
C39, C56, C57,
C58, C59, C74,
C75, C60, C66,
C67, C68, C69,
C72
402 Capacitor, 0.1 F, ceramic, 10% Murata GRM155R71C104KA88D
0 CR1 Led_ss LED green, USS type 0603 Panasonic LNJ314G8TRA
0 CR3 Diode Schottky diode Agilent HSMS2812
0 805 Tyco/Raychem NANOSMDC110F-2
0 E6, E15, E16,
E17, E18, E19,
E20
Connector, header, 0.1" Samtec TSW-150-08-G-S
0 J1 10-pin
header
TSW-110-08-G-D Samtec TSW-110-08-G-D
0 J4 SMA Connector, PCB coax SMA end launch,
Johnson 142
Johnson 142-0701-851
0 L6 1206 Inductor, 10 nH Murata BLM31P500S
0 P12, P13, P14,
P15
SMA Amphenol RF ARFX1231-ND
AD9601
Rev. 0 | Page 30 of 32
Qty
Reference
Designator Package Description Vendor Part Number
0 R3, R14, R33,
R34, R35, R48,
R49
402 Resistor, 49.9 Ω Susumu RR0510R-49R9-D
0 R42, R43, R54,
R85, R86
402 Resistor, 10 kΩ NIC Components NRC04J103TRF
0 R28, R29, R30,
R31, R32
402 Resistor, 5 kΩ NIC Components NRC04F4991TRF
0 R37, R38 402 Resistor, 25 Ω NIC Components NRC04F24R9TRF
0 R39, R45 402 Resistor, 5 Ω NIC Components NRC04J5R1TRF
0 R58, R59 402 Resistor, 100 Ω NIC Components NRC04F1000TRF
0 R60, R61 402 Resistor, 240 Ω NIC Components NRC04J241TRF
0 R8, R9, R17,
R36, R40, R41,
R44, R46, R47,
R87, R50, R51,
R52, R53, R55,
R56, R57, R62,
R63, R64, R65,
R66, R67, R68,
R69, R70, R71,
R72, R73, R74,
R75, R76, R77,
R78, R79, R80,
R81, R82, R83,
R84
402 Resistor, 0 Ω NIC Components NRC04ZOTRF
0 P1, P2, P16, P17 805 Resistor, 0 Ω NIC Components NRC10ZOTRF
0 SW1 EVQ-
Q2F03W
Switch, light touch SMD Panasonic P12937SCT-ND
0 T4 Transformer, RF, 0.4 MHz to 800 MHz, SMD case
style CD542
Mini-Circuits ADT1-1WT+
0 T5, T6 sm-22 Balun M/A-Com MABA007159-0000
0 U2 SOIC-8 PIC12F629 Microchip Tech PIC12F629-I/SN
0 U6 Crystal Cvhd_956 crystal CVHD_956
0 U10 SOT-223 Regulator ADP3339AKCZ-5.0
0 Z1 16CSP4X4 AD8352
0 U1 16CSP8X8 AD9515
0 P6 8-pin power connector post Wieland Z5.530.0825.0
0 P6 8-pin power connector top Wieland 25.602.2853.0
AD9601
Rev. 0 | Page 31 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
112805-0
PIN 1
INDICATOR
TOP
VIEW 7.75
BSC SQ
8.00
BSC SQ
1
56
14
15
43
42
28
29
4.45
4.30 SQ
4.15
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC 0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0
.85
0
.80
6.50
REF
SEATING
PLANE
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
0.05 MAX
0.02 NOM
0.30 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 49. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9601BCPZ-2001−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2
AD9601BCPZ-2501−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2
AD9601-250EBZ1 CMOS Evaluation Board with AD9601BCPZ-250
1 Z = RoHS Compliant Part.
AD9601
Rev. 0 | Page 32 of 32
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07100-0-11/07(0)
