CY7C106D CY7C1006D PRELIMINARY 1-Mbit (256K x 4) Static RAM Functional Description[1] Features The CY7C106D and CY7C1006D are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. * Pin- and function-compatible with CY7C106B/CY7C1006B * High speed -- tAA = 10 ns * CMOS for optimum speed/power * Low active power Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). -- ICC = 60 mA @ 10 ns * Low CMOS standby power -- ISB2 = 3.0 mA * Data Retention at 2.0V * Automatic power-down when deselected * TTL-compatible inputs and outputs * Available in Pb-Free packages Reading from the devices is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106D is available in a standard 400-mil-wide Pb-Free SOJ; the CY7C1006D is available in a standard 300-mil-wide Pb-Free SOJ. Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND I/O3 512 x 512 x 4 ARRAY SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE I/O1 I/O0 POWER DOWN CE WE OE A0 A 10 A11 A12 A13 A14 A15 A16 A17 COLUMN DECODER Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05459 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 11, 2005 CY7C106D CY7C1006D PRELIMINARY Selection Guide CY7C106D-10 CY7C1006D-10 CY7C106D-12 CY7C1006D-12 Maximum Access Time (ns) 10 12 Maximum Operating Current (mA) 60 50 Maximum Standby Current (mA) 3 3 Document #: 38-05459 Rev. *C Page 2 of 10 CY7C106D CY7C1006D PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. -65C to +150C Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. -55C to +125C Operating Range Supply Voltage on VCC Relative to GND [2] .... -0.5V to +7.0V Range Commercial Industrial DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V DC Input Voltage[2] .................................-0.5V to VCC + 0.5V Ambient Temperature 0C to +70C -45C to +85C VCC 5V 10% Electrical Characteristics Over the Operating Range 7C106D-10 7C1006D-10 Test Conditions Min. VOH Parameter Output HIGH Voltage VCC = Min., IOH = -4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage VIH Description Max. 7C106D-12 7C1006D-12 Min. Max. V 0.4 Voltage[2] Unit 2.4 0.4 V V 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW -0.5 0.8 -0.5 0.8 V IIX Input Load Current GND < VI < VCC -1 +1 -1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled -1 +1 -1 +1 A IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND -300 -300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 60 50 mA ISB1 Automatic CE Max. VCC, CE > VIH, Power-Down Current VIN > VIH or VIN < VIL, --TTL Inputs f = fMAX 10 10 mA ISB2 Automatic CE Max. VCC, CE > VCC - 0.3V, Power-Down Current VIN > VCC - 0.3V --CMOS Inputs or VIN < 0.3V, f=0 3 3 mA Capacitance[4] Parameter CIN: Addresses Description Input Capacitance CIN: Controls Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Output Capacitance COUT Max. Unit 7 pF 10 pF 10 pF Thermal Resistance[4] Parameter Description JA Thermal Resistance (Junction to Ambient)[4] JC Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board All-Packages Unit TBD C/W TBD C/W Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: 38-05459 Rev. *C Page 3 of 10 CY7C106D CY7C1006D PRELIMINARY AC Test Loads and Waveforms ALL INPUT PULSES 10-ns Device 3.0V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT GND 30 pF* 90% 10% 10% Rise Time < 1V/ns 1.5V Fall Time < 1V/ns (a) High-Z Characteristics 12 -ns Devices R1 480 R1 480 5V 5V OUTPUT R2 255 30 pF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE (b) R2 255 5 pF (c) THEVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: Switching Characteristics Over the Operating Range[5] 7C106D-10 7C1006D-10 Parameter Description Min. 7C106D-12 7C1006D-12 Max. Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 100 100 s tRC Read Cycle Time 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE 10 5 [7, 8] [8] CE LOW to Low Z 3 tHZCE CE HIGH to High Z CE LOW to Power-Up ns 6 ns ns 6 5 CE HIGH to Power-Down tPD 12 3 0 ns ns 6 0 10 ns ns 0 5 [7, 8] tPU 12 3 0 OE HIGH to High Z tLZCE 10 3 ns ns 12 ns [9, 10] Write Cycle tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 8 10 ns tAW Address Set-Up to Write End 7 10 ns tHA Address Hold from Write End 0 0 ns Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05459 Rev. *C Page 4 of 10 CY7C106D CY7C1006D PRELIMINARY Switching Characteristics Over the Operating Range[5] 7C106D-10 7C1006D-10 Parameter Description Min. 7C106D-12 7C1006D-12 Max. Min. Max. Unit tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 10 ns tSD Data Set-Up to Write End 6 7 ns tHD Data Hold from Write End 0 0 ns [8] tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z[7, 8] 3 2 ns 6 6 ns Data Retention Characteristics Over the Operating Range Parameter VDR Description Conditions Min. VCC for Data Retention tCDR[4] tR[11, 12] Unit 3 mA 1.2 mA 2.0 Non-L, Com'l / Ind'l VCC = VDR = 2.0V, Data Retention Current L-Version Only CE > VCC - 0.3V, VIN > VCC - 0.3V or Chip Deselect to Data Retention Time VIN < 0.3V Operation Recovery Time ICCDR Max. V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V 4.5V tR tCDR CE Switching Waveforms Read Cycle No.1[13, 14] 1 tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DA TA VALID DATA VALID Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 12. tr < 3 ns for all speeds. 13. Device is continuously selected, OE and CE = VIL. 14. WE is HIGH for read cycle. Document #: 38-05459 Rev. *C Page 5 of 10 CY7C106D CY7C1006D PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 15. Address valid prior to or coincident with CE transition LOW. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. Data I/O is high impedance if OE = VIH. Document #: 38-05459 Rev. *C Page 6 of 10 CY7C106D CY7C1006D PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATA VALID tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[10, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE Input/Output Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05459 Rev. *C Page 7 of 10 CY7C106D CY7C1006D PRELIMINARY Ordering Information Speed (ns) 10 12 Package Name Ordering Code Operating Range Package Type CY7C106D-10VXC V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial CY7C1006D-10VXC V21 28-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C106D-10VXI V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial CY7C1006D-10VXI V21 28-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C106D-12VXC V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial CY7C1006D-12VXC V21 28-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C106D-12VXI V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial CY7C1006D-12VXI V21 28-Lead (300-Mil) Molded SOJ (Pb-Free) Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Package Diagrams 28-Lead (300-Mil) Molded SOJ V21 28-Lead (300-Mil) Molded SOJ V21 MIN. MAX. DIMENSIONS IN INCHES PIN 1 ID 14 DETAIL A EXTERNAL LEAD DESIGN 1 0.291 0.300 15 0.330 0.350 OPTION 1 0.697 0.713 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 28 A 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*B Document #: 38-05459 Rev. *C Page 8 of 10 CY7C106D CY7C1006D PRELIMINARY Package Diagrams (continued) 28-Lead (400-Mil) Molded SOJ V28 PIN 1 I.D 14 1 .395 .405 15 DIMENSIONS IN INCHES .435 .445 MIN. MAX. 28 .720 .730 SEATING PLANE .128 .148 .026 .032 .007 .013 0.004 .025 MIN. .360 .380 51-85032-*B .015 .020 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05459 Rev. *C Page 9 of 10 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C106D CY7C1006D PRELIMINARY Document History Page Document Title: CY7C106D, CY7C1006D 1-Mbit (256K x 4) Static RAM (Preliminary) Document Number: 38-05459 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance information data sheet for C9 IPP *A 233693 See ECN RKF ICC,ISB1,ISB2 Specs are modified as per EROS (Spec # 01-2165) Pb-free offering in the `ordering information' *B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Shaded `Ordering Information' *C 307596 See ECN RKF Reduced Speed bins to -10 and -12 ns Document #: 38-05459 Rev. *C Page 10 of 10