PRELIMINARY
1-Mbit (256K x 4) Static RAM
CY7C106D
CY7C1006D
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05459 Rev. *C Revised January 11, 2005
Features
• Pin- and function-compatible with
CY7C106B/CY7C1006B
•High speed
—t
AA = 10 ns
• CMOS for optimum speed/po we r
• Low active pow er
—I
CC = 60 mA @ 10 ns
• Low CMOS standby power
—I
SB2 = 3.0 mA
• Data Retention at 2.0V
• Automatic power-down wh en deselected
• TTL-compatible inputs and outputs
• Available in Pb-F ree packages
Functional Description[1]
The CY7C106D and CY7C1006D are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and tri-state
drivers. These devices have an automatic power-down feature
that reduces power consumption by more than 65% when the
devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location
specified on the address pins (A0 through A17).
Reading from the devices is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a wri te
operation (CE and WE LOW).
The CY7C106D is available in a standard 400-mil-wide
Pb-Free SOJ; the CY7C1006D is available in a standard
300-mil-wide Pb-Free SOJ.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
LogicBlockDiagram Pin Configuration
512 x512 x4
ARRAY
A
1
A
0
A
10
A
12
A
11
A
13
A
14
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
OE
INPUTBUFFER
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A1
A2
A3
A4
A5
A6
A7
A8
A17
VCC
A16
A15
A14
A13
I/O3
I/O2
I/O1
I/O0
A9
A0
A10
CE
OE
NC
A12
A11
WE
WE
CE
I/O
0
I/O
1
I/O
2
I/O
3
A
2
A
3
A
4
A
6
A
7
A
8
A
9
A
5
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 2 of 10
Selection Guide
CY7C106D-10
CY7C1006D-10 CY7C106D-12
CY7C1006D-12
Maximum Access Time (ns) 10 12
Maximum Operating Current (mA) 60 50
Maximum Standby Current (mA) 3 3
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 3 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[2] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z S tate[2]....................................–0.5V to VCC + 0.5V
DC Input V oltage[2].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW ).........................................20 mA
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –45°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter Description Test Con ditions
7C106D-10
7C1006D-10 7C106D-12
7C1006D-12
UnitMin. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min. , IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIL Input LOW Voltage[2] –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VI < V CC,
Output Disabled –1 +1 –1 +1 µA
IOS Output Short
Circuit Curre nt[3] VCC = Max., VOUT = GND –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC 60 50 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
10 10 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V, f=0
33mA
Capacitance[4]
Parameter Description Test Co nditions Max. Un it
CIN: A d d r e s s e s Input Capacitance T A = 25°C, f = 1 MHz,
VCC = 5.0V 7pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
Thermal Resistance[4]
Parameter Description Test Conditions All-Packages Unit
ΘJA Thermal Resistance
(Junction to Ambient)[4] Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board TBD °C/W
ΘJC Thermal Resistance
(Junction to Case)[4] TBD °C/W
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 4 of 10
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[5]
Parameter Description
7C106D-10
7C1006D-10 7C106D-12
7C1006D-12
UnitMin. Max. Min. Max.
Read Cycle
tpower[6] VCC(typical) to the first access 100 100 µs
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[7, 8] 56ns
tLZCE CE LOW to Low Z[8] 33ns
tHZCE CE HIGH to High Z[7, 8] 56ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 10 12 ns
Write Cycle[9, 10]
tWC Write Cycle Ti me 10 12 ns
tSCE CE LOW to Write End 8 10 ns
tAW Address Set-Up to Write End 7 10 ns
tHA Address Hold from Write End 0 0 ns
Notes:
4. Tested initially and after any design or process changes that may af fect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load cap acitanc e.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE ar e specified with a lo ad capacita nce of 5 pF as in p art (b) of AC Test Loads. Tran sition is measured ±200 mV from steady-st ate voltag e.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time o f the memory is defined by the overlap of C E and WE LOW . CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10.The minimum write cycle time for Write Cycle No. 3 (WE controlled , OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
30 pF
INCLUDING
5V
OUTPUT
5 pF
(c)
R1 480 Ω
R2
255 ΩR2
255Ω
Rise Time < 1V/ns Fall Time < 1V/ns
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
OUTPUT Z = 50Ω
50Ω
1.5V
(a)
10-ns Device
OUTPUT 167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
High-Z Characteristics
12 -ns Devices
JIG AND
SCOPE INCLUDING
JIG AND
SCOPE
(b)
R1 480 Ω
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 5 of 10
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 7 10 ns
tSD Data Set-Up to Write End 6 7 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[8] 32ns
tHZWE WE LOW to High Z[7, 8] 66ns
Switching Characteristics Over the Operating Range[5]
Parameter Description
7C106D-10
7C1006D-10 7C106D-12
7C1006D-12
UnitMin. Max. Min. Max.
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions Min. Max. Unit
VDR VCC for Dat a Retention 2.0 V
ICCDR Data Retention Current Non-L, Com’l / Ind’l VCC = VDR = 2. 0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
3mA
L-Version Only 1.2 mA
tCDR[4] Chip Deselect to Data Retention Time 0 ns
tR[11, 12] Operation Recove ry Time tRC ns
Data Retention Waveform
4.5V4.5V
CE
VCC tCDR
VDR >2V
DATA RETENTION MODE
tR
Switching Waveforms
Read Cycle No.1[13, 14]
Notes:
11.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
12.tr < 3 ns for all speeds.
13.Device is continuously selected, OE and CE = VIL.
14.WE is HIGH for read cycle.
1
PREVIOUS DA TA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 6 of 10
Read Cycle No. 2 (OE Controlled)[14, 15]
Write Cycle No. 1 (CE Controlled)[16, 17]
Notes:
15.Address valid prior to or coincident with CE transition LOW.
16.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17.Data I/O is high impedance if OE = VIH.
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 7 of 10
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 17]
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA I/O
OE
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA I/O
Truth Table
CE OE WE Input/Output Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 8 of 10
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C106D-10VXC V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial
CY7C1006D-10VXC V21 28-Lead (300-Mil) Molded SOJ (Pb-Free)
CY7C106D-10VXI V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial
CY7C1006D-10VXI V21 28-Lead (300-Mil) Molded SOJ (Pb-Free)
12 CY7C106D-12VXC V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial
CY7C1006D-12VXC V21 28-Lead (300-Mil) Molded SOJ (Pb-Free)
CY7C106D-12VXI V28 28-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial
CY7C1006D-12VXI V21 28-Lead (300-Mil) Molded SOJ (Pb-Free)
Shaded areas conta i n advance information. Please contact your local Cypress sales representative for availability of the se parts.
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
DIMENSIONS IN INCHES MIN.
MAX.
PIN1ID
0.291
0.300
0.050
TYP.
0.007
0.013
0.330
0.350
0.120
0.140
0.025 MIN.
0.262
0.272
0.697
0.713
0.013
0.019 0.014
0.020
0.032
0.026
A
A
DETAIL
EXTERNAL LEAD DESIGN
OPTION 1 OPTION 2
114
15 28
0.004
SEATING PLANE
28-Lead (300-Mil) Molded SOJ V21
51-85031-*B
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 9 of 10
© Cypress Semi con duct or Cor po rati on , 20 05 . The information contained he rein is subject to change without notice. Cypress Semiconductor Corpo ration assume s no resp onsib ility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthe rmore, Cypress does not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
PIN 1 I.D
.435
.395 .445
.405
.128
.148
.360
.380
.026
.015
.032
.020
DIMENSIONS IN INCHES MIN.
MAX.
.025 MIN.
.007
.013
.720
.730
114
15 28
0.004
SEATING PLANE
28-Lead (400-Mil) Molded SOJ V28
51-85032-*B
PRELIMINARY CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *C Page 10 of 10
Document History Page
Document Title: CY7C106D, CY7C1006D 1- Mbit (256K x 4) Static RAM (Preliminary)
Document Number: 38-05459
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance information data sheet for C9 IPP
*A 233693 See ECN RKF ICC,ISB1,ISB2 Specs are modified as per EROS (Spec # 01-2165)
Pb-free offering in the ‘ordering information’
*B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table
Shaded ‘Ordering Information’
*C 307596 See ECN RKF Reduced Speed bins to -10 and -12 ns
