LTC2320-16
1
232016fb
For more information www.linear.com/LTC2320-16
TYPICAL APPLICATION
FEATURES DESCRIPTION
Octal, 16-Bit, 1.5Msps/Ch
Simultaneous Sampling ADC
The LT C
®
2320-16 is a low noise, high speed octal 16-bit
successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2320-16
has an 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range with high
common mode rejection. The LTC2320-16 achieves ±2LSB
INL typical, no missing codes at 16 bits and 82dB SNR.
The LTC2320-16 has an onboard low drift (20ppm/°C max)
2.048V or 4.096V temperature-compensated reference.
The LTC2320-16 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
1.5Msps per channel throughput with no latency makes
the LTC2320-16 ideally suited for a wide variety of high
speed applications. The LTC2320-16 dissipates only 20mW
per channel and offers nap and sleep modes to reduce the
power consumption to 26μW for further power savings
during inactive periods.
32k Point FFT fSMPL = 1.5Msps,
fIN = 500kHz
APPLICATIONS
n 1.5Msps/Ch Throughput Rate
n Eight Simultaneously Sampling Channels
n Guaranteed 16-Bit, No Missing Codes
n 8VP-P Differential Inputs with Wide Input
Common Mode Range
n 82dB SNR (Typ) at fIN = 500kHz
n –90dB THD (Typ) at fIN = 500kHz
n Guaranteed Operation to 125°C
n Single 3.3V or 5V Supply
n Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
n 1.8V to 2.5V I/O Voltages
n CMOS or LVDS SPI-Compatible Serial I/O
n Power Dissipation 20mW/Ch (Typ)
n Small 52-Pin (7mm × 8mm) QFN Package
n High Speed Data Acquisition Systems
n Communications
n Optical Networking
n Multiphase Motor Control
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
SNR = 82.2dB
THD = –91.2dB
SINAD = 81.8dB
SFDR = 94.7dB
FREQUENCY (MHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
–140
–120
–100
–80
–60
–40
–20
0
IN
232016 TA01b
BIPOLAR UNIPOLAR
ARBITRARY
TRUE DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
IN+, IN–
DIFFERENTIAL
0V
VDD VDD
VDD VDD
0V
0V 0V
1µF
10µF
10µF
10µF
10µF
10µF
1µF
S/H
AIN1+
AIN1–
S/H
AIN2+
AIN2–
MUX
16-BIT
SAR ADC
S/H
AIN3+
AIN3–
S/H
AIN4+
AIN4–
MUX
16-BIT
SAR ADC
S/H
AIN5+
AIN5–
S/H
AIN6+
AIN6–
MUX
16-BIT
SAR ADC
S/H
AIN7+
AIN7–
S/H
AIN8+
AIN8–
MUX
16-BIT
SAR ADC
OVDD
REF
GND
GND
REFOUT1
V
DD
1.8V TO 2.5V
3.3V OR 5V
CMOS/LVDS
SDR/DDR
REFBUFEN
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
SDO8
CLKOUT
SCK
CNV
SAMPLE
CLOCK
REFOUT2
REFOUT3
REFOUT4
EIGHT SIMULTANEOUS
SAMPLING CHANNELS
LTC2320-16
232016 TA01a
LTC2320-16
2
232016fb
For more information www.linear.com/LTC2320-16
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ..................................................6V
Supply Voltage (OVDD) ................................................3V
Analog Input Voltage
AIN+, AIN– (Note 3) ................... –0.3V to (VDD + 0.3V)
REFOUT1,2,3,4........................ .–0.3V to (VDD + 0.3V)
CNV........................................ –0.3V to (OVDD + 0.3V)
Digital Input Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Operating Temperature Range
LTC2320C ................................................ 0°C to 70°C
LTC2320I .............................................–40°C to 85°C
LTC2320H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
1615 17 18 19
TOP VIEW
53
GND
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
20 21 22 23 24 25 26
5152 50 49 48 47 46 45 44 43 42 41
33
34
35
36
37
38
39
40
8
7
6
5
4
3
2
1AIN6–
AIN6+
GND
AIN5–
AIN5+
REFOUT3
GND
REF
REFOUT2
AIN4–
AIN4+
GND
AIN3–
AIN3+
SDO8/SDOD–
SDO7/SDOD+
GND
OVDD
SDO6/SDOC–
SDO5/SDOC+
CLKOUTEN/CLKOUT–
CLKOUT/CLKOUT+
GND
OVDD
SDO4/SDOB–
SDO3/SDOB+
SDO2/SDOA–
SDO1/SDOA+
VDD
AIN7+
AIN7–
GND
AIN8+
AIN8–
GND
REFOUT4
VDD
REFBUFEN
DNC/SCK–
SCK/SCK+
VDD
AIIN2–
AIN2+
GND
AIN1–
AIN1+
VDD
REFOUT1
SDR/DDR
CNV
CMOS/LVDS
GND
32
31
30
29
28
27
9
10
11
12
13
14
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2320CUKG-16#PBF LTC2320CUKG-16#TRPBF 2320UKG-16 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2320IUKG-16#PBF LTC2320IUKG-16#TRPBF 2320UKG-16 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
LTC2320HUKG-16#PBF LTC2320HUKG-16#TRPBF 2320UKG-16 52-Lead (7mm × 8mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC2320-16#orderinfo
LTC2320-16
3
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For more information www.linear.com/LTC2320-16
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+Absolute Input Range (AIN+ to AIN–) (Note 5) l0 VDD V
VIN–Absolute Input Range (AIN+ to AIN–) (Note 5) l0 VDD V
VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN–l–REFOUT1,2,3,4 REFOUT1,2,3,4 V
VCM Common Mode Input Range VCM = (VIN+ – VIN–)/2 l0 VDD V
IIN Analog Input DC Leakage Current l–1 1 μA
CIN Analog Input Capacitance 10 pF
CMRR Input Common Mode Rejection Ratio fIN = 500kHz 102 dB
VIHCNV CNV High Level Input Voltage l1.5 V
VILCNV CNV Low Level Input Voltage l0.5 V
IINCNV CNV Input Current l–10 10 μA
CONVERTER CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l16 Bits
No Missing Codes l16 Bits
Transition Noise 1.5 LSBRMS
INL Integral Linearity Error (Note 6) l–12 ±2 12 LSB
DNL Differential Linearity Error l–0.99 ±0.4 0.99 LSB
BZE Bipolar Zero-Scale Error (Note 7) l–12 0 12 LSB
Bipolar Zero-Scale Error Drift 0.01 LSB/°C
FSE Bipolar Full-Scale Error VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) (Note 7) l–30 ±10 30 LSB
Bipolar Full-Scale Error Drift VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) 15 ppm/°C
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l75.5 81 dB
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference 81 dB
SNR Signal-to-Noise Ratio fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l76.5 82 dB
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference 82.5 dB
THD Total Harmonic Distortion fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l–90 –78 dB
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference –91 dB
SFDR Spurious Free Dynamic Range fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l78 93 dB
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference 93 dB
–3dB Input Bandwidth 55 MHz
Aperture Delay 500 ps
Aperture Delay Matching 500 ps
Aperture Jitter 1 psRMS
Transient Response Full-Scale Step 30 ns
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
LTC2320-16
4
232016fb
For more information www.linear.com/LTC2320-16
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFOUT1,2,3,4 Internal Reference Output Voltage 4.75V < VDD < 5.25V
3.13V < VDD < 3.47V
l
l
4.078
2.034
4.096
2.048
4.115
2.064
V
V
VREF Temperature Coefficient (Note 14) l3 20 ppm/°C
REFOUT1,2,3,4 Output Impedance 0.25 Ω
VREFOUT1,2,3,4 Line Regulation 4.75V < VDD < 5.25V 0.3 mV/V
IREFOUT1,2,3,4 External Reference Current REFBUFEN = 0V
REFOUT1,2,3,4 = 4.096V
REFOUT1,2,3,4 = 2.048V
(Notes 9, 10)
385
204
μA
μA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMOS Digital Inputs and Outputs CMOS/LVDS = GND
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA
CIN Digital Input Capacitance l5 pF
VOH High Level Output Voltage IO = –500μA lOVDD – 0.2 V
VOL Low Level Output Voltage IO = 500μA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA
ISOURCE Output Source Current VOUT = 0V l–10 mA
ISINK Output Sink Current VOUT = OVDD l10 mA
LVDS Digital Inputs and Outputs CMOS/LVDS = OVDD
VID LVDS Differential Input Voltage 100Ω Differential Termination
OVDD = 2.5V
l240 600 mV
VIS LVDS Common Mode Input Voltage 100Ω Differential Termination
OVDD = 2.5V
l1 1.45 V
VOD LVDS Differential Output Voltage 100Ω Differential Termination
OVDD = 2.5V
l220 350 600 mV
VOS LVDS Common Mode Output Voltage 100Ω Differential Termination
OVDD = 2.5V
l0.85 1.2 1.4 V
VOD_LP Low Power LVDS Differential Output Voltage 100Ω Differential Termination
OVDD = 2.5V
l100 200 350 mV
VOS_LP Low Power LVDS Common Mode Output Voltage 100Ω Differential Termination
OVDD = 2.5V
l0.85 1.2 1.4 V
LTC2320-16
5
232016fb
For more information www.linear.com/LTC2320-16
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation
3.3V Operation
l
l
4.75
3.13
5.25
3.47
V
V
IVDD Supply Current 1.5Msps Sample Rate (IN+ = IN– = 0V) l31 39 mA
CMOS I/O Mode CMOS/LVDS = GND
OVDD Supply Voltage l1.71 2.63 V
IOVDD Supply Current 1.5Msps Sample Rate (CL = 5pF) l4.4 8 mA
INAP Nap Mode Current Conversion Done (IVDD)l5.3 6.9 mA
ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD)l20 110 µA
PD_3.3V Power Dissipation VDD = 3.3V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
102
18
20
133
22.7
355
mW
mW
µW
PD_5V Power Dissipation VDD = 5V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
162
27
30
210
34.4
525
mW
mW
µW
LVDS I/O Mode CMOS/LVDS = OVDD, OVDD = 2.5V
OVDD Supply Voltage l2.37 2.63 V
IOVDD Supply Current 1.5Msps Sample Rate (CL = 5pF, RL = 100Ω) l26 38 mA
INAP Nap Mode Current Conversion Done (IVDD)l5.3 6.9 mA
ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD)l20 110 µA
PD_3.3V Power Dissipation VDD = 3.3V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
151
52
80
248
61.5
355
mW
mW
µW
PD_5V Power Dissipation VDD = 5V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
214
52
30
300
73
525
mW
mW
µW
LTC2320-16
6
232016fb
For more information www.linear.com/LTC2320-16
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l1.5 Msps
tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT l0.667 1000 µs
tCONV Conversion Time l450 ns
tCNVH CNV High Time l30 ns
tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC – tCONV 215 ns
tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10µF 50 ms
CMOS I/O Mode, SDR CMOS/LVDS = GND, SDR/ DDR = GND
tSCK SCK Period (Note 13) l9.1 ns
tSCKH SCK High Time l4.1 ns
tSCKL SCK Low Time l4.1 ns
tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF (Note 12) l0 1.5 ns
tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l2 4.5 ns
tDCNVSDOZ Bus Relinquish Time After CNV↑(Note 11) l3 ns
tDCNVSDOV SDO Valid Delay from CNV↓(Note 11) l3 ns
tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns
CMOS I/O Mode, DDR CMOS/LVDS = GND, SDR/ DDR = OVDD
tSCK SCK Period l18.2 ns
tSCKH SCK High Time l8.2 ns
tSCKL SCK Low Time l8.2 ns
tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF, OVDD = 2.5V l0 1.5 ns
tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l2 4.5 ns
tDCNVSDOZ Bus Relinquish Time After CNV↑(Note 11) l3 ns
tDCNVSDOV SDO Valid Delay from CNV↓(Note 11) l3 ns
tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns
LVDS I/O Mode, SDR CMOS/LVDS = OVDD, SDR/DDR = GND
tSCK SCK Period l3.3 ns
tSCKH SCK High Time l1.5 ns
tSCKL SCK Low Time l1.5 ns
tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF, OVDD = 2.5V l0 1.5 ns
tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l2 4 ns
tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns
LVDS I/O Mode, DDR CMOS/LVDS = OVDD, SDR/DDR = OVDD
tSCK SCK Period l6.6 ns
tSCKH SCK High Time l3 ns
tSCKL SCK Low Time l3 ns
tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF (Note 12) l0 1.5 ns
tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l2 4 ns
tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
LTC2320-16
7
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For more information www.linear.com/LTC2320-16
Figure 1. Voltage Levels for Timing Specifications
0.8 • OVDD
0.2 • OVDD
50% 50%
232016 F01
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
tDELAY
tWIDTH
tDELAY
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below ground, or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle input
currents up to 100mA below ground, or above VDD or OVDD, without latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 1.5MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with REF = 4.096V.
Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer
must be turned off by setting REFBUFEN = 0V.
Note 10: fSMPL = 1.5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.
Note 13: tSCK of 9.1ns allows a shift clock frequency up to 105MHz for
rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OVDD
logic levels.
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
LTC2320-16
8
232016fb
For more information www.linear.com/LTC2320-16
TYPICAL PERFORMANCE CHARACTERISTICS
THD, Harmonics vs Input Common
Mode
SNR, SINAD vs Reference Voltage,
fIN = 500kHz
32k Point FFT, IMD, fSMPL = 1.5Msps,
AIN+ = 490kHz, AIN– = 510kHz
32k Point FFT, fSMPL = 1.5Msps,
fIN = 500kHz
SNR, SINAD vs Input Frequency
(1kHz to 750kHz)
THD, Harmonics vs Input
Frequency (1kHz to 750kHz)
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 =
4.096V, fSMPL = 1.5Msps, unless otherwise noted.
σ = 1.5
CODE
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
4000
8000
12000
16000
20000
24000
28000
32000
36000
40000
DC HISTOGRAM
232016 G03
SNR = 82.2dB
THD = –91.2dB
SINAD = 81.8dB
SFDR = 94.7dB
FREQUENCY (MHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
SMPL
IN
232016 G04
SNR
SINAD
FREQUENCY (MHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
81.0
81.2
81.4
81.6
81.8
82.0
82.2
82.4
82.6
82.8
83.0
(1kHz to 750kHz)
232016 G05
THD
HD3
HD2
fIN = 500kHz
INPUT COMMON MODE (V)
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
–120
–116
–112
–108
–104
–100
–96
–92
–88
–84
–80
THD, HARMONICS LEVEL (dBFS)
Mode
232016 G07
THD = 88dB
V
CM
= 20kHz, 4VP-P
FREQUENCY (MHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
–140
–120
–100
–80
–60
–40
–20
0
IN
IN
232016 G09
OUTPUT CODE
–32768
–16384
0
16384
32768
–8
–6
–4
–2
0
2
4
6
8
INL ERROR (LSB)
232016 G01
THD
HD3
HD2
FREQUENCY (MHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
–120
–116
–112
–108
–104
–100
–96
–92
–88
–84
–80
232016 G06
OUTPUT CODE
–32768
–16384
0
16384
32768
–1.0
–0.5
0
0.5
1.0
vs Output Code
232016 G02
SNR
SINAD
fIN = 500kHz
V
REFOUT
(V)
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
f
IN
= 500kHz
232016 G08
LTC2320-16
9
232016fb
For more information www.linear.com/LTC2320-16
TYPICAL PERFORMANCE CHARACTERISTICS
Step Response
(Fine Settling)
External Reference Supply
Current vs Sample Frequency REF Output vs Temperature
Offset Error vs Temperature
Supply Current
vs Sample Frequency
OVDD Current vs SCK Frequency,
CLOAD = 10pF
CMRR vs Input Frequency Crosstalk vs Input Frequency
Step Response
(Large Signal Settling)
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 =
4.096V, fSMPL = 1.5Msps, unless otherwise noted.
V
CM
= 4VP-P
FREQUENCY (kHz)
0
500
1000
1500
90
95
100
105
110
115
120
CMRR (dB)
232016 G10
FREQUENCY (kHz)
0
100
200
300
400
500
600
700
–100
–99
–98
–97
–96
–95
–94
–93
–92
–91
–90
232016 G11
V
DD
= 3.3V
V
DD
= 5V
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–3.00
–2.50
–2.00
–1.50
–1.00
–0.50
0
0.50
1.00
REF Output vs Temperature
232016 G15
V
DD
= 5V
V
DD
= 3.3V
SAMPLE FREQUENCY (Msps)
0
0.3
0.6
0.9
1.2
1.5
19
21
23
25
27
29
31
33
SUPPLY CURRENT (mA)
232016 G17
4.096V RANGE
IN+ = 1.5MHz SQUARE WAVE
IN– = 0V
SETTLING TIME (ns)
–20
–10
0
10
20
30
40
50
60
70
80
90
–8192
0
8192
16384
24576
32768
(Large Signal Settling)
232016 G12
4.096V RANGE
SETTLING TIME (ns)
–20
–10
0
10
20
30
40
50
60
70
80
90
–250
–200
–150
–100
–50
0
50
100
150
200
250
DEVIATION FROM FINAL VALUE (LSB)
(Fine Settling)
232016 G13
IN+ = 1.5MHz
SQUARE WAVE
IN– = 0V
V
REFOUT1,2,3,4
= 4.096V
V
REFOUT1,2,3,4
= 2.048V
REFBUFEN = 0V
(EXT REF BUF
OVERDRIVING REF BUF)
SAMPLE FREQUENCY (Msps)
0
0.3
0.6
0.9
1.2
1.5
0
50
100
150
200
250
300
350
400
SUPPLY CURRENT (μA)
Current vs Sample Frequency
232016 G14
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–3
–2
–1
0
1
2
3
LSB
Offset Error vs Temperature
232016 G16
LVDS (4 LANES)
CMOS (2.5V, 8 LANES)
LOW POWER LVDS (4 LANES)
CMOS(1.8V, 8 LANES)
FULL SCALE SINUSOIDAL INPUT
SCK FREQUENCY (MHz)
0
50
100
150
200
250
300
0
1
2
3
4
5
6
7
8
12
14
16
18
20
22
24
26
28
30
32
DD
DD
C
LOAD
= 10pF,
232016 G18
LTC2320-16
10
232016fb
For more information www.linear.com/LTC2320-16
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL
I/OMODES
AIN6+, AIN6– (Pins 2, 1): Analog Differential Input Pins.
Full-scale range (AIN6+ – AIN6–) is ±REFOUT3 voltage.
These pins can be driven from VDD to GND.
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.
These pins and exposed pad (Pin 53) must be tied directly
to a solid ground plane.
AIN5+, AIN5– (Pins 5, 4): Analog Differential Input Pins.
Full-scale range (AIN5+ – AIN5–) is ±REFOUT3 voltage.
These pins can be driven from VDD to GND.
REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
REF (Pin 8): Common 4.096V reference output. Decouple
to GND with a 1μF low ESR ceramic capacitor. May be
overdriven with a single external reference to establish a
common reference for ADC cores 1 through 4.
REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
AIN4+, AIN4– (Pins 11, 10): Analog Differential Input Pins.
Full-scale range (AIN4+ – AIN4–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
AIN3+, AIN3– (Pins 14, 13): Analog Differential Input Pins.
Full-scale range (AIN3+ – AIN3–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
VDD (Pins 15, 21, 44, 52): Power Supply. Bypass VDD to
GND with a 10µF ceramic capacitor and a 0.1µF ceramic
capacitor close to the part. The VDD pins should be shorted
together and driven from the same supply.
AIN2+, AIN2– (Pins 17, 16): Analog Differential Input Pins.
Full-scale range (AIN2+ – AIN2–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
AIN1+, AIN1– (Pins 20, 19): Analog Differential Input Pins.
Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
REFOUT1 (Pin 22): Reference Buffer 1 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
SDR/DDR (Pin 23): Double Data Rate Input. Controls the
frequency of SCK and CLKOUT. Tie to GND for the falling
edge of SCK to shift each serial data output (Single Data
Rate, SDR). Tie to OVDD to shift serial data output on each
edge of SCK (Double Data Rate, DDR). CLKOUT will be a
delayed version of SCK for both pin states.
CNV (Pin 24): Convert Input. This pin, when high, defines
the acquisition phase. When this pin is driven low, the
conversion phase is initiated and output data is clocked
out. This input must be driven at OVDD levels with a low
jitter pulse. This pin is unaffected by the CMOS/LVDS pin.
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
to enable CMOS mode, tie to OVDD to enable LVDS mode.
Float this pin to enable low power LVDS mode.
OVDD (Pins 31, 37): I/O Interface Digital Power. The range
of OVDD is 1.71V to 2.63V. This supply is nominally set
to the same supply as the host interface (CMOS: 1.8V or
2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38)
with 0.1µF capacitors.
LTC2320-16
11
232016fb
For more information www.linear.com/LTC2320-16
PIN FUNCTIONS
REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie
to VDD when using the internal reference. Tie to ground
to disable the internal REFOUT1–4 buffers for use with
external voltage references. This pin has a 500k internal
pull-up to VDD.
REFOUT4 (Pin 45): Reference Buffer 4 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
AIN8+, AIN8– (Pins 48, 47): Analog Differential Input Pins.
Full-scale range (AIN8+ – AIN8–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
AIN7+, AIN7– (Pins 51, 50): Analog Differential Input Pins.
Full-scale range (AIN7+ – AIN7–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
Exposed Pad (Pin 53): Ground. Solder this pad to ground.
CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)
SDO1 (Pin 27): CMOS Serial Data Output for ADC Chan-
nel 1. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN1 on SDO1 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH2, CH3, CH4,
CH5, CH6, CH7, CH8).
SDO2 (Pin 28): CMOS Serial Data Output for ADC Chan-
nel 2. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN2 on SDO2 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH3, CH4, CH5,
CH6, CH7, CH8, CH1).
SDO3 (Pin 29): CMOS Serial Data Output for ADC Chan-
nel 3. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN3 on SDO3 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH4, CH5, CH6,
CH7, CH8, CH1, CH2).
SDO4 (Pin 30): CMOS Serial Data Output for ADC Chan-
nel 4. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN4 on SDO4 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH5, CH6, CH7,
CH8, CH1, CH2, CH3).
CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver (FPGA). The logic level is determined by
OVDD. This pin echoes the input at SCK with a small delay.
CLKOUTEN (Pin 34): CLKOUT can be disabled by tying
Pin 34 to OVDD for a small power savings. If CLKOUT is
used, ground this pin.
SDO5 (Pin 35): CMOS Serial Data Output for ADC Chan-
nel 5. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN5 on SDO5 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH6, CH7, CH8,
CH1, CH2, CH3, CH4).
SDO6 (Pin 36): CMOS Serial Data Output for ADC Chan-
nel 6. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN6 on SDO6 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH7, CH8, CH1,
CH2, CH3, CH4, CH5).
LTC2320-16
12
232016fb
For more information www.linear.com/LTC2320-16
SDO7 (Pin 39): CMOS Serial Data Output for ADC Chan-
nel 7. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN7 on SDO7 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH8, CH1, CH2,
CH3, CH4, CH5, CH6).
SDO8 (Pin 40): CMOS Serial Data Output for ADC Chan-
nel 8. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN8 on SDO8 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH1, CH2, CH3,
CH4, CH5, CH6, CH7).
SCK (Pin 41): Serial Data Clock Input. The falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins in SDR mode (DDR = LOW). In DDR mode
(SDR/DDR = HIGH) each edge of this clock shifts the
conversion result MSB first onto the SDO pins. The logic
level is determined by OVDD.
DNC (Pin 42): In CMOS mode, do not connect this pin.
LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR
FLOAT)
SDOA+, SDOA– (Pins 27, 28): LVDS Serial Data Output for
ADC Channels 1 and 2. The conversion result is shifted CH1
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 32 SCK edges are required
for 16-bit conversion data to be read from AIN1 and AIN2
on SDOA in SDR mode, 16 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH3, CH4, CH5, CH6, CH7, CH8).Terminate
with a 100Ω resistor at the receiver (FPGA).
SDOB+, SDOB– (Pins 29, 30): LVDS Serial Data Output for
ADC Channels 3 and 4. The conversion result is shifted CH3
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 32 SCK edges are required
for 16-bit conversion data to be read from AIN3 and AIN4
on SDOB in SDR mode, 16 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH5, CH6, CH7, CH8, CH1, CH2).Terminate
with a 100Ω resistor at the receiver (FPGA).
CLKOUT+, CLKOUT– (Pins 33, 34): Serial Data Clock
Output. CLKOUT provides a skew-matched clock to
latch the SDO output at the receiver. These pins echo the
input at SCK with a small delay. These pins must be dif-
ferentially terminated by an external 100Ω resistor at the
receiver(FPGA).
SDOC+, SDOC– (Pins 35, 36): LVDS Serial Data Output for
ADC channels 5 and 6. The conversion result is shifted CH5
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 32 SCK edges are required
for 16-bit conversion data to be read from AIN5 and AIN6
on SDOA in SDR mode, 16 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH7, CH8, CH1, CH2, CH3, CH4).Terminate
with a 100Ω resistor at the receiver (FPGA).
SDOD+, SDOD– (Pins 39, 40): LVDS Serial Data Output
for ADC Channels 7 and 8. The conversion result is shifted
CH7 MSB first on each falling edge of SCK in SDR mode
and each SCK edge in DDR mode. 32 SCK edges are re-
quired for 16-bit conversion data to be read from AIN7 and
AIN8 on SDOA in SDR mode, 16 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH1, CH2, CH3, CH4, CH5, CH6).Terminate
with a 100Ω resistor at the receiver (FPGA).
SCK+, SCK– (Pins 41, 42): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins in SDR mode (SDR/DDR = LOW).
In DDR mode (SDR/DDR = HIGH) each edge of this clock
shifts the conversion result MSB first onto the SDO pins.
These pins must be differentially terminated by an external
100Ω resistor at the receiver (ADC).
PIN FUNCTIONS
LTC2320-16
13
232016fb
For more information www.linear.com/LTC2320-16
FUNCTIONAL BLOCK DIAGRAM
27
28
22
CMOS
I/O
SDO1
SDO2
20
24
19
AIN1+
REF
AIN1–
CNV
VDD
(15, 21, 44, 52)
REF ×1
41
42
CMOS
RECEIVERS
OUTPUT
CLOCK DRIVER
+
–
17
16
AIN2+
AIN2–+
–
S/H
S/H
16-BIT
SAR ADC
29
30
33
34
23
9
CMOS
I/O
SDO3
SDO4
14
13
AIN3+
AIN3–
REF ×1
+
–
11
10
AIN4+
AIN4–+
–
S/H
S/H
16-BIT
SAR ADC
35
36
6
CMOS
I/O
SDO6
SDO6
5
4
AIN5+
DNC
SCK
AIN5–
REF ×1
+
–
2
1
AIN6+
AIN6–+
–
S/H
S/H
16-BIT
SAR ADC
39
40
43
25
45
CMOS
I/O
SDO7
SDO8
REFOUT4
CMOS/LVDS
51
50
AIN7+
AIN7–
REF ×1
+
–
48
47
8
AIN8+
AIN8–+
–
S/H
S/H
16-BIT
SAR ADC
SDR/DDR
REFOUT3
×1.7
×3.4 1.2V INT REF REFBUFEN
OVDD (31, 37)
CLKOUTEN
CLKOUT
REFOUT2
REFOUT1
250μA
GND
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
232016 BDa
MUX
MUX
MUX
MUX
CMOS IO Mode
LTC2320-16
14
232016fb
For more information www.linear.com/LTC2320-16
27
28
22
LVDS
I/O
SDOA+
SDOA–
20
24
19
AIN1+
REF
AIN1–
CNV
VDD
(15, 21, 44, 52)
REF ×1
41
42
LVDS
RECEIVERS
OUTPUT
CLOCK DRIVER
+
–
17
16
AIN2+
AIN2–+
–
S/H
S/H
16-BIT
SAR ADC
29
30
33
34
23
9
LVDS
I/O
SDOB+
SDOB–
14
13
AIN3+
AIN3–
REF ×1
+
–
11
10
AIN4+
AIN4–+
–
S/H
S/H
16-BIT
SAR ADC
35
36
6
LVDS
I/O
SDOC+
SDOC–
5
4
AIN5+
SCK–
SCK+
AIN5–
REF ×1
+
–
2
1
AIN6+
AIN6–+
–
S/H
S/H
16-BIT
SAR ADC
39
40
43
25
45
LVDS
I/O
SDOD+
SDOD–
REFOUT4
CMOS/LVDS
51
50
AIN7+
AIN7–
REF ×1
+
–
48
47
8
AIN8+
AIN8–+
–
S/H
S/H
16-BIT
SAR ADC
SDR/DDR
REFOUT3
×1.7
×3.4 1.2V INT REF REFBUFEN
OVDD (31, 37)
CLKOUT–
CLKOUT+
REFOUT2
REFOUT1
250μA
GND
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
232016 BDb
MUX
MUX
MUX
MUX
LVDS IO Mode
FUNCTIONAL BLOCK DIAGRAM
LTC2320-16
15
232016fb
For more information www.linear.com/LTC2320-16
TIMING DIAGRAM
SDR Mode, CMOS (Reading 1 Channel per SDO)
DDR Mode, CMOS (Reading 1 Channel per SDO)
D15
CNV
SCK
SDO1
CLKOUT
D14
Hi-Z
CMOS SDR Mode
1
2
DONT CARE
ACQUIRE
CONVERT
SAMPLE N
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMPLE N+1
D15
SDO8
D14
Hi-Z
DONT CARE
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
CHANNEL 8
CONVERSION N
CHANNEL 1
CONVERSION N
Hi-Z
Hi-Z
Hi-Z
Hi-Z
232016 TD01
D15
CNV
SCK
SDO1
CLKOUT
D14
Hi-Z
1
2
DONT CARE
ACQUIRE
CONVERT
SAMPLE N
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMPLE N+1
D15
SDO8
D14
Hi-Z
DONT CARE
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
CHANNEL 8
CONVERSION N
CHANNEL 1
CONVERSION N
Hi-Z
Hi-Z
Hi-Z
Hi-Z
232016 TD02
LTC2320-16
16
232016fb
For more information www.linear.com/LTC2320-16
SDR Mode, LVDS (Reading 2 Channels per SDO Pair)
DDR Mode, LVDS (Reading 2 Channels per SDO Pair)
D15
CNV
SCK
SDOA
CLKOUT
D14
1
2
DONT CARE
ACQUIRE
CONVERT
SAMPLE N
CHANNEL 1
CONVERSION N
CHANNEL 3
CONVERSION N
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMPLE N+1
D15
SDOD
D14
DONT CARE
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CHANNEL 7
CONVERSION N
CHANNEL 1
CONVERSION N
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CHANNEL 2
CONVERSION N
CHANNEL 8
CONVERSION N
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D15
232016 TD03
D15
CNV
SCK
SDOA
CLKOUT
D14
LVDS DDR Mode
1
2
DONT CARE
ACQUIRE
CONVERT
SAMPLE N
CHANNEL 1
CONVERSION N
CHANNEL 3
CONVERSION N
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMPLE N+1
D15
SDOD
D14
DONT CARE
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
CHANNEL 7
CONVERSION N
CHANNEL 1
CONVERSION N
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CHANNEL 2
CONVERSION N
CHANNEL 8
CONVERSION N
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
232016 TD04
TIMING DIAGRAM
LTC2320-16
17
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
OVERVIEW
The LTC2320-16 is a low noise, high speed 16-bit succes-
sive approximation register (SAR) ADC with differential
inputs and a wide input common mode range. Operating
from a single 3.3V or 5V supply, the LTC2320-16 has a
4VP-P or 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range. The
LTC2320-16 achieves ±2LSB INL typical, no missing codes
at 16 bits and 82dB SNR.
The LTC2320-16 has an onboard reference buffer and low
drift (20ppm/°C max) 4.096V temperature-compensated
reference. The LTC2320-16 also has a high speed SPI-
compatible serial interface that supports CMOS or LVDS.
The fast 1.5Msps per channel throughput with no latency
makes the LTC2320-16 ideally suited for a wide variety of
high speed applications. The LTC2320-16 dissipates only
20mW per channel. Nap and sleep modes are also provided
to reduce the power consumption of the LTC2320-16 dur-
ing inactive periods for further power savings.
CONVERTER OPERATION
The LTC2320-16 operates in two phases. During the ac-
quisition phase, the sample capacitor is connected to the
analog input pins AIN+ and AIN– to sample the differential
analog input voltage, as shown in Figure 3. A falling edge on
the CNV pin initiates a conversion. During the conversion
phase, the 16-bit CDAC is sequenced through a successive
approximation algorithm effectively comparing the sampled
input with binary-weighted fractions of the reference volt-
age (e.g., VREFOUT/2, VREFOUT/4 … VREFOUT/32768) using
a differential comparator. At the end of conversion, a CDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 16-bit digital output code
for serial transfer.
TRANSFER FUNCTION
The LTC2320-16 digitizes the full-scale voltage of 2 ×
REFOUT1,2,3,4 into 216 levels, resulting in an LSB size of
125µV with REF = 4.096V. The ideal transfer function is
shown in Figure 2. The output data is in 2’s complement
format.
Analog Input
The differential inputs of the LTC2320-16 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2320-16 digitizes the
difference voltage between the AIN+ and AIN– pins while
supporting a wide common mode input range. The analog
input signals can have an arbitrary relationship to each
other, provided that they remain between VDD and GND.
The LTC2320-16 can also digitize more limited classes of
analog input signals such as pseudo-differential unipolar/
bipolar and fully differential with no configuration required.
The analog inputs of the LTC2320-16 can be modeled
by the equivalent circuit shown in Figure 3. The back-
to-back diodes at the inputs form clamps that provide
ESD protection. In the acquisition phase, 10pF (CIN)
Figure 2. LTC2320-16 Transfer Function
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2320-16
RON
15Ω
RON
15Ω
BIAS
VOLTAGE
232016 F03
CIN
10pF
VDD
CIN
10pF
VDD
AIN–
AIN+
INPUT VOLTAGE (V)
–FSR/2 +FSR/2 – 1LSB
OUTPUT CODE (TWO’S COMPLEMENT)
232016 F02
011...111
011...110
111...111
100...000
100...001
000...000
000...001
–1
LSB
FSR = +FS – –FS
1LSB = FSR/65535
0 1
LSB
LTC2320-16
18
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
from the sampling capacitor in series with approximately
15Ω(RON) from the on-resistance of the sampling switch
is connected to the input. Any unwanted signal that is
common to both inputs will be reduced by the common
mode rejection of the ADC sampler. The inputs of the
ADC core draw a small current spike while charging the
CIN capacitors during acquisition.
Single-Ended Signals
Single-ended signals can be directly digitized by the
LTC2320-16. These signals should be sensed pseudo-
differentially for improved common mode rejection. By
connecting the reference signal (e.g., ground sense) of
the main analog signal to the other AIN pin, any noise or
disturbance common to the two signals will be rejected
by the high CMRR of the ADC. The LTC2320-16 flexibility
handles both pseudo-differential unipolar and bipolar
signals, with no configuration required. The wide common
mode input range relaxes the accuracy requirements of
any signal conditioning circuits prior to the analog inputs.
Pseudo-Differential Bipolar Input Range
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typically
VREF/2, and applying a signal to the other AIN pin. In this
case the analog input swings symmetrically around the
fixed input yielding bipolar two’s complement output codes
with an ADC span of half of full-scale. This configuration
is illustrated in Figure 4, and the corresponding transfer
function in Figure 5. The fixed analog input pin need not
be set at VREF/2, but at some point within the VDD rails
allowing the alternate input to swing symmetrically around
this voltage. If the input signal (AIN+ – AIN–) swings beyond
±REFOUT1,2,3,4/2, valid codes will be generated by the
ADC and must be clamped by the user, if necessary.
Figure 4. Pseudo-Differential Bipolar Application Circuit
Figure 5. Pseudo-Differential Bipolar Transfer Function
25Ω
25Ω
220pF
VREF
0V
VREF
0V
VREF /2
VREF /2
VREF
10k
10k
ONLY CHANNEL 1 SHOWN FOR CLARITY
+
–
+
–
LTC2320-16LT1819
232016 F04
SDO1
REF
REFOUT1
CLKOUT
AIN1–
AIN1+
SCK
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
10µF
1µF
232016 F05
–VREF
–16385
16384
–32768
32767
VREF
DOTTED REGIONS AVAILABLE
AIN
(AIN+ – AIN–)
ADC CODE
(2’s COMPLEMENT)
–VREF/2 VREF /20
LTC2320-16
19
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
Pseudo-Differential Unipolar Input Range
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
signal to the other AIN pin. In this case, the analog input
swings between ground and VREF yielding unipolar two’s
complement output codes with an ADC span of half of
full-scale. This configuration is illustrated in Figure 6,
and the corresponding transfer function in Figure 7. If
the input signal (AIN+ – AIN–) swings negative, valid codes
will be generated by the ADC and must be clamped by the
user, if necessary. A possible variant of this mode would
be to tie AIN+ to ground and drive AIN– between ground
and VREF yielding a code span illustrated by the dotted
line in Figure 7.
desired. By producing a differential signal at the inputs of
the LTC2320-16, the signal swing presented to the ADC is
maximized, thus increasing the achievable SNR.
The LT
®
1819 high speed dual operational amplifier is
recommended for performing single-ended-to-differential
conversions, as shown in Figure 8. In this case, the first
amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high imped-
ance input of this amplifier.
Figure 6. Pseudo-Differential Unipolar Application Circuit
Figure 7. Pseudo-Differential Unipolar Transfer Function
232016 F07
–VREF
–16385
16384
–32768
32767
VREF
DOTTED REGIONS AVAILABLE
AIN
(AIN+ – AIN–)
ADC CODE
(2’s COMPLEMENT)
–VREF/2 VREF/20
Figure 8. Single-Ended to Differential Driver
Figure 9. LT1819 Buffering a Fully-Differential Signal Source
VREF
0V
VREF
0V
VREF
0V
VREF /2
+
–
+
–
200Ω
200Ω
LT1819
232016 F08
VREF
0V
VREF
0V
VREF
0V
VREF
0V
+
–
+
–
LT1819
232016 F09
25Ω
25Ω
220pF
V
REF
0V
V
REF
0V
+
–
LTC2320-16
LT1818
232016 F06
SDO1
REF
REFOUT1
CLKOUT
AIN1–
AIN1+
SCK
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
10µF
Single-Ended-to-Differential Conversion
While single-ended signals can be directly digitized as pre-
viously discussed, single-ended to differential conversion
circuits may also be used when higher dynamic range is
Fully-Differential Inputs
To achieve the best distortion performance of the
LTC2320-16, we recommend driving a fully-differential
signal through LT1819 amplifiers configured as two
unity-gain buffers, as shown in Figure 9. This circuit
achieves the full data sheet THD specification of –90dB at
input frequencies up to 500kHz. Afully-differential input
signal can span the maximum full-scale of the ADC, up to
±REFOUT1,2,3,4. The common mode input voltage can
span the entire supply range up to VDD,limited by the
input signal swing. The fully-differential configuration is
illustrated in Figure 10, with the corresponding transfer
function illustrated in Figure 11.
LTC2320-16
20
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
25Ω
25Ω
220pF
VREF
0V
VREF
0V
VREF
0V
VREF
0V
ONLY CHANNEL 1 SHOWN FOR CLARITY
+
–
+
–
LTC2320-16LT1819
232016 F10
SDO1
REF
REFOUT1
CLKOUT
AIN1–
AIN1+
SCK
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
10µF
232016 F11
–VREF
–16385
16384
–32768
32767
VREF
AIN
(AIN+ – AIN–)
ADC CODE
(2’s COMPLEMENT)
–VREF/2 VREF /20
Figure 10. Fully-Differential Application Circuit
Figure 11. Fully-Differential Transfer Function
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance inputs of the LTC2320-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when during acquisition.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2320-16. The amplifier
provides low output impedance to minimize gain error
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs, which draw a small
current spike during acquisition.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter
to minimize noise. The simple 1-pole RC lowpass filter
shown in Figure 12 is sufficient for many applications.
LTC2320-16
21
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
The sampling switch on-resistance (RON) and the sample
capacitor (CIN) form a second lowpass filter that limits
the input bandwidth to the ADC core to 110MHz. A buffer
amplifier with a low noise density must be selected to
minimize the degradation of the SNR over this bandwidth.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
ADC REFERENCE
Internal Reference
The LTC2320-16 has an on-chip, low noise, low
drift(20ppm/°C max), temperature compensated band-
gap reference. It is internally buffered and is available
at REF (Pin8). The reference buffer gains the internal
reference voltage to 4.096V for supply voltages VDD = 5V
and to 2.048V for VDD = 3.3V. The REF pin also drives
the four internal reference buffers with a current limited
output(250μA) so it may be easily overdriven with an
external reference in the range of 1.25V to 5V. Bypass
REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor
to compensate the reference buffer and minimize noise.
The 1μF capacitor should be as close as possible to the
LTC2320-16 package to minimize wiring inductance. The
REFBUFEN pin does not affect the internal REF buffer. The
voltage on the REF pin must be externally buffered if used
for external circuitry.
Figure 12. Input Signal Chain
Table 1. Reference Configurations and Ranges
REFERENCE CONFIGURATION VDD REFBUFEN REF PIN
REFOUT1,2,3,4
PIN
DIFFERENTIAL INPUT
RANGE PIN
Internal Reference with Internal Buffers 5V 5V 4.096V 4.096V ±4.096V
3.3V 3.3V 2.048V 2.048V ±2.048V
Common External Reference with Internal Buffer (REF Pin
Externally Overdriven)
5V 5V 1.25V to 5V 1.25V to 3.3V ±1.25V to ±5V
3.3V 3.3V 1.25V to 5V 1.25V to 3.3V ±1.25V to ±3.3V
External Reference with REF Buffers Disabled 5V 0V 4.096V 1.25V to 5V ±1.25V to ±5V
3.3V 0V 2.048V 1.25V to 3.3V ±1.25V to ±3.3V
50Ω
SINGLE-ENDED
INPUT SIGNAL
232016 F12
BW = 1MHz
3.3nF
SINGLE-ENDED
TO DIFFERENTIAL
DRIVER
IN+
IN–LTC2320
LTC2320-16
22
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
External Reference
The internal REFOUT1,2,3,4 buffers can also be over-
driven from 1.25V to 5V with an external reference at
REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,
REFBUFEN must be grounded to disable the REF buffers.
A 55k internal resistance loads the REFOUT1,2,3,4 pins
when the REF buffers are disabled. To maximize the input
signal swing and corresponding SNR, the LTC6655-5 is
(13a) LTC2320-16 Internal Reference Circuit (13b) LTC2320-16 with a Shared External Reference Circuit
(13c) LTC2320-16 with Different External Reference Voltages
Figure 13. Reference Connections
recommended when overdriving REFOUT. The LTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-4.096. By using a 5V
reference, a higher SNR can be achieved. We recommend
bypassing the LTC6655-5 with a 10μF ceramic capacitor
(X5R, 0805 size) close to each of the REFOUT1,2,3,4
pins. If the REF pin voltage is used as a REFOUT refer-
ence when REFBUFEN is connected to GND, it should be
buffered externally.
LTC6655-4.096
5V TO
13.2V
0.1µF
VDD
LTC2320-16
GND
232016 F13b
+5V
REF
REFOUT1
REFOUT2
REFOUT3
REFOUT4
REFBUFEN
10µF
10µF
10µF
10µF
10µF
VIN
SHDN
VOUT_F
VOUT_S
5V TO 13.2V
0.1µF
VDD
LTC2320-16
GND
232016 F13c
+5V
REFOUT1
REF
REFOUT2
REFOUT3
REFOUT4
REFBUFEN
10µF
LTC6655-4.096
1µF
VIN
SHDN
VOUT_F
VOUT_S
5V TO 13.2V
0.1µF
10µF
LTC6655-2.048
VIN
SHDN
VOUT_F
VOUT_S
5V TO 13.2V
0.1µF
10µF
LTC6655-2.5
VIN
SHDN
VOUT_F
VOUT_S
5V TO 13.2V
0.1µF
10µF
LTC6655-3
VIN
SHDN
VOUT_F
VOUT_S
VDD
LTC2320-16
GND
232016 F13a
3.3V TO 5V
REF
REFOUT1
REFOUT2
REFOUT3
REFOUT4
REFBUFEN
1µF
10µF
10µF
10µF
10µF
LTC2320-16
23
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
Internal Reference Buffer Transient Response
The REFOUT1,2,3,4 pins of the LTC2320-16 draw charge
(QCONV) from the external bypass capacitors during each
conversion cycle. If the internal reference buffer is over-
driven, the external reference must provide all of this charge
with a DC current equivalent to IREF = QCONV/tCYC.
Thus, the DC current draw of IREFOUT1,2,3,4 depends
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
periods, as shown in Figure 14 , IREFBUF quickly goes from
approximately ~75µA to a maximum of 500µA for REFOUT
= 5V at 1.5Msps. This step in DC current draw triggers a
transient response in the external reference that must be
considered since any deviation in the voltage at REFOUT
will affect the accuracy of the output code. If an external
reference is used to overdrive REFOUT1,2,3,4, the fast
settling LTC6655 reference is recommended.
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2320-16 provides
guaranteed tested limits for both AC distortion and noise
measurements. The typical large signal transient pulse
response of the ADC is illustrated in Figure 15.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
to frequencies from above DC and below half the sampling
frequency. Figure 16 shows that the LTC2320-16 achieves
a typical SINAD of 81dB at a 1.5MHz sampling rate with
a 500kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 16 shows
that the LTC2320-16 achieves a typical SNR of 82dB at a
1.5MHz sampling rate with a 500kHz input.
CNV
232016 F14
IDLE
PERIOD
Figure 14. CNV Waveform Showing Burst Sampling
Figure 15. Transient Response of the LTC2320-16
Figure 16. 32k Point FFT of the LTC2320-16
SNR = 82.2dB
THD = –91.2dB
SINAD = 81.8dB
SFDR = 94.7dB
FREQUENCY (MHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
IN
232016 F16
4.096V RANGE
IN+ = 1.5MHz SQUARE WAVE
IN– = 0V
SETTLING TIME (ns)
–20
–10
0
10
20
30
40
50
60
70
80
90
–8192
0
8192
16384
24576
32768
OUTPUT CODE (LSB)
(Large Signal Settling)
232016 F15
LTC2320-16
24
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD=20log V22+V32+V42+… +VN2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2320-16 requires two power supplies: the 3.3V
to 5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2320-16 to communicate with any digital
logic operating between 1.8V and 2.5V. When using LVDS
I/O, the OVDD supply must be set to 2.5V.
Power Supply Sequencing
The LTC2320-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2320-16
has a power-on-reset (POR) circuit that will reset the
LTC2320-16 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
Figure 17. Power Supply Current of the LTC2320-16 Versus Sampling Rate
V
DD
= 5V
V
DD
= 3.3V
SAMPLE FREQUENCY (Msps)
0
0.3
0.6
0.9
1.2
1.5
19
21
23
25
27
29
31
33
232016 F17
LTC2320-16
25
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
TIMING AND CONTROL
CNV Timing
The LTC2320-16 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
falling edge starts the conversion and readout process. The
conversion process is timed by the SCK input clock. For
optimum performance, CNV should be driven by a clean
low jitter signal. The Typical Application at the back of the
data sheet illustrates a recommended implementation to
reduce the relatively large jitter from an FPGA CNV pulse
source. Note the low jitter input clock times the falling
edge of the CNV signal. The rising edge jitter of CNV is
much less critical to performance. The typical pulse width
of the CNV signal is 30ns with < 1.5ns rise and fall times
at a 1.5Msps conversion rate.
SCK Serial Data Clock Input
In SDR mode (SDR/DDR Pin 23 = GND), the falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins. A 100MHz external clock must be applied at
the SCK pin to achieve 1.5Msps throughput using all eight
SDO outputs. In DDR mode (SDR/DDR Pin 23 = OVDD),
each input edge of SCK shifts the conversion result MSB
first onto the SDO pins. A 50MHz external clock must be
applied at the SCK pin to achieve 1.5Msps throughput
using all eight SDO1 through SDO8 outputs.
CLKOUT Serial Data Clock Output
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK to
capture the SDO output eases timing requirements at the
receiver. For low throughput speed applications, CLKOUT
can be disabled by tying Pin 34 to OVDD.
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-up delays for subsequent conversions. Sleep mode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2320-16,
the SCK signal must be held high or low and a series of
two CNV pulses must be applied. This is the case for both
CMOS and LVDS modes. The second rising edge of CNV
initiates the nap state. The nap state will persist until either
a single rising edge of SCK is applied, or further CNV pulses
are applied. The SCK rising edge will put the LTC2320-16
back into the operational (full-power) state. When in nap
mode, two additional pulses will put the LTC2320-16 in
sleep mode. When configured for CMOS I/O operation, a
single rising edge of SCK can return the LTC2320-16 into
operational mode. A 10ms delay is necessary after exiting
sleep mode to allow the reference buffer to recharge the
external filter capacitor. In LVDS mode, exit sleep mode
by supplying a fifth CNV pulse. The fifth pulse will return
the LTC2320-16 to operational mode, and further SCK
pulses will keep the part from re-entering nap and sleep
modes. The fifth SCK pulse also works in CMOS mode
as a method to exit sleep. In the absence of SCK pulses,
repetitive CNV pulses will cycle the LTC2320-16 between
operational, nap and sleep modes indefinitely.
Refer to the timing diagrams in Figure 18, Figure 19, Figure 20
and Figure 21 for more detailed timing information about
sleep and nap modes.
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
FULL POWER MODE
1 2CNV
SCK HOLD STATIC HIGH OR LOW
NAP MODE
SDO1
– 8
WAKE ON 1ST SCK EDGE
Z Z
232016 F18
LTC2320-16
26
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For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
Figure 19. CMOS Mode SLEEP and WAKE Using SCK
Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
Figure 21. LTC2320-16 Timing Diagram
FULL POWER MODE
1234
4.096V4.096V
REFOUT
RECOVERY
REFOUT1 – 4
CNV
SCK HOLD STATIC HIGH OR LOW
NAP MODE SLEEP MODE
SDO1 – 8
WAKE ON 1ST SCK EDGE
ZZZZ 232016 F19
tWAKE
1234 5
4.096V4.096V
REFOUT
RECOVERY
CNV
SCK HOLD STATIC HIGH OR LOW
NAP MODE SLEEP MODE FULL POWER MODE
WAKE ON 5TH
CNV EDGE
ZZZZ Z 232016 F20
tWAKE
REFOUT1 – 4
SDO1 – 8
232016 F21
D15
t
SCKL
t
SCKH
t
SCK
t
CNVH
t
CYC
CNV
SCK
SDO
1
15
16
CLKOUT
D14
D2
D13
t
CONV
t
READOUT
D15
D0
D1
t
DSCKCLKOUT
t
DCNVSDOZ
t
HSDO
t
DCNVSDOV
HI-Z
HI-Z
t
DSCKCNVH
DDR MODE TIMING
1
15
16
2
2
3
3
14
14
1
2
3
D15
14
15
16
t
SCKL
t
SCKH
t
SCK
t
CNVH
t
CYC
CNV
SCK
SDO
1
2
3
14
15
16
CLKOUT
D14
D2
D13
t
CONV
t
READOUT
D15
D0
D1
t
DSCKCLKOUT
t
DCNVSDOZ
t
HSDO
t
DCNVSDOV
HI-Z
HI-Z
t
DSCKCNVH
SDR MODE TIMING
LTC2320-16
27
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For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
Figure 22. LTC2320-16 Using the LVDS Interface
DIGITAL INTERFACE
The LTC2320-16 features a serial digital interface that
is simple and straightforward to use. The flexible OVDD
supply allows the LTC2320-16 to communicate with any
digital logic operating between 1.8V and 2.5V. In addi-
tion to a standard CMOS SPI interface, the LTC2320-16
provides an optional LVDS SPI interface to support low
noise digital design. The CMOS /LVDS pin is used to select
the digital interface mode. The SCK input clock shifts the
conversion result MSB first on the SDO pins. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver. The timing skew of the CLKOUT and SDO
outputs are matched. For high throughput applications,
using CLKOUT instead of SCK to capture the SDO output
eases timing requirements at the receiver. In CMOS mode,
use the SDO1 – SDO8, and CLKOUT pins as outputs. Use
the SCK pin as an input. In LVDS mode, use the SDOA+/
SDOA– through SDOD+/SDOD– and CLKOUT+/CLKOUT–
pins as differential outputs. Each LVDS lane yields two
channels worth of data: SDOA yields CH1 and CH2 data,
SDOB yields CH3 and CH4 data, SDOC yields CH5 and CH6
data and SDOD yields CH7 and CH8 data. These pins must
be differentially terminated by an external 100Ω resistor at
the receiver (FPGA). The SCK+/SCK– pins are differential
inputs and must be terminated differentially by an external
100Ω resistor at the receiver(ADC).
Figure 23. LTC2320-16 Using the LVDS Interface with One Lane
100Ω
2.5V
2.5V
OVDD
LTC2320-16 FPGA OR DSP
232016 F22
SCK+
SCK–
SDOD+
SDOD–
SDOC+
SDOC–
SDOB+
SDOB–
SDOA+
SDOA–
CMOS/LVDS
+
–
+
–
100Ω
+
–
100Ω
+
–
100Ω
+
–
100Ω
+
–
100Ω
CLKOUT+
CLKOUT–
CNV RETIMING
FLIP-FLOP
100Ω
2.5V
2.5V
OVDD
LTC2320-16 FPGA OR DSP
232016 F23
SCK+
SCK–
SDOD+
SDOD–
SDOC+
SDOC–
SDOB+
SDOB–
SDOA+
SDOA–
CMOS/LVDS
+
–
+
–
100Ω
+
–
100Ω
CLKOUT+
CLKOUT–
CNV RETIMING
FLIP-FLOP
LTC2320-16
28
232016fb
For more information www.linear.com/LTC2320-16
APPLICATIONS INFORMATION
SDR/DDR Modes
The LTC2320-16 has an SDR (single data rate) and DDR
(double data rate) mode for reading conversion data from
the SDO pins. In both modes, CLKOUT is a delayed version
of SCK. In SDR mode, each negative edge of SCK shifts
the conversion data out the SDO pins. In DDR mode,
each edge of the SCK input shifts the conversion data
out. In DDR mode, the required SCK frequency is half of
what is required in SDR mode. Tie SDR/DDR to ground
to configure for SDR mode and to OVDD for DDR mode.
Multiple Data Lanes
The LTC2320-16 has up to eight SDO data lanes in CMOS
mode and four SDO lanes in LVDS mode. In CMOS mode,
the number of possible data lanes range from eight
(SDO1–SDO8), four (SDO1, SDO3, SDO5 and SDO7), two
(SDO1 and SDO5) and one (SDO1). Generally, the more
data lanes used, the lower the required SCK frequency.
When using less than eight lanes in CMOS mode, there
is a limit on the maximum possible conversion frequency
(see Table 2). Each SDO pin will hold the MSB of the con-
version data. In DDR mode you can use a SCK frequency
half of SDR mode. See Table 2 for examples of various
possibilities and the resulting SCK frequency required.
Multiple Data Lanes
The LTC2320-16 has up to eight serial data output data
lanes in CMOS mode and four serial data output lane pairs
in LVDS mode. The data on each lane consists of 16-bit
conversion results presented MSB first.
CMOS
In CMOS mode, the number of possible data lanes range
from eight (SDO1 – SDO8), four (SDO1, SDO3, SDO5
and SDO7), two (SDO1 and SDO5) and one (SDO1). As
suggested in the CMOS Timing Diagrams, each SDO lane
outputs the conversion results for all analog input chan-
nels in a sequential circular manner. For example, the first
conversion result on SDO1 corresponds to analog input
channel 1, followed by the conversion results for chan-
nels2 through 8. The data output on SDO1 then wraps
back to channel 1 and this pattern repeats indefinitely. Other
SDO lanes follow a similar circular pattern except the first
conversion result presented on each lane corresponds to
its associated analog input channel.
Applications that cannot accommodate the full eight
lanes of serial data may employ fewer lanes without
reconfiguring the LTC2320-16. For example, capturing
the first two conversion results (32 SCK cycles total in
Table 2. Conversion Frequency for Various I/O Modes
I/O MODE
CMOS/
LVDS PIN
SDR/
DDR PIN
SDO1 – 8
LANES
SDOA – D
LANES
SCK FREQ
(MHz)
CLKOUT FREQ
(MHz)
SCK
CYCLES OVDD
CONVERSION
FREQUENCY
(Msps/CH)
CMOS GND
(CMOS)
GND (SDR) SDO1 – SDO8 100 100 16
1.8V to 2.5V
1.5
OVDD (DDR) SDO1 – SDO8 50 50 8 1.5
OVDD (DDR) SDO1, SDO3,
SDO5, SDO7 50 50 16 1.25
GND (SDR) SDO1 100 100 128 0.5
LVDS OVDD
(LVDS)
GND (SDR) SDOA – SDOD 200 200 32
2.5V
1.5
OVDD (DDR) SDOA – SDOD 100 100 16 1.5
OVDD (DDR) SDOA, SDOC 150 150 32 1.4
GND (SDR) SDOA 300 300 128 1.0
Notes: Conversion Period (SDR) = tCNV_MIN + tCONV_MAX + (128/(Lanes • fSCK))
Conversion Period (DDR) = tCNV_MIN + tCONV_MAX + (64/(Lanes • fSCK))
Conversion Frequency = 1/Conversion Period
SCK Cycles (SDR) = 128/Lanes
SCK Cycles (DDR) = 64/Lanes
LTC2320-16
29
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For more information www.linear.com/LTC2320-16
SDR mode and 32 SCK edges in DDR mode) from SDO1,
SDO3, SDO5, and SDO7 provides data for analog input
channels 1 and 2, 3 and 4, 5 and 6, and 7 and 8, respec-
tively, using four output lanes. Similarly, capturing the
first four conversion results (64 SCK cycles total in SDR
mode and 64 SCK edges in DDR mode) from SDO1 and
SDO5 provides data for analog input channels 1 to 4 and 5
to8, respectively, using two output lanes. If only one lane
can be accommodated, capturing the first eight conver-
sion results (128SCK cycles total in SDR mode and 128
SCK edges in DDR mode) from SDO1 provides data for
all analog input channels. Generally, the more data lanes
used, the lower the required SCK frequency. When using
less than eight lanes in CMOS mode, there is a limit on
the maximum possible conversion frequency. See Table
2 for examples of various possibilities and the resulting
SCK frequency required.
LVDS
In LVDS mode, the number of possible data lane pairs range
from four (SDOA – SDOD), two (SDOA and SDOC) and
one (SDOA). As suggested in the LVDS Timing Diagrams,
each SDO lane pair outputs the conversion results for all
analog input channels in a sequential circular manner.
For example, the first conversion result on SDOA cor-
responds to analog input channel pair 1 and 2, followed
by the conversion results for channels 3 through 8. The
data output on SDOA then wraps back to channel 1 and
this pattern repeats indefinitely. Other SDO lanes follow a
similar circular pattern except the first conversion result
presented on each lane corresponds to its associated
analog input channel pairs (SDOA: analog inputs 1 and
2, SDOB: analog inputs 3 and 4, SDOC: analog inputs 5
and 6 and SDOD: analog inputs 7 and 8).
Applications that cannot accommodate the full four lanes
of serial data may employ fewer lanes without reconfigur-
ing the LTC2320-16. For example, capturing the first four
conversion results (64 SCK cycles total in SDR mode
and 64 SCK edges in DDR mode) from SDOA and SDOC
provides data for analog input channels 1 through 4, and
5 through 8, respectively, using two output lanes. If only
one lane can be accommodated, capturing the first eight
conversion results (128 SCK cycles total in SDR mode
and 128 SCK edges in DDR mode) from SDOA provides
data for all analog input channels. Generally, the more
data lanes used, the lower the required SCK frequency.
When using less than four lanes in LVDS mode, there is
a limit on the maximum possible conversion frequency.
See Table 2 for examples of various possibilities and the
resulting SCK frequency required.
BOARD LAYOUT
To obtain the best performance from the LTC2320-16,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common re-
turns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Recommended Layout
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2395A, the evaluation kit for the LTC2320-16.
APPLICATIONS INFORMATION
LTC2320-16
30
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For more information www.linear.com/LTC2320-16
PACKAGE DESCRIPTION
7.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
0.40 ±0.10
5251
1
2
BOTTOM VIEW—EXPOSED PAD
TOP VIEW
SIDE VIEW
6.50 REF
(2 SIDES)
8.00 ±0.10
(2 SIDES)
5.50 REF
(2 SIDES)
0.75 ±0.05
0.75 ±0.05
R = 0.115
TYP
R = 0.10
TYP 0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
6.45 ±0.10
5.41 ±0.10
0.00 – 0.05
(UKG52) QFN REV Ø 0306
5.50 REF
(2 SIDES)
5.41 ±0.05
6.45 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
6.10 ±0.05
7.50 ±0.05
6.50 REF
(2 SIDES) 7.10 ±0.05 8.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
Please refer to http://www.linear.com/product/LTC2320-16#packaging for the most recent package drawings.
LTC2320-16
31
232016fb
For more information www.linear.com/LTC2320-16
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 01/17 Corrected VREFOUT voltages 4
B 02/17 Corrected text to specify no latency operation 17, 23
LTC2320-16
32
232016fb
For more information www.linear.com/LTC2320-16
LINEAR TECHNOLOGY CORPORATION 2016
LT 0217 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2320-16
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NC7SVU04P5X (× 9)
50Ω
NC7SVUO4P5X
CONV ENABLE
MASTER_CLOCK
CONV
1k
1k
LTC2320-16
232016 TA02
SDO1 – 8
SCK
GND
CLR
NC7SV74K8X CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
PRE
CLKOUT
CNV
CMOS/LVDS
GND SDR/DDR
VCC
VCC
Q
D
0.1µF
10Ω
10Ω