74HC373; 74HCT373 Octal D-type transparent latch; 3-state Rev. 03 -- 20 January 2006 Product data sheet 1. General description The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the highimpedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74HC373; 74HCT373 is functionally identical to: * 74HC533; 74HCT533: but inverted outputs * 74HC563; 74HCT563: but inverted outputs and different pin arrangement * 74HC573; 74HCT573: but different pin arrangement 2. Features 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and 74HC533; 74HCT533 ESD protection: HBM EIA/JESD22-A114-C exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol Parameter Conditions Min Typ Max Unit Dn to Qn - 12 - ns LE to Qn - 15 - ns - 3.5 - pF - 45 - pF Dn to Qn - 14 - ns LE to Qn - 13 - ns - 3.5 - pF - 41 - pF 74HC373 tPHL, tPLH propagation delay VCC = 5 V; CL = 15 pF input capacitance Ci power dissipation capacitance CPD [1] per latch; VI = GND to VCC 74HCT373 tPHL, tPLH propagation delay input capacitance Ci power dissipation capacitance CPD [1] VCC = 5 V; CL = 15 pF [1] per latch; VI = GND to (VCC - 1.5 V) CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC373N -40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74HC373D -40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74HC373DB -40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74HC373PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74HC373BQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 74HC373 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 2 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 2: Ordering information ...continued Type number Package Temperature range Name Description Version 74HCT373N -40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74HCT373D -40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74HCT373DB -40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74HCT373PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74HCT373BQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 74HCT373 5. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 LATCH 1 TO 8 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 LE 11 OE 1 001aae050 Fig 1. Functional diagram OE LE 1 11 EN C1 11 3 4 7 8 13 14 17 18 D0 LE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 2 5 6 D2 9 D3 12 15 16 19 OE 1 D4 D5 D6 D7 001aae048 Fig 2. Logic symbol 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae049 Fig 3. IEC logic symbol 74HC_HCT373_3 Product data sheet D1 3 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 3 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state LE LE LE D Q LE 001aae051 Fig 4. Logic diagram (one latch) D0 D1 D Q D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae052 Fig 5. Logic diagram 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 4 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 6. Pinning information 6.1 Pinning 74HC373 74HCT373 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 Q1 terminal 1 index area OE 1 1 OE 20 VCC 74HC373 74HCT373 Q0 2 19 Q7 D0 3 18 D7 17 D6 D1 4 17 D6 5 16 Q6 Q1 5 16 Q6 Q2 6 15 Q5 Q2 6 15 Q5 D2 7 14 D5 D2 7 D3 8 Q3 9 13 D4 Q3 9 12 Q4 GND 10 11 LE 13 D4 12 Q4 LE 11 8 GND 10 D3 14 D5 GND(1) 001aae047 Transparent top view 001aae046 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 6. Pin configuration DIP20, SO20, SSOP20 and TSSOP20 Fig 7. Pin configuration DHVQFN20 6.2 Pin description Table 3: Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) Q0 2 3-state latch output 0 D0 3 data input 0 D1 4 data input 1 Q1 5 3-state latch output 1 Q2 6 3-state latch output 2 D2 7 data input 2 D3 8 data input 3 Q3 9 3-state latch output 3 GND 10 ground (0 V) LE 11 latch enable input (active HIGH) Q4 12 3-state latch output 4 D4 13 data input 4 D5 14 data input 5 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 5 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 3: Pin description ...continued Symbol Pin Description Q5 15 3-state latch output 5 Q6 16 3-state latch output 6 D6 17 data input 6 D7 18 data input 7 Q7 19 3-state latch output 7 VCC 20 supply voltage 7. Functional description 7.1 Function table Table 4: Function table [1] Operating mode LE Dn Internal latches Output OE Enable and read register (transparent mode) L H L L L H H H Latch and read register L l L L h H H Latch register and disable outputs H X X Z [1] Control Input L X H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don't care; Z = high-impedance OFF-state. 74HC_HCT373_3 Product data sheet Qn (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 6 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V -0.5 +7 V - 20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - 20 mA VO = -0.5 V to (VCC + 0.5 V) IO output current - 35 mA ICC quiescent supply current - +70 mA IGND ground current - -70 mA Tstg storage temperature -65 +150 C Ptot total power dissipation DIP20 package [1] - 750 mW SO20 package [2] - 500 mW SSOP20 package [3] 500 mW TSSOP20 package [3] DHVQFN20 package [4] [1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO20: Ptot derates linearly with 8 mW/K above 70 C. - [3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C. 500 mW 500 mW 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC373 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 C tr, tf input rise and fall time VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns 74HCT373 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 C tr, tf input rise and fall time - 6.0 500 ns VCC = 4.5 V 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 7 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 10. Static characteristics Table 7: Static characteristics 74HC373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 C VIH VIL VOH VOL HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V VI = VIH or VIL - - - IO = -20 A; VCC = 2.0 V 1.9 2.0 - V IO = -20 A; VCC = 4.5 V 4.4 4.5 - V IO = -20 A; VCC = 6.0 V 5.9 6.0 - V IO = -6.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = -7.8 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 A; VCC = 2.0 V - 0 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 V VI = VIH or VIL IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 A IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND - - 0.5 A ICC quiescent supply current VCC = 6.0 V; IO = 0 A; VI = VCC or GND - - 8.0 A Ci input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V Tamb = -40 C to +85 C VIH VIL VOH HIGH-state input voltage LOW-state input voltage HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V 1.9 - - V IO = -20 A; VCC = 4.5 V 4.4 - - V IO = -20 A; VCC = 6.0 V 5.9 - - V IO = -6.0 mA; VCC = 4.5 V 3.84 - - V IO = -7.8 mA; VCC = 6.0 V 5.34 - - V 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 8 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 7: Static characteristics 74HC373 ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-state output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 6.0 mA; VCC = 4.5 V - - 0.33 V IO = 7.8 mA; VCC = 6.0 V - - 0.33 V ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND - - 5.0 A ICC quiescent supply current VCC = 6.0 V; IO = 0 A; VI = VCC or GND - 80 A Tamb = -40 C to +125 C VIH VIL VOH VOL HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = -20 A; VCC = 2.0 V 1.9 - - V IO = -20 A; VCC = 4.5 V 4.4 - - V IO = -20 A; VCC = 6.0 V 5.9 - - V IO = -6.0 mA; VCC = 4.5 V 3.7 - - V IO = -7.8 mA; VCC = 6.0 V 5.2 - - V IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 6.0 mA; VCC = 4.5 V - - 0.4 V IO = 7.8 mA; VCC = 6.0 V - - 0.4 V VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND - - 10.0 A ICC quiescent supply current VCC = 6.0 V; IO = 0 A; VI = VCC or GND - - 160 A 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 9 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 8: Static characteristics 74HCT373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 C VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V VOH HIGH-state output voltage VI = VIH or VIL VOL LOW-state output voltage IO = -20 A; VCC = 4.5 V 4.4 4.5 - V IO = -6.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = 20 A; VCC = 4.5 V - 0.0 0.1 V VI = VIH or VIL IO = 6.0 mA; VCC = 4.5 V - 0.16 0.26 V ILI input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - 0.5 A ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 A ICC additional quiescent supply current VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn - 30 108 A LE - 150 540 A OE - 100 360 A - 3.5 - pF Ci input capacitance Tamb = -40 C to +85 C VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 4.5 V 4.4 - - V IO = -6.0 A; VCC = 4.5 V 3.84 - - V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 6.0 mA; VCC = 4.5 V - - 0.33 V VOL LOW-state output voltage VI = VIH or VIL ILI input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - 5.0 A ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 A ICC additional quiescent supply current VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn - - 135 A LE - - 675 A OE - - 450 A 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 10 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 8: Static characteristics 74HCT373 ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 C to +125 C VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 4.5 V 4.4 - - V IO = -6.0 mA; VCC = 4.5 V 3.7 - - V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 6.0 mA; VCC = 4.5 V - - 0.4 V VOL LOW-state output voltage VI = VIH or VIL ILI input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 A ICC additional quiescent supply current VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn - - 147 A LE - - 735 A OE - - 490 A 11. Dynamic characteristics Table 9: Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit - 41 150 ns Tamb = 25 C tPHL, tPLH propagation delay Dn to Qn see Figure 8 VCC = 2.0 V LE to Qn VCC = 4.5 V - 15 30 ns VCC = 5 V; CL = 15 pF - 12 - ns VCC = 6.0 V - 12 26 ns see Figure 9 VCC = 2.0 V - 50 175 ns VCC = 4.5 V - 18 35 ns VCC = 5 V; CL = 15 pF - 15 - ns VCC = 6.0 V - 14 30 ns 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 11 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 9: Dynamic characteristics 74HC373 ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions tPZH, tPZL see Figure 10 tPHZ, tPLZ tTHL, tTLH tW tsu th CPD 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time pulse width LE HIGH set-up time Dn to LE hold time Dn to LE power dissipation capacitance Min Typ Max Unit VCC = 2.0 V - 44 150 ns VCC = 4.5 V - 16 30 ns VCC = 6.0 V - 13 26 ns VCC = 2.0 V - 47 150 ns VCC = 4.5 V - 17 30 ns VCC = 6.0 V - 14 26 ns VCC = 2.0 V - 14 60 ns VCC = 4.5 V - 5 12 ns VCC = 6.0 V - 4 10 ns VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns VCC = 2.0 V 50 14 - ns VCC = 4.5 V 10 5 - ns VCC = 6.0 V 9 4 - ns VCC = 2.0 V +5 -8 - ns VCC = 4.5 V +5 -3 - ns VCC = 6.0 V +5 -2 - ns - 45 - pF VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns VCC = 2.0 V - - 220 ns VCC = 4.5 V - - 44 ns VCC = 6.0 V - - 37 ns VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns see Figure 10 see Figure 9 see Figure 9 see Figure 11 see Figure 11 per latch; VI = GND to VCC [1] Tamb = -40 C to +85 C tPHL, tPLH propagation delay Dn to Qn LE to Qn tPZH, tPZL 3-state output enable time OE to Qn see Figure 8 see Figure 9 see Figure 10 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 12 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 9: Dynamic characteristics 74HC373 ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions tPHZ, tPLZ see Figure 10 tTHL, tTLH tW tsu th 3-state output disable time OE to Qn output transition time pulse width LE HIGH set-up time Dn to LE hold time Dn to LE Min Typ Max Unit VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns VCC = 2.0 V - - 75 ns VCC = 4.5 V - - 15 ns VCC = 6.0 V - - 13 ns VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 65 - - ns VCC = 4.5 V 13 - - ns VCC = 6.0 V 11 - - ns VCC = 2.0 V 5 - - ns VCC = 4.5 V 5 - - ns VCC = 6.0 V 5 - - ns VCC = 2.0 V - - 225 ns VCC = 4.5 V - - 45 ns VCC = 6.0 V - - 38 ns VCC = 2.0 V - - 265 ns VCC = 4.5 V - - 53 ns VCC = 6.0 V - - 45 ns VCC = 2.0 V - - 225 ns VCC = 4.5 V - - 45 ns VCC = 6.0 V - - 38 ns VCC = 2.0 V - - 225 ns VCC = 4.5 V - - 45 ns VCC = 6.0 V - - 38 ns see Figure 8 see Figure 9 see Figure 11 see Figure 11 Tamb = -40 C to +125 C tPHL, tPLH propagation delay Dn to Qn LE to Qn tPZH, tPZL tPHZ, tPLZ 3-state output enable time OE to Qn 3-state output disable time OE to Qn see Figure 8 see Figure 9 see Figure 10 see Figure 10 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 13 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 9: Dynamic characteristics 74HC373 ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions tTHL, tTLH see Figure 8 pulse width LE HIGH tW set-up time Dn to LE tsu hold time Dn to LE th [1] output transition time Min Typ Max Unit VCC = 2.0 V - - 90 ns VCC = 4.5 V - - 18 ns VCC = 6.0 V - - 15 ns VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns VCC = 2.0 V 5 - - ns VCC = 4.5 V 5 - - ns VCC = 6.0 V 5 - - ns see Figure 9 see Figure 11 see Figure 11 CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs. Table 10: Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit VCC = 4.5 V - 17 30 ns VCC = 5 V; CL = 15 pF - 14 - ns VCC = 4.5 V - 16 32 ns VCC = 5 V; CL = 15 pF - 13 - ns Tamb = 25 C tPHL, tPLH propagation delay Dn to Qn LE to Qn see Figure 8 see Figure 9 tPZH, tPZL 3-state output enable time OE to Qn VCC = 4.5 V; see Figure 10 - 19 32 ns tPHZ, tPLZ 3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10 - 18 30 ns tTHL, tTLH output transition time - 5 12 ns VCC = 4.5 V; see Figure 8 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 14 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state Table 10: Dynamic characteristics 74HCT373 ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit tW pulse width LE HIGH VCC = 4.5 V; see Figure 9 16 4 - ns tsu set-up time Dn to LE VCC = 4.5 V; see Figure 11 12 6 - ns th hold time Dn to LE VCC = 4.5 V; see Figure 11 4 -1 - ns CPD power dissipation capacitance per latch; VI = GND to (VCC - 1.5 V) - 41 - pF [1] Tamb = -40 C to +85 C tPHL, tPLH propagation delay Dn to Qn VCC = 4.5 V; see Figure 8 - - 38 ns LE to Qn VCC = 4.5 V; see Figure 9 - - 40 ns tPZH, tPZL 3-state output enable time OE to Qn VCC = 4.5 V; see Figure 10 - - 40 ns tPHZ, tPLZ 3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10 - - 38 ns tTHL, tTLH output transition time VCC = 4.5 V; see Figure 8 - - 15 ns tW pulse width LE HIGH VCC = 4.5 V; see Figure 9 20 - - ns tsu set-up time Dn to LE VCC = 4.5 V; see Figure 11 15 - - ns th hold time Dn to LE VCC = 4.5 V; see Figure 11 4 - - ns Dn to Qn VCC = 4.5 V; see Figure 8 - - 45 ns LE to Qn VCC = 4.5 V; see Figure 9 - - 48 ns Tamb = -40 C to +125 C tPHL, tPLH propagation delay tPZH, tPZL 3-state output enable time OE to Qn VCC = 4.5 V, see Figure 10 - - 48 ns tPHZ, tPLZ 3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10 - - 45 ns tTHL, tTLH output transition time VCC = 4.5 V; see Figure 8 - - 18 ns tW pulse width LE HIGH VCC = 4.5 V; see Figure 8 24 - - ns tsu set-up time Dn to LE VCC = 4.5 V; see Figure 11 18 - - ns th hold time Dn to LE VCC = 4.5 V; see Figure 11 4 - - ns [1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs. 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 15 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 12. Waveforms VM Dn input t PLH t PHL 90 % VM Qn output 10 % t TLH t THL 001aae082 Measurement points are given in Table 11. Fig 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn) LE input VM tW t PHL t PLH 90 % VM Qn output 10 % t THL t TLH 001aae083 Measurement points are given in Table 11. Fig 9. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn) 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 16 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM 10% VOL tPHZ tPZH VOH 90% output HIGH-to-OFF OFF-to-HIGH GND VM outputs disabled outputs enabled outputs enabled 001aae307 Measurement points are given in Table 11. Fig 10. 3-state enable and disable time VM LE input t su t su th th VM Dn input 001aae084 Measurement points are given in Table 11. Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE) Table 11: Type Measurement points Input Output VM VM 74HC373 0.5VCC 0.5VCC 74HCT373 1.3 V 1.3 V 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 17 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC PULSE GENERATOR VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 12. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 12. Load circuitry for measuring switching times Table 12: Type Test data Input Load VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC373 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT373 3V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT373_3 Product data sheet S1 position (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 18 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 13. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2 0.25 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC JEITA MS-001 SC-603 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 13. Package outline SOT146-1 (DIP20) 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 19 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT163-1 (SO20) 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 20 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 15. Package outline SOT339-1 (SSOP20) 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 21 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 16. Package outline SOT360-1 (TSSOP20) 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 22 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT764-1 (DHVQFN20) 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 23 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 14. Abbreviations Table 13: Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74HC_HCT373_3 20060120 Product data sheet - 74HC_HCT373_CNV_2 Modifications: 74HC_HCT373_CNV_2 * The format of this data sheet is redesigned to comply with the current presentation and information standard of Philips Semiconductors. * * * Added type numbers 74HC373BQ and 74HCT373BQ (package DHVQFN20). Added family specifications. Added abbreviations list. 19970827 Product specification - 74HC_HCT373_3 Product data sheet - - - (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 24 of 26 74HC373; 74HCT373 Philips Semiconductors Octal D-type transparent latch; 3-state 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Trademarks 18. Disclaimers Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 20. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74HC_HCT373_3 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 -- 20 January 2006 25 of 26 Philips Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state 21. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information . . . . . . . . . . . . . . . . . . . . 25 (c) Koninklijke Philips Electronics N.V. 2006 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 January 2006 Document number: 74HC_HCT373_3 Published in The Netherlands