1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
•74HC533; 74HCT533: but inverted outputs
•74HC563; 74HCT563: but inverted outputs and different pin arrangement
•74HC573; 74HCT573: but different pin arrangement
2. Features
■3-state non-inverting outputs for bus oriented applications
■Common 3-state output enable input
■Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and
74HC533; 74HCT533
■ESD protection:
◆HBM EIA/JESD22-A114-C exceeds 2000 V
◆MM EIA/JESD22-A115-A exceeds 200 V
■Specified from −40 °Cto+85°C and from −40 °C to +125 °C
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 03 — 20 January 2006 Product data sheet
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 2 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
3. Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
4. Ordering information
Table 1: Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
74HC373
tPHL, tPLH propagation delay VCC =5V; C
L=15pF
Dn to Qn - 12 - ns
LE to Qn - 15 - ns
Ciinput capacitance - 3.5 - pF
CPD power dissipation
capacitance per latch; VI= GND to VCC [1] -45-pF
74HCT373
tPHL, tPLH propagation delay VCC =5V; C
L=15pF
Dn to Qn - 14 - ns
LE to Qn - 13 - ns
Ciinput capacitance - 3.5 - pF
CPD power dissipation
capacitance per latch;
VI= GND to (VCC −1.5 V) [1] -41-pF
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74HC373
74HC373N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC373D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HC373DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HC373PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HC373BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 ×4.5 ×0.85 mm
SOT764-1
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 3 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
5. Functional diagram
74HCT373
74HCT373N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT373D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HCT373DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HCT373PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HCT373BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 ×4.5 ×0.85 mm
SOT764-1
Table 2: Ordering information
…continued
Type number Package
Temperature range Name Description Version
Fig 1. Functional diagram
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aae050
LATCH
1 TO 8
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
11
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
3-STATE
OUTPUTS
LE
OE
001aae048
D0
D1
D2
D3
D4
D5
D6
D7 OE
LE Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
001aae049
1
11 C1
1D
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
OE
LE
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
EN
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 4 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 4. Logic diagram (one latch)
001aae051
LE QD
LE
LE
LE
Fig 5. Logic diagram
001aae052
D
LE LE
Q
LATCH
8
Q7
D7
D
LE LE
Q
LATCH
7
Q6
D6
D
LE LE
Q
LATCH
6
Q5
D5
D
LE LE
Q
LATCH
5
Q4
D4
D
LE LE
Q
LATCH
4
Q3
D3
D
LE LE
Q
LATCH
3
Q2
D2
D
LE LE
Q
LATCH
2
Q1
D1
D
LE LE
Q
LATCH
1
Q0
D0
LE
OE
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 5 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input.
Fig 6. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20 Fig 7. Pin configuration DHVQFN20
74HC373
74HCT373
OE VCC
Q0 Q7
D0 D7
D1 D6
Q1 Q6
Q2 Q5
D2 D5
D3 D4
Q3 Q4
GND LE
001aae046
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aae047
74HC373
74HCT373
Transparent top view
Q4
D3
Q3
D4
D2 D5
Q2 Q5
Q1 Q6
D1 D6
D0 D7
Q0
GND(1)
Q7
GND
LE
OE
VCC
912
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
Table 3: Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
Q0 2 3-state latch output 0
D0 3 data input 0
D1 4 data input 1
Q1 5 3-state latch output 1
Q2 6 3-state latch output 2
D2 7 data input 2
D3 8 data input 3
Q3 9 3-state latch output 3
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
Q4 12 3-state latch output 4
D4 13 data input 4
D5 14 data input 5
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 6 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
Q5 15 3-state latch output 5
Q6 16 3-state latch output 6
D6 17 data input 6
D7 18 data input 7
Q7 19 3-state latch output 7
VCC 20 supply voltage
Table 3: Pin description
…continued
Symbol Pin Description
Table 4: Function table[1]
Operating mode Control Input Internal
latches Output
OE LE Dn Qn
Enable and
read register
(transparent mode)
LHLL L
HH H
Latch and
read register LLl L L
hH H
Latch register and
disable outputs HXXX Z
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 7 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
8. Limiting values
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI>V
CC + 0.5 V - ±20 mA
IOK output clamping current VO<−0.5 V or
VO>V
CC + 0.5 V -±20 mA
IOoutput current VO = −0.5 V to (VCC + 0.5 V) - ±35 mA
ICC quiescent supply current - +70 mA
IGND ground current - −70 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation
DIP20 package [1] - 750 mW
SO20 package [2] - 500 mW
SSOP20 package [3] 500 mW
TSSOP20 package [3] 500 mW
DHVQFN20 package [4] - 500 mW
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74HC373
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
tr, tfinput rise and fall time VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
74HCT373
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
tr, tfinput rise and fall time VCC = 4.5 V - 6.0 500 ns
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 8 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
10. Static characteristics
Table 7: Static characteristics 74HC373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
VIH HIGH-state input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-state input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-state output voltage VI = VIH or VIL ---
IO=−20 µA; VCC = 2.0 V 1.9 2.0 - V
IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=−20 µA; VCC = 6.0 V 5.9 6.0 - V
IO=−6.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO=−7.8 mA; VCC = 6.0 V 5.48 5.81 - V
VOL LOW-state output voltage VI = VIH or VIL
IO=20µA; VCC = 2.0 V - 0 0.1 V
IO=20µA; VCC = 4.5 V - 0 0.1 V
IO=20µA; VCC = 6.0 V - 0 0.1 V
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V
ILI input leakage current VI=V
CC or GND; VCC = 6.0 V - - ±0.1 µA
IOZ OFF-state output current VI=V
IH or VIL; VCC = 6.0 V;
VO=V
CC or GND --±0.5 µA
ICC quiescent supply current VCC = 6.0 V; IO = 0 A;
VI=V
CC or GND - - 8.0 µA
Ciinput capacitance - 3.5 - pF
Tamb =−40 °C to +85 °C
VIH HIGH-state input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-state input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-state output voltage VI = VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 - - V
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−20 µA; VCC = 6.0 V 5.9 - - V
IO = −6.0 mA; VCC = 4.5 V 3.84 - - V
IO = −7.8 mA; VCC = 6.0 V 5.34 - - V
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 9 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
VOL LOW-state output voltage VI = VIH or VIL
IO=20µA; VCC = 2.0 V - - 0.1 V
IO=20µA; VCC = 4.5 V - - 0.1 V
IO=20µA; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IO = 7.8 mA; VCC = 6.0 V - - 0.33 V
ILI input leakage current VI=V
CC or GND; VCC = 6.0 V - - ±1.0 µA
IOZ OFF-state output current VI=V
IH or VIL; VCC = 6.0 V;
VO=V
CC or GND --±5.0 µA
ICC quiescent supply current VCC = 6.0 V; IO = 0 A;
VI=V
CC or GND -80µA
Tamb =−40 °C to +125 °C
VIH HIGH-state input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-state input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-state output voltage VI = VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 - - V
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−20 µA; VCC = 6.0 V 5.9 - - V
IO = −6.0 mA; VCC = 4.5 V 3.7 - - V
IO = −7.8 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-state output voltage VI = VIH or VIL
IO=20µA; VCC = 2.0 V - - 0.1 V
IO=20µA; VCC = 4.5 V - - 0.1 V
IO=20µA; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - - 0.4 V
ILI input leakage current VI=V
CC or GND; VCC = 6.0 V - - ±1.0 µA
IOZ OFF-state output current VI=V
IH or VIL; VCC = 6.0 V;
VO=V
CC or GND --±10.0 µA
ICC quiescent supply current VCC = 6.0 V; IO = 0 A;
VI=V
CC or GND - - 160 µA
Table 7: Static characteristics 74HC373
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 10 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Table 8: Static characteristics 74HCT373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-state output voltage VI=V
IH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=−6.0 mA; VCC = 4.5 V 3.98 4.32 - V
VOL LOW-state output voltage VI=V
IH or VIL
IO=20µA; VCC = 4.5 V - 0.0 0.1 V
IO= 6.0 mA; VCC = 4.5 V - 0.16 0.26 V
ILI input leakage current VI=V
CC or GND; VCC = 5.5 V - - ±0.1 µA
IOZ OFF-state output current VI=V
IH or VIL; VCC = 5.5 V;
VO=V
CC or GND per input pin;
other inputs at VCC or GND; IO=0 A
--±0.5 µA
ICC quiescent supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V - - 8.0 µA
∆ICC additional quiescent supply
current VI=V
CC −2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO=0A
Dn - 30 108 µA
LE - 150 540 µA
OE - 100 360 µA
Ciinput capacitance - 3.5 - pF
Tamb =−40 °C to +85 °C
VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-state output voltage VI=V
IH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−6.0 µA; VCC = 4.5 V 3.84 - - V
VOL LOW-state output voltage VI=V
IH or VIL
IO=20µA; VCC = 4.5 V - - 0.1 V
IO= 6.0 mA; VCC = 4.5 V - - 0.33 V
ILI input leakage current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 µA
IOZ OFF-state output current VI=V
IH or VIL; VCC = 5.5 V;
VO=V
CC or GND per input pin;
other inputs at VCC or GND; IO=0 A
--±5.0 µA
ICC quiescent supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V --80µA
∆ICC additional quiescent supply
current VI=V
CC −2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO=0A
Dn - - 135 µA
LE - - 675 µA
OE - - 450 µA
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 11 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
11. Dynamic characteristics
Tamb =−40 °C to +125 °C
VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-state output voltage VI=V
IH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−6.0 mA; VCC = 4.5 V 3.7 - - V
VOL LOW-state output voltage VI=V
IH or VIL
IO=20µA; VCC = 4.5 V - - 0.1 V
IO= 6.0 mA; VCC = 4.5 V - - 0.4 V
ILI input leakage current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 µA
IOZ OFF-state output current VI=V
IH or VIL; VCC = 5.5 V;
VO=V
CC or GND per input pin;
other inputs at VCC or GND; IO=0 A
--±10 µA
ICC quiescent supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V - - 160 µA
∆ICC additional quiescent supply
current VI=V
CC −2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO=0A
Dn - - 147 µA
LE - - 735 µA
OE - - 490 µA
Table 8: Static characteristics 74HCT373
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 9: Dynamic characteristics 74HC373
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
tPHL,
tPLH
propagation delay
Dn to Qn see Figure 8
VCC = 2.0 V - 41 150 ns
VCC = 4.5 V - 15 30 ns
VCC =5V; C
L=15pF - 12 - ns
VCC = 6.0 V - 12 26 ns
LE to Qn see Figure 9
VCC = 2.0 V - 50 175 ns
VCC = 4.5 V - 18 35 ns
VCC =5V; C
L=15pF - 15 - ns
VCC = 6.0 V - 14 30 ns
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 12 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
tPZH,
tPZL
3-state output enable time OE to
Qn see Figure 10
VCC = 2.0 V - 44 150 ns
VCC = 4.5 V - 16 30 ns
VCC = 6.0 V - 13 26 ns
tPHZ,
tPLZ
3-state output disable time OE to
Qn see Figure 10
VCC = 2.0 V - 47 150 ns
VCC = 4.5 V - 17 30 ns
VCC = 6.0 V - 14 26 ns
tTHL,
tTLH
output transition time see Figure 9
VCC = 2.0 V - 14 60 ns
VCC = 4.5 V - 5 12 ns
VCC = 6.0 V - 4 10 ns
tWpulse width LE HIGH see Figure 9
VCC = 2.0 V 80 17 - ns
VCC = 4.5 V 16 6 - ns
VCC = 6.0 V 14 5 - ns
tsu set-up time Dn to LE see Figure 11
VCC = 2.0 V 50 14 - ns
VCC = 4.5 V 10 5 - ns
VCC = 6.0 V 9 4 - ns
thhold time Dn to LE see Figure 11
VCC = 2.0 V +5 −8- ns
VCC = 4.5 V +5 −3- ns
VCC = 6.0 V +5 −2- ns
CPD power dissipation capacitance per latch; VI= GND to VCC [1] -45-pF
Tamb =−40 °C to +85 °C
tPHL,
tPLH
propagation delay
Dn to Qn see Figure 8
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
LE to Qn see Figure 9
VCC = 2.0 V - - 220 ns
VCC = 4.5 V - - 44 ns
VCC = 6.0 V - - 37 ns
tPZH,
tPZL
3-state output enable time OE to
Qn see Figure 10
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
Table 9: Dynamic characteristics 74HC373
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 13 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
tPHZ,
tPLZ
3-state output disable time OE to
Qn see Figure 10
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
tTHL,
tTLH
output transition time see Figure 8
VCC = 2.0 V - - 75 ns
VCC = 4.5 V - - 15 ns
VCC = 6.0 V - - 13 ns
tWpulse width LE HIGH see Figure 9
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
tsu set-up time Dn to LE see Figure 11
VCC = 2.0 V 65 - - ns
VCC = 4.5 V 13 - - ns
VCC = 6.0 V 11 - - ns
thhold time Dn to LE see Figure 11
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Tamb =−40 °C to +125 °C
tPHL,
tPLH
propagation delay
Dn to Qn see Figure 8
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
LE to Qn see Figure 9
VCC = 2.0 V - - 265 ns
VCC = 4.5 V - - 53 ns
VCC = 6.0 V - - 45 ns
tPZH,
tPZL
3-state output enable time OE to
Qn see Figure 10
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tPHZ,
tPLZ
3-state output disable time OE to
Qn see Figure 10
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
Table 9: Dynamic characteristics 74HC373
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 14 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
tTHL,
tTLH
output transition time see Figure 8
VCC = 2.0 V - - 90 ns
VCC = 4.5 V - - 18 ns
VCC = 6.0 V - - 15 ns
tWpulse width LE HIGH see Figure 9
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 - - ns
VCC = 6.0 V 20 - - ns
tsu set-up time Dn to LE see Figure 11
VCC = 2.0 V 75 - - ns
VCC = 4.5 V 15 - - ns
VCC = 6.0 V 13 - - ns
thhold time Dn to LE see Figure 11
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Table 9: Dynamic characteristics 74HC373
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Table 10: Dynamic characteristics 74HCT373
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
tPHL,
tPLH
propagation delay
Dn to Qn see Figure 8
VCC = 4.5 V - 17 30 ns
VCC =5V; C
L=15pF - 14 - ns
LE to Qn see Figure 9
VCC = 4.5 V - 16 32 ns
VCC =5V; C
L=15pF - 13 - ns
tPZH,
tPZL
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 10 - 1932ns
tPHZ,
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10 - 1830ns
tTHL,
tTLH
output transition time VCC = 4.5 V; see Figure 8 - 5 12 ns
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 15 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
tWpulse width LE HIGH VCC = 4.5 V; see Figure 9 16 4 - ns
tsu set-up time Dn to LE VCC = 4.5 V; see Figure 11 12 6 - ns
thhold time Dn to LE VCC = 4.5 V; see Figure 11 4−1- ns
CPD power dissipation capacitance per latch;
VI= GND to (VCC −1.5 V) [1] -41-pF
Tamb =−40 °C to +85 °C
tPHL,
tPLH
propagation delay
Dn to Qn VCC = 4.5 V; see Figure 8 --38ns
LE to Qn VCC = 4.5 V; see Figure 9 --40ns
tPZH,
tPZL
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 10 --40ns
tPHZ,
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10 --38ns
tTHL,
tTLH
output transition time VCC = 4.5 V; see Figure 8 --15ns
tWpulse width LE HIGH VCC = 4.5 V; see Figure 9 20--ns
tsu set-up time Dn to LE VCC = 4.5 V; see Figure 11 15--ns
thhold time Dn to LE VCC = 4.5 V; see Figure 11 4--ns
Tamb =−40 °C to +125 °C
tPHL,
tPLH
propagation delay
Dn to Qn VCC = 4.5 V; see Figure 8 --45ns
LE to Qn VCC = 4.5 V; see Figure 9 --48ns
tPZH,
tPZL
3-state output enable time OE to Qn VCC = 4.5 V, see Figure 10 --48ns
tPHZ,
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10 --45ns
tTHL,
tTLH
output transition time VCC = 4.5 V; see Figure 8 --18ns
tWpulse width LE HIGH VCC = 4.5 V; see Figure 8 24--ns
tsu set-up time Dn to LE VCC = 4.5 V; see Figure 11 18--ns
thhold time Dn to LE VCC = 4.5 V; see Figure 11 4--ns
Table 10: Dynamic characteristics 74HCT373
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 16 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
12. Waveforms
Measurement points are given in Table 11.
Fig 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
Measurement points are given in Table 11.
Fig 9. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and
transition time output (Qn)
001aae082
Dn input
Qn output
VM
tPLH tPHL
tTHL
tTLH
VM
90 %
10 %
VM
VM
tPLH
tPHL
tW
LE input
Qn output
001aae083
tTLH
tTHL
90 %
10 %
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 17 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Measurement points are given in Table 11.
Fig 10. 3-state enable and disable time
Measurement points are given in Table 11.
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE)
Table 11: Measurement points
Type Input Output
VMVM
74HC373 0.5VCC 0.5VCC
74HCT373 1.3 V 1.3 V
001aae307
tPLZ
tPHZ
outputs
disabled outputs
enabled
90%
10%
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
001aae084
VM
LE input
Dn input VM
th
tsu
th
tsu
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 18 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 12. Load circuitry for measuring switching times
Table 12: Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC373 VCC 6 ns 15 pF, 50 pF 1 kΩopen GND VCC
74HCT373 3 V 6 ns 15 pF, 50 pF 1 kΩopen GND VCC
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
PULSE
GENERATOR
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 19 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
13. Package outline
Fig 13. Package outline SOT146-1 (DIP20)
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1 99-12-27
03-02-13
A
min. A
max. bZ
max.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 26.92
26.54 6.40
6.22 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 24.2 0.51 3.2
0.068
0.051 0.021
0.015 0.014
0.009 1.060
1.045 0.25
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0780.17 0.02 0.13
SC-603MS-001
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 20 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 14. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 21 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 15. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 22 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 16. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 23 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 17. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 24 of 26
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
14. Abbreviations
15. Revision history
Table 13: Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 14: Revision history
Document ID Release date Data sheet status Change notice Doc. number Supersedes
74HC_HCT373_3 20060120 Product data sheet - - 74HC_HCT373_CNV_2
Modifications: •The format of this data sheet is redesigned to comply with the current presentation and
information standard of Philips Semiconductors.
•Added type numbers 74HC373BQ and 74HCT373BQ (package DHVQFN20).
•Added family specifications.
•Added abbreviations list.
74HC_HCT373_CNV_2 19970827 Product
specification ---
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
74HC_HCT373_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 January 2006 25 of 26
16. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
19. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Level Data sheet status[1] Product status[2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.Date of release: 20 January 2006
Document number: 74HC_HCT373_3
Published in The Netherlands
Philips Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
21. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
16 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 25
17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20 Contact information . . . . . . . . . . . . . . . . . . . . 25
