INDUSTRIAL TEMPERATURE RANGE
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
1JUNE 2006INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2006 Integrated Device Technology, Inc. DSC-5487/4
FEATURES:
• A and C grades
• Low input and output leakage ≤≤
≤≤
≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
–VOH = 3.3V (typ.)
–VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in the SOIC and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT823AT/CT
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTER
DESCRIPTION:
The FCT823T series is built using an advanced dual metal CMOS
technology. The FCT823T series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The FCT823T is a 9-bit wide buffered register with Clock Enable
(EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance
microprogrammed systems.
The FCT823T high-performance interface family can drive large capacitive
loads, while providing low-capacitance bus loading at both inputs and
outputs. All inputs have clamp diodes and all outputs are designed for low-
capacitance bus loading in high-impedance state.
D
CP Q
Q
CL
D
CP Q
Q
CL
D0DN
Y0YN
EN
CLR
CP
OE
INDUSTRIAL TEMPERATURE RANGE
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IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
PIN CONFIGURATION Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
COUT Output Capacitance VOUT = 0V 8 12 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1)
Internal/
Inputs Outputs
OE CLR EN Dx CP Qx Yx Function
HHLL↑L Z High Z
HHLH↑HZ
H L X X X L Z Clear
LLXXXLL
H H H X X NC Z Hold
LHHXXNCNC
HHLL↑L Z Load
HHLH↑HZ
LHLL↑LL
LHLH↑HH
NOTE:
1 . H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance
2
3
1
20
19
18
15
16
9
10
D6
D7
D2
D5
D3
D4
D8
23
22
24
21
17
5
6
7
4
8
D0
VCC
CP
OE
13
14
11
12
D1
GND
CLR
Y6
Y7
Y2
Y5
Y3
Y4
Y8
Y0
Y1
EN
SOIC/ QSOP
TOP VIEW
Pin Names I/O Description
Dx I D Flip-Flop Data Inputs
CLR I When the clear input is LOW and OE is LOW, the
Qx outputs are LOW. When the clear input is HIGH,
data can be entered into the register.
CP I Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Yx O Register 3-State Outputs
EN I Clock Enable. When the clock enable is LOW, data
on the Dx output is transferred to the Qx output on the
LOW-to-HIGH transition. When the clock enable is
HIGH, the Qx outputs do not change state, regardless
of the data or clock input transitions.
OE I Output Control. When the OE is HIGH, the Yx
outputs are in the high-impedance state. When the
OE is LOW, the TRUE register data is present at the
Yx outputs.
PIN DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
3
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1µA
IIL Input LOW Current(4) VCC = Max. VI = 0.5V — — ±1µA
IOZH High Impedance Output Current(4) VCC = Max., VI = VCC (Max.) VI = 2.7V — — ±1µA
IOZL VI = 0.5V — — ±1
IIInput HIGH Current(4) VCC = Max., VI = VCC (Max.) — — ±1µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis — — 200 — m V
ICC Quiescent Power Supply Current VCC = Max. — 0.01 1 mA
VIN = GND or VCC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VOH Output HIGH Voltage VCC = Min IOH = –8mA 2 .4 3.3 — V
VIN = VIH or VIL IOH = –15mA 2 3 —
VOL Output LOW Voltage VCC = Min IOL = 48mA — 0.3 0.5 V
VIN = VIH or VIL
IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 –225 mA
IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO
≤≤
≤≤
≤
4.5V — — ±1µA
OUTPUT DRIVE CHARACTERISTICS
INDUSTRIAL TEMPERATURE RANGE
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IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ΔICC Quiescent Power Supply Current VCC = Max. — 0.5 2 mA
TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply VCC = Max. VIN = VCC — 0.15 0.25 mA/
Current(4) Outputs Open VIN = GND M Hz
OE = EN = GND
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 1.5 3.5 mA
Outputs Open VIN = GND
fCP = 10MHz
50% Duty Cycle
OE = EN = GND VIN = 3.4V — 2 5.5
One Bit Toggling VIN = GND
at fi = 5MHz
VCC = Max. VIN = VCC — 3.8 7.3(5)
Outputs Open VIN = GND
fCP = 10MHz
50% Duty Cycle
OE = EN = GND VIN = 3.4V — 6 16.3(5)
Eight Bits Toggling VIN = GND
at fi = 2.5MHz
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT823AT FCT823CT
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 10 1.5 6 ns
tPHL CP to Yx (OE = LOW) RL = 500Ω
CL = 300pF(4) 1.5 20 1.5 12.5 ns
RL = 500Ω
tSU Set-up Time HIGH or LOW Dx to CP CL = 50pF 4 — 3 — ns
tHHold Time HIGH or LOW Dx to CP RL = 500Ω2 — 1.5 — ns
tSU Set-up Time HIGH or LOW EN to CP 4 — 3 — ns
tHHold Time HIGH or LOW EN to CP 2 — 0 — ns
tPHL Propagation Delay, CLR to Yx 1.5 14 1.5 8 ns
tREM Recovery Time CLR to CP 6 — 6 — ns
tWClock Pulse Width HIGH or LOW 7 — 6 — ns
tWCLR Pulse Width LOW 6 — 6 — ns
tPZH Output Enable Time OE to Yx CL = 50pF 1.5 12 1.5 7 ns
tPZL RL = 500Ω
CL = 300pF(4) 1.5 23 1.5 12.5 ns
RL = 500Ω
tPHZ Output Disable Time OE to Yx CL = 5pF(4) 1.5 7 1.5 6 ns
tPLZ RL = 500Ω
CL = 50pF 1.5 8 1.5 6.5 ns
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
INDUSTRIAL TEMPERATURE RANGE
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IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
Pulse
Generator
RT
D.U.T
.
VCC
VIN
CL
VOUT
50pF 500W
500W
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU tH
tREM
tSU tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal Link
Octal Link
Octal Link
Octal Link
Octal Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
7
ORDERING INFORMATION
XX
Temp. Range
XXXX
Device Type
X
Package
SO
SOG
Q
QG
823AT
823CT
Small Outline IC
SOIC - Green
Quarter-size Small Outline Package
QSOP - Green
Bus Interface Register
74 - 40°C to +85°C
IDT FCT
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
