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LM4879 1.1 Watt Audio Power Amplifier
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1FEATURES DESCRIPTION
The LM4879 is an audio power amplifier primarily
23• No Output Coupling Capacitors, Snubber designed for demanding applications in mobile
Networks or Bootstrap Capacitors Required phones and other portable communication device
• Unity Gain Stable applications. It is capable of delivering 1.1 watt of
• Ultra Low Current Shutdown Mode continuous average power to an 8ΩBTL load with
less than 1% distortion (THD+N) from a 5VDC power
• Fast Turn On: 80ms (typ), 110ms (max) with supply.
1.0µF Capacitor Boomer™ audio power amplifiers were designed
• BTL Output Can Drive Capacitive Loads up to specifically to provide high quality output power with a
100pF minimal amount of external components. The
• Advanced Pop and Click Circuitry Eliminates LM4879 does not require output coupling capacitors
Noises During Turn-On and Turn-Off or bootstrap capacitors, and therefore is ideally suited
Transitions for lower-power portable applications where minimal
space and power consumption are primary
• 2.2V - 5.0V Operation requirements.
• Available in Space-Saving DSBGA, WSON, and
VSSOP Packages The LM4879 features a low-power consumption
global shutdown mode, which is achieved by driving
the shutdown pin with logic low. Additionally, the
APPLICATIONS LM4879 features an internal thermal shutdown
• Mobile Phones protection mechanism.
• PDAs The LM4879 contains advanced pop and click
• Portable electronic devices circuitry which eliminates noises which would
otherwise occur during turn-on and turn-off
KEY SPECIFICATIONS transitions.
• PSRR: 5V, 3V at 217Hz: 62dB (typ) The LM4879 is unity-gain stable and can be
configured by external gain-setting resistors.
• Power Output at 5V, 1%THD+N: 1.1W (typ)
• Power Output at 3V, 1%THD+N: 350mW (typ)
• Shutdown Current: 0.1µA (typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Boomer is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
7
6
5
8SHUTDOWN
BYPASS
+IN
-IN Vo
1
VDD
GN
D
Vo
2
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CONNECTION DIAGRAMS
Top View Top View
Figure 2. 8 Bump DSBGA Package Figure 3. VSSOP Package
See Package Number YPB0008 See Package Number DGS0010A
NC = No Connect
Top View Top View
Figure 4. 9 Bump DSBGA Package Figure 5. 9 Bump DSBGA Package
See package Number BLA09AAB See package Number YZR0009AAA
Top View
Figure 6. WSON Package
See Package Number NGT0008A
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage(3) 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation(4)(5) Internally Limited
ESD Susceptibility(6) 2000V
ESD Susceptibility(7) 200V
Junction Temperature 150°C
θJA (YPB0008) 220°C/W(8)
θJA (NGT0008A) 64°C/W(9)
θJA (YZR0009AAA) 180°C/W(8)
Thermal Resistance θJA (BLA09AAB) 180°C/W(8)
θJC (DGS0010A) 56°C/W
θJA (DGS0010A) 190°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) If the product is in shutdown mode, and VDD exceeds 6V (to a max of 8V VDD), then most of the excess current will flow through the
ESD protection circuits. If the source impedance limits the current to a max of 10ma, then the part will be protected. If the part is
enabled when VDD is above 6V, circuit performance will be curtailed or the part may be permanently damaged.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower. For the LM4879, see power derating curves for additional information.
(5) Maximum power dissipation (PDMAX) in the device occurs at an output power level significantly below full output power. PDMAX can be
calculated using Equation 2 shown in the APPLICATION INFORMATION section. It may also be obtained from the power dissipation
graphs.
(6) Human body model, 100pF discharged through a 1.5kΩresistor.
(7) Machine Model, 220pF–240pF discharged through all pins.
(8) All bumps have the same thermal resistance and contribute equally when used to lower thermal resistance.
(9) The stated θJA is achieved when the WSON package's DAP is soldered to a 4in2copper heatsink plain.
OPERATING RATINGS
Temperature Range TMIN ≤TA≤TMAX −40°C ≤TA≤85°C
Supply Voltage 2.2V ≤VDD ≤5.5V
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ELECTRICAL CHARACTERISTICS VDD = 5V(1)(2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA= 25°C.
LM4879 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)(5)
IDD Quiescent Power Supply Current VIN = 0V, 8ΩBTL 5 10 mA (max)
ISD Shutdown Current Vshutdown = GND 0.1 2.0 µA (max)
VOS Output Offset Voltage 5 40 mV (max)
PoOutput Power THD+N = 1% (max); f = 1kHz 1.1 0.9 W (min)
THD+N Total Harmonic Distortion+Noise Po= 0.4Wrms; f = 1kHz 0.1 %
Vripple = 200mVsine p-p, CB= 1.0µF 68 (f = 1kHz)
PSRR Power Supply Rejection Ratio 55 dB (min)
62 (f = 217Hz)
Input terminated with 10Ωto ground
VSDIH Shutdown High Input Voltage 1.4 V (min)
VSDIL Shutdown Low Input Voltage 0.4 V (max)
TWU Wake-up Time CB= 1.0µF 80 110 ms (max)
A-Weighted; Measured across 8ΩBTL
NOUT Output Noise 26 µVRMS
Input terminated with 10Ωto ground
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(5) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
ELECTRICAL CHARACTERISTICS VDD = 3.0V(1)(2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA= 25°C.
LM4879 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)(5)
IDD Quiescent Power Supply Current VIN = 0V, 8ΩBTL 4.5 9 mA (max)
ISD Shutdown Current Vshutdown = GND 0.1 2.0 µA (max)
VOS Output Offset Voltage 5 40 mV (max)
PoOutput Power THD+N = 1% (max); f = 1kHz 350 320 mW
THD+N Total Harmonic Distortion+Noise Po= 0.15Wrms; f = 1kHz 0.1 %
Vripple = 200mVsine p-p, CB= 1.0µF 68 (f = 1kHz)
PSRR Power Supply Rejection Ratio 55 dB (min)
62 (f = 217Hz)
Input terminated with 10Ωto ground
VSDIH Shutdown High Input Voltage 1.4 V (min)
VSDIL Shutdown Low Input Voltage 0.4 V (max)
TWU Wake-up Time CB= 1.0µF 80 110 ms (max)
A-Weighted; Measured across 8Ω
NOUT Output Noise BTL 26 µVRMS
Input terminated with 10Ωto ground
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(5) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
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ELECTRICAL CHARACTERISTICS VDD = 2.6V(1)(2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA= 25°C.
LM4879 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)(5)
IDD Quiescent Power Supply Current VIN = 0V, 8ΩBTL 3.5 mA
ISD Shutdown Current Vshutdown = GND 0.1 µA
VOS Output Offset Voltage 5 mV
THD+N = 1% (max); f = 1kHz
PoOutput Power RL= 8Ω250 mW
RL= 4Ω350
THD+N Total Harmonic Distortion+Noise Po= 0.1Wrms; f = 1kHz 0.1 %
Vripple = 200mVsine p-p, CB= 1.0µF 55 (f = 1kHz)
PSRR Power Supply Rejection Ratio dB
Input terminated with 10Ωto ground 55 (f = 217Hz)
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(5) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
EXTERNAL COMPONENTS DESCRIPTION
(See Figure 1)
Components Functional Description
1. RiInverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass
filter with Ciat fC= 1/(2πRiCi).
2. CiInput coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with
Riat fc= 1/(2πRiCi). Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for an explanation
of how to determine the value of Ci.
3. RfFeedback resistance which sets the closed-loop gain in conjunction with Ri.
4. CSSupply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for
information concerning proper placement and selection of the supply bypass capacitor.
5. CBBypass pin capacitor which provides half-supply filtering. Refer to the section, PROPER SELECTION OF EXTERNAL
COMPONENTS, for information concerning proper placement and selection of CB.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 8Ω, PWR = 250mW VDD = 3V, RL= 8Ω, PWR = 150mW
Figure 7. Figure 8.
THD+N vs Frequency THD+N vs Frequency
VDD = 2.6V, RL= 8Ω, PWR = 100mW VDD = 2.6V, RL= 4Ω, PWR = 100mW
Figure 9. Figure 10.
THD+N vs Power Out THD+N vs Power Out
VDD = 5V, RL= 8Ω, f = 1kHz VDD = 3V, RL= 8Ω, f = 1kHz
Figure 11. Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Power Out THD+N vs Power Out
VDD = 2.6V, RL= 8Ω, f = 1kHz VDD = 2.6V, RL= 4Ω, f = 1kHz
Figure 13. Figure 14.
Power Supply Rejection Ratio Power Supply Rejection Ratio
VDD = 5V VDD = 3V
Figure 15. Figure 16.
Power Dissipation
Power Supply Rejection Ratio vs Output Power
VDD = 2.6V VDD = 5V
Figure 17. Figure 18.
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RL = 4:
OUTPUT POWER (W)
POWER DISSIPATION (W)
RL = 8:
0 0.4 0.8 1.2 1.6 2
VDD = 5V
f = 1 kHz
THD + N d 1%
BW < 80 kHz
1.4
1.2
0.8
0.6
0.2
0
0.4
1.0
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Dissipation Power Dissipation
vs Output Power vs Output Power
VDD = 3V VDD = 2.6V
Figure 19. Figure 20.
Power Dissipation Power Derating - MSOP
vs Output Power (LLP Package) PDMAX = 670mW
VDD = 5V VDD = 5V, RL= 8Ω
Figure 21. Figure 22.
Power Derating - 8 Bump µSMD Power Derating - 9 Bump µSMD
PDMAX = 670mW PDMAX = 670mW
VDD = 5V, RL= 8ΩVDD = 5V, RL= 8Ω
Figure 23. Figure 24.
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0 20 40 60 80 100 120 140 160
AMBIENT TEMPERATURE (qC)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
POWER DISSIPATION (W)
4 in2 Heatsink Area
1 in2 Heatsink Area
2 in2 Heatsink Area
No
Heatsink
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Derating - LLP
PDMAX = 670mV Output Power
VDD = 5V, RL= 8 vs Supply Voltage
Figure 25. Figure 26.
Output Power Output Power
vs Supply Voltage vs Load Resistance
Figure 27. Figure 28.
Clipping (Dropout) Voltage Supply Current
vs Supply Voltage Shutdown Voltage
Figure 29. Figure 30.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Shutdown Hysterisis Voltage Shutdown Hysterisis Voltage
VDD = 5V VDD = 3V
Figure 31. Figure 32.
Shutdown Hysterisis Voltage Open Loop
VDD = 2.6V Frequency Response
Figure 33. Figure 34.
Frequency Response
vs Input Capacitor Size
Figure 35.
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APPLICATION INFORMATION
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4879 has two operational amplifiers internally, allowing for a few different amplifier
configurations. The first amplifier's gain is externally configurable, while the second amplifier is internally fixed in
a unity-gain, inverting configuration. The closed-loop gain of the first amplifier is set by selecting the ratio of Rfto
Riwhile the second amplifier's gain is fixed by the two internal 20 kΩresistors. Figure 1 shows that the output of
amplifier one serves as the input to amplifier two which results in both amplifiers producing signals identical in
magnitude, but out of phase by 180°. Consequently, the differential gain for the IC is
AVD = 2 *(Rf/Ri) (1)
By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closed-
loop gain without causing excessive clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section.
A bridge configuration, such as the one used in LM4879, also creates a second advantage over single-ended
amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across
the load. This eliminates the need for an output coupling capacitor which is required in a single supply, single-
ended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would
result in both increased internal IC power dissipation and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. Since the LM4879 has two operational amplifiers in one package, the
maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation
for a given application can be derived from the power dissipation graphs or from Equation 2.
PDMAX = 4*(VDD)2/(2π2RL) (2)
It is critical that the maximum junction temperature (TJMAX) of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced from a free air value of 150°C/W, resulting in higher PDMAX.
Additional copper foil can be added to any of the leads connected to the LM4879. It is especially effective when
connected to VDD, GND, and the output pins. Refer to the application information on the LM4879 reference
design board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional changes must be
made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient
temperature. Internal power dissipation is a function of output power. Refer to the TYPICAL PERFORMANCE
CHARACTERISTICS curves for power dissipation information for different output powers and output loading.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as
possible. Typical applications employ a 5V regulator with 10 µF tantalum or electrolytic capacitor and a ceramic
bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM4879. The selection of a bypass capacitor, especially CB, is dependent upon PSRR requirements, click
and pop performance (as explained in the section, PROPER SELECTION OF EXTERNAL COMPONENTS),
system cost, and size constraints.
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SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the LM4879 contains a shutdown pin to externally turn off
the amplifier's bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the
shutdown pin. By switching the shutdown pin to ground, the LM4879 supply current draw will be minimized in idle
mode. While the device will be disabled with shutdown pin voltages less than 0.4VDC, the idle current may be
greater than the typical value of 0.1µA. (Idle current is measured with the shutdown pin tied to ground).
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry to
provide a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch in
conjunction with an external pull-up resistor. When the switch is closed, the shutdown pin is connected to ground
which disables the amplifier. If the switch is open, then the external pull-up resistor to VDD will enable the
LM4879. This scheme ensures that the shutdown pin will not float thus preventing unwanted state changes.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers is critical to optimize
device and system performance. While the LM4879 is tolerant of external component combinations,
consideration to component values must be used to maximize overall system quality.
The LM4879 is unity-gain stable which gives the designer maximum system flexibility. The LM4879 should be
used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain
configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1
Vrms are available from sources such as audio codecs. Please refer to the section, AUDIO POWER AMPLIFIER
DESIGN, for a more complete explanation of proper gain selection.
Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the
bandwidth is dictated by the choice of external components shown in Figure 1. The input coupling capacitor, Ci,
forms a first order high pass filter which limits low frequency response. This value should be chosen based on
needed frequency response for a few distinct reasons.
SELECTION OF INPUT CAPACITOR SIZE
Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized
capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers
used in portable systems, whether internal or external, have little ability to reproduce signals below 100 Hz to
150 Hz. Thus, using a large input capacitor may not increase actual system performance.
In addition to system cost and size, click and pop performance is effected by the size of the input coupling
capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally
1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable.
Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be
minimized.
Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value.
Bypass capacitor, CB, is the most critical component to minimize turn-on pops since it determines how fast the
LM4879 turns on. The slower the LM4879's outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the
smaller the turn-on pop. Choosing CBequal to 1.0 µF along with a small value of Ci(in the range of 0.1 µF to
0.39 µF), should produce a virtually clickless and popless shutdown function. While the device will function
properly, (no oscillations or motorboating), with CBequal to 0.1 µF, the device will be much more susceptible to
turn-on clicks and pops. Thus, a value of CBequal to 1.0 µF is recommended in all but the most cost sensitive
designs.
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AUDIO POWER AMPLIFIER DESIGN
A 1W/8ΩAUDIO AMPLIFIER
Given:
Power Output 1 Wrms
Load Impedance 8Ω
Input Level 1 Vrms
Input Impedance 20 kΩ
Bandwidth 100 Hz–20 kHz ± 0.25 dB
A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating
from the Output Power vs Supply Voltage graphs in the TYPICAL PERFORMANCE CHARACTERISTICS
section, the supply rail can be easily found. A second way to determine the minimum supply rail is to calculate
the required Vopeak using Equation 3 and add the output voltage. Using this method, the minimum supply voltage
would be (Vopeak + (VODTOP + VODBOT)), where VODBOT and VODTOP are extrapolated from the Dropout Voltage vs
Supply Voltage curve in the TYPICAL PERFORMANCE CHARACTERISTICS section.
(3)
5V is a standard voltage, in most applications, chosen for the supply rail. Extra supply voltage creates headroom
that allows the LM4879 to reproduce peaks in excess of 1W without producing audible distortion. At this time, the
designer must make sure that the power supply choice along with the output impedance does not violate the
conditions explained in the POWER DISSIPATION section.
Once the power dissipation equations have been addressed, the required differential gain can be determined
from Equation 4.(4)
AVD = (Rf/Ri) 2 (5)
From Equation 4, the minimum AVD is 2.83; use AVD = 3.
Since the desired input impedance was 20 kΩ, and with a AVD of 3, a ratio of 1.5:1 of Rfto Riresults in an
allocation of Ri= 20 kΩand Rf= 30 kΩ. The final design step is to address the bandwidth requirements which
must be stated as a pair of −3 dB frequency points. Five times away from a −3 dB point is 0.17 dB down from
passband response which is better than the required ±0.25 dB specified.
fL= 100 Hz/5 = 20 Hz
fH= 20 kHz * 5 = 100 kHz
As stated in the EXTERNAL COMPONENTS DESCRIPTION section, Riin conjunction with Cicreate a high pass
filter.
Ci≥1/(2π*20 kΩ*20 Hz) = 0.397 µF; use 0.39 µF
The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain,
AVD. With a AVD = 3 and fH= 100 kHz, the resulting GBWP = 300 kHz which is much smaller than the LM4879
GBWP of 10 MHz. This figure displays that if a designer has a need to design an amplifier with a higher
differential gain, the LM4879 can still be used without running into bandwidth limitations.
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SNAS142G –SEPTEMBER 2001–REVISED MAY 2013
Figure 36. Higher Gain Audio Amplifier
The LM4879 is unity-gain stable and requires no external components besides gain-setting resistors, an input
coupling capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential
gain of greater than 10 is required, a feedback capacitor (C4) may be needed as shown in Figure 36 to
bandwidth limit the amplifier. This feedback capacitor creates a low pass filter that eliminates possible high
frequency oscillations. Care should be taken when calculating the -3dB frequency in that an incorrect
combination of R3and C4will cause rolloff before 20kHz. A typical combination of feedback resistor and
capacitor that will not produce audio band high frequency rolloff is R3= 20kΩand C4= 25pf. These components
result in a -3dB point of approximately 320 kHz.
Figure 37. Differential Amplifier Configuration for LM4879
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM4879 LM4879MMBD LM4879SDBD
LM4879, LM4879MMBD, LM4879SDBD
SNAS142G –SEPTEMBER 2001–REVISED MAY 2013
www.ti.com
Figure 38. Reference Design Board and Layout - DSBGA
Figure 39. Reference Design Board and PCB Layout Guidelines - VSSOP and SO Boards
16 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: LM4879 LM4879MMBD LM4879SDBD
LM4879, LM4879MMBD, LM4879SDBD
www.ti.com
SNAS142G –SEPTEMBER 2001–REVISED MAY 2013
Figure 47. Bottom Layer
Table 1. Mono LM4879 Reference Design Boards Bill of Material for all 3 Demo Boards
Item Part Number Part Description Qty Ref Designator
1 551011208-001 LM4879 Mono Reference Design Board 1
10 482911183-001 LM4879 Audio AMP 1 U1
20 151911207-001 Tant Cap 1uF 16V 10 1 C1
21 151911207-002 Cer Cap 0.39uF 50V Z5U 20% 1210 1 C2
25 152911207-001 Tant Cap 1.0uF 16V 10 1 C3
30 472911207-001 Res 20K Ohm 1/10W 5 3 R1, R2, R3
35 210007039-002 Jumper Header Vertical Mount 2X1 0.100 2 J1, J2
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM4879 LM4879MMBD LM4879SDBD
LM4879, LM4879MMBD, LM4879SDBD
www.ti.com
SNAS142G –SEPTEMBER 2001–REVISED MAY 2013
Figure 50. Bottom Layer
PCB LAYOUT GUIDELINES
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
GENERAL MIXED SIGNAL LAYOUT RECOMMENDATION
POWER AND GROUND CIRCUITS
For 2 layer mixed signal design, it is important to isolate the digital power and ground trace paths from the
analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central
point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal
performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even
device. This technique will take require a greater amount of design time but will not increase the final price of the
board. The only extra parts required may be some jumpers.
SINGLE-POINT POWER / GROUND CONNECTIONS
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing high frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
PLACEMENT OF DIGITAL AND ANALOG COMPONENTS
All digital components and high-speed digital signals traces should be located as far away as possible from
analog components and circuit traces.
AVOIDING TYPICAL DESIGN / LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM4879 LM4879MMBD LM4879SDBD
LM4879, LM4879MMBD, LM4879SDBD
SNAS142G –SEPTEMBER 2001–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision F (May 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: LM4879 LM4879MMBD LM4879SDBD
PACKAGE OPTION ADDENDUM
www.ti.com 9-Aug-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4879ITL/NOPB ACTIVE DSBGA YZR 9 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 G
B3
LM4879MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 G79
LM4879SD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 L4879SD
LM4879SDX/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 L4879SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 9-Aug-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4879ITL/NOPB DSBGA YZR 9 250 178.0 8.4 1.7 1.7 0.76 4.0 8.0 Q1
LM4879MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM4879SD/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM4879SDX/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4879ITL/NOPB DSBGA YZR 9 250 210.0 185.0 35.0
LM4879MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0
LM4879SD/NOPB WSON NGT 8 1000 210.0 185.0 35.0
LM4879SDX/NOPB WSON NGT 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2013
Pack Materials-Page 2
MECHANICAL DATA
NGT0008A
www.ti.com
SDC08A (Rev A)
MECHANICAL DATA
YZR0009xxx
www.ti.com
TLA09XXX (Rev C)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
4215046/A 12/12
NOTES:
D: Max =
E: Max =
1.542 mm, Min =
1.542 mm, Min =
1.481 mm
1.481 mm
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