LT8490
1
8490fa
For more information www.linear.com/LT8490
Typical applicaTion
FeaTures DescripTion
High Voltage, High Current
Buck-Boost Battery Charge Controller with
Maximum Power Point Tracking (MPPT)
The LT
®
8490 is a buck-boost switching regulator battery
charger that implements a constant-current constant-
voltage (CCCV) charging profile used for most battery
types, including sealed lead-acid (SLA), flooded, gel and
lithium-ion. The device operates from input voltages
above, below or equal to the output voltage and can be
powered by a solar panel or a DC power supply. On-chip
logic provides automatic maximum power point tracking
(MPPT) for solar powered applications. The LT8490 can
perform automatic temperature compensation by sensing
an external thermistor thermally coupled to the battery.
STATUS and FAULT pins containing charger information
can be used to drive LED indicator lamps. The device is
available in a low profile (0.75mm) 7mm × 11mm 64-lead
QFN package.
Simplified Solar Powered Battery Charger Schematic
applicaTions
n VIN Range: 6V to 80V
n VBAT Range: 1.3V to 80V
n Single Inductor Allows VIN Above, Below, or Equal
to VBAT
n Automatic MPPT for Solar Powered Charging
n Automatic Temperature Compensation
n No Software or Firmware Development Required
n Operation from Solar Panel or DC Supply
n Input and Output Current Monitor Pins
n Four Integrated Feedback Loops
n Synchronizable Fixed Frequency: 100kHz to 400kHz
n 64-Lead (7mm × 11mm × 0.75mm) QFN Package
n Solar Powered Battery Chargers
n Multiple Types of Lead-Acid Battery Charging
n Li-Ion Battery Charger
n Battery Equipped Industrial or Portable Military
Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LT8490
SOLAR PANEL
TG1 BOOST1
CSNIN
CSPIN
V
IN
CSPOUT
CSNOUT
EXTV
CC
AV
DD
TEMPSENSE
GATEV
CC
INTV
CC
SW1 BG1 CSP CSN
STATUS FAULT
AV
DD
BG2 SW2 BOOST2 TG2
GND
RECHARGABLE
BATTERY
LOAD
THERMISTOR
+ –
8490 TA01a
AV
DD
GATEV
CC
´
GATEV
CC
´ GATEV
CC
´
V
BAT
8490 TA01b
0.5s/DIV
VPANEL
6V/DIV
IPANEL
1.36A/DIV
BACK PAGE APPLICATION
PERTURB &
OBSERVE
PERTURB &
OBSERVE
FULL PANEL SCAN
Maximum Power Point Tracking
LT8490
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8490fa
For more information www.linear.com/LT8490
pin conFiguraTionabsoluTe MaxiMuM raTings
VCSP – VCSN, VCSPIN – VCSNIN,
VCSPOUT – VCSNOUT ................................... –0.3V to 0.3V
SS, CLKOUT, CSP, CSN Voltage .................. –0.3V to 3V
VC Voltage (Note 2) ................................... –0.3V to 2.2V
LDO33, VDD, AVDD Voltage .......................... –0.3V to 5V
RT, FBOUT Voltage ....................................... –0.3V to 5V
IMON_IN, IMON_OUT Voltage .................... –0.3V to 5V
SYNC Voltage ............................................ –0.3V to 5.5V
INTVCC, GATEVCC Voltage ........................... –0.3V to 7V
VBOOST1 – VSW1, VBOOST2 – VSW2 ................ –0.3V to 7V
SWEN, MODE Voltage ................................. –0.3V to 7V
SRVO_FBIN, SRVO_FBOUT Voltage ........... –0.3V to 30V
SRVO_IIN, SRVO_IOUT Voltage ................. –0.3V to 30V
FBIN, SHDN Voltage ................................... –0.3V to 30V
CSNIN, CSPIN, CSPOUT, CSNOUT Voltage .. –0.3V to 80V
VIN, EXTVCC Voltage .................................. –0.3V to 80V
SW1, SW2 Voltage .....................................81V (Note 5)
BOOST1, BOOST2 Voltage ........................ –0.3V to 87V
BG1, BG2, TG1, TG2 ........................................... (Note 4)
IOW, ECON, CLKDET Voltage ......... –0.3V to VDD + 0.5V
SWENO, STATUS Voltage ................ –0.3V to VDD + 0.5V
FBOW, FBIW, FAULT Voltage .......... –0.3V to VDD + 0.5V
VINR, FBOR, IIR, IOR Voltage ......... –0.3V to VDD + 0.5V
TEMPSENSE Voltage....................... –0.3V to VDD + 0.5V
CHARGECFG2,
CHARGECFG1 Voltage ..................... –0.3V to VDD + 0.5V
Operating Junction Temperature Range
LT8490E (Notes 1, 3) ......................... –40°C to 125°C
LT8490I (Notes 1, 3) .......................... –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
(Note 1)
TOP VIEW
UKJ PACKAGE
64-LEAD (7mm × 11mm) PLASTIC QFN
65
GND
FBIR 1
FAULT 2
TEMPSENSE 3
VDD 4
FBOW 5
FBIW 6
INTVCC 7
SWEN 8
MODE 9
IMON_IN 10
SHDN 11
CSN 12
CSP 13
LDO33 14
FBIN 15
FBOUT 16
IMON_OUT 17
VC 18
SS 19
CLKOUT 20
52 NC
51 STATUS
50 IOW
49 SWENO
48 ECON
46 VIN
45 CSPIN
44 CSNIN
42 CSPOUT
41 CSNOUT
40 EXTVCC
38 SRVO_FBOUT
37 SRVO_IOUT
36 SRVO_IIN
35 SRVO_FBIN
33 BOOST1
64 IOR
63 CHARGECFG2
62 GND
61 CHARGECFG1
60 NC
59 GND
58 AVDD
57 FBOR
56 CLKDET
55 GND
54 VINR
53 IIR
SYNC 21
RT 22
BG1 23
GATEVCC 24
BG2 25
BOOST2 27
TG2 28
SW2 29
SW1 31
TG1 32
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8490EUKJ#PBF LT8490EUKJ#TRPBF LT8490UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C
LT8490IUKJ#PBF LT8490IUKJ#TRPBF LT8490UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
LT8490
3
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For more information www.linear.com/LT8490
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Supply and Regulators
VIN Operating Voltage Range (Note 7) l6 80 V
VIN Quiescent Current Not Switching, VEXTVCC = 0, VDD = AVDD = Float 2.65 4.2 mA
VIN Quiescent Current in Shutdown VSHDN = 0V 0 1 µA
VDD Quiescent Current IAVDD + IVDD, VDD = AVDD = 3.3V l2.5 4 6.5 mA
EXTVCC Switchover Voltage IINTVCC = 20mA, VEXTVCC Rising l6.15 6.4 6.6 V
EXTVCC Switchover Hysteresis 0.18 V
LDO33 Pin Voltage 5mA from LDO33 Pin l3.23 3.295 3.35 V
LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 %
LDO33 Pin Current Limit l12 17.25 22 mA
LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V
LDO33 Pin Undervoltage Lockout Hysteresis 35 mV
Switching Regulator Control
SHDN Input Voltage High SHDN Rising to Enable the Device l1.184 1.234 1.284 V
SHDN Input Voltage High Hysteresis 50 mV
SHDN Input Voltage Low Device Disabled, Low Quiescent Current l0.35 V
SHDN Pin Bias Current VSHDN = 3V
VSHDN = 12V
0
11
1
22
µA
µA
SWEN Rising Threshold Voltage l1.156 1.206 1.256 V
SWEN Threshold Voltage Hysteresis 22 mV
MODE Pin Thresholds Discontinuous Mode
Forced Continuous Mode
l
l
0.4
2.3 V
V
IMON_OUT Rising threshold for CCM Operation MODE = 0V l168 195 224 mV
IMON_OUT Falling threshold for DCM MODE = 0V l95 122 150 mV
Voltage Regulation
Regulation Voltage for FBOUT VC = 1.2V, EXTVCC = 0V l1.193 1.207 1.222 V
Regulation Voltage for FBIN VC = 1.2V, EXTVCC = 0V l1.184 1.205 1.226 V
FBOUT Pin Bias Current Current Out of Pin 15 nA
FBIN Pin Bias Current Current Out of Pin 10 nA
Current Regulation
Regulation Voltage for IMON_IN and IMON_OUT VC = 1.2V, EXTVCC = 0V l1.187 1.208 1.229 V
IMON_IN Output Current VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V
VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V
VCSPIN – VCSNIN = 0mV, VCSPIN = 5V
l
l
54
53
2.5
57
57
7
60
61
11.5
µA
µA
µA
IMON_IN Overvoltage Threshold l1.55 1.61 1.67 V
IMON_OUT Output Current VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V
VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V
l
l
47.5
47
3.25
2.75
50
50
5
5
52.5
54.25
6.75
8
µA
µA
µA
µA
IMON_OUT Overvoltage Threshold l1.55 1.61 1.67 V
LT8490
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8490fa
For more information www.linear.com/LT8490
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Oscillator (OSC1)
Switch Frequency Range Syncing or Free Running 100 400 kHz
Switching Frequency, fOSC RT = 365k
RT = 215k
RT = 124k
l
l
l
102
170
310
120
202
350
142
235
400
kHz
kHz
kHz
SYNC High Level for Synchronization l1.3 V
SYNC Low Level for Synchronization l0.5 V
SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 %
Recommended Min SYNC Ratio, fSYNC /f
OSC 3/4
CLKOUT Output Voltage HIGH 1mA Out of CLKOUT Pin 2.3 2.45 2.55 V
CLKOUT Output Voltage LOW 1mA into CLKOUT Pin 25 100 mV
CLKOUT Duty Cycle TJ = –40°C
TJ = 25°C
TJ = 125°C
22.7
44.1
77
%
%
%
Charging Control
STATUS, FBOW, FBIW, SWENO, IOW,
ECON Output Low Voltage
IOL = 5mA l0.22 0.5 V
STATUS, FBOW, FBIW, SWENO, IOW,
ECON Output High Voltage
IOH = –5mA l2.7 3.0 V
FAULT Output Voltage Low IOL = 0.5mA l0.1 0.25 V
FAULT Output Voltage High IOH = –0.1mA l1.7 2.2 V
Power Supply Mode Detection Threshold (Note 6) VINR Pin Falling l155 174 mV
Power Supply Mode Detection Threshold Hysteresis (Note 6) VINR Pin 29 mV
Minimum VINR Voltage for Start-Up (Note 6) Not in Power Supply Mode
Low Power Mode Enabled
Low Power Mode Disabled
l
l
380
213
395
225
410
237
mV
mV
High Charging Current Threshold on IOR (Note 6) IOR Rising g ECON Rising l168 195 224 mV
Low Charging Current Threshold on IOR (Note 6) IOR Falling g ECON Falling l95 122 150 mV
Minimum CHARGECFG1 % of AVDD to Disable Stage 3
(Note 6)
Temperature Compensation Enabled l94 95 96 %
Maximum CHARGECFG1 % of AVDD to Disable Stage 3
(Note 6)
Temperature Compensation Disabled l4 5 6 %
Minimum CHARGECFG2 % of AVDD to Disable Time Limits
(Note 6)
Wide Valid Temperature Range l94 95 96 %
Maximum CHARGECFG2 % of AVDD to Disable Time Limits
(Note 6)
Narrow Valid Temperature Range l4 5 6 %
Minimum TEMPSENSE % of AVDD to Detect Battery Disconnected
(Note 6)
l94.5 96 97.5 %
VCSPOUT – VCSNOUT Threshold for C/5 Detection (Note 6) VCSxOUT Common Mode = 5.0V, RTOTAL from
IMON_OUT to Ground = 24.3kΩ
9 10 11 mV
VCSPOUT – VCSNOUT Threshold for C/10 Detection (Note 6) VCSxOUT Common Mode = 5.0V, IOR Falling,
RTOTAL from IMON_OUT to Ground = 24.3kΩ
4.25 5 5.75 mV
FBIW, FBOW PWM Frequency (OSC2) 31.25 kHz
FBIW, FBOW PWM Resolution 8 Bits
STATUS UART Bit Rate l2160 2400 2640 Baud
Internal A/D Resolution 10 Bits
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)
LT8490
5
8490fa
For more information www.linear.com/LT8490
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not force voltage on the VC pin.
Note 3: The LT8490E is guaranteed to meet performance specifications from
0°C to 125°C junction temperature. Specifications over the –40°C to 125°C
operating junction temperature range are assured by design, characterization
and correlation with statistical process controls. The LT8490I is guaranteed
over the full –40°C to 125°C junction temperature range.
Note 4: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Note 5: Negative voltages on the SW1 and SW2 pins are limited in the
applications by the body diodes of the external NMOS devices M2 and
M3 or parallel Schottky diodes when present. The SW1 and SW2 pins
are tolerant of these negative voltages in excess of one diode drop below
ground, guaranteed by design.
Note 6: These thresholds are measured by the internal A-D converter. The
A-D reference voltage is AVDD. AVDD, VDD and an additional 2.8mA load are
regulated by LDO33 to create the AVDD reference for these measurements.
The absolute threshold voltages will shift with corresponding changes in
the AVDD voltage.
Note 7: 10V minimum VIN required for solar powered start-up if low power
mode is enabled.
LT8490
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For more information www.linear.com/LT8490
Typical perForMance characTerisTics
STATUS VOH and VOL
(VDD = AVDD = 3.3V)
FAULT VOH and VOL
(VDD = AVDD = 3.3V)
LDO33 Load Regulation (Not
Connected to AVDD and VDD)IMON Output Currents
Power Supply Mode Charging
Lead Acid Battery "B”
TA = 25°C, unless otherwise noted.
|IFAULT| (mA)
0
VFAULT (V)
1
3
2
02
8490 G06
31
–40°C
125°C
–40°C
25°C
VOH
VOL
125°C
25°C
LOAD CURRENT (mA)
0
LDO33 (V)
3.1
3.3
3.4
3.2
38
8490 G07
204 12 16
25°C
–40°C
125°C
CSxIN-CSxOUT (mV)
–100
PIN CURRENT (µA)
0
175
200
125
150
100
50
75
25
–25 0 50
8490 G08
200–50 100 150
IMON_OUT
IMON_IN
|ISTATUS| (mA)
0
VSTATUS (V)
1
3
2
015
8490 G05
205 10
–40°C
125°C 25°C
–40°C
125°C
VOH
VOL
25°C
STAGE 2STAGE 1 STAGE 3
CHARGING TIME (HOURS)
0
VBAT (V) AND IBAT (A)
2.50
15.0
12.5
0
7.50
10.0
5.00
8490 G04
12
VBAT
BACK PAGE APPLICATION
IBAT
VIN = 36V
FBOUT, FBIN, IMONIN, IMONOUT
Voltage Rise vs Power
INTVCC REGULATOR POWER (W)
0
VOLTAGE RISE (%)
0.2
1.0
0.6
0.8
0.4
00.5
8490 G09
21 1.5
INTVCC REGULATED
FROM VIN
INTVCC REGULATED
FROM EXTVCC
Solar Powered Charging Lead
Acid Battery "A”
Solar Powered Charging Lead
Acid Battery "B”
Solar Powered Charging Lithium
Ion Battery
TIME OF DAY
9AM
VBAT (V) AND IBAT (A)
2.50
17.5
15.0
12.5
10.0
7.50
5.00
0
8490 G01
6PM
PARTLY CLOUDY
STAGE
SOME TRANSIENTS
FROM FULL PANEL
SCANS REMOVED
FOR CLARITY.
VBAT
IBAT SUNSET
CHARGING STAGE
0
3
BACK PAGE APPLICATION
TIME OF DAY
10AM
VBAT (V) AND IBAT (A)
CHARGING STAGE
2.50
17.5
15.0
12.5
10.0
7.50
5.00
0
8490 G02
6PM
VBAT
IBAT
CLOUDY DAY
STAGE
SOME TRANSIENTS
FROM FULL PANEL
SCANS REMOVED
FOR CLARITY.
0
SUNSET
3
BACK PAGE APPLICATION
TIME OF DAY
1PM
VBAT (V)
IBAT (A)
30
28
26
24
20
8490 G03
5PM
VBAT
PARTLY CLOUDY
STAGE 2STAGE 1
0
2
4
6
8
10
IBAT
SOME TRANSIENTS
FROM FULL PANEL
SCANS REMOVED
FOR CLARITY.
UART AND
STATUS
INDICATE
< C/10
FIGURE 34 APPLICATION
LT8490
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For more information www.linear.com/LT8490
Typical perForMance characTerisTics
Perturb and Observe
Maximum Power Point Tracking
Full Panel Scan Single Power
Peak
Full Panel Scan—Partially
Shaded with Dual Power Peaks
Panel Voltage in Low Power
Mode
Panel Voltage in Low Power
Mode
Maximum Power Point Tracking Perturb and Observe Perturb and Observe
TA = 25°C, unless otherwise noted.
8490 G10
30s/DIV
VPANEL
5V/DIV
IMON_OUT
500mV/DIV
PERTURB & OBSERVE
FIGURE 34 APPLICATION
FULL PANEL
SCANS
8490 G11
0.5s/DIV
VPANEL
5V/DIV
IMON_OUT
200mV/DIV
FIGURE 34 APPLICATION
8490 G12
0.5s/DIV
VPANEL
5V/DIV
IMON_OUT
100mV/DIV
FIGURE 34 APPLICATION
8490 G13
5s/DIV
VPANEL
6V/DIV
IMON_OUT
100mV/DIV
FIGURE 34 APPLICATION
ROTATE PANEL
TOWARDS THE SUN.
PANEL VOLTAGE
AND CURRENT ARE
AUTOMATICALLY
ADJUSTED TO
NEW MAX.
8490 G14
0.5s/DIV
VPANEL
10V/DIV
IMON_IN
500mV/DIV
IMON_OUT
500mV/DIV
FIGURE 34 APPLICATION
POWER PEAK
8490 G15
0.5s/DIV
VPANEL
10V/DIV
IMON_IN
200mV/DIV
IMON_OUT
200mV/DIV
FIGURE 34 APPLICATION
LOWER POWER PEAK
MAX POWER PEAK
8490 G16
40ms/DIV
VPANEL
5V/DIV
SWEN
5V/DIV
IMON_OUT
50mV/DIV
FIGURE 34 APPLICATION
10.6mV
10.4V
17.6V
3.3V
8490 G17
40ms/DIV
VPANEL
5V/DIV
SWEN
5V/DIV
IMON_OUT
50mV/DIV
FIGURE 34 APPLICATION
10.6mV
10.1V
3.3V
LT8490
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8490fa
For more information www.linear.com/LT8490
pin FuncTions
FBIR (Pin 1): A/D Input Pin. Connects to FBIN pin to
measure input feedback voltage.
FAULT (Pin 2): FAULT Pin. This pin generates an active
high digital output that, when used with an LED, provides
a visual indication of a fault event.
TEMPSENSE (Pin 3): A/D Input Pin. Connects to a thermis-
tor divider network for sensing battery temperature or a
resistor divider if unused. This pin is frequently monitored
for temperature compensation and enforcing temperature
limits.
VDD (Pin 4): Control Logic Power Supply Pin. Connect
this pin to LDO33 and AVDD.
FBOW (Pin 5): PWM Digital Output Pin. Connects to FBOUT
through an RCR network to temperature compensate the
battery voltage.
FBIW (Pin 6): PWM Digital Output Pin. Connects to FBIN
through an RCR network to adjust the solar panel volt-
age for MPPT.
INTVCC (Pin 7): Internal 6.35V Regulator Output Pin. Con-
nects to the GATEVCC pin. INTVCC is powered from EXTVCC
when the EXTVCC voltage is higher than 6.4V, otherwise
INTVCC is powered from VIN. Bypass this pin to ground
with a minimum 4.7µF ceramic capacitor. See Switching
Configuration - MODE Pin for additional details.
SWEN (Pin 8): Switch Enable Pin. Tie to the SWENO pin.
MODE (Pin 9): Mode Pin. The voltage applied to this pin
sets the operating mode of the switching regulator. Tie this
pin to INTVCC to make discontinuous current mode active.
Tie this pin to ground to operate in discontinuous current
mode for low battery charging currents and continuous
current mode for high battery charging currents. Do not
float this pin. See Switching Configuration - MODE Pin
for additional details.
IMON_IN (Pin 10): Input Current Monitor Pin. The current
out of this pin is proportional to the input current. See the
Applications Information section for more information.
SHDN (Pin 11): Shutdown Pin. In conjunction with the
UVLO (undervoltage lockout) circuit, this pin is used to
enable/disable the chip. Do not float this pin.
CSN (Pin 12): The (–) Input to the Inductor Current Sense
and Reverse Current Detect Amplifier.
CSP (Pin 13): The (+) Input to the Inductor Current Sense
and Reverse Current Detect Amplifier. The VC pin voltage
and built-in offsets between the CSP and CSN pins set the
current trip threshold.
LDO33 (Pin 14): 3.3V Regulator Output. This supply
provides power to the VDD and AVDD pins. Bypass this
pin to ground with a minimum 4.7µF ceramic capacitor.
FBIN (Pin 15): Input Feedback Pin. This pin is connected
to the input error amplifier input.
FBOUT (Pin 16): Output Feedback Pin. This pin connects
the error amplifier input to an external resistor divider
from the output.
IMON_OUT (Pin 17): Output Current Monitor Pin. The
current out of this pin is proportional to the average out-
put current. See the Applications Information section for
more information.
VC (Pin 18): Error Amplifier Output Pin. Tie the external
compensation network to this pin.
SS (Pin 19): Soft-Start Pin. Place 100nF of capacitance
from this pin to ground. Upon start-up, this pin will be
charged by an internal resistor to 2.5V.
CLKOUT (Pin 20): Switching Regulator Clock Output Pin.
CLKOUT will toggle at the same frequency as the switch-
ing regulator oscillator (OSC1 on the Block Diagram) or
as the SYNC pin, but is approximately 180° out-of-phase.
CLKOUT can also be used as a temperature monitor of the
switching regulator since the CLKOUT duty cycle varies
linearly with the junction temperature of the switching
regulator. It is connected to CLKDET through an RC filter.
The CLKOUT pin can drive capacitive loads up to 200pF.
SYNC (Pin 21): To synchronize the switching frequency
to an outside clock, simply drive this pin with a clock. The
high voltage level of the clock needs to exceed 1.3V, and
the low level should be less than 0.5V. Drive this pin to
less than 0.5V to revert to the internal free-running clock
(OSC1 in the Block Diagram).
LT8490
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For more information www.linear.com/LT8490
pin FuncTions
RT (Pin 22): Timing Resistor Pin. Adjusts the switching
regulator frequency (OSC1) when SYNC is not driven by
a clock. Place a resistor from this pin to ground to set
the free-running frequency of OSC1. Do not float this pin.
BG1, BG2 (Pin 23/Pin 25): Bottom Gate Drive. Drives the
gates of the bottom N-channel MOSFETs between ground
and GATEVCC.
GATEVCC (Pin 24): Power Supply for Gate Drivers. Must
be connected to the INTVCC pin. Do not power from any
other supply. Locally bypass to ground.
BOOST1, BOOST2 (Pin 33/Pin 27): Boosted Floating Driver
Supply. The (+) terminal of the bootstrap capacitor con-
nects here. The BOOST1 pin swings from a diode voltage
below GATEVcc up to VIN + GATEVCC. The BOOST2 pin
swings from a diode voltage below GATEVCC up to VBAT
+ GATEVCC.
TG1, TG2 (Pin 32/Pin 28): Top Gate Drive. Drives the top
N-channel MOSFETs with voltage swings equal to GATEVCC
superimposed on the switch node voltages.
SW1, SW2 (Pin 31/Pin 29): Switch Nodes. The (–) terminal
of the bootstrap capacitors connect here.
SRVO_FBIN (Pin 35): Open-Drain Logic Output. This pin
is pulled to ground when the input voltage feedback loop
is active. This pin is unused for most LT8490 applications
and can be floated.
SRVO_IIN (Pin 36): Open-Drain Logic Output. This pin is
pulled to ground when the input current feedback loop is
active. This pin is unused for most LT8490 applications
and can be floated.
SRVO_IOUT (Pin 37): Open-Drain Logic Output. This pin
is pulled to ground when the output current feedback loop
is active. This pin is unused for most LT8490 applications
and can be floated.
SRVO_FBOUT (Pin 38): Open-Drain Logic Output. This pin
is pulled to ground when the output voltage feedback loop
is active. This pin is unused for most LT8490 applications
and can be floated.
EXTVCC (Pin 40): External VCC Input. When EXTVCC ex-
ceeds 6.4V (typical), INTVCC will be powered from this pin.
When EXTVCC is lower than 6.22V (typical), INTVCC will be
powered from VIN. See Switching Configuration - MODE
Pin for additional details.
CSNOUT (Pin 41): The (–) Input to the Output Current
Sense Amplifier.
CSPOUT (Pin 42): The (+) Input to the Output Current
Sense Amplifier. This pin and the CSNOUT pin measure
the voltage across the sense resistor to provide the output
current signals.
CSNIN (Pin 44): The (–) Input to the Input Current Sense
Amplifier. This pin and the CSPIN pin measure the voltage
across the sense resistor to provide the instantaneous
input current signals.
CSPIN (Pin 45): The (+) Input to the Input Current Sense
Amplifier.
VIN (Pin 46): Main Input Supply Pin. Must be bypassed
to local ground plane.
ECON (Pin 48): Digital Output Pin. Optional control output
signal used to disconnect EXTVCC from the battery when
the average charge current drops below a predetermined
threshold.
SWENO (Pin 49): Digital Output Pin. Connect to SWEN.
Enables the switching regulator. A 200kΩ pull-down resis-
tor is required from this pin to ground.
IOW (Pin 50): Digital Output Pin. Connects to IMON_OUT
through a resistor. By switching the pin between logic low
and high impedance, the total RIMON_OUT changes, which
changes the output current limit.
STATUS (Pin 51): Digital Output Pin. When used with
an LED, this signal provides a visual indication of the
progress of the charging algorithm. In addition, STATUS
transmits two UART bytes (8 bits, no parity, one stop bit,
2400 baud) every 3.5 seconds (typical), which indicates
status and fault information.
IIR (Pin 53): A/D Input Pin. Connects to IMON_IN to read
input current. Used to manage MPPT.
LT8490
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VINR (Pin 54): A/D Input Pin. Connects to resistive divider
on VIN to measure input voltage. Used to manage MPPT
and start-up.
CLKDET (Pin 56): A/D Input Pin. Connects to CLKOUT
through an RC filter to detect the duty cycle of CLKOUT.
Used to manage start-up.
FBOR (Pin 57): A/D Input Pin. Connects to FBOUT pin to
read charger output voltage. Used to manage the charg-
ing algorithm.
AVDD (Pin 58): A/D Positive Reference Pin. Tie this pin to
VDD and LDO33.
pin FuncTions
CHARGECFG1 (Pin 61): A/D Input Pin. Used to configure
the float voltage, temperature compensation and enable
stage 3 charging.
CHARGECFG2 (Pin 63): A/D Input Pin. Used to configure
time limits and the valid battery temperature range.
IOR (Pin 64): A/D Input Pin. Connects to IMON_OUT pin
to read the charger output current. Used to manage the
charging algorithm.
GND (Exposed Pad 65 and Pins 55, 59, 62): Ground. Tie
directly to local ground plane.
NC (Pins 52, 60): Not connected.
LT8490
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block DiagraM
FBOW 5
2.5V
1.234V
8490 BD
V
IN
ADC
AV
DD
AV
DD
AV
DD
NC
1.208V
1.208V
1.207V
NTC
ADC
AV
DD
ADC
AV
DD
ADC
AV
DD
AV
DD
ADC
AV
DD
ADC
AV
DD
ADC
AV
DD
CONTROL,
CHARGING,
MPPT
LOGIC
BUCK,BOOST
LOGIC
UV_GATEV
CC
UV_V
IN
NC
START-UP AND
FAULT LOGIC
OSC1
1.205V
OI_OUTUV_INTV
CC
OI_INOT
UV_LDO33
10
10
10
10
10
10
10
10
10
+
–
A5
+
–
EA1
+
–
A7
+
–
EA2
+
–
A8
+
–
A9
+
–
+
–
+
–
EA3
FBIN
15
SHDN
11
SYNC
21
RT
22
CLKOUT
20
CLKDET
56
SWEN
8
SWENO
49
SRVO_IIN
36
CSNIN
44
CSPIN
45
IMONIN
10
IIR
53
VINR
54
SS
19
V
IN
46
MODE
9
CSN
12
CSP
13
SRVO_FBIN
35
SRVO_FBOUT 38
FBOUT 16
ECON 48
AV
DD
58
V
DD
4
SRVO_IOUT 37
TEMPSENSE
3
FBIW
6
FBIR
1
CHARGECFG1
61
CHARGECFG2
63
ADC
AV
DD
FBOR 57
ADC
AV
DD
IOR 64
IMONOUT
IOW
17
50
CSNOUT 41
CSPOUT 42
INTV
CC
7
LDO33 14
V
C
18
TG2 28
SW2 29
BG2 25
BG1 23
EXTV
CC
40
GATEV
CC
24
V
BAT
PWM
PWM
3.3V REG
NC
NC
REG
6.35V REG
6.4V
6.35V REG
305k
INTERNAL
SUPPLY1
INTERNAL
SUPPLY2
+
–
EA4
BOOST2 27
TG1 32
BOOST1 33
SW1 31
OSC2
SOLAR PANEL
+
–
RECHARGEABLE BATTERY
+
–
GND
55 STATUS
51 FAULT
2
–
+
A6
AV
DD
AV
DD
Figure 1. Block Diagram
LT8490
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Overview
The LT8490 is a powerful and easy to use battery charging
controller with automatic maximum power point tracking
(MPPT) and temperature compensation. The LT8490 is
based on the LT8705 buck-boost controller with additional
battery charging and MPPT control functions. Refer to the
LT8705 data sheet for more detailed information about the
switching regulator portions of the LT8490. Several refer-
ence applications are included in this data sheet to simplify
system design. Many battery charging applications can be
implemented using one of the reference applications with
little or no modification required. Configuration for the
various charging parameters is implemented in the hard-
ware. No software or firmware development is required.
The LT8490 includes four different forms of regulation:
output current, input current, input voltage and output
voltage (EA1-EA4 respectively as shown in Figure 1).
Whichever form of regulation requires the lowest voltage
on the VC pin limits the commanded inductor current.
When powered by a solar panel, the MPPT function uses
input voltage regulation to locate and track the maximum
power point of the panel. Input current regulation is used
to limit the maximum current drawn from the input supply.
The output current regulation limits the battery charging
current, and the output voltage regulation is used to set
the maximum battery charging voltage.
The LT8490 offers user configurable timers that can
be enabled with the appropriate resistor divider on the
CHARGECFG2 pin. If a timer has been set and expires, the
LT8490 will halt charging and communicate this through
the STATUS and FAULT pins. Options for automatic restart
of the charge cycle are discussed later in the Automatic
Charger Restart and Fault Recovery section.
The LT8490 also includes a TEMPSENSE pin, which can
be connected to an NTC resistor divider network ther-
mally coupled to the battery pack. When connected, the
TEMPSENSE pin can provide temperature compensated
charging and/or can be used to disable charging when
the battery is outside of safe temperature limits. The
presence of the NTC resistor can also give an indication
to the charger if the battery is connected or not.
The LT8490 also provides charging status and fault indica-
tors through the STATUS and FAULT pins. The behavior
of these pins is described in the STATUS and FAULT
Indicators section.
Battery Charging Algorithm
The LT8490 implements a CCCV charging algorithm.
The idealized charging profile is shown in Figure 2 and
assumes constant temperature and adequate input power.
As battery temperature and illumination conditions on the
panel change, the actual current and voltage seen by the
battery will vary accordingly.
After start-up, the LT8490 frequently measures the bat-
tery voltage and charging current to determine the proper
charging stage.
Figure 2. Typical Battery Charging Cycle
8490 F01
CHARGING TIME
STAGE 0
TRICKLE
CHARGE
STAGE 1
CONSTANT
CURRENT
STAGE 2
CONSTANT
VOLTAGE
STAGE 3
REDUCED
CONSTANT
VOLTAGE
STAGE 3
VOLTAGE LIMIT
STAGE 2
VOLTAGE LIMIT
MAXIMUM CHARGING
CURRENT (C)
CHARGING
CURRENT
BATTERY
VOLTAGE
(OPTIONAL)
VS3
VS2
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STAGE 0: In Stage 0 (reduced constant-current/trickle
charge) the LT8490 charges the battery with a hardware
configurable reduced constant current. This trickle charge
stage occurs for battery voltages between 35% to 70%
(typical) of the Stage 2 voltage limit (VS2).
STAGE 1: In Stage 1 (full constant-current) the LT8490
charges the battery with a hardware configurable constant
current equal to or higher than in Stage 0. This constant
current stage occurs for battery voltages between 70% to
98% (typical) of the Stage 2 voltage limit. This charging
stage is often referred to as bulk charging. This charg-
ing stage will be called Stage 1 for the remainder of this
document.
STAGE 2: In Stage 2 (constant-voltage) the LT8490 charges
the battery with a hardware configurable constant voltage.
This constant voltage stage occurs for battery voltages
above 98% (typical) of the Stage 2 voltage limit. This
charging stage is often referred to as float charging for
lithium-ion batteries and absorption charging for lead-acid
batteries. To avoid confusion, this charging stage will be
called Stage 2 for the remainder of this document.
If the optional Stage 3 is enabled, the LT8490 will proceed
from Stage 2 to Stage 3 when the charging current drops
below C/10. Other conditions for exiting Stage 2 depend
on whether time limits are enabled for the charger. See
the Charging Time Limits section for more details about
Stage 2 termination.
STAGE 3 (OPTIONAL): Stage 3 is optional as configured
with the CHARGECFG1 pin. In Stage 3 the LT8490 charges
the battery with a hardware configurable reduced constant
voltage. This charging stage is often referred to as float
charging in lead-acid battery charging. This charging stage
will be called Stage 3 for the remainder of this document.
Charging will automatically restart if, during Stage 3, the
charging current exceeds C/5 or the battery voltage falls
below 96% (typical) of the Stage 3 voltage limit (VS3). In
addition, an optional time limit can be enabled to terminate
charging in Stage 3. See the Charging Time Limits section
for more details about Stage 3 termination.
Table 1. Description of LT8490 Charging Stages
STAGE NAME METHOD DURATION
0 Trickle
Charge
Constant Current
at a Configured
Fraction of Full
Charge Current
Until Battery Voltage Rises
Above VS0 (70% of Stage 2
Voltage Limit)
Optional Max Time Limit
1 Constant
Current
Constant Full
Charge Current
Until Battery Voltage Rises
Above VS1 (98% of Stage 2
Voltage Limit)
Optional Max Time Limit for
Stage 1 + Stage 2
2 Constant
Voltage
Constant Voltage Until Charging Current Falls
Below C/10 or Optional
Indefinite Charging
Optional Max Time Limit for
Stage 1 + Stage 2
3
(Optional)
Reduced
Constant
Voltage
Constant Voltage
at a Configured
Fraction of
Stage 2
Constant Voltage
Until Battery Voltage Falls
below 96% of VS3 (Stage 3
Voltage Limit - Configurable)
or Charging Current Rises
Above C/5
Optional Max Time Limit.
The same duration as the
Stage 1 + Stage 2 Time Limit.
Maximum Power Point Tracking
When powered by a solar panel, the LT8490 employs a pro-
prietary Perturb and Observe algorithm for identifying the
maximum power point. This algorithm provides accurate
MPPT for slow to moderate changes in panel illumination.
The panel is also scanned periodically to avoid settling on
a false maximum power point for long periods of time, in
the case of non-uniform panel illumination.
Fault Conditions
The LT8490 can indicate the presence of a fault condi-
tion through the STATUS and FAULT pins. These faults
include: battery undervoltage, battery overtemperature,
battery under temperature and timer expiration. Follow-
ing a fault, the LT8490 will discontinue charging until the
fault condition is removed, at which point it will continue
or restart the charging cycle. See the Automatic Charger
Restart and Fault Recovery section for more information.
LT8490
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Input Voltage Sensing and Modulation Network
The passive component network shown in Figure 3 is re-
quired to properly measure and modulate the input supply
voltage. This network is required whether the supply is a
solar panel or a DC voltage source.
Due to the granularity of standard resistor values, simply
rounding the calculated results to their nearest standard
values may result in unwanted errors. Consider using
multiple resistors in series to more closely match the
calculated results. Otherwise, use standard resistor values
and check the final results with the following equations:
VX2 =1.205 •RFBIN1
RDACI1 +RDACI2
+RFBIN1
RFBIN2
⎛
⎝
⎜⎞
⎠
⎟+1
⎡
⎣
⎢⎤
⎦
⎥
VX2 indicates the actual VMAX using the selected resis-
tors. Make sure this result is greater than or equal to the
desired VMAX for the application.
VX1 =VX2 −3.3 •RFBIN1
RDAC1 +RDAC2
⎛
⎝
⎜⎞
⎠
⎟
VX1 should be as close to 6V as possible. Iterations may
be required to determine the best standard resistor values.
Table 2 shows good sets of standard value components
for maximum input voltages of 20V, 40V, 60V and 80V.
Iterative calculations were required to select these values
that achieve the best overall results.
Table 2. Input Feedback Network vs Panel Voltage
VMAX
(V)
RFBIN1
(kΩ)
RFBIN2
(kΩ)
RDACI1
(kΩ)
RDACI2
(kΩ)
CDACI
(nF)
20 95.3 8.45 3.4 19.1 270
40 107 4.87 1.69 8.66 560
60 105 3.24 1.05 5.36 1000
80 133 3.09 1.05 4.87 1000
As discussed later in DC Supply Powered Charging, ar-
bitrarily setting VMAX to 80V may not result in the best
operation of the LT8490 for all conditions, particularly at
low input voltages. Be sure to give proper consideration
to the required voltage range for each application.
Solar Powered Charging
VINR DIVIDER NETWORK: The LT8490 can be powered
by a solar panel or a DC power supply. As discussed later
in DC Supply Powered Charging, the VINR pin must be
pulled low when being powered by a DC supply. Otherwise,
VINR must be connected to the resistor divider network
as shown in Figure 4.
Figure 3. Input Feedback Resistor Network
8490 F03
LT8490
GND
VIN
VIN
RDACI1
CDACI
FBIR
FBIN
FBIW
RDACI2
RFBIN1
RFBIN2
Choosing the components requires knowing the maxi-
mum panel open-circuit voltage (VOCMAX) as well as the
maximum DC input supply voltage (VDCMAX) desired
(see the DC Supply Powered Charging section for more
information). VOCMAX typically occurs at cold temperatures
and should be specified in the panel manufacturer’s data
sheet. Use the following equations to determine proper
component values:
RFBIN1 =100k •
1+4.470V
VMAX −6V
⎛
⎝
⎜⎞
⎠
⎟
1+5.593
VMAX −6V
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
⎥
Ω
RDACI2 =2.75 •RFBIN1
VMAX −6V
⎛
⎝
⎜⎞
⎠
⎟Ω
RFBIN2 =1
1
100k −RFBIN1
⎛
⎝
⎜⎞
⎠
⎟−1
RDACI2
⎛
⎝
⎜⎞
⎠
⎟
Ω
RDACI1 =0.2 •RDACI2Ω
CDACI =1
1000 •R
DACI1
F
where VMAX is the greater of VOCMAX and VDCMAX with
some additional margin. These resistors should have a
1% tolerance or better.
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The LT8490 uses this divider network to measure abso-
lute panel voltage (as part of its maximum power point
calculations) and to check for adequate input voltage to
operate the charger. These resistors should have a 1%
tolerance or better
.
TIMER TERMINATION DISABLED: When powered by a
solar panel, the timer termination option (see the Charging
Time Limits section for more detail) is automatically dis-
abled. This is due to the inability to guarantee full charging
current during the entire charging cycle in cases where
the panel illumination conditions change. In addition, the
timers can reset if all power to the charger is lost due to
insufficient lighting. This makes the use of timer termina-
tion potentially unreliable in solar powered applications.
C/10 DETECTION: When powered by a solar panel, charg-
ing current may drop below C/10 because the battery is
approaching full charge, or because the solar panel has
insufficient lighting. If sufficient panel power is available,
the LT8490 can determine if the charging current has
dropped below C/10 due to the battery approaching full
charge. In this case, the charger will proceed from Stage 2
to the next appropriate stage. If the LT8490 is able to de-
termine that the charging current has dropped below C/10
due to insufficient panel power, the charger will continue
operating in Stage 2.
MINIMUM PANEL VOLTAGE REQUIREMENT: A minimum
panel voltage of 6V is required to operate the charger.
However, higher panel voltages are required in various
other cases.
Figure 4. VINR Resistor Divider Circuit
8490 F04
LT8490
GND
VIN
VIN
VINR
196k
8.06k
1. LOW POWER MODE ENABLED: Low power mode al-
lows additional power to be recovered from the solar
panel under very weak lighting conditions. When low
power mode is enabled, the panel voltage must initially
exceed 10V (typical – as measured through the VINR
pin) before the charger will attempt to charge the bat-
tery. Read the Optional Low Power Mode section for
more details.
2. LOW POWER MODE DISABLED: If low power mode is
disabled the charger will attempt to charge the battery
as long as the panel is above 6V. However, if sufficient
panel current is not detected the LT8490 will temporarily
stop charging. The charger will check for sufficient panel
current at 30 second intervals (typical) or will check
sooner if the LT8490 detects either a significant rise
in panel voltage or a significant fall in battery voltage.
3. LOW INPUT VOLTAGE EFFECTS: Figure 5 shows the
minimum input voltage, below which the maximum
charging current can be reduced. This limit is a function
of the input VMAX as discussed previously in the Input
Voltage and Modulation Network section. Maximum
charging current can reduce as FBIN gets closer to
its regulation voltage of 1.205V (typical). This is not
normally a significant issue unless 1) the charger is
powered by a low voltage DC power supply or 2) a low
voltage panel is used with a charger that was configured
for a much higher voltage panel. The farther that VIN
is below the Normal Configuration line in Figure 5 the
more the current can reduce.
Figure 5. Minimum Full Charging Current VIN Voltage
VMAX (V)
0
0
5
10
15
MINIMUM FULL-CHARGING CURRENT
VIN VOLTAGE (V)
20
25
20 40 6010 30 50 70 80
8490 F05
NORMAL CONFIGURATION
DC SUPPLY ONLY WITH FBIN = LDO33
LT8490
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When VIN is powered by a DC voltage supply, main-
tain VIN higher than the Normal Configuration line in
Figure 5. Operating VIN below this line can reduce
the maximum charging current and the VS2 and VS3
charging voltages. If VIN is never going to be supplied
by a solar panel then FBIN can be disconnected from
FBIR (see Figure 3) and reconnected to the LDO33 pin.
This allows the charger to operate with VIN as low as 6V
with no charging current or voltage reduction.
When using a solar panel supply, choose a panel having
a maximum open-circuit voltage (VOC) close to VMAX
(discussed in the prior Input Voltage Sensing and
Modulation Network section). The maximum power
point voltage is typically well above the voltage limit in
Figure 5 and current limiting is rarely an issue. Avoid
using solar panels that operate dramatically below VMAX,
particularly if the maximum power point voltage is typi-
cally below the Normal Configuration line in Figure 5.
DC Supply Powered Charging
SELECTING POWER SUPPL
Y MODE: When powered by
a DC voltage source, the VINR pin must be pulled below
174mV (typical) to activate power supply mode. This
disables unnecessary solar panel functions and allows the
LT8490 to operate properly from a DC voltage source. If
the application is never powered by a solar panel, VINR
can be grounded. If the application is only powered by
a solar panel, then connect VINR as shown in Figure 4.
Otherwise, see the Optional DC Supply Detection Circuit
section for a method to pull down the VINR pin when a
DC supply is detected.
MINIMUM INPUT VOLTAGE REQUIREMENT: When power
supply mode is enabled, the LT8490 will operate from an
input as low as 6V. However, charging current capability
can become limited at low input voltages depending on
the VMAX voltage used to select the input voltage sensing
network (see previous Input Voltage Sensing and Modula-
tion Network section). Figure 5 shows the minimum input
supply voltage required, below which charging current can
become less than the maximum output current limit. If
the LT8490 is powered by a DC supply only, the minimum
input voltage shown in Figure 5 can be reduced to 6V by
Figure 6. Load Connection to Battery in LT8490 Application
(1) disconnecting FBIN from FBIR and (2) connecting the
FBIN pin directly to LDO33.
INPUT CURRENT LIMITING: Input current limiting should
be considered when using DC power supplies. This is
discussed later in the Input Current Limiting section.
In Situ Battery Charging
The LT8490 can be used to charge a battery while the
battery is powering a load. The load should be directly
connected to the battery terminals as shown in Figure
6. The variable nature of some loads can make charg-
ing times unpredictable. Due to this unpredictability it is
recommended that charging time limits be disabled (see
Charger Configuration – CHARGECFG2 Pin section for
more information).
Because a load connected to the battery may draw more
power than provided by the charger, the battery may
discharge while the LT8490 is charging the battery. If
this case occurs and the battery voltage falls below 31%
(typical) of the Stage 2 voltage limit, the undervoltage
fault will become active and the charger will halt until the
battery voltage rises above 35% (typical) of the Stage 2
voltage limit. Consider automatically disabling the load if
the battery depletes below an unacceptably low voltage.
The arrow in Figure 6 shows the proper disconnect point if
removing the battery from the charger in an in situ battery
charging application. This disconnect point is specified
because the LT8490 is not designed to provide power
directly to a load without the presence of a battery.
8490 F06
LT8490
BASED
CHARGER
CABLE
TO/FROM
CHARGER
VBAT
+
–
LOAD
LT8490
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Stage Voltage Limits
The Stage 2 voltage limit (VS2) is the maximum battery
charging voltage. The voltage limits for Stages 0, 1 and
3 are all related to the Stage 2 limit as shown in Table 3
and Figure 11. If temperature compensated charging is
enabled, then VS2 will change with temperature as shown
in Figure 13. As such, the limits for the other stages will
also change with temperature since they are a constant
proportion of VS2.
Table 3. Typical Charging Stage Voltage Thresholds
STAGE TRANSITION
VBAT RISING OR
FALLING
TYPICAL
VB AT /VS2
TYPICAL
VBAT /VS3
VBAT Undervoltage
Fault → STAGE 0
Rising 35% –
STAGE 0 → STAGE 1 Rising 70% –
STAGE 1 → STAGE 2 Rising 98% –
STAGE 3 → STAGE 0 Falling – 96%
STAGE 2 → STAGE 1 Falling 95% –
STAGE 1 → STAGE 0 Falling 66% –
STAGE 0 → VBAT
Undervoltage Fault
Falling 31%
RFBOUT2 is often chosen between 4.99kΩ and 49.9kΩ.
Choosing higher values for RFBOUT2 reduces the amount
of current draw from the battery through the feedback
network.
RFBOUT1 =RFBOUT2 •VS2 •1.241
1.211−0.128
⎛
⎝
⎜⎞
⎠
⎟−1
⎡
⎣
⎢⎤
⎦
⎥Ω
RDACO2 =RFBOUT1 •RFBOUT2 •0.833
RFBOUT2 •VS2 •1.241
1.211
⎛
⎝
⎜⎞
⎠
⎟−RFBOUT2 −RFBOUT1
Ω
RDACO1 =0.2 •RDACO2Ω
CDACO =1
500 •RDACO1
F
For greater charging voltage accuracy, it is recommended
that 0.1% tolerance resistors be used for the output feed-
back resistor network.
Due to the granularity of standard resistor values, simply
rounding the calculated results to their nearest standard
values may result in unwanted errors. Consider using
multiple resistors in series to match the calculated results.
Otherwise, use standard resistor values and check the final
results with the following equations.
VX3 =RFBOUT1
RDACO1 +RDACO2
⎛
⎝
⎜⎞
⎠
⎟•X−1.89
( )
where
X=1.211•1+RDACO1 +RDACO2
RFBOUT2
⎛
⎝
⎜⎞
⎠
⎟+RDACO1 +RDACO2
RFBOUT1
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥
VX3 indicates the actual 25°C VS2 voltage using the se-
lected resistors.
N1=
X
−
1.89
X−3.3
N1 should be as close as possible to 1.22.
N2 =1−
1.89
X
N2 should be as close as possible to 0.805. Iterations may
be required to determine best standard resistor values.
Figure 7. Output Feedback Resistor Network
8490 F07
LT8490
GND
VBAT
RDACO2
CDACO
FBOR
FBOUT
FBOW
RDACO1
RFBOUT1
RFBOUT2
SETTING THE STAGE 2 VOLTAGE LIMIT: The resistor
network shown in Figure 7 is used to set the Stage 2 volt-
age limit. Battery manufacturers typically call for a higher
Stage 2 voltage limit than the nominal battery voltage.
For example, a 12V lead-acid battery used in automotive
applications commonly has a Stage 2 charging voltage
limit of 14.2V. If temperature compensated charging will
be used (see Temperature Measurement, Compensation
and Fault section) then use the 25°C value for VS2 in the
equations below.
LT8490
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Table 4 shows good sets of standard value components
for charging nominal battery voltages of 12V, 24V, 36V,
48V and 60V. Iterative calculations were required to select
these values that achieve the best overall results.
Table 4. Standard Value Output Feedback Network vs Output
Regulation Voltage
BATTERY
VOLTAGE
TARGET
VS2 (V)
RFBOUT1
(kΩ)
RFBOUT2
(kΩ)
RDACO1
(kΩ)
RDACO2
(kΩ)
CDACO
(nF)
12 14.2 274 23.2 26.1 124 82
24 28.4 487 20 28 107 68
36 42.6 787 21 22.6 121 100
48 56.8 1000 20 22.6 115 100
60 71.0 866 13.7 13.3 80.6 150
SETTING THE STAGE 3 VOLTAGE LIMIT: When enabled,
Stage 3 charging maintains the battery voltage at 85% to
99% of VS2. This proportion is adjustable and is discussed
in the Charger Configuration – CHARGECFG1 Pin section.
BATTERY UNDERVOLTAGE LIMIT: Upon start-up, the
LT8490 checks for battery voltage above 35% (typical)
of the Stage 2 voltage limit. If the battery voltage is less
than this, charging will not start and a battery undervoltage
fault will be indicated on the FAULT pin. Charging will begin
after the battery voltage rises above 35% (typical) of the
Stage 2 voltage limit. If the battery voltage subsequently
falls below 31% (typical), charging will again stop and
the fault will be indicated on the FAULT and STATUS pins.
Charge Current Limiting
The maximum charging current is configured with the
output current limiting circuit. The output current is sensed
through RSENSE2 and converted to a proportional current
flowing out of the IMON_OUT pin (see Figure 8).
applicaTions inForMaTion
Figure 8. Output Current Regulation Loop
IMON_OUT voltages above 1.208V (typical) cause VC to
reduce due to EA1, and thus limit the output current. IOW
is either driven to ground or floated depending on charg-
ing conditions. This allows the current limit for Stage 0
(IOUT(MAXS0)) to be set independently of the remaining
Stages (IOUT(MAX)) with proper selection of RIOW and
RIMON_OUT. Use the following equations to configure the
charging current limits:
RSENSE2 =
0.0497
IOUT(MAX)
Ω
RIMON _ OUT =1208
IOUT(MAXS0) •RSENSE2
Ω
RIOW =24.3k •RIMON _ OUT
RIMON _ OUT −24.3k Ω
RIOR =3.01kΩ
CIMON _ OUT =read below
where IOUT(MAX) is the maximum charging current in Amps,
IOUT(MAXS0) is the maximum trickle charging current in
Stage 0 and IOUT(MAXS0) is no greater than IOUT(MAX). For
cases where IOUT(MAX) = IOUT(MAXS0), it is OK to exclude
RIOW and float the IOW pin. IOUT(MAXS0) must be at least
20% of IOUT(MAX).
8490 F08
LT8490
RIMON_OUT CIMON_OUT
FAULT
CONTROL –
+
EA1
–
+
1.208V1.61V
IOW IOR VC
IMON_OUT
TO BATTERY
CSNOUTCSPOUT
FROM
CONTROLLER
VOUT1
+–
RSENSE2
OUTPUT
CURRENT
RIOR
3.01k
RIOW
gm = 1m
A6
Ω
LT8490
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CIMON_OUT reduces IMON_OUT ripple and stabilizes the con-
stant charging current control loop. Reducing CIMON_OUT
improves stability and minimizes inductor current over-
shoot that can occur if a discharged battery is quickly
disconnected then reconnected to the charger
. However
,
this is at the expense of increased IMON_OUT ripple that
can introduce more noise into the ADC measurements.
The higher frequency pole created at IMON_OUT must be
adequately separated from the lower frequency pole at the
VC pin for proper stability. A CIMON_OUT capacitor in the
range of 4.7nF to 22nF is adequate for most applications.
Input Current Limiting
SOLAR PANEL SUPPLY: Solar panels are inherently current
limited and may not be able to provide maximum charging
power at the lowest input voltages. The LT8490 uses its
MPPT algorithm to sweep the panel voltage as low as 6V
to find the maximum power point. Make sure that the input
current limit is set higher than the maximum panel current
capability, plus at least 20% to 30% margin, in order to
achieve the maximum charging capability of the system.
In addition, note that the LT8490 uses the same circuit
(shown in Figure 9) to measure the input current as to limit
it. The input current is measured by an A/D conversion of
the IIR pin voltage which is connected to IMON_IN and is
proportional to input current. The digitized input current is
used to locate the maximum power point of the solar panel.
Setting a higher input current limit reduces the resolution
of the digitized reading of the input current. Avoid setting
the input current limit dramatically higher than necessary,
as this may affect the accuracy of the maximum power
point calculations.
DC POWER SUPPLY: When charging a battery at maxi-
mum current, and thus power, a low voltage supply must
provide more current than a high voltage supply. This can
be seen by equating output power to input power, less
some efficiency loss.
VIN • IIN • η = VBAT • IBAT
or
IIN(MAX) =
V
BAT
•I
BAT(MAX)
V
IN(MIN) •η
Figure 9. Input Current Regulation Loop
where the efficiency factor η is typically between 0.95
and 0.99.
When powered by a DC supply, appropriate input cur-
rent limiting is recommended for supplies that might
(1) become overloaded as the supply ramps up or down
through 6V or (2) provide more input current than the
charger components can tolerate.
SETTING THE INPUT CURRENT LIMIT: The input current
is sensed through RSENSE1 as shown in Figure 9. The
current through RSENSE1 is converted to a voltage on the
IMON_IN pin according to the following equation:
V
IMON _IN =IIN •RSENSE1
1000 +7µA
⎛
⎝
⎜⎞
⎠
⎟•RIMON _ IN
⎡
⎣
⎢⎤
⎦
⎥V
IMON_IN voltages exceeding 1.208V (typical) cause the VC
voltage to reduce, thus limiting the input current. RIMON_IN
should be 21kΩ ± 1% or better. Using this information,
the appropriate value for RSENSE1 can be calculated using
the following equation:
RSENSE1 =
1000 •
1.208V
21kΩ−7µA
⎛
⎝
⎜⎞
⎠
⎟
IIN(MAX)
=0.0505
IIN(MAX)
Ω
where IIN(MAX) is the maximum input current limit in Amps.
RSENSE1 values greater than 25mΩ are not recommended.
8490 F09
LT8490
21k
RIMON_IN CIMON_IN
FAULT
CONTROL –
+
EA2
–
+
1.208V
7mV
1.61V
IIR VC
IMON_IN
TO REMAINDER
OF SYSTEM
CSNINCSPIN
FROM SOLAR PANEL OR
DC POWER SUPPLY
+–
RSENSE1
OUTPUT
CURRENT
gm = 1m
A7
+
–
Ω
LT8490
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8490fa
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CIMON_IN reduces IMON_IN ripple and stabilizes the input
current limit control loop. Reducing CIMON_IN improves sta-
bility and minimizes possible inductor current overshoot.
However, this is at the expense of increased IMON_IN ripple
that can introduce more noise into the ADC measurements.
The higher frequency pole created at IMON_IN must be
adequately separated from the lower frequency pole at the
VC pin for proper stability. A CIMON_IN capacitor of 4.7nF
to 22nF is adequate for most applications.
Input and Output Current Sense Filtering
The CSX and RSX current sense filtering shown in Figure 10
can improve the accuracy of the input and output current
measurements at low average current levels. Amplifiers A7
and A8 (Figures 8 and 9) can only amplify positive RSENSE
voltages. Although the average RSENSE voltage is always
positive, the voltage ripple at low average current levels
may contain negative components that are averaged out
by the filter. Recommended values for RS1, RS2 and CS1,
CS2 are 10Ω and 470nF.
CC1 and CC2 may be required, depending on board layout,
to reduce common mode noise that may reach the LT8490
pins. 100nF ceramic capacitors, with the appropriate volt-
age ratings, work well in most cases. Be sure to place all of
the filter components (CSX, RSX, CCX) close to the LT8490
for best performance.
Finally, note that a small voltage drop (typically ~0.25mV
per 10Ω) will occur across RS1 and RS2 due to the input
bias currents of CSNOUT and CSNIN. This represents a
~0.5% reduction in the maximum current limit which typi-
cally occurs with ~50mV across RSENSE. The C/10 threshold
(typically when 5mV is measured across CSPOUT and
CSNOUT) will also reduce to C/10.5 due to the 0.25mV
drop across RS2.
applicaTions inForMaTion
Charger Configuration – CHARGECFG1 Pin
The CHARGECFG1 pin is a multifunctional pin as shown in
Figure 11. Set this pin using a resistor divider totaling no
less than 100kΩ to the AVDD pin (see the Typical Applica-
tions section for examples). The voltage on CHARGECFG1,
as a percentage of AVDD, makes the selections discussed
below. Avoid setting the divider ratio directly at any of
the inflection points on Figure 11 (e.g. 5%, 45%, 50%,
55% or 95%)
ENABLE/DISABLE TEMPERATURE COMPENSATED VOLT-
AGE LIMITS: Setting the CHARGECFG1 pin in the upper
half of the voltage range (> 50%) enables battery voltage
temperature compensation, while using the bottom half
(< 50%) disables the temperature compensation, even if a
thermistor is coupled to the battery pack. The next section
provides more detailed information.
DISABLE STAGE 3: Setting the CHARGECFG1 pin to AVDD
or 0V disables Stage 3. When the CHARGECFG1 pin is set
in this manner, the charging algorithm will never proceed
to Stage 3. Stage 3 is commonly used for lead-acid battery
charging but is not typically used for lithium-ion battery
charging.
ENABLE STAGE 3: Setting the CHARGECFG1 pin between
5% to 95% of AVDD enables Stage 3 charging and sets the
Stage 3 voltage limit (VS3) as a percentage of the Stage
2 voltage limit (VS2) according to the following formulas.
Figure 10. Recommended Current Sense Filter
Figure 11. CHARGECFG1 Pin Configuration
RSENSE1
CS1
8490 F10
LT8490
CSPIN CSNIN
RS1
RSENSE2
CS2
LT8490
CSPOUT CSNOUT
RS2
CC2
CC1
8490 F11
100
95
90
85
0 5 50
CHARGECFG1 PIN VOLTAGE (% OF AVDD)
55 95 10045
TEMPERATURE
COMPENSATED
CHARGING LIMITS
NON-TEMPERATURE
COMPENSATED
CHARGING LIMITS
S3
DISABLED
S3
DISABLED
VS3/VS2 (%)
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Figure 12. Battery Temperature Sensing Circuit Figure 13. Stage 2 Voltage Limit vs Temperature
When Temperature Compensation Is Enabled
8490 F12
LT8490
GND
AVDD
TEMPSENSE
100nF
11.5k
CABLE
TO/FROM
CHARGER
10k NTC THERMISTOR
THERMALLY COUPLED
WITH BATTERY PACK
TO CHARGER OUTPUT
AT RSENSE2
When temperature compensated charging and Stage 3
are enabled, use:
CHARGECFG1% =2.67 •VS3
VS2
−0.85
⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟+0.55
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
•100%
When temperature compensated charging is disabled and
Stage 3 is enabled, use:
CHARGECFG1% =2.72−2.67 •VS3
VS2
⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
•100%
where VS3/VS2 should be between 0.86 to 0.99.
For example, to enable temperature compensated charg-
ing with VS3 set to 93% of VS2, choose a divider that puts
CHARGECFG1 at 76% of AVDD. For best accuracy use
resistors that have a 1% tolerance or better.
Temperature Measurement, Compensation and Fault
The LT8490 can measure the battery temperature using
an NTC (negative temperature coefficient) thermistor
thermally coupled to the battery pack. The temperature
monitoring function is enabled by connecting a 10kΩ,
ß = 3380 NTC thermistor from the TEMPSENSE pin to
ground and an 11.5kΩ (1% tolerance or better) resistor
from AVDD to TEMPSENSE (as shown in Figure 12). If
battery temperature monitoring is not required, then use a
10kΩ resistor in place of the thermistor. This will indicate
to the LT8490 that the battery is always at 25°C.
The LT8490 monitors the voltage on the TEMPSENSE pin
to determine the battery temperature and also to detect if
the thermistor is connected or not. A TEMPSENSE volt-
age greater than 96% of AVDD (typical) indicates that the
thermistor has been disconnected. Three charger functions
rely on the TEMPSENSE information.
1. INVALID BATTERY TEMPERATURE FAULT: A tempera-
ture fault occurs when the battery temperature is outside
of the valid range as configured on the CHARGECFG2 pin
(–20°C to 50°C or 0°C to 50°C). The temperature fault
condition remains until the temperature returns within
–15°C to 45°C or 5°C to 45°C (5°C of hysteresis). During
a temperature fault, charging is halted and the STATUS
and FAULT pins follow the pattern described in Table 6.
If timer termination is enabled with the CHARGECFG2
pin, the timer count is paused during the temperature
fault and resumes when the fault state is exited.
2. BATTERY VOLTAGE TEMPERATURE COMPENSATION:
Some battery chemistries charge best when the voltage
limit is adjusted with battery temperature. Lead-acid
batteries, in particular, experience a significant change
in the ideal charging voltage as temperature changes. If
enabled with the CHARGECFG1 pin, the battery charging
voltage and all related voltage thresholds are automati-
cally adjusted with battery temperature. As the voltage
on the TEMPSENSE pin changes, the PWM duty cycle
from the FBOW pin changes such that the voltage limits
of the LT8490 follow the curve shown in Figure 13.
BATTERY TEMPERATURE (°C)
–25
96
98
100
102
104
% OF VS2 AT 25°C (%)
106
108
112
110
–5 15 35–15 5 25 40 55
8490 F13
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3. BATTERY DISCONNECT SENSING: The LT8490 detects
if the battery and thermistor have been disconnected
from the charger by monitoring the TEMPSENSE pin
voltage. When the connection to the battery is severed,
as shown by the arrow in Figure 12, the connection to
the thermistor is also severed and the TEMPSENSE
voltage rises up to AVDD through the 11.5kΩ resis-
tor. During the time when the battery is not present,
the LT8490 halts charging. The charger automatically
restarts the charging at Stage 0 when a battery (along
with integrated thermistor or resistor) is sensed through
the TEMPSENSE pin.
Charger Configuration – CHARGECFG2 Pin
The CHARGECFG2 pin is a multifunctional pin as shown in
Figure 14. Set this pin using a resistor divider totaling no
less than 100kΩ to the AVDD pin (see the Typical Applica-
tions section for examples). The voltage on CHARGECFG2,
as a percentage of AVDD, makes the selections discussed
below. Avoid setting the divider ratio directly at any of the
inflection points on Figure 14 (e.g. 5%, 10%, 45%, 50%,
55%, 90% or 95%)
limits using the CHARGECFG2 pin. For more information
about the operation of the time limits see the Charging
Time Limits section.
Setting the CHARGECFG2 pin between 5% to 95% of
AVDD allows for time limit settings between 0.5 hours to
3 hours for Stage 0, 2 hours to 12 hours for Stage 1 and 2
combined and 2 hours to 12 hours for Stage 3. The
Stage 0 time limit is always 1/4th of the Stage 1 + Stage 2
time limit and the Stage 3 time limit is always the same
length as the Stage 1 + Stage 2 limit. When choosing a
Stage 1 + Stage 2 time limit of 12 hours, choose a divider
ratio very close to 7.5% or 92.5%. When choosing a
Stage 1 + Stage 2 time limit of 2 hours, choose a divider
ratio very close to 47.5% or 52.5%. For time limits in
between, use one of the following formulas.
When the wide valid battery temperature range (–20°C to
50°C) is desired use:
CHARGECFG2% = 3.5% • (TS1S2 – 2) + 55%
where TS1S2 is the desired Stage 1 + Stage 2 time limit in
hours between 2.1 and 11.9.
When the narrow valid battery temperature range (0°C to
50°C) is desired use:
CHARGECFG2% = 45% – 3.5% • (TS1S2 – 2)
where TS1S2 is the desired Stage 1 + Stage 2 time limit in
hours between 2.1 and 11.9.
Setting CHARGECFG2 below 4% (i.e., ground) or above
96% of AVDD (i.e., tie to AVDD) disables the time limits,
allowing the charging to run indefinitely in lieu of any
fault conditions.
SELECT THE VALID BATTERY TEMPERATURE RANGE:
Setting the CHARGECFG2 pin in the top half of the voltage
range (> 50%) selects a wider valid battery temperature
range (–20°C to 50°C), while using the bottom half of the
voltage range (< 50%) selects a narrower valid battery
temperature range (0°C to 50°C). Generally, lead-acid
batteries would use the wide range, while lithium-ion bat-
teries would use the narrow range. See the Temperature
Measurement, Compensation and Fault section for more
information about the invalid battery temperature fault.
Figure 14. CHARGECFG2 Pin Voltage Settings
CHARGECFG2 PIN VOLTAGE (% OF AVDD)
NARROW VALID
BATTERY TEMP. RANGE
WIDE VALID
BATTERY TEMP. RANGE
0.5
2
3
12
TIME (HRS)
NO TIME LIMIT
NO TIME LIMIT
0 5 10 45 50
TIME LIMITS ONLY AVAILABLE
IN POWER SUPPLY MODE
55
STAGE 0
TIMER
STAGE 1 AND 2
COMBINED TIMER
AND
STAGE 3
TIMER
90 95 100
8490 F14
ENABLE/DISABLE CHARGING TIME LIMITS: The LT8490
supports charging time limits only when power supply
mode is enabled (see the DC Supply Powered Charging
section). When power supply mode is disabled, any finite
time limit setting on CHARGECFG2 is interpreted as no time
limit. This section discusses how to configure the time
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Charging Time Limits
Charging time limits can be enabled only in power supply
mode by properly configuring the CHARGECFG2 pin (see
the Charger Configuration – CHARGECFG2 Pin section).
Charging time limits are not recommended for use when
a load is present on the battery due to the unpredictable
amount of time that may be required to achieve full charge.
When enabled, the appropriate timers start at the beginning
of Stages 0, 1 and 3. If the timer expires while operating
in its respective stage or the LT8490 returns to a charging
stage after its respective timer has expired, charging stops
immediately. As shown in Table 5, expiration of a timer is
treated as either a fault or as done charging depending on
the timer that expired and the configuration of the charger.
In any case, when charging stops, the fault or done charg-
ing status is indicated on the STATUS and FAULT pins as
described in the STATUS and FAULT Indicators section.
Table 5. Charger Conditions and Timer Expiration Results
CHARGING
STAGE WHEN
TIMER EXPIRES
STAGE 3
ENABLED? TIMER USED
RESULT
OF TIMER
EXPIRATION
0 – Stage 0 Fault
1 – Stage 1 + Stage 2 Fault
2 – Stage 1 + Stage 2 Fault
3Yes Stage 3 Done Charging
STAGE 2 TERMINATION (TIME LIMITS ENABLED): Timer
expiration in Stage 2 causes a fault and charging stops im-
mediately with a fault indication on the STATUS and FAULT
pins. If the Stage 2 output current drops below C/10 before
the timer expires and Stage 3 is disabled then charging
stops and done charging is indicated on the STATUS pin.
STAGE 2 TERMINATION (TIME LIMITS DISABLED): If time
limits are disabled, Stage 2 can only terminate if Stage 3
is also enabled. After charging current falls below C/10,
charging will proceed to Stage 3. If Stage 3 is also disabled
then the charger will operate in Stage 2 indefinitely unless
the battery voltage falls enough for charging to revert back
to Stage 1. During the indefinite Stage 2 charging, the
STATUS pin will indicate if Stage 2 current is below C/10
or above C/5 (as shown in Tables 6 and 7).
STAGE 3 TERMINATION CONDITIONS: If Stage 3
is enabled and time limits are disabled, the LT8490 will
remain in Stage 3 forcing reduced constant-voltage indefi-
nitely unless the battery voltage falls below 96% of VS3 or
charging current rises above C/5 causing the charger to
revert back to Stage 0. If Stage 3 is enabled and time limits
are enabled, timer expiration in Stage 3 will stop charging
and communicate the done charging state through the
STATUS pin (as shown in Tables 6 and 7).
Lithium-Ion Battery Charging
The LT8490 is well suited to charge lithium-ion batteries.
Connecting the CHARGECFG1 and CHARGECFG2 pins to
ground puts the LT8490 into a typical configuration for
lithium-ion battery charging (0°C to 50°C valid battery
temperature, Stage 3 disabled, no temperature compensa-
tion, no time limits). Figure 15 shows a typical lithium-ion
charging cycle in this configuration.
If no timer termination has been selected, the LT8490 will
charge the lithium-ion battery stack to the desired Stage 2
voltage limit, maintaining that limit indefinitely. When the
charging current is < C/10, the STATUS pin will go high
as described in Table 6.
NOTE: When solar charging a Li-Ion battery without time
limits it is recommended that the Stage 2 voltage limit
not exceed 95% of the lithium-ion maximum cell voltage.
Since this configuration can charge indefinitely, follow-
ing this guideline keeps the lifetime of the batteries from
degrading quickly.
Figure 15. Lithium-Ion Battery Charging Cycle
8490 F15
CHARGING TIME
CHARGING
CURRENT
BATTERY VOLTAGE
(FLOAT)
STAGE 0
TRICKLE
CHARGE
STAGE 1
CONSTANT
CURRENT
STAGE 2
CONSTANT
VOLTAGE
STAGE 2
VOLTAGE LIMIT
MAXIMUM CHARGING
CURRENT (C)
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Figure 17. Example Waveform for STATUS Pin in STAGE 3
Figure 16. Lead-Acid Battery Charging Cycle
8490 F16
CHARGING TIME
CHARGING
CURRENT
BATTERY VOLTAGE
(ABSORPTION)(BULK) (FLOAT)
STAGE 0
TRICKLE
CHARGE
STAGE 1
CONSTANT
CURRENT
STAGE 2
CONSTANT
VOLTAGE
STAGE 3
REDUCED
CONSTANT
VOLTAGE
STAGE 2
VOLTAGE LIMIT
STAGE 3
VOLTAGE LIMIT
MAXIMUM CHARGING
CURRENT (C)
Lead-Acid Battery Charging
The LT8490 can be used to charge lead-acid batteries.
Setting the CHARGECFG1 pin to 87.6% of AVDD and
CHARGECFG2 pin equal to AVDD configures the LT8490
for typical lead-acid battery charging (–20°C to 50°C
valid battery temperature, Stage 3 enabled with VS3/VS2 =
97.2%, temperature compensated voltage limits, no time
limits). Figure 16 shows a typical lead-acid charging cycle.
If time limits have been disabled, the LT8490 will charge
the lead-acid battery stack to the desired Stage 3 voltage
limit and restart the charging cycle if 1) the battery voltage
falls below 96% of the Stage 3 voltage limit (VS3) or 2)
the charging current rises above C/5.
8490 F17
LED ON
LED OFF
3.5s
0.5s
A
Table 6. STATUS and FAULT LED INDICATORS
CHARGER
STATUS
LED PULSES/3.5s,
APPROXIMATE ON-TIME PER
PULSE FOR MORE
INFORMATION SEE
SECTIONSTATUS FAULT
Stage 0 1, 10ms OFF Battery Charging
Algorithm
Stage 1 1, 250ms OFF Battery Charging
Algorithm
Stage 2 and
(Stage 3 Enabled
or Time Limits
Enabled or IOUT
Rising Above C/5)
2, 250ms OFF Battery Charging
Algorithm
and Charger
Configuration
Sections
Stage 2 and
Stage 3 Disabled
and Time Limits
Disabled and IOUT
Falling Below C/10
ON OFF Battery Charging
Algorithm
and Charger
Configuration
Sections
Stage 3 3, 250ms OFF Battery Charging
Algorithm
Done Charging ON OFF Charging Time
Limits
Battery Present
Detection Fault
1, 10ms 1, 250ms Temperature
Measurement,
Compensation and
Fault
Invalid Battery
Temperature Fault
1, 10ms 2, 250ms Temperature
Measurement,
Compensation and
Fault
Timer Expiration
Fault
1, 10ms 3, 250ms Charging Time
Limits
Battery
Undervoltage Fault
1, 10ms 4, 250ms Stage Voltage
Limits
STATUS and FAULT Indicators
The LT8490 reports charger status through two outputs,
the STATUS and FAULT pins. These pins can be used to
drive LEDs for user feedback. In addition, the STATUS pin
doubles as a UART output to send status information to a
peripheral device. Table 6 describes the LED behavior of
these pins in relationship to the charger status.
While the LT8490 is operating, the STATUS pin toggles on
a 3.5 sec (typical) interval as shown in Figure 17. The three
pulses shown in Figure 17 represent the charger operating
in Stage 3. The STATUS and FAULT pins pull up to turn the
LEDs on and drive to ground to turn the LEDs off.
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Driving LEDs with the STATUS and FAULT Pins
The STATUS and FAULT pins on the LT8490 can be used
to drive LED indicators. Figure 18 shows the simplest
configuration for driving LEDs from these two pins.
The STATUS pin can drive up to 2.5mA into an LED. Choose
RDSA to limit the LED current to 2.5mA or less when STATUS
is driven close to 3.3V. Choose RDSB to conduct a current
equivalent to the LED current when STATUS is driven close
to ground and RDSB has ~3.3V across the terminals. DS, in
Figure 18, conducts ~2.5mA when STATUS is driven high.
RDSB conducts ~2.5mA when the STATUS is driven low.
The FAULT pin has a weak pull up in comparison to the
STATUS pin (see the Typical Performance Characteristics
section). The LED current is typically self-limited to less
than 1mA by the FAULT pin driver. RDFB in Figure 18 is
typically 3.32kΩ and increases the FAULT LED current.
When configured as shown in Figure 18, the DF LED cur-
rent should be limited to less than 1.5mA.
For driving higher current LEDs, the circuit in Figure 19 can
be used. Note that the LED current for DF is provided by the
INTVCC regulator in this case. Excessive LED current can
overload the INTVCC regulator and/or cause excessive
heating in the LT8490. 7.5mA is a good starting point
when using this circuit. Higher currents can be possible
with careful board evaluation. Transistor Q2 must have a
collector-emitter breakdown voltage greater than INTVCC.
The MMBT3646 has a breakdown voltage of 15V and is
well suited for this application.
The LED current for DS is provided by VIN in this case. Do
not draw current for DS from INTVCC since this increases
power dissipation in the LT8490. Transistor Q1 must
have a collector-emitter breakdown greater than VIN. The
MMBT5550L has a breakdown voltage of 140V and is
suitable for most applications.
To properly set the resistors shown in Figure 19, use the
following equations:
RE1 ≅
2.6
ID
Ω
RC1 ≅INTVCC −VF
ID
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟Ω
RB1 =50
ID
Ω
where INTVCC is typically 6.35V, VF is the forward voltage
of the LED (often about 1.7V) and ID is the desired bias
current through the LED.
Figure 19. Higher Current Drive for STATUS/FAULT LEDsFigure 18. Default STATUS/FAULT LED Indicators
8490 F18
LT8490
STATUS
LDO33
VDD
VDD
FAULT
RDSB
1.3k
RDSA
549Ω
DS
DS: OSRAM, LGL29KF2J124Z
DF: OSRAM, LGL29K-H1J2-1-Z
RDFA
549Ω
RDFB
DF
8490 F19
LT8490
STATUS
VIN
VIN INTVCC
FAULT
RE1
DS
Q1: MMBT5550L
Q2: MMBT3646
RC1
RB1
DF
Q2Q1
LT8490
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Figure 20. UART Transmission Waveform from
Figure 17 Label (A)
Figure 21. Status Byte Decode
STATUS Pin UART
The STATUS pin also provides a UART (transmit only)
communication function. This feature allows for remote
monitoring of the LT8490. Immediately after each initial
pulse described in Table 6 the STATUS pin sends out a
synchronizing byte (0x55) followed by a status byte. UART
data is transmitted with the LSB first. Figure 20 shows the
zoomed in region labeled (A) from Figure 17.
LP: “0” if in low power mode (see the Low Power Mode
section)
S2/S1/S0: Stage description (see Table 7)
F2/F1/F0: Fault description (see Table 8)
Table 7. Stage Description
STAGE CONDITIONS S2 S1 S0
Stage 0 – 0 0 0
Stage 1 – 0 0 1
Stage 2 Stage 3 Enabled 0 1 0
Timers and Stage 3
Disabled, Charging Current
Has Risen Above C/5
Timers and Stage 3
Disabled, Charging Current
Falls Below C/10
1 0 0
Stage 3 – 0 1 1
Done Charging – 1 0 1
Table 8. Fault Description
FAULT INFORMATION F2 F1 F0
No Faults Present 0 0 0
Battery Disconnected
(Thermistor Disconnected)
0 0 1
Invalid Battery Temperature 0 1 0
Timer Fault 0 1 1
Battery Undervoltage 1 0 0
If multiple faults are present, the fault listed highest in
Table 8 is reported through the STATUS and FAULT pins.
8490 F20
UART START BIT
SYNC BYTE 0x55 STATUS 0x14
LSB MSB
UART STOP BITUART START BITUART STOP BIT
8490 F20
LSBMSB
0LP S2 S1 S0 F2 F1 F0
The status byte shown in Figure 20 has information regard-
ing the present charging stage as well as fault informa-
tion. The data format for each UART byte is 8 data bits,
no parity, with one stop bit. The baud rate is 2400 baud
±10% which may require auto baud rate detection, using
the sync byte, for proper data reception. Figure 21 defines
each bit present in the status byte. The status byte always
contains an MSB of 0. Status bytes containing an MSB of
1 should be disregarded.
LT8490
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Automatic Charger Restart and Fault Recovery
The LT8490 employs many features and checks that may
cause the charger to stop until favorable operating condi-
tions return. Table 9 summarizes the typical cause for the
LT8490 to stop charging along with the conditions under
which it will automatically restart charging. Upon automatic
restart all timers are reset except when resuming from an
invalid battery temperature fault.
Table 9. Automatic Restart Conditions
CAUSE FOR
CHARGING TO
STOP REQUIREMENT FOR RESTART
RESTART
OR RESUME
CHARGING
Done Charging Stage 3 disabled and VBAT drops
below 95% of VS2
Restart
Stage 3 enabled and VBAT drops
below 96% of VS3
Restart
Battery
Undervoltage Fault
VBAT rises to 35% of VS2 Restart
Stage 0 Timeout VBAT rises to 70% of VS2 or every
hour after stopping (read below)
Restart
Stage 1 Timeout VBAT rises 5% or VBAT rises to 98%
of VS2 or every hour after stopping
(read below)
Restart
Stage 2 Timeout VBAT falls below 66% of VS2 or every
hour after stopping (read below)
Restart
Invalid Battery
Temperature
Battery temperature returns within
the valid temperature range with 5°C
hysteresis
Resume
Battery
Disconnected Fault
Re-Connect Thermistor Restart
The charger will attempt to restart every hour (typically)
after having stopped due to a timeout fault in Stage 0,
Stage 1 or Stage 2. Configuring the charger in any of the
following ways prevents the charger from automatically
restarting every hour:
1. Stage 3 disabled and narrow battery temperature range
selected and temperature compensated battery voltage
not selected.
2. Not operating in power supply mode.
3. Timer limits disabled.
SHDN Pin Connection
The LT8490 requires 1.234V (typical) on the SHDN pin
to start-up. A minimum of 5V on VIN is also required for
proper start-up operation; therefore, a resistor divider
from VIN to the SHDN pin is used to set this threshold.
Connect the SHDN pin as shown in Figure 22 (1% resistor
tolerance or better required).
Figure 22. SHDN Pin Resistor Divider
8490 F22
LT8490
GND
VIN
VIN
SHDN
110k
35.7k
LT8490
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Figure 23. Simplified Diagram of Switches
applicaTions inForMaTion
Switching Configuration – MODE Pin
The LT8490 has two modes of switching behavior con-
trolled by the state of the MODE pin. Tying MODE to a
voltage above 2.3V (i.e., VDD or INTVCC) configures the
part for discontinuous conduction mode (DCM) which
allows only positive current flow to the battery. More
information about this mode of operation can be found
in the LT8705 data sheet.
Tying the MODE pin below 0.4V (i.e. ground) changes the
configuration as follows:
1. AUTOMATIC CCM/DCM MODE SWITCHING: Very large
inductor current ripple can lead the LT8490 to operate
at high currents while still in DCM. In this case, the M4
switch (highlighted in Figure 23) can become hot due to
the battery charging current flowing through the body
diode of this device.
Connecting the MODE pin low can reduce the M4 heat-
ing by activating the continuous conduction threshold
mode (CCTM). In this mode the average charging cur-
rent is monitored by the IMON_OUT pin. The LT8490
will operate in conventional DCM while the battery
charging current, and thus IMON_OUT, is low (below
122mV typically). As the charging current increases,
IMON_OUT will eventually rise above ~195mV signal-
ing the LT8490 to enter CCM operation that will turn
on M4 and reduce heating. While the average charging
current will be positive, this mode does allow some
negative current flow within each switching cycle. Use
DCM operation if this behavior is not desired.
2. AUTOMATIC EXTVCC REGULATOR DISCONNECT: As
discussed in more detail in the LT8705 data sheet,
the INTVCC pin is regulated to 6.35V from one of two
possible input pins, VIN or EXTVCC. The EXTVCC pin is
often connected to the battery allowing INTVCC to be
regulated from a low voltage supply which minimizes
power loss and heating in the LT8490. However, EXTVCC
should be disconnected from the battery when charging
current is low to avoid discharging the battery.
When MODE is low, the LT8490 automatically forces
the INTVCC regulator to use VIN instead of EXTVCC for
the input supply when charging current becomes low.
Charging current is monitored on the IMON_OUT pin.
When IMON_OUT falls below 122mV (typical) the
INTVCC regulator uses VIN as the input supply. When
IMON_OUT rises above ~195mV INTVCC will regulate
from EXTVCC if EXTVCC is also above 6.4V (typical).
This same functionality can be achieved when MODE
is tied high by using the external circuit discussed in
the Optional EXTVCC Disconnect section.
Finally, a 305kΩ (typical) resistor is connected from
EXTVCC to ground inside the LT8490. This resistor
can draw current from the battery unless EXTVCC is
disconnected. See the Optional EXTVCC Disconnect
section for a way to automatically disconnect EXTVCC
when charging current becomes low or charging stops.
8490 F23
VIN VOUT
RSENSE
M2
SW1 SW2
L
BG1
M1
M3
M4
TG1
BG2
TG2
LT8490
29
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Optional Low Power Mode
When current from the solar panel is not high enough to
reliably measure the maximum power point, the LT8490
may automatically begin operating in low power mode.
Low power mode is automatically disabled when operat-
ing from a DC supply in power supply mode. Otherwise,
the low power mode feature is enabled by default and
allows the LT8490 to charge a battery under very low
light conditions that would otherwise cause the LT8490
to stop charging. Low power mode can also be disabled
with a method discussed later in this section.
In low power mode, the LT8490 momentarily stops charg-
ing, allowing the panel voltage to rise. When the panel
has sufficiently charged the input capacitor, the LT8490
transfers energy from the input capacitor to the battery
while drawing down the panel voltage. This behavior re-
peats rapidly, delivering charge to the battery as shown in
the Panel Voltage in Low Power Mode plots in the Typical
Performance Characteristics section.
MINIMUM INPUT CAPACITANCE FOR LOW POWER MODE:
A minimum amount of energy must be transferred from
the input capacitor to the battery during each charge
transfer cycle. Otherwise the battery may be drained
instead of being charged. Figure 24 shows the minimum
input capacitance required when the charger is operating
near the 10V minimum input voltage. As the panel volt-
age rises, due to increased illumination, more energy is
stored in the input capacitor and a corresponding increase
of energy is delivered to the battery. Carefully check the
solar panel voltage for good stability and minimal ripple
when operating with low input capacitance.
MINIMUM INPUT VOLTAGE: With low power mode enabled,
the panel voltage must initially exceed 10V (typical – as
measured through the VINR pin) before the charger will
attempt to charge the battery. If adequate charge is not
being delivered to the battery, the charger may temporarily
wait for even more input voltage before transferring the
input charge to the battery.
EXITING LOW POWER MODE: The charger will automati-
cally exit low power mode and resume normal charging
after adequate input current is detected. The charger
typically requires the input current to exceed 2.5% to Figure 25. Disabling Low Power Mode with Resistor RNLP
3% of the maximum input current limit to make a valid
power point reading and exit low power mode. The panel
voltage may be adjusted as low as 6V when searching for
the maximum power point.
DISABLING LOW POWER MODE: If the minimum input
capacitance, or 10V minimum start-up voltage are not suit-
able for the application, low power mode can be disabled
by including the resistor RNLP = 3.01kΩ as shown in Figure
25. When low power mode is disabled, the LT8490 will
attempt to charge the battery after 6V or more is detected
on the panel. If the input current is too low (typically less
than 1.5% of the maximum input current limit) charging
is temporarily halted. The LT8490 will attempt to charge
the battery on 30 second intervals or when the LT8490
measures a significant rise in the panel voltage. When the
LT8490 determines that there is sufficient panel current,
normal charging operation will automatically resume.
8490 F25
LT8490
GND
VIN
VIN
RDACI1
CDACI
FBIR
FBIN
FBIW
RNLP
3.01k
RDACI2
RFBIN1
RFBIN2
Figure 24. Minimum Input Capacitor
Required for Low Power Mode
BATTERY VOLTAGE (V)
0
0
50
100
150
200
MINIMUM INPUT CAPACITANCE (µF)
250
20 40 6010 30 50 70 80
8490 F24
LT8490
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Figure 26. Battery Discharge When Not Charging
Figure 27. Optional Feedback Resistor Disconnect Circuit
Optional Output Feedback Resistor Disconnect
To measure and regulate the battery voltage, the LT8490
uses a resistor feedback network connected to the battery.
Unless these resistors are disconnected from the battery,
they will draw current from the battery even when it is not
being charged as seen in Figure 26. This may be undesir-
able when using small capacity batteries.
If desired, the resistors can be automatically disconnected
from the battery when charging stops by using the cir-
cuit shown in Figure 27. This circuit is controlled by the
SWENO signal from the LT8490 and connects the resistor
feedback network when charging is taking place. When
charging stops, the network is disconnected and current
draw from the battery becomes negligible.
8490 F26
LT8490
RDACO1
GND
FBOW
FBOR
SWEN
SWENO
200k
RDACO2
FBOUT
RFBOUT2
VBAT
+
–
CDACO
RFBOUT1
IDRAIN
8490 F27
RDACO1
GND
FBOW
SWEN
SWENO
200k
RDACO2
RFBOUT2
Q3
OPTIONAL
FEEDBACK
RESISTOR
DISCONNECT
CIRCUIT
Z1
(OPT.)
VBAT
+
–
CDACO
RVGS1
100k
TO CHARGER OUT
AT RSENSE2
RLIM3
26.1k
RFBOUT1
M5
LT8490
FBOR
FBOUT
SELECTING M5: This PMOS must have a drain to source
breakdown voltage greater than the maximum VBAT. The
ZVP3310F is rated for 100V making it suitable for most
applications.
SELECTING Q3: This NPN must have a collector to emitter
breakdown voltage greater than the maximum VBAT. The
MMBT5550L is also suitable for most applications due to
its 140V breakdown rating.
SELECTING RLIM3: Using VGSon and setting RVGS1 to 100kΩ
RLIM3 =RVGS1
VGSon
⎛
⎝
⎜⎞
⎠
⎟•2.6V
⎡
⎣
⎢⎤
⎦
⎥Ω
where VGSon is the desired gate to source voltage needed
to turn on M5. If M5 is not properly selected, the on re-
sistance may be large enough to cause a significant volt-
age drop across the drain-source terminal of this device.
Check this voltage drop to determine if the application
can tolerate this error
.
SELECTING Z1: Due to the transients that may occur
during hot-plugging of a battery, this Zener diode is rec-
ommended to protect device M5 from excessive gate to
source voltage. If using device Z1, the reverse breakdown
voltage should be selected such that VGSon < VZ1breakdown
< VGSMAX where VGSMAX is the maximum rated gate to
source voltage specified by the device manufacturer. The
BZT52C13 has a reverse breakdown voltage of 13V making
it suitable for the RLIM3 value shown in Figure 27.
ALTERNATE CIRCUIT: For lower battery voltages (< 20V),
Q3 in Figure 27 can saturate. To avoid this, consider con-
necting the emitter of Q3 directly to ground by removing
RLIM3 and adding resistor RLIM4 to the base of Q3 as
shown in Figure 28. Employing the optional feedback
resistor disconnect at arbitrarily low battery voltages will
be limited by the required gate to source voltage of M5.
Use the following equation to properly set RLIM4:
RLIM4 =91•
R
VGS1
V
BAT
LT8490
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Figure 30. IR Drop Present in Battery Connection
8490 F29
LT8490
GND
EXTVCC
ECON
200k
Q4
OPTIONAL
EXTVCC
DISCONNECT
CIRCUIT
M6: ZVP3310F
Q4: MMBT5550L
Z2: BZT52C13
Z2
(OPT.)
VBAT
+
–
1µF
RVGS2
100k
TO CHARGER OUT
AT RSENSE2
RLIM4
26.1k
10Ω
M6
Optional EXTVCC Disconnect
It is often desirable to connect EXTVCC to the battery to
reduce power loss (increase efficiency) and heating in the
LT8490. However, the LT8490 draws current into the EXT-
VCC pin that can drain the battery when charging currents
are low or when charging stops. Tying the MODE pin low,
as discussed in the Switching Configuration – MODE Pin
section, eliminates most of the current draw from EXTVCC
when the charging current becomes low. However, there is
a 305kΩ (typical) path from EXTVCC to ground through the
LT8490 at all times. If MODE is tied high or if the 305kΩ
load is undesirable, EXTVCC can be disconnected with the
optional circuit shown in Figure 29.
The LT8490, via the ECON signal, disconnects EXTVCC from
the battery when charging current becomes low. Charging
current is monitored by measuring the IMON_OUT pin
voltage with the IOR pin’s A/D input. When IMON_OUT
falls below 122mV (typical) the ECON signal goes low and
EXTVcc is disconnected from the battery. When IMON_OUT
rises above 195mV (typical) the ECON signal goes high
and EXTVCC is reconnected to the battery.
Follow the same recommendations and equations from
the previous section for choosing components for the
optional EXTVCC disconnect circuit.
Optional Remote Battery Voltage Sensing
The LT8490 measures the battery voltage continually
during charging. The apparent battery voltage is sensed
from ground of the LT8490 to the top of RFBOUT1. Dur-
ing charging, resistance in the battery cables (RCABLE+/
RCABLE– in Figure 30) causes the apparent voltage to be
higher than the actual battery voltage by 2 • VIR.
The effects of this cable drop are most significant when
charging low voltage batteries at high currents. As an
example, a 4 foot battery cable using 14 AWG wire can
have a voltage drop exceeding 0.5V at 15A of current. Note
however that the voltage drop, along with the charging
current, reduces automatically as the battery approaches
full charge.
Figure 29. Optional EXTVCC Disconnect Circuit
8490 F29
RDACO1
GND
FBOW
SWEN
SWENO
200k
RDACO2
RLIM4
RFBOUT2
Q3
OPTIONAL
FEEDBACK
RESISTOR
DISCONNECT
CIRCUIT
VBAT
+
–
CDACO
RVGS1
100k
TO CHARGER OUT
AT RSENSE2
RFBOUT1
M5
LT8490
FBOR
FBOUT
Figure 28. Optional Low Battery Voltage Feedback
Resistor Disconnect Circuit
8490 F30
LT8490
GND
VIR
RDACO2
CDACO
FBOR
FBOW
FBOUT
RCABLE+
RCABLE–
RDACO1
RFBOUT1
ICHARGE
RFBOUT2
VBAT
+
+ –
VIR
– +
–
TO CHARGER OUT
AT RSENSE2
LT8490
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Figure 31. Remove (+) and (–) Cable VIR Measurement Errors
8490 F31
LT8490
GND
RDACO2
CDACO
FBOR
FBOW
RDACO1
R´FBOUT1 INTVCC
1µF
Q5
RFBOUT2
R5
R3
R2
VBAT
+
–
TO CHARGER OUT
AT RSENSE2
10Ω
D2A D2B D2C
R˝FBOUT1
–
+
LT1636
D3A D3B
R4
RCABLE–
RCABLE+
FBOUT
applicaTions inForMaTion
The most significant effects from the VIR voltage drops
are as follows:
1. When approaching full charge in Stage 2, the VIR er-
ror causes the charger to reduce the charging current
earlier than otherwise necessary. This increases the
total charging time.
2. Terminating at C/10 in Stage 2 will occur at a reduced
battery voltage equal to C/10 • (RCABLE+ + RCABLE–) which
is 10% of the voltage drop at full charging current.
3. The STATUS pin will indicate a transition from Stage 1
to Stage 2 earlier than would otherwise occur without
the cable drop.
Again, these effects become less significant at higher
battery voltages because the charging current is typically
lower and the cable drop becomes a smaller percentage
of the total battery voltage. Using thicker and/or shorter
battery cables is the simplest method for reducing these
effects. Otherwise, the remote battery sensing circuit in
Figure 31 can correct for these effects.
The RCABLE+ measurement error is eliminated by includ-
ing an additional (+) terminal sensing cable. The negative
cable error is eliminated by subtracting the RCABLE– drop
from the voltage measured at the positive battery terminal
using a (–) terminal sensing cable, the LT1636, Q5 and
R5. R´FBOUT, R˝FBOUT and R5 are determined as follows:
RʺFBOUT1 =
0.5 •R
FBOUT1
VS2 −1.211 Ω
RʹFBOUT1 =RFBOUT1 −RʺFBOUT1
( )
Ω
R5 =Rʺ
FBOUT1
Ω
where VS2 is the room temperature Stage 2 voltage limit
and the solution for RFBOUT1 was discussed previously in
the Stage Voltage Limits section. Solutions for determining
RDACO1, RDACO2, RFBOUT2 and CDACO are also discussed
in the Stage Voltage Limits section.
Due to its low current draw (< 1mA) Q5 can be a small
signal device with a collector-emitter breakdown voltage
at least as high as the battery voltage. The MMBT3904 is
a good BJT rated to 40V. Alternatively, the MMBT5550L
is rated for 140V.
R3 is for safety in case the (+) battery sensing cable
becomes disconnected. R3 prevents overcharging the
battery in such an event by creating an alternate path to
pull up the R˝FBOUT1 battery voltage sensing resistor. The
R3 resistance should be less than 1% of RFBOUT1. Select-
ing R3 as a 100Ω resistor is often a good choice. During
LT8490
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normal operation the voltage across R3 is about the same
as across RCABLE+. However, R3 may experience voltage
up to VS2-VBAT across its terminals if RCABLE+ becomes
disconnected. R3 should be selected with an appropriate
power rating, often at least 1W.
D2A-D2C protect the charger if the positive charging cable
(RCABLE+) becomes disconnected while the others remain
intact. Without the diodes, the output of the charger may
overvoltage and become damaged. BAV99 diodes are a
good choice and are available in a dual-diode package
to minimize board space. Note that the diodes limit the
maximum RCABLE+ error to 0.3V to 0.5V. If a greater volt-
age drop is typical in the positive cable then place more
diodes in series. D2D protects the M5 device by limiting
the gate to source voltage when making the remote sense
connection.
D3A, D3B and R4 protect the input of the LT1636 from
possible voltage extremes at the (–) battery terminal sens-
ing connection. The dual-diode BAV99 is also suitable in
this case. 4.99kΩ is a good value for R4.
R2 maintains a negative voltage reference in case RCABLE–
becomes disconnected. Selecting R2 as a 100Ω resistor is
often a good choice. During normal operation the voltage
across R2 is about the same as across RCABLE–. However,
R2 may experience voltage in excess of VS2-VBAT across its
terminals if RCABLE– becomes disconnected. R2 should be
selected with an appropriate power rating, often at least 1W
due to the case where the (+) and (–) wires of the remote
sense circuit are first connected to the battery to address
hot plugging issues (see the Hot Plugging Considerations
section for more detail).
Figure 32 shows how to combine the remote sensing circuit
(Figure 31) and the feedback resistor disconnect (Figure
27) for applications that require the most accurate battery
voltage sensing and negligible battery drain when charging
completes. The RVGS1 resistor can no longer connect to
the source of M5 (as in Figure 27) since the RVGS1 current
would also flow through R˝FBOUT1 causing an error in the
measured battery voltage. Figure 31 shows that RVGS1
has been reconnected to the (+) battery sensing terminal.
Figure 32. How to Combine Figure 27 and Figure 30
8490 F32
LT8490
GND
RDACO2
CDACO
FBOR
FBOW
RDACO1
R´FBOUT1
M5
RVGS1
100k
INTVCC
1µF
Q5
RFBOUT2
R5
R2
VBAT
+
–
TO CHARGER OUT
AT RSENSE2
10Ω
D2A
D2D
D2B D2C
R˝FBOUT1
–
+
R3
LT1636
D3A D3B
R4
RCABLE–
RCABLE+
SWEN
SWENO
200k
Q3
RLIM3
26.1k
FBOUT
LT8490
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Figure 33. Optional DC Supply Detection Circuit
8490 F33
LT8490
DVDC
GND
VIN
VDC TO RSENSE1
Q6: 2SD2704K
VPANEL
VINR
100k
33k
196k
8.06k
Q6
DPANEL
Optional DC Supply Detection Circuit
A dual input application can be configured where the
charger can be supplied by either a solar panel or a DC
supply. When powered by a DC supply, the VINR pin must
be pulled low to activate power supply mode. In addition,
blocking diodes should be incorporated to prevent the sup-
plies from back-feeding into each other. The circuit shown
in Figure 33 shows a way to incorporate those features.
As shown in Figure 33, when the DC supply is connected
the Q6 NPN pulls VINR below 174mV (typical) to activate
the Power Supply Mode of the LT8490. Be sure to choose
an NPN that can pull VINR below the power supply mode
threshold before fully saturating. Alternatively, Q6 can be
replaced with an NMOS device with proper care taken to
avoid overvoltage of the NMOS gate.
Depending on the current limit settings, diodes DPANEL
and DVDC can incur significant current and heat. Con-
sider the use of Schottky diodes or an appropriate ideal
diode such as the LTC4358, LTC4412, LTC4352, etc. to
minimize heating.
applicaTions inForMaTion
Board Layout Considerations
For all power components and board routing associated
with the LT8705 portion of the LT8490, please refer to the
LT8705 documentation for which a circuit board layout
checklist and drawing is provided.
Hot Plugging Considerations
When connecting a battery to an LT8490 charger, there can
be significant inrush current due to charge equalization
between the partially charged battery stack and the charger
output capacitors. To a lesser extent a similar effect can
occur when connecting an illuminated panel or powered
DC supply to the input. The magnitude of the inrush current
depends on (1) the battery, panel or supply voltage, (2)
ESR of the input or output capacitors, (3) initial voltage of
the capacitors, and (4) cable impedance. Excessive inrush
current can lead to sparking that can compromise con-
nector integrity and/or voltage overshoot that can cause
electrical overstress on LT8490 pins.
Excessive inrush current can be mitigated by first con-
necting the battery or supply to the charger through a
resistive path, followed quickly by a short circuit. This can
be accomplished using staggered length pins in a multi-pin
connector. This can also be accomplished through the use
of the optional circuit shown in Figure 31 by first connecting
the (+) and (–) battery remote sense connections, which
allow the charger output capacitors to charge through
resistors R2 and R3. Alternatively, consider the use of a
Hot Swap™ controller such as the LT1641, LT4256, etc.
to make a current limited connection.
Design Example
In this design example, the LT8490 is paired with a
175W/5.4A panel (VMAX < 53V) and a 12V flooded lead-
acid battery. The desired maximum battery charging
current (C) is 10A with a trickle charge current of 2.5A
(C/4). Charger settings are as follows: –20°C to 50°C valid
battery temperature range, temperature compensated
charging limits, no time limits and Stage 3 is enabled with
VS3/VS2 = 97.2%. In this example resistors are rounded to
the nearest standard value. If better accuracy is required
then multiple resistors in series may be required.
LT8490
35
8490fa
For more information www.linear.com/LT8490
• With RFBOUT2 set at 20kΩ and a desired Stage 2 voltage
limit of 14.2V, the top output feedback resistor, RFBOUT1,
is calculated according to the following equation:
RFBOUT1 =RFBOUT2 •VS2 •1.241
1.211−0.128
⎛
⎝
⎜⎞
⎠
⎟−1
⎡
⎣
⎢⎤
⎦
⎥Ω
=20k •14.2 •1.241
1.211−0.128
⎛
⎝
⎜⎞
⎠
⎟−1
⎡
⎣
⎢⎤
⎦
⎥Ω
=234,684Ω
Choose RFBOUT1 = 237kΩ which is the closest standard
value resistor.
• Following the calculation of RFBOUT1, solve for RDACO1,
RDACO2 and CDACO according to the following formulas:
RDACO2 =RFBOUT1 •RFBOUT2 •0.833
RFBOUT2 •VS2 •1.241
1.211
⎛
⎝
⎜⎞
⎠
⎟−RFBOUT2 −RFBOUT1
Ω
=234,684 •20k •0.833
20k •14.2 •1.241
1.211
⎛
⎝
⎜⎞
⎠
⎟−20k −234,684
Ω
=107,556Ω
Choose RDACO2 = 107kΩ which is the closest standard
value resistor.
RDACO1 = (0.2 • RDACO2) Ω
= 0.2 • 107,556Ω
= 21,511Ω
Choose RDACO1 = 21.5kΩ which is the closest standard
value resistor.
CDACO =
1
500 •RDACO1
F
=1
500 •21,511F
=93nF
applicaTions inForMaTion
• Using the standard value resistors calculated above, the
VX3, N1 and N2 checking equations yield the following:
VX3 = 14.31V
N1 = 1.22
N2 = 0.804
• In order to find a resistor combination that yields VX3
closer to the desired 14.2V, RFBOUT2 is increased to the
next higher standard value and the above calculations
are repeated.
• Iterations of the previous step are performed that
include adjustments to RFBOUT1, RDACO1 and RDACO2
until the following standard value feedback resistors
were chosen:
RFBOUT1 = 274kΩ
RFBOUT2 = 23.2kΩ
RDACO1 = 26.1kΩ
RDACO2 = 124kΩ
CDACO = 0.082µF
where:
VX3 = 14.27V
N1 = 1.22
N2 = 0.805
• With the output feedback network determined, use
VMAX and solve for the input resistor feedback network
according to the following formulas:
RFBIN1 =100k •
1+4.47V
VMAX −6V
⎛
⎝
⎜⎞
⎠
⎟
1+5.593V
VMAX −6V
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
⎥
Ω
=100k •
1+4.47V
53V −6V
⎛
⎝
⎜⎞
⎠
⎟
1+5.593V
53V −6V
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
⎥
Ω
=97,865Ω
LT8490
36
8490fa
For more information www.linear.com/LT8490
applicaTions inForMaTion
The closest standard value for RFBIN1 is 97.6kΩ.
RDACI2 =2.75 •RFBIN1
VMAX −6V
⎛
⎝
⎜⎞
⎠
⎟Ω
=2.75 •97,865
53V −6V
⎛
⎝
⎜⎞
⎠
⎟Ω
=5,726Ω
Choose RDACI2 = 5.76kΩ which is the closest standard
value.
RFBIN2 =
1
1
100k −RFBIN1
⎛
⎝
⎜⎞
⎠
⎟−1
RDACI2
⎛
⎝
⎜⎞
⎠
⎟
Ω
=1
1
100k −97,865
⎛
⎝
⎜⎞
⎠
⎟−1
5,726
⎛
⎝
⎜⎞
⎠
⎟
Ω
=3,404Ω
Choose RFBIN2 = 3.4kΩ which is the closest standard
value.
R
DACI1 =
0.2 •R
DACI2 Ω
=0.2 •5,726Ω
=1,145Ω
Choose RDAC1 = 1.1kΩ which is the closest standard
value.
CDACI =
1
1000 •RDACI1
F
=1
1000 •1,145F
=873nF
• Similar to the output feedback resistors, the final input
feedback resistors were chosen to be standard values
using an iterative process. The VX1 and VX2 equations
in the Input Voltage Sensing and Modulation Network
section were used to validate the selections:
RFBIN1 = 93.1kΩ
RFBIN2 = 3.24kΩ
RDACI1 = 1.05kΩ
RDACI2 = 5.49kΩ
CDACI = 1µF
where:
VX1 = 6V
VX2 = 53V
• The 10A maximum charge current limit and 2.5A
trickle charge current limit are set by choosing RSENSE2,
RIMON_OUT and RIOW using the following formulas:
RSENSE2 =
0.0497
IOUT(MAX)
Ω =
0.0497
10 ≅5mΩ
RIMON _ OUT =1208
IOUT(MAXS0) •RSENSE2
Ω
=1208
2.5 •5mΩ
=96.64kΩ
where the nearest standard value is 97.6kΩ.
RIOW =
24.3k •R
IMON _ OUT
RIMON _ OUT −24.3k Ω
=24.3k •47.6k
97.6k −24.3k Ω
=32,356Ω
where the nearest standard value is also 32.4kΩ.
LT8490
37
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For more information www.linear.com/LT8490
applicaTions inForMaTion
• The input current limit is set by properly choosing
RSENSE1. In this example, the panel can deliver up to
5.4A. Choosing a margin of 30% yields:
RSENSE1 =
0.0505
IIN(MAX)
=
0.0505
1.3 •5.4 =7.2mΩ
• To enable temperature compensated charging limits
and allow a Stage 3 regulation voltage of 97.2% of
Stage 2, use VS3 /V
S2 = 0.972 in the following equation:
CHARGECFG1% =2.67 •VS3
VS2
−0.85
⎛
⎝
⎜⎞
⎠
⎟+0.55
⎡
⎣
⎢⎤
⎦
⎥•100%
CHARGECFG1% =87.6%
Standard resistor values of 90.9kΩ (from CHARGECFG1
to ground) and 13kΩ (from AVDD to CHARGECFG1) can
be used to set CHARGECFG1.
• To set no time limits with a –20°C to 50°C valid battery
temperature range requires CHARGECFG2 to be tied to
AVDD.
• For greater charging voltage accuracy, it is recom-
mended that 0.1% tolerance resistors be used for the
output feedback resistor network.
• Please reference the LT8705 data sheet for completing
the remaining power portions of the LT8490.
LT8490
38
8490fa
For more information www.linear.com/LT8490
applicaTions inForMaTion
Figure 34. 27.4V Lithium-Ion Polymer Battery Charger
CIN2
2.2µF
×2
8490 F34
3.3nF
3.3nF
10Ω
CSPBG1SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2
CSPOUT
CSNOUT
EXTVCC
FBOR
FBOUT
FBOW
10Ω
6mΩ
L1
10µH
2Ω
COUT3
10µF
×2
COUT2
10µF
×2
CIN3
2.2µF
×2 COUT1
150µF
100Ω
220nF
220nF
DB1
24.3k
M3
GATEVCC´
442k
VDD
AVDD
CIN4
2.2µF
DB2
GATEVCC´
TENERGY 31417
Li-Ion POLYMER
10Ah
7S1P
LOAD
+
–
½W
7mΩ ½W
10mΩ
470nF
+
–
549Ω
VOC < 53V
SOLAR
PANEL
2Ω
M1 M4
18.7k
TEMPSENSE
SRVO_FBIN
SRVO_IIN
SRVO_FBOUT
SRVO_IOUT
ECON
SWEN
SWENO
CHARGECFG1CHARGECFG2
RT
SS
IIR
IMON_IN
IOW
IMON_OUT
IOR
STATUS FAULTSYNCVCCLKDET CLKOUT
LT8490
549Ω
DFDS
102k
LDO33
CSNIN
CSPIN
VIN
GATEVCC
GATEVCC´
MODE
INTVCC
FBIN
FBIR
FBIW
VINR
SHDN
4.7µF
82nF
1µF
100nF
10Ω 10Ω
200k
4.7µF
×2
196k
8.06k
93.1k
3.24k
110k
35.7k
4Ω
5.49k
215k
53.6k
1.3k
3.32k
1.05k
0.82µF
100nF
10nF
27.4V STAGE 2 (FLOAT) CHARGE VOLTAGE (VS2)
STAGE 3 DISABLED
5A CHARGING CURRENT LIMIT
2A TRICKLE CURRENT LIMIT
7.2A INPUT CURRENT LIMIT
53V MAXIMUM PANEL VOLTAGE (VMAX)
NO TIMER LIMITS
TEMPERATURE COMPENSATION DISABLED
202kHz SWITCHING FREQUENCY
EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W
M1, M2: INFINEON BSC028N06NS
M3, M4: INFINEON BSC059N04LSG
L1: 10µH COILCRAFT SER2915H-103KL
DB1, DB2: CENTRAL SEMI CMMR1U-02
CIN1: 33µF, 63V, SUNCON 63HVH33M
CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A
COUT1: 150µF, 50V PANASONIC EEU-FR1H151
COUT2, COUT3: 10µF, 35V, MURATA GRM32ER7YA106KA12
COUT4: 1µF, 50V, TDK CGA6L2X7R1H105K
CCSPOUT: 100nF, 50V, AVX 08055C10
68nF
10k
3.01k
40.2k
220pF
8.2nF
21k
60.4k
10nF
470nF
M2
11.5k
10k
AVDD
CIN1
33µF
×3 COUT4
1µF
CCSPOUT
100nF
LT8490
39
8490fa
For more information www.linear.com/LT8490
applicaTions inForMaTion
56.8V Lead-Acid Battery Charger (Four 12V Batteries in Series)
CIN2
2.2µF
×2
8490 TA02
10nF
10nF
10Ω
CSPBG1SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2
CSPOUT
CSNOUT
EXTVCC
FBOR
FBOUT
FBOW
10Ω
6mΩ
L1
15µH ½W
10mΩ
COUT2
4.7µF
×2
COUT3
4.7µF
×2
CIN3
2.2µF
×2 COUT1
220µF
100Ω
220nF
220nF
DB1
22.6k
M3
GATEVCC´
1M
VDD
AVDD
CIN4
2.2µF
DB2
GATEVCC´
FLOODED
LEAD
ACID
LOAD
+
–
½W
5mΩ
470nF
+
–
549Ω
VOC < 80V
SOLAR
PANEL
M1 M4
20k
TEMPSENSE
SRVO_FBIN
SRVO_IIN
SRVO_FBOUT
SRVO_IOUT
ECON
SWEN
SWENO
CHARGECFG1CHARGECFG2
RT
SS
IIR
IMON_IN
IOW
IMON_OUT
IOR
STATUS FAULTSYNCVCCLKDET CLKOUT
LT8490
549Ω
DFDS
115k
LDO33
CSNIN
CSPIN
VIN
GATEVCC
GATEVCC´
MODE
INTVCC
FBIN
FBIR
FBIW
VINR
SHDN
4.7µF
0.1µF
1µF
100nF
10Ω 10Ω
90.9k
200k
4.7µF
×2
196k
8.06k
133k
3.09k
110k
35.7k
4Ω
4.87k
301k
53.6k
1.3k 13k
3.32k
1.05k
1µF
100nF
8.2nF
56.8V STAGE 2 (ABSORPTION) CHARGE VOLTAGE (VS2) AT 25°C
55.2V STAGE 3 (FLOAT) CHARGE VOLTAGE (VS3) AT 25°C
5A CHARGING CURRENT LIMIT
1.25A TRICKLE CURRENT LIMIT
11.4A INPUT CURRENT LIMIT
80V MAXIMUM PANEL VOLTAGE (VMAX)
NO TIMER LIMITS
TEMPERATURE COMPENSATION ENABLED
–20°C TO 50°C BATTERY TEMPERATURE RANGE
145kHz SWITCHING FREQUENCY
EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W,
SHARP NU-U235F3 235W
M1: INFINEON BSC046N10NS
M2: INFINEON BSC109N10NS
M3, M4: INFINEON BSC057N08NS
L1: 15µH COILCRAFT SER2915H-153KL
DB1, DB2: CENTRAL SEMI CMMR1U-02
CIN1, COUT1: 220µF, 100V, UNITED CHEMI-CON EKZE101ELL221MK255
CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A
COUT2, COUT3: 4.7µF, 100V, TDK C4532X7S2A475M230KB
COUT4: 1µF, 100V AVX 12101C105KAT2A
CCSPOUT: 100nF, 50V, AVX 08055C10
68nF
11.3k
3.01k
32.4k
220pF
10nF
21k
97.6k
10nF
470nF
M2
11.5k
10k
AT 25°C
ß = 3380
NTC
AVDD AVDD
CIN1
220µF
COUT4
1µF
CCSPOUT
100nF
LT8490
40
8490fa
For more information www.linear.com/LT8490
package DescripTion
UKJ Package
Variation: UKJ64(58)
64(58)-Lead Plastic QFN (7mm × 11mm)
(Reference LTC DWG # 05-08-1922 Rev Ø)
11.00 ±0.10
7.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
63
1
2
BOTTOM VIEW—EXPOSED PAD
11.00 ±0.10 9.50 REF
0.75 ±0.05
0.25 ±0.05 (UKJ64(58)) QFN 0412 REV Ø
0.50 BSC
0.50 REF
0.200 REF
0.00 – 0.05
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
0.325
REF
0.40 ±0.10
0.50 BSC
0.45
9.50 REF
5.50 REF
11.50 ±0.05
10.10 ±0.05
7.50 ±0.05
0.70 ±0.05
1.50 ±0.05
9.38 ±0.05
3.60 ±0.05
3.83
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
6453
52
44
40
35
33
31 27 25 21
20
UKJ Package
Variation: UKJ64(58)
64(58)-Lead Plastic QFN (7mm × 11mm)
(Reference LTC DWG # 05-08-1922 Rev Ø)
3.60 ±0.10
3.83 ±0.10
0.45 ±0.10
9.38 ±0.10
1.50 ±0.10
1.20 ±0.10
1.80 ±0.05
Please refer to http://www.linear.com/product/LT8490#packaging for the most recent package drawings.
LT8490
41
8490fa
For more information www.linear.com/LT8490
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 11/15 Changed diode type symbol.
Modified the Block Diagram.
1, 38, 39, 42
11
LT8490
42
8490fa
For more information www.linear.com/LT8490
LINEAR TECHNOLOGY CORPORATION 2014
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT8490
LT 1115 REV A • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT3652/LT3652HV Power Tracking 2A Battery Charger for Solar Power VIN Range = 4.95V to 32V (LT3652), 4.95V to 34V (HV),
MPPC
LTC4000-1 High Voltage, High Current Controller for Battery Charger with MPPC VIN and VOUT Range = 3V to 60V, MPPC
LTC4020 55V VIN/VOUT Buck-Boost Multi-Chemistry Battery Charging Controller Li-Ion and Lead-Acid Algorithms, MPPC
14.2V Flooded Lead-Acid Battery Charger
CIN2
2.2µF
×2
8490 TA03
3.3nF
3.3nF
10Ω
CSPBG1SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2
CSPOUT
CSNOUT
EXTVCC
FBOR
FBOUT
FBOW
10Ω
5mΩ
L1
15µH
2Ω
COUT2
10µF
×2
COUT3
10µF
×2
CIN3
2.2µF
×2 COUT1
150µF
220nF
220nF
DB1
26.1k
M3
GATEVCC´
274k
VBAT
VDD
AVDD
CIN4
2.2µF
DB2
GATEVCC´
FLOODED
LEAD
ACID
LOAD
+
–
½W
7mΩ 1W
5mΩ
470nF
+
–
549Ω
VOC < 53V
SOLAR
PANEL
2Ω
M1 M4
23.2k
TEMPSENSE
SRVO_FBIN
SRVO_IIN
SRVO_FBOUT
SRVO_IOUT
ECON
SWEN
SWENO
CHARGECFG1CHARGECFG2
RT
SS
IIR
IMON_IN
IOW
IMON_OUT
IOR
STATUS FAULTSYNCVCCLKDET CLKOUT
LT8490
549Ω
DFDS
124k
LDO33
CSNIN
CSPIN
VIN
GATEVCC
GATEVCC´
MODE
INTVCC
FBIN
FBIR
FBIW
VINR
SHDN
4.7µF
10k
AT 25°C
ß = 3380
NTC
0.082µF
1µF
100nF
10Ω 10Ω
200k
90.9k
4.7µF
×2
196k
8.06k
93.1k
3.24k
110k
35.7k
4Ω
5.49k
249k
53.6k 1.3k
AVDD
3.32k
1.05k
1µF
100nF
4.7nF
14.27V STAGE 2 (ABSORPTION) CHARGE VOLTAGE (VS2) AT 25°C
13.87V STAGE 3 (FLOAT) CHARGE VOLTAGE (VS3) AT 25°C
10A CHARGING CURRENT LIMIT
2.5A TRICKLE CURRENT LIMIT
7.2A INPUT CURRENT LIMIT
53V MAXIMUM PANEL VOLTAGE (VMAX)
NO TIMER LIMITS
TEMPERATURE COMPENSATION ENABLED
–20°C TO 50°C BATTERY TEMPERATURE RANGE
175kHz SWITCHING FREQUENCY
EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W
M1, M2: INFINEON BSC028N06NS
M3, M4: INFINEON BSC042N03LSG
L1: 15µH COILCRAFT SER2915H-153KL
DB1, DB2: CENTRAL SEMI CMMR1U-02
CIN1: 33µF, 63V, SUNCON 63HVH33M
CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A
COUT1: 150µF, 35V NICHICON UPJ151MPD6TD
COUT2, COUT3: 10µF, 35V, MURATA GRM32ER7YA106KA12
COUT4: 1µF, 25V AVX 12063C105KAT2A
68nF
8.45k
3.01k
32.4k
470pF
10nF
21k
97.6k
8.2nF
470nF
M2
11.5k
13k AVDD
CIN1
33µF
×3 COUT4
1µF
