Data Sheet FEATURES Filterless mono, digital input Class-D amplifier I2C control interface Serial digital audio interface supports common formats (I2S, PCM, LJ, RJ, TDM1-16, PDM) Supports wide range of sample rates: 8.0 kHz to 96.0 kHz MCLK and BCLK can be provided by built-in phase-locked loop (PLL) Supports single power supply mode; DVDD can be provided by built-in low dropout (LDO) regulator 2.5 V to 5.5 V SPKVDD operating supply voltage 1.08 V to 1.98 V DVDD operating supply voltage Support off-chip volume control without I2C 2.4 W into 4 and 1.4 W into 8 at 5 V supply with <1% THD + N Available in a 16-ball, 1.92 mm x 1.94 mm, 0.4 mm pitch WLCSP Efficiency 95% at full scale into 8 Signal-to-noise ratio (SNR): 103 dB, A-weighted Power supply rejection ratio (PSRR): >80 dB at 217 Hz Digital volume control: -70 dB to +24 dB in 0.375 dB steps Ultralow idle current Autosample rate detection Pop-and-click suppression Short-circuit and thermal protection with programmable autorecovery Supports smart power-down when no input signal is detected Power-on reset and UVLO voltage monitoring Selectable ultralow EMI emission mode Supports SPKVDD voltage monitor Digital audio processing 7-band programmable equalizer Programmable dynamic range compression (DRC) with noise gate, expander, compressor, and limiter APPLICATIONS Mobile phones Portable media players Laptop PCs Wireless speakers Portable gaming Navigation systems GENERAL DESCRIPTION The SSM2529 is a digital input, Class-D power amplifier that combines a digital-to-analog converter (DAC), a low power audio specific digital signal processor, and a sigma-delta (-) Class-D modulator. Digital Input, Mono 2 W, Class-D Audio Power Amplifier SSM2529 This unique architecture enables extremely low real-world power consumption from digital audio sources with excellent audio performance. The SSM2529 is ideal for power sensitive applications, such as mobile phones and portable media players, where system noise can the corrupt small analog signals that are sent to an analog input audio amplifier. Using the SSM2529, audio data can be transmitted to the amplifier over a standard digital audio serial interface, thereby significantly reducing the effect of noise sources such as GSM interference or other digital signals on the transmitted audio. The closed-loop digital input design retains the benefits of an all-digital amplifier, yet enables very good PSRR and audio performance. The three-level, - Class-D modulator is designed to provide the least amount of EMI, the lowest quiescent power dissipation, and the highest audio efficiency without sacrificing audio quality. The audio input is provided via a serial audio interface that can be programmed to accept all common audio formats, including I2S, TDM, and PDM. Control of the IC is provided via an I2C control interface. An alternative to I2C control is standalone operation mode, which allows several settings that are adjusted by off-chip external resistors. The SSM2529 can accept a variety of input MCLK frequencies and can use BCLK as the clock source in some configurations. An integrated PLL can also provide the device master clock. The integrated DSP includes soft digital volume control circuits; a de-emphasis, high-pass filter; a seven-band programmable equalizer; and a programmable digital dynamic range compressor. In addition, the part includes a feedforward speaker temperature prediction module to protect the loudspeaker. The SSM2529 supports single-supply mode, where DVDD is provided by the on-chip LDO regulator, eliminating the need for an external digital core supply. The digital interface is very flexible and convenient. It can offer a better system solution for other products whose sole audio source is digital, such as wireless speakers, laptop PCs, portable digital televisions, and navigation systems. The SSM2529 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output shortcircuit protection. It is available in a 16-ball, 1.92 mm x 1.94 mm wafer level chip scale package (WLCSP). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2012 Analog Devices, Inc. All rights reserved. SSM2529 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Serial Audio Interface and Sample Rate Control (SAI_FMT1) Register ........................................................................................ 28 General Description ......................................................................... 1 Serial Audio Interface Control (SAI_FMT2) Register .......... 29 Revision History ............................................................................... 3 Channel Mapping Control Register ......................................... 30 Functional Block Diagram .............................................................. 4 Volume Control Before FDSP (VOL_BF_FDSP) Register ... 31 Specifications..................................................................................... 5 Volume Control After FDSP (VOL_AF_FDSP) Register ..... 31 Performance Specifications ......................................................... 5 Volume and Mute Control Register ......................................... 31 Power Supply Requirements ....................................................... 6 DPLL_CTRL Register ................................................................ 32 Digital Input/Output .................................................................... 6 APLL_CTRL1 Register .............................................................. 32 Digital Interpolation Filter .......................................................... 6 APLL_CTRL2 Register .............................................................. 32 Digital Timing ............................................................................... 6 APLL_CTRL3 Register .............................................................. 32 Absolute Maximum Ratings ............................................................ 8 APLL_CTRL4 Register .............................................................. 32 Thermal Resistance ...................................................................... 8 APLL_CTRL5 Register .............................................................. 33 ESD Caution .................................................................................. 8 APLL_CTRL6 Register .............................................................. 33 Pin Configuration and Function Descriptions ............................. 9 FAULT_CTRL1 Register ........................................................... 34 Typical Performance Characteristics ........................................... 10 FAULT_CTRL2 Register ........................................................... 34 Theory of Operation ...................................................................... 14 DEEMP_CTRL Register ............................................................ 34 Overview...................................................................................... 14 HPF_CTRL Register .................................................................. 35 Master Clock ............................................................................... 14 EQ1_COEF0_HI Register ......................................................... 35 Internal Clock Generator .......................................................... 14 EQ1_COEF0_LO Register ........................................................ 35 Digital Input Serial Audio Interface......................................... 14 EQ1_COEF1_HI Register ......................................................... 35 PDM Mode Setup and Control ................................................. 15 EQ1_COEF1_LO Register ........................................................ 35 High-Pass Filter .......................................................................... 15 EQ1_COEF2_HI Register ......................................................... 36 Fully Programmable Seven-Band Equalizer............................... 15 EQ1_COEF2_LO Register ........................................................ 36 Dynamic Range Control ............................................................ 18 EQ1_COEF3_HI Register ......................................................... 36 DRC Mode Control .................................................................... 18 EQ1_COEF3_LO Register ........................................................ 36 Gain Ripple Remove .................................................................. 21 EQ1_COEF4_HI Register ......................................................... 36 Speaker Protection ..................................................................... 21 EQ1_COEF4_LO Register ........................................................ 36 Power Supplies ............................................................................ 21 EQ2_COEF0_HI Register ......................................................... 36 Power Control ............................................................................. 21 EQ2_COEF0_LO Register ........................................................ 36 Power-On Reset/Voltage Supervisor........................................ 22 EQ2_COEF1_HI Register ......................................................... 36 Standalone Mode ........................................................................ 22 EQ2_COEF1_LO Register ........................................................ 36 I2C Port......................................................................................... 22 EQ2_COEF2_HI Register ......................................................... 37 Register Summary .......................................................................... 24 EQ2_COEF2_LO Register ........................................................ 37 Register Details ............................................................................... 27 EQ2_COEF3_HI Register ......................................................... 37 Software Reset and Master Software Power-Down Control (PWR_CTRL) Register .............................................................. 27 EQ2_COEF3_LO Register ........................................................ 37 MCLK Ratio and Frequency ..................................................... 27 EQ2_COEF4_LO Register ........................................................ 37 Edge Speed and Clocking Control (SYS_CTRL) Register .... 28 EQ3_COEF0_HI Register ......................................................... 37 EQ2_COEF4_HI Register ......................................................... 37 EQ3_COEF0_LO Register ........................................................ 37 Rev. 0 | Page 2 of 52 Data Sheet SSM2529 EQ3_COEF1_HI Register ..........................................................37 EQ7_COEF1_LO Register ......................................................... 41 EQ3_COEF1_LO Register .........................................................37 EQ7_COEF2_HI Register.......................................................... 41 EQ3_COEF2_HI Register ..........................................................38 EQ7_COEF2_LO Register ......................................................... 41 EQ3_COEF2_LO Register .........................................................38 EQ_CTRL1 Register ................................................................... 42 EQ3_COEF3_HI Register ..........................................................38 EQ_CTRL2 Register ................................................................... 42 EQ3_COEF3_LO Register .........................................................38 DRC_CTRL1 Register ................................................................ 43 EQ3_COEF4_HI Register ..........................................................38 DRC_CTRL2 Register ................................................................ 43 EQ3_COEF4_LO Register .........................................................38 DRC_CTRL3 Register ................................................................ 44 EQ4_COEF0_HI Register ..........................................................38 DRC_CURVE1 Register............................................................. 44 EQ4_COEF0_LO Register .........................................................38 DRC_CURVE2 Register............................................................. 45 EQ4_COEF1_HI Register ..........................................................38 DRC_CURVE3 Register............................................................. 45 EQ4_COEF1_LO Register .........................................................38 DRC_CURVE4 Register............................................................. 45 EQ4_COEF2_HI Register ..........................................................39 DRC_CURVE5 Register............................................................. 45 EQ4_COEF2_LO Register .........................................................39 DRC_HOLD_TIME Register .................................................... 46 EQ4_COEF3_HI Register ..........................................................39 DRC_RIPPLE_CTRL Register .................................................. 46 EQ4_COEF3_LO Register .........................................................39 DRC Mode Control Register ..................................................... 46 EQ4_COEF4_HI Register ..........................................................39 FDSP_EN Register ...................................................................... 47 EQ4_COEF4_LO Register .........................................................39 SPK_PROT_EN Register ........................................................... 47 EQ5_COEF0_HI Register ..........................................................39 TEMP_AMBIENT Register....................................................... 47 EQ5_COEF0_LO Register .........................................................39 SPKR_DCR Register................................................................... 47 EQ5_COEF1_HI Register ..........................................................39 SPKR_TC Register ...................................................................... 47 EQ5_COEF1_LO Register .........................................................39 SP_CF1_H Register .................................................................... 47 EQ5_COEF2_HI Register ..........................................................40 SP_CF1_L Register ..................................................................... 47 EQ5_COEF2_LO Register .........................................................40 SP_CF2_H Register .................................................................... 47 EQ5_COEF3_HI Register ..........................................................40 SP_CF2_L Register ..................................................................... 48 EQ5_COEF3_LO Register .........................................................40 SP_CF3_H Register .................................................................... 48 EQ5_COEF4_HI Register ..........................................................40 SP_CF3_L Register ..................................................................... 48 EQ5_COEF4_LO Register .........................................................40 SP_CF4_H Register .................................................................... 48 EQ6_COEF0_HI Register ..........................................................40 SP_CF4_L Register ..................................................................... 48 EQ6_COEF0_LO Register .........................................................40 SPKR_TEMP Register ................................................................ 48 EQ6_COEF1_HI Register ..........................................................40 SPKR_TEMP_MAG Register .................................................... 48 EQ6_COEF1_LO Register .........................................................40 MAX_SPKR_TEMP Register .................................................... 48 EQ6_COEF2_HI Register ..........................................................41 SPK_GAIN Register ................................................................... 49 EQ6_COEF2_LO Register .........................................................41 SOFT_RST Register .................................................................... 49 EQ7_COEF0_HI Register ..........................................................41 Applications Information ............................................................... 50 EQ7_COEF0_LO Register .........................................................41 Outline Dimensions ........................................................................ 51 EQ7_COEF1_HI Register ..........................................................41 Ordering Guide ........................................................................... 51 REVISION HISTORY 7/12--Revision 0: Initial Version Rev. 0 | Page 3 of 52 SSM2529 Data Sheet FUNCTIONAL BLOCK DIAGRAM SCL/ SDA/ VOLUME VOLUME CONTROL A CONTROL B SDATA LRCLK BCLK DVDD GND I2S PLL VOLUME CONTROL A DIGITAL FILTERS HPF SPKVDD LDO_OUT SUPPLY DETECTOR LDO I2C MONO IDAC VOLUME CONTROL B 3+2+2 EQ (7B) -70dB TO +24dB SPKGND - CLASS-D MODULATOR (MONO) FULL BRIDGE POWER STAGE (STEREO) -70dB TO +24dB OUTP OUTN DRC CLOCKING CONTROL SPEAKER TEMPERATURE ESTIMATION POWER-ON RESET AND UVLO STDBN POP-AND-CLICK SUPPRESSION ADDR/PDM Figure 1. Rev. 0 | Page 4 of 52 SA_MODE SSM2529 10749-001 MCLK Data Sheet SSM2529 SPECIFICATIONS Standard test condition: SPKVDD = 4.2 V; DVDD = 1.8 V; fS = 48 kHz; MCLK = 128 x fS; TA = 25C; RL = 8 + 33 H; LP_MODE = 0; 0 dB volume control setting, unless otherwise noted. PERFORMANCE SPECIFICATIONS Table 1. Parameter DEVICE CHARACTERISTICS Output Power Symbol Test Conditions/Comments POUT f = 1 kHz, BW = 20 kHz RL = 4 , THD = 1%, SPKVDD = 5.0 V RL = 4 , THD = 10%, SPKVDD = 5.0 V RL = 8 , THD = 1%, SPKVDD = 5.0 V RL = 8 , THD = 10%, SPKVDD = 5.0 V RL = 4 , THD = 1%, SPKVDD = 4.2 V RL = 4 , THD = 10%, SPKVDD = 4.2 V RL = 8 , THD = 1%, SPKVDD = 4.2 V RL = 8 , THD = 10%, SPKVDD = 4.2 V RL = 4 , THD = 1%, SPKVDD = 3.6 V RL = 4 , THD = 10%, SPKVDD = 3.6 V RL = 8 , THD = 1%, SPKVDD = 3.6 V RL = 8 , THD = 10%, SPKVDD = 3.6 V RL = 4 , THD = 1%, SPKVDD = 2.5 V RL = 4 , THD = 10%, SPKVDD = 2.5 V RL = 8 , THD = 1%, SPKVDD = 2.5 V RL = 8 , THD = 10%, SPKVDD = 2.5 V POUT = 2 W into 4 , SPKVDD = 5.0 V POUT = 1.4 W into 8 , SPKVDD = 5.0 V, normal operation POUT = 1.4 W into 8 , SPKVDD = 5.0 V, ultralow EMI operation POUT = 1 W into 8 , f = 1 kHz, SPKVDD = 5.0 V Efficiency Total Harmonic Distortion Plus Noise THD + N Min POUT = 0.7 W into 8 , f = 1 kHz, SPKVDD = 4.2 V POUT = 0.5 W into 8 , f = 1 kHz, SPKVDD = 3.6 V Average Switching Frequency Differential Output Offset Voltage Power Supply Rejection Ratio fSW VOOS Supply Current PSRR (DC) PSRRGSM ISPKVDD Supply Current IDVDD Output Voltage Noise Signal-to-Noise Ratio Mute Attenuation en SNR SPKVDD = 2.5 V to 5.0 V VRIPPLE = 100 mV rms at 217 Hz, dither input Dither input, SPKVDD = 5.0 V Dither input, SPKVDD = 4.2 V Dither input, SPKVDD = 3.6 V Dither input, SPKVDD = 2.5 V Power-down Dither input, DVDD = 1.8 V Dither input, DVDD = 1.08 V Power-down f = 20 Hz to 20 kHz, dither input A-weighted reference to 0 dBFS, SPKVDD = 4.2 V Soft mute on Rev. 0 | Page 5 of 52 70 100 Typ Max Unit 2.4 3.1 1.4 1.8 1.7 2.2 0.95 1.2 1.2 1.6 0.7 0.9 0.55 0.72 0.32 0.42 91 95 86 0.03 W W W W W W W W W W W W W W W W % % % % 0.03 0.03 280 2.0 % % kHz mV 80 80 3.0 2.8 2.7 2.4 100 0.6 0.3 2 22 103 dB dB mA mA mA mA nA mA mA A V dB dB SSM2529 Data Sheet POWER SUPPLY REQUIREMENTS Table 2. Parameter SPKVDD DVDD Min 2.5 1.08 Typ 4.2 1.8 Max 5.5 1.98 Unit V V Min 0.7 x DVDD -0.3 Typ Max 3.6 +0.3 x DVDD 1 1 3 3 5 Unit V V A A A A pF Min Typ 20 Max Unit kHz dB kHz kHz dB s DIGITAL INPUT/OUTPUT Table 3. Parameter Input Voltage, High Input Voltage, Low Input Leakage Current, High Input Leakage Current, Low MCLK Input Leakage, High MCLK Input Leakage, Low Input Capacitance Symbol VIH VIL IIH IIL IIH IIL Test Conditions/Comments Excluding MCLK Excluding MCLK and bidirectional pins DIGITAL INTERPOLATION FILTER Table 4. Parameter Pass Band (-3 dB) Pass-Band Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Mode 48 kHz mode, typical at 48 kHz 48 kHz mode, typical at 48 kHz 48 kHz mode, typical at 48 kHz 48 kHz mode, typical at 48 kHz 48 kHz mode, typical at 48 kHz 48 kHz mode, typical at 48 kHz Factor 0.423 fS 0.5 fS 0.03 24 28 0.582 fS 60 14/fS 292 DIGITAL TIMING All timing specifications are given for the default setting (I2S mode) of the serial input port. Table 5. Limit Parameter MASTER CLOCK (See Figure 2) tBP tBP SERIAL PORT (See Figure 2) tBIL tBIH tLIS tLIH tSIS tSIH TMIN TMAX Unit Description 74 148 136 271 ns ns MCLK period, 256 fS mode MCLK period, 128 fS mode ns ns ns ns ns ns BCLK low pulse width BCLK high pulse width LRCLK setup; time to BCLK rising LRCLK hold; time from BCLK rising SDATA setup; time to BCLK rising SDATA hold; time from BCLK rising 40 40 10 10 10 10 Rev. 0 | Page 6 of 52 Data Sheet SSM2529 Limit Parameter I2C PORT (See Figure 3) fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT TMIN TMAX Unit Description 400 kHz s s s s ns ns ns ns ns s SCL frequency (not shown in Figure 3) SCL high SCL low Setup time, relevant for repeated start condition Hold time; after this period, the first clock is generated Data setup time SCL rise time SCL fall time SDA rise time (not shown in Figure 3) SDA fall time (not shown in Figure 3) Bus-free time; time between stop and start 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6 tBIH tBP BCLK tBIL tLIH tLIS LRCLK SDATA LEFT-JUSTIFIED MODE tSIS MSB MSB - 1 tSIH tSIS SDATA I2S-JUSTIFIED MODE MSB tSIH tSIS tSIS MSB 10749-002 SDATA RIGHT-JUSTIFIED MODE LSB tSIH tSIH Figure 2. Serial Input Port Timing tDS tSCH tSCH SDA tSCR tSCLH tSCS tSCLL tSCF tBFT START CONDITION STOP CONDITION Figure 3. I2C Port Timing Rev. 0 | Page 7 of 52 10749-003 SCL SSM2529 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 6. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter SPKVDD Supply Voltage DVDD Supply Voltage Input Voltage (Signal Source) ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating -0.3 V to +5.5 V -0.3 V to +1.98 V -0.3 V to +3.6 V 4 kV -65C to +150C -40C to +85C -65C to +165C 300C Table 7. Thermal Resistance Package Type 16-Ball, 1.92 mm x 1.94 mm WLCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 52 JA 56.1 Unit C/W Data Sheet SSM2529 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 2 1 SCL/ VOLUME CONTROL A SDA/ VOLUME CONTROL B 3 4 OUTP SPKVDD A STDBN SA_MODE ADDR/PDM DVDD LDO_OUT GND SPKGND MCLK SDATA BCLK LRCLK OUTN B C TOP VIEW (BALL SIDE DOWN) Not to Scale (SOLDER BALLS ON OPPOSITE SIDE) 10749-004 D Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin Number A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Mnemonic SCL/VOLUME CONTROL A SDA/VOLUME CONTROL B SPKVDD OUTP STDBN SA_MODE ADDR/PDM OUTN DVDD LDO_OUT GND SPKGND MCLK SDATA BCLK LRCLK Function Input Input/Output Power Output Input Input Input Output Power Power Power Power Input Input Input Input Description I2C Clock in I2C Mode/Volume Controller A in Standalone Mode I2C Data in I2C Mode/Volume Controller B in Standalone Mode 2.5 V to 5.5 V Amplifier Power Positive Output Power-Down Control; Active Low Standalone and Hardware Selection; 1 = Standalone Mode I2C Chip Address Select/Input Interface Select in Standalone Mode Negative Output Digital Power LDO Output Digital and Analog Ground Amplifier Ground Serial Audio Interface Master Clock and I2S/TDM/PDM Channel Select I2S Serial Data/PDM Data I2S Bit Clock/PDM Clock I2S Left-Right Frame Clock Rev. 0 | Page 9 of 52 SSM2529 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 8 + 33H 10 4 + 15H 10 THD + N (%) THD + N (%) 1 2.5V 0.1 3.6V 3.6V 0.1 5V 0.01 5V 0.01 0.001 0.01 0.1 1 10 POUT (W) 0.001 0.001 10749-005 0.0001 0.001 0.01 0.1 1 10 POUT (W) Figure 5. THD + N vs. Output Power into 8 , 5.0 V Gain Setting 100 2.5V 1 10749-008 100 Figure 8. THD + N vs. Output Power into 4 , 3.6 V Gain Setting 1 4 + 15H 8 + 33H 0.1 2.5V 1 THD + N (%) THD + N (%) 10 3.6V 5V 0.1 1W 500mW 0.01 0.01 0.1 1 10 POUT (W) 0.001 0.01 10749-006 0.001 0.001 10 100 Figure 9. THD + N vs. Frequency into 8 , SPKVDD = 5.0 V 100 8 + 33H 10 4 + 15H 10 THD + N (%) 2.5V 1 3.6V 0.1 1 2W 0.1 1W 0.01 0.001 0.001 0.01 0.1 1 0.01 10 POUT (W) Figure 7. THD + N vs. Output Power into 8 , 3.6 V Gain Setting 0.001 0.01 500mW 0.1 1 10 100 FREQUENCY (kHz) Figure 10. THD + N vs. Frequency into 4 , SPVKDD = 5.0 V Rev. 0 | Page 10 of 52 10749-010 5V 10749-007 THD + N (%) 1 FREQUENCY (kHz) Figure 6. THD + N vs. Output Power into 4 , 5.0 V Gain Setting 100 0.1 10749-009 250mW 0.01 Data Sheet 1 SSM2529 100 8 + 33H 4 + 15H 10 THD + N (%) THD + N (%) 0.1 500mW 125mW 1 500mW 0.1 250mW 0.01 250mW 0.01 0.1 1 10 100 FREQUENCY (kHz) 0.001 0.01 10749-011 QUIESCENT CURRENT (mA) THD + N (%) 100 3.4 10 1 1W 0.1 500mW 0.01 250mW 1 10 100 3.2 3.0 4 NO LOAD 2.8 8 2.6 2.4 2.5 10749-012 0.1 FREQUENCY (kHz) 3.0 3.5 4.0 4.5 5.0 SPKVDD (V) Figure 12. THD + N vs. Frequency into 4 , SPVKDD = 3.6 V 100 10 Figure 14. THD + N vs. Frequency into 4 , SPVKDD = 2.5 V 4 + 15H 0.001 0.01 1 FREQUENCY (kHz) Figure 11. THD + N vs. Frequency into 8 , SPVKDD = 3.6 V 100 0.1 10749-015 0.001 0.01 10749-014 125mW Figure 15. Quiescent Current (Power Stage) vs. Supply Voltage 800 8 + 33H 700 QUIESCENT CURRENT (A) 1 0.1 250mW 125mW 0.01 600 500 400 48kHz 300 24kHz 200 62.5mW 100 0.1 1 10 100 FREQUENCY (kHz) Figure 13. THD + N vs. Frequency into 8 , SPKVDD = 2.5 V 0 1.08 1.18 1.28 1.38 1.48 1.58 1.68 1.78 1.88 1.98 DVDD (V) Figure 16. Quiescent Current (Digital Core) vs. Supply Voltage Rev. 0 | Page 11 of 52 10749-017 8kHz 0.001 0.01 10749-013 THD + N (%) 10 SSM2529 2.0 Data Sheet 100 fIN = 1kHz RL = 8 + 33H 4 + 15H 5V 80 2.5V EFFICIENCY (%) OUTPUT POWER (W) 1.5 THD+N = 10% 1.0 THD+N = 1% 3.6V 60 40 0.5 3.0 3.5 4.0 4.5 5.0 SPKVDD (V) 0 10749-018 0 2.5 0 1.2 1.6 2.0 2.4 0.35 8 + 33H fIN = 1kHz RL = 4 + 15H 0.30 POWER SUPPLY CURRENT (A) 2.0 2.8 Figure 20. Efficiency vs. Output Power into 4 2.5 THD+N = 10% 1.5 THD+N = 1% 1.0 0.5 5V 3.6V 0.25 2.5V 0.20 0.15 0.10 0.05 3.0 3.5 4.0 4.5 5.0 SPKVDD (V) 0 10749-019 0 2.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 POUT (W) 10749-022 OUTPUT POWER (W) 0.8 POUT (W) Figure 17. Maximum Output Power vs. Supply Voltage, RL = 8 3.0 0.4 10749-021 20 Figure 21. Power Supply Current vs. Output Power, RL = 8 Figure 18. Maximum Output Power vs. Supply Voltage, RL = 4 0.7 100 4 + 15H 2.5V 3.6V 0.6 POWER SUPPLY CURRENT (A) 80 5V 60 40 20 0.5 5V 0.4 2.5V 0.3 0.2 0.1 0 0 0.3 0.6 0.9 1.2 POUT (W) 1.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 POUT (W) Figure 22. Power Supply Current vs. Output Power, RL = 4 Figure 19. Efficiency vs. Output Power into 8 Rev. 0 | Page 12 of 52 10749-023 8 + 33H 10749-020 EFFICIENCY (%) 3.6V Data Sheet 0 SSM2529 8 + 33H -20 -10 -20 -40 -30 PSRR (dB) -60 -80 -100 -40 -50 SPKVDD = 2.5V -60 SPKVDD = 5V -120 -70 -140 -80 -160 -90 0.1 1 10 FREQUENCY (kHz) 100 Figure 23. Output Spectrum vs. Frequency (FFT with 100 mW Output Power into 8 Load) -100 0.01 0.1 1 FREQUENCY (kHz) Figure 24. PSRR vs. Frequency Rev. 0 | Page 13 of 52 10 100 10749-025 SPKVDD = 3.6V -180 0.01 10749-024 OUTPUT SPECTRUM (dBV) 0 5V 3.6V 2.5V SSM2529 Data Sheet THEORY OF OPERATION OVERVIEW INTERNAL CLOCK GENERATOR The SSM2529 is a fully integrated, mono, digital switching audio amplifier. The SSM2529 receives digital audio inputs and produces the PDM differential switching outputs using the internal power stage. The part has built-in protections for overtemperature and overcurrent conditions. The SSM2529 also has built-in soft turn-on and soft turn-off for pop-and-click suppression. The part has programmable register control via the I2C port. The digital core clock can be derived directly from the external clock, or it can be generated using the PLL. Clocks for the DSPs, the serial ports, and the converters are derived from the core clock. The core clock rate is always an integer multiple of the sample rate used for the part. MASTER CLOCK In master mode, the built-in PLL can provide the master clock. In slave mode, the SSM2529 receives an external clock at the MCLK or BCLK input pin. The external clock must be fully synchronous with the incoming digital audio on the serial interface. The internal clock for the SSM2529 always runs at 5.6448 MHz to 8.192 MHz, depending on the input sample rate. The three options for providing the master clock to the part are as follows: Using the clock generated by the built-in PLL Using the BCLK pin Using the MCLK pin Figure 25 shows the clock generation block diagram. For the digital PLL, the source clock is selected by the DPLL_REF_SEL bits (Register 0x08), and the frequency relationship between the DPLL input and the output clock is defined by the DPLL_NDIV bit. The frequency relationship between the APLL input and output is fPLL = fIN x(R + (N/M))/X The MCLK option can use the built-in PLL or the BCLK pin to generate the internal clock as long as the clock is provided at the same rate that is required by the MCLK pin. By setting the PLLEN bit in Register 0x0E, this is enabled. In this case, there is no need to provide the master clock to the MCLK pin, which in turn saves a pin connection from the audio source. If using the MCLK pin, various multiples of the sample frequency can be used for MCLK. See Table 48 for all available options and settings. When the SSM2529 enters its power-down state, it is possible to gate this clock to further conserve system power. However, an MCLK must be present for the audio amplifier to operate. The input MCLK rate is determined by setting the MCS bits in Register 0x00. For more information, see Table 48. where R, N, M, and X are defined by the corresponding PLL registers (Register 0x09 to Register 0x0D). DIGITAL INPUT SERIAL AUDIO INTERFACE The SSM2529 includes a standard serial audio interface that is slave only. The interface is capable of receiving I2S, left justified, right justified, PCM/TDM, or PDM input formats. The number of data bits must be set when in right-justified mode only. CLOCK HIGHER THAN 8MHz 44.4kHz x 1024/ 48kHz x 1024 APLL /X x(R + N/M) CLK_IN LRCLK/BCLK x2N N = 1 TO 10 CLK_IN x 2N ANALOG PLL DIGITAL PLL Figure 25. Clock Generation Block Diagram Rev. 0 | Page 14 of 52 10749-029 * * * The clock generation block is composed of a digital PLL and an analog PLL. The analog PLL can accept input frequencies in the 8 MHz to 27 MHz range. To support lower frequencies (8 kHz to 8 MHz), the chip provides a digital PLL. It can boost the input clock frequency by 2N, where N = 1 to 10. Data Sheet SSM2529 The left or right data can be registered on either the rising or falling BCLK edge in both standalone mode or in I2C mode by setting the BCLK_EDGE bit (Register 0x03, Bit 0). 10 0 -10 When the part is in standalone mode and the PDM interface is selected, pull the MCLK pin to logic level low to register the left channel data (L data) on the rising BCLK edge, and the right channel data (R data) on the falling BCLK edge. When the MCLK pin is connected to logic high, the R data is registered on the rising BCLK edge, and the L data is registered on the falling BCLK edge. When this part is in I2C PDM mode, if BCLK_EDGE = 0, the L data is registered on the rising BCLK edge and the R data is registered on the falling BCLK edge. If BCLK_EDGE = 1, the L data is registered on the falling BCLK edge, and the R data is registered on the rising BCLK edge. Parameter tFALL tRISE tSETUP tHOLD -30 -40 -50 -60 0 100 Unit ns ns ns ns Description Clock fall time Clock rise time Data setup time Data hold time 200 300 400 500 600 R DATA D7 D6 Reserved D5 D4 D3 HPFCUT HIGH-PASS FILTER The audio processing block contains a configurable first-order, high-pass filter. When the high-pass filter is enabled, the dc values are continuously calculated and subtracted from the input signal. By setting HPFOR (Register 0x15, Bit 1), the last calculated dc value is stored. When the high-pass filter is disabled, the stored value is still subtracted from the input signal until the HPFOR is cleared to 0. The high-pass filter can work in audio mode or application mode, as configured by the HPF_CTRL register. In audio mode, the high-pass filter's 3 dB cutoff frequency is 3.7 Hz when the BIQUAD2 D2 D1 HPFOR D0 HPFEN Table 11. Bit Description of HPF_CTRL Register HPFOR Description HPF cut-off frequency selection HPF mode selection HPFEN HPF enable Settings See the Table 66 0: audio mode (cutoff frequency is 3.7 Hz) 1: application mode (cutoff frequency selectable) 0: disable 1: enable The programmable seven-band equalizer comprises five biquad filters (Band 1 to Band 5) and two first-order IIR filters (Band 6 and Band 7). Figure 28 shows the system block diagram. Figure 26. PDM Input Format BIQUAD1 1000 Table 10. HPF_CTRL Register BIQUAD3 BIQUAD4 All filter coefficients are programmable via the corresponding registers. When not all five midfrequency bands are needed, the filter bank can be configured as other filters, such as de-emphasis and notch filters. To operate as a seven-band equalizer, the two first-order IIR filters are usually configured as one low-pass shelving filter and one highpass shelving filter, and the biquad filters are configured as peak filters. By using the coefficient registers, the cutoff frequencies and peak gains of the shelving filters and the center frequencies and bandwidths of the peak filters are programmable. For frequency bands lower than 200 Hz, the low-pass shelving filter is suggested. BIQUAD5 SEVEN-BAND EQUALIZER Figure 28. System Block Diagram Rev. 0 | Page 15 of 52 FIRST ORDER IIR 1 FIRST ORDER IIR 1 10749-031 L DATA 10749-100 SDATA R DATA 900 FULLY PROGRAMMABLE SEVEN-BAND EQUALIZER tHOLD L DATA 800 Figure 27. High-Pass Filter Response from HPFCUT Adjustment BCLK tSETUP 700 FREQUENCY (kHz) Bit Name HPFCUT[3:0] Table 9. PDM Timing Parameters Limit TMIN TMAX 10 10 10 7 -20 10749-030 If the ADDR pin is tied to DVDD while in standalone mode, or the PDM_MODE bit (Register 0x01, Bit 7) is set to 1 while in I2C mode, the SSM2529 operates in PDM mode. In PDM mode, the SDATA pin receives the 1-bit PDM input to the DAC, and the BCLK pin provides the system clock for registering the input data. The PDM data input is registered directly on each clock edge. sampling rate is 48 kHz. In application mode, the 3 dB cutoff frequency varies from 50 Hz to 750 Hz, which is selected by using the HPFCUT bits (Register 0x15, Bits[5:2]). (dBFS) PDM MODE SETUP AND CONTROL SSM2529 Data Sheet Table 14. Bit Description of EQ_CTRL1 Register P0 + P1 x Z -1 + P2 x Z -2 1 - D1 x Z -1 - D2 x Z -2 The first-order IIR filter transfer function is H(z) = P0 + P1 x Z -1 1 - D1 x Z -1 In normal mode, the supported coefficients range from -4 to approximately +4. For equalizer mode, this range means that the cutoff and center frequencies can vary from 40 Hz to 12 kHz when the input sampling rate is 48 kHz, and the peak gain varies from -18 dB to +18 dB. The EQ_FORMAT bit in Register 0x54 defines the coefficient format. The default value is 0, and the corresponding format is Q3.13. Setting this bit to 1 achieves a larger coefficient range (from -8 to approximately +8), which enables a larger gain boost or decreases the range. Online coefficient update is supported. If the filter bank coefficients are updated when the EQ is operating, set the EQ_UPD bit after the coefficient is written. The coefficient update procedure requires approximately 0.05 ms to complete. The read only bit, EQ_UPDING, in the EQ_CTRL1 register represents the coefficient update status. If the system clock is removed during this period, the update procedure cannot be finished, and the EQ_UPD_CLR bit must be set to cancel this update. The filter bank can be disabled, and all seven bands can be bypassed separately to save power. The corresponding bits are EQEN and EQBP1 to EQBP7 in Register 0x55. Table 12. EQ Coefficients Registers Register Address 0x16 0x17 0x18 0x19 0x1A 0x1B ... 0x52 0x53 Register Name EQ1_COEF0_HI[15:8] EQ1_COEF0_LO[7:0] EQ1_COEF1_HI[15:8] EQ1_COEF1_LO[7:0] EQ1_COEF2_HI[15:8] EQ1_COEF2_LO[7:0] ... EQ7_COEF2_HI[15:8] EQ7_COEF2_LO[7:0] Description EQ Band 1, Coefficient 0 MSB EQ Band 1, Coefficient 0 LSB EQ Band 1, Coefficient 1 MSB EQ Band 1, Coefficient 1 LSB EQ Band 1, Coefficient 2 MSB EQ Band 1, Coefficient 2 LSB ... EQ Band 7, Coefficient 2 MSB EQ Band 7, Coefficient 2 LSB Table 13. EQ_CTRL1 Register D7 D6 D5 D4 EQ_RESERVED D3 EQ_ UPDING D2 EQ_UPD_ CLR D1 EQ_ FORMAT D0 EQ_ UPD Bit Name EQ_RESERVED EQ_UPDING Description Reserved EQ coefficient updating flag Settings EQ_UPD_CLR EQ coefficient update clear EQ_FORMAT EQ coefficient format selection EQ_UPD EQ coefficient registers update flag 0: EQ coefficients updating 1: None 0: normal operation 1: interrupt coefficient update 0: normal 1: large gain 1: update 0: none Table 15. EQ_CTRL2 Register D7 EQEN D6 EQBP7 D5 EQBP6 D4 EQBP5 D3 EQBP4 D2 EQBP3 D1 EQBP2 D0 EQBP1 Table 16. Bit Description of EQ_CTRL2 Register Bit Name EQEN Description EQ enabled EQBP7 EQ Band 7 bypass when EQ enabled EQBP6 EQ Band 6 bypass when EQ enabled EQBP5 EQ Band 5 bypass when EQ enabled EQBP4 EQ Band 4 bypass when EQ enabled EQBP3 EQ Band 3 bypass when EQ enabled EQBP2 EQ Band 2 bypass when EQ enabled EQBP1 EQ Band 1 bypass when EQ enabled Settings 0: EQ disabled 1: EQ enabled 0: no bypass 1: bypass EQ Band 7 0: no bypass 1: bypass EQ Band 6 0: no bypass 1: bypass EQ Band 5 0: no bypass 1: bypass EQ Band 4 0: no bypass 1: bypass EQ Band 3 0: no bypass 1: bypass EQ Band 2 0: no bypass 1: bypass EQ Band 1 The typical characteristic of each EQ band is shown in Figure 29 to Figure 36. 15 10 5 0 -5 -10 -15 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 10749-101 H(z) = GAIN (dBFS) The common biquad filter transfer function is Figure 29. Low-Pass Shelving Filter Frequency Response Across Bandwidth Settings Rev. 0 | Page 16 of 52 SSM2529 15 10 10 5 5 0 0 -5 -5 -10 -10 -15 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) -15 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 10749-033 GAIN (dBFS) 15 10749-032 GAIN (dBFS) Data Sheet Figure 33. Peak Filter Frequency Response Across Gain Settings Figure 30. Low-Pass Shelving Filter Frequency Response Across Gain Settings 20 15 10 10 0 GAIN (dBFS) GAIN (dBFS) 5 0 -10 -20 -30 -5 -40 -10 100k 1M 10M 100M FREQUENCY (Hz) Figure 31. Peak Filter Frequency Response with Different Center Frequencies 10 10 5 5 GAIN (dBFS) 15 -5 -10 -10 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 32. Peak Filter Frequency Response Across Bandwidth Settings 1M 10M 100M 0 -5 -15 1k 100k Figure 34. Notch Filter Response (A0 = +1982 to +2048, A1 = -2041 to +2048, Bandwidth = 251 Hz, Center Frequency = 631 Hz) 15 0 10k FREQUENCY (Hz) -15 1k 10749-103 GAIN (dBFS) -60 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 10749-104 10k 10749-102 -15 1k 10749-034 -50 Figure 35. Treble Band Frequency Response Across Bandwidth Settings Rev. 0 | Page 17 of 52 SSM2529 Data Sheet The overall DRC characteristics are illustrated in Figure 37. A number of threshold levels (referred to the input) are used, which are defined as the limiter threshold (LT), compressor threshold (CT), expander threshold (ET), noise gate threshold (NT), maximum output signal amplitude (SMAX), and minimum output signal amplitude (SMIN). The corresponding bits are DRC_LT, DRC_CT, DRC_ET, DRC_NT, DRC_SMAX, and DRC_SMIN and can be found in Register 0x59 to Register 0x5D. 15 10 GAIN (dBFS) 5 0 -5 NT ET CT LT -10 POINT1 (LT, SMAX) 1M 10M 100M FREQUENCY (Hz) SMAX LINEAR POINT2 (CT, CT) Figure 36. Treble Band Frequency Response Across Gain Settings DYNAMIC RANGE CONTROL The dynamic range control function is used to alter (usually reduce) the dynamic range of the audio signal so that a loud signal can be heard without disturbing the hearing perception, and a weak signal can still be heard. In addition, very large signals and very weak signals are usually treated with different methods to ensure the overall sound quality. The DRC functions include the following: * * * * LIMITER Limiter Compressor Expander Noise Gate COMPRESSOR POINT3 (ET, ET) EXPANDER NOISE GATE SMIN POINT4 (NT, SMIN) INPUT 10749-036 100k OUTPUT 10k 10749-035 -15 1k WITHOUT DRC WITH DRC Figure 37. DRC Input/Output Relationship DRC MODE CONTROL The DRC_EN bits in Register 0x60 control the DRC. The noise gating function can be disabled by setting the NG_EN bit in Register 0x60. The dynamic range is not altered when the signal level is in the middle. These functions can be enabled or disabled individually. Limiter If the input audio samples are large, the output is clipped at a predefined level so that the speakers are not overdriven. If the ADC power tracking function is enabled, the maximum output level is set automatically to correspond to the speaker SPKVDD power. Table 17. DRC Mode Control Register D7 VBAT_ EN D6 LIM_ SRC D5 LIM_ EN D4 COMP_ EN D3 EXP_EN D1 D0 DRC_EN Table 18. Bit Description of DRC Mode Control Register Bit Name VBAT_EN Description VBAT tracking enabled Compressor LIM_SRC Limiter source selection The compressor is used to reduce the signal dynamic range when the input level is large and within predefined boundaries. This helps reduce the loudness when the signal level is high. LIM_EN Limiter enabled COMP_EN Compressor disabled The expander is used to increase the signal dynamic range when the input signal level is small and within predefined upper and lower boundaries. This helps increase the loudness when the signal is weak. EXP_EN Expander enabled NG_EN Noise gating enabled Noise Gate DRC_EN DRC enabled Expander D2 NG_EN When the signal level is lower than a predefined threshold level, it is treated as noise. Under this condition, the output is set to zero. Rev. 0 | Page 18 of 52 Settings 0: disable 1: enable 0: peak 1: RMS 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable Data Sheet SSM2529 yR(n) DELAY GAIN SMOOTH yL(n) DELAY Figure 38. DRC Block Diagram Level Measurement The DRC level measurement includes the peak and rms value measurements. The parameters that affect the peak measurement are attack time and release time (AT and RT). The parameter that affects the rms measurement is average time (TAV). The attack time can vary from 0 ms to 1.536 sec; the release time and average time can vary from 0 ms to 24.576 sec. The corresponding bits are PEAK_ATT, PEAK_REL, and DRCLELTAV and can be found in Register 0x56 and Register 0x57. Table 19. DRC_CTRL1 Register D7 D6 D5 Reserved D4 D3 D2 D1 D0 DRCLELTAV[3:0] An example of such a static curve is given in Figure 39, which shows the input and output signal levels. The blue line shows a linear relationship where the output dynamic range is identical to the input dynamic range. The red line shows a different output dynamic range from the input. Furthermore, this curve indicates that the signal dynamic range is larger when the input signal is low. RELATIONSHIP BETWEEN INPUT AND OUTPUT WITHOUT DRC RELATIONSHIP BETWEEN INPUT AND OUTPUT WITH DRC 0 -10 -20 Description DRC rms detector average time Settings 0000: 0 ms 0001: 0.075 ms 0011: 0.30 ms (default) 1111: 24.576 sec D4 PEAK_REL[3:0] -60 -70 SMIN NT -90 -80 D3 D2 D1 PEAK_REL[3:0] Description DRC peak detector attack time DRC peak detector decay time Settings 0000: 0 ms 0001: 0.09 ms 0010: 0.19 ms 0011: 0.37 ms 0100: 0.75 ms 0101: 1.5 ms 0110: 3.0 ms 0111: 6.0 ms ... 1111: 1.536 sec 0000: 0 ms 0001: 1.5 ms 0010: 3 ms 0011: 6 ms 0100: 12 ms ... 1111: 24.576 sec ET -70 -60 -50 CT -40 -30 LT -20 -10 0 INPUT (dBFS) Figure 39. DRC Output vs. Input Figure 40 shows the gain values at various input signal levels. 0 -10 Table 22. Bit Description of DRC_CTRL2 Register Bit Name PEAK_ATT[3:0] ET -50 -100 -100 D0 DRC GAIN -20 -30 DRC GAIN (dBFS) D6 D5 PEAK_ATT[3:0] CT -90 Table 21. DRC_CTRL2 Register D7 -40 -80 Table 20. Bit Description of DRC_CTRL1 Register Bit Name DRCLELTAV[3:0] -30 SMAX 10749-038 xL(n) 10749-037 STATIC CURVE LEVEL MEASUREMENT The static curve is the DRC core function used to define the targeted input and output relationship. The role for the DRC block is to find the appropriate gain values with the various signal levels. To change the dynamic range of the original audio signal, the gain values vary with the input signal level. -40 -50 -60 -70 -80 -90 -100 -100 NT -90 -80 -70 ET -60 -50 CT -40 -30 INPUT (dBFS) LT -20 -10 0 10749-039 xR(n) Static Curve DRC OUTPUT (dBFS) Figure 38 shows a high level system block diagram of the DRC function. Figure 40. DRC Gain vs. Input DRC Static Curve Function A number of threshold levels (referred to the input) are used in Figure 39 and Figure 40; these levels are defined as the limiter threshold (LT), compressor threshold (CT), expander threshold (ET), noise gate threshold (NT), maximum output signal amplitude (SMAX), and minimum output signal amplitude (SMIN). The corresponding bits, DRC_LT, DRC_CT, DRC_ET, DRC_NT, DRC_SMAX, DRC_SMIN, can be found in Register 0x59 to Register 0x5D. Rev. 0 | Page 19 of 52 SSM2529 Data Sheet Table 23. DRC_CURVE1 Register D7 Reserved D6 D5 D4 Table 31. DRC_CURVE5 Register D3 D2 DRC_LT[6:0] D1 D0 D7 D6 D5 Reserved D4 D3 D2 D1 D0 DRC_SMIN[3:0] Table 24. Bit Description of DRC_CURVE1 Register Table 32. Bit Description of DRC_CURVE5 Register Bit Name DRC_LT[6:0] Bit Name DRC_SMIN[3:0] Description DRC limiter threshold Settings 0000000: +6 dB 0000001: +5.5 dB -0.5 dB step to 1010000: -35 dB D6 D5 D4 D3 D2 DRC_CT[6:0] D1 DRC Gain Smooth D0 Before the gain calculated by the static curve function multiplies with the input signal, smooth it to ensure that it does not change rapidly for this can lead to noise. Table 26. Bit Description of DRC_CURVE2 Register Bit Name DRC_CT[6:0] Description DRC compressor threshold Settings 0000000: +6 dB 0000001: +5.5 dB -0.5 dB step to 1010000: -35 dB The gain smooth is affected by its attack and decay time parameters. The attack time can vary from 0 ms to 1.536 sec, while the decay time can vary from 0 ms to 24.576 sec. The corresponding bits are DRC_ATT and DRC_DEC and can be found in Register 0x58. Table 27. DRC_CURVE3 Register D7 Reserved D6 D5 D4 D3 D2 DRC_SMAX[6:0] D1 Table 33. DRC_CTRL3 Register D0 D7 Table 28. Bit Description of DRC_CURVE3 Register Bit Name DRC_SMAX[6:0] Description DRC maximum output signal amplitude Settings 0000000: +6 dB 0000001: +5.5 dB -0.5 dB step to 1010000: -35 dB D6 D5 DRC_ATT[3:0] D4 D3 D6 D5 DRC_NT[3:0] D4 D3 Bit Name DRC_ATT[3:0] Description DRC attack time DRC_DEC[3:0] DRC decay time D2 D1 D0 DRC_ET[3:0] Table 30. Bit Description of DRC_CURVE4 Register Bit Name DRC_NT[3:0] DRC_ET[3:0] Description DRC noise gating threshold DRC expander threshold Settings 0000: -51 dB 0001: -54 dB -3 dB step to 1111: -96 dB 0000: -36 dB 0001: -39 dB -3 dB step to 1111: -81 dB D2 D1 D0 DRC_DEC[3:0] Table 34. Bit Description of DRC_CTRL3 Register Table 29. DRC_CURVE4 Register D7 Settings 0000: -51 dB 0001: -54 dB -3 dB step to 1111: -96 dB Table 25. DRC_CURVE2 Register D7 Reserved Description DRC minimum output signal level Rev. 0 | Page 20 of 52 Settings 0000: 0 ms 0001: 0.1 ms 0010: 0.19 ms 0011: 0.37 ms 0100: 0.75 ms 0101: 1.5 ms 0110: 3 ms 0111: 6 ms ... 1111: 1.536 sec 0000: 0 ms 0001: 1.5 ms 0010: 3 ms 0011: 6 ms 0100: 12 ms ... 1111: 24.576 sec Data Sheet SSM2529 DRC Hold Time Two types of hold time are used in the DRC. One is used in normal mode to prevent the calculated gain from increasing too quickly, and the other is used during DRC transiting from expander mode to noise gating mode to prevent the DRC from entering noise gating too quickly. The DRCHTNOR and DRCHTNG bits in Register 0x5E set which type is used. D6 D5 D4 DRCHTNG[3:0] D3 D2 D1 D0 DRCHTNOR[3:0] Table 36. Bit Description of DRC_HOLD_TIME Register Bit Name DRCHTNG[3:0] Description DRC hold time for noise gating DRCHTNOR[3:0] DRC hold time for normal operation Settings 0000: 0 ms 0001: 0.67 ms xxxx: double time 0111: 42.67 ms (default) 1111: 43.7 sec 0000: 0 ms 0001: 0.67 ms 0010: 1.33 ms 0011: 2.67 ms 0100: 5.33 ms .... 1111: 43.7 sec GAIN RIPPLE REMOVE Due to the swing of the peak/rms value detected by the level measurement, the gain to apply to the input signal has a little ripple, which leads to the modulation of the output signal. The ripple remove function suppresses this effect. The ripple threshold is defined by the DRCRRH bit in Register 0x5F. Table 37. DRC_RIPPLE_CTRL Register D7 D6 D5 D4 Reserved D3 D2 D1 D0 DRCRRH[1:0] Table 38. Bit Description of DRC_RIPPLE_CTRL Register Bit Name DRCRRH[1:0] Description DRC ripple remove threshold In this thermal model, R1, R2, C1, and C2 are temperature coefficients derived by measuring loudspeaker characteristics. They are set by the I2C control registers, Register 0x84 to Register 0x8B (SP_CF1_H, SP_CF1_L, SP_CF2_H, SP_CF2_L, SP_CF3_H, SP_CF3_L, SP_CF4_H and SP_CF4_L). Other critical parameters needed include ambient temperature, dc resistance of the loudspeaker, and temperature coefficient of the voice coil material. These parameters are set by Register 0x81 to Register 0x83 (TEMP_AMBIENT, SPKR_DCR, and SPKR_TC). Table 35. DRC_HOLD_TIME Register D7 of the loudspeaker. The temperature prediction method is based on the general thermal model of the loudspeaker. Settings 00: 0 dB 01: 0.28 dB 10: 0.47 dB 11: 0.75 dB (default) After running the thermal model by setting the speaker protection enable bit (SP_EN, Register 0x80), the speaker voice coil temperature status and speaker magnet temperature status can be obtained by an I2C reading of the SPKR_TEMP register (Register 0x8C) and the SPKR_TEMP_MAG register (Register 0x8D). The user sets the voice coil temperature threshold (maximum speaker voice coil temperature before gain reduction occurs) by using the MAX_SPKR_TEMP register (Register 0x8E). If this threshold is crossed, the output volume is reduced according to the speed set by the SP_AR bits (speaker protection gain reduction attack rate, Register 0x8F, Bits[7:4]) and the SP_RR bits (speaker protection gain reduction release rate, Register 0x8F, Bits[3:0]). POWER SUPPLIES The SSM2529 has two internal power supplies that must be provided: SPKVDD and DVDD. The SPKVDD supply powers to the full bridge power stage of the MOSFET and its associated drive, control, and protection circuitry. SPKVDD can operate from 2.5 V to 5.5 V and must be present to obtain audio output. Lowering the SPKVDD supply results in lower output power and correspondingly lower power consumption, and it does not affect audio performance. DVDD provides power to the digital logic and analog components. DVDD can operate from 1.08 V to 1.98 V, and it must be provided to write to the I2C or to obtain audio output. Lowering the supply voltage results in lower power consumption; however, it also results in lower audio performance. POWER CONTROL SPEAKER PROTECTION The IC includes a speaker temperature prediction module to protect the loudspeaker. Loudspeakers can be damaged when the voice coil overheats due to operation higher than the rated power. Typically, the thermal time constants of the loudspeakers are long, approximately 1 sec for voice coil and 60 sec for core. They can handle momentary power spikes without overheating; however, they cannot handle sustained high power. The speaker protection method used in the IC can reduce the volume when the temperature of the loudspeaker exceeds the temperature threshold set by the user while preserving the maximum power The SSM2529 includes various programmable power-down modes that are contained in the first I2C register (Register 0x00), power/ reset control. By default, the IC is set in software power-down, which is the I2C programmable master power-down. Only I2C functionality operates when in software power-down mode. The SSM2529 also contains a smart power-down feature that, when enabled, looks at the incoming digital audio. In addition, if the audio is zero for 1024 consecutive samples, regardless of sample rate, it puts the IC in a smart power-down state. In this state, all circuitry, except the I2S and I2C ports, are placed in a low power state. After a single nonzero input is received, the SSM2529 leaves this state and resumes normal operation. Rev. 0 | Page 21 of 52 SSM2529 Data Sheet POWER-ON RESET/VOLTAGE SUPERVISOR The SSM2529 includes an internal power-on reset and voltage supervisor circuit. This circuit provides an internal reset to all circuitry during initial power-up. It also monitors the power supplies to the IC, and it mutes the outputs and issues a reset when the voltages are lower than the minimum operating range. This ensures that no damage due to low voltage operation occurs and that no pops can occur under nearly any power removal conditions. STANDALONE MODE When the SA_MODE pin is pulled high, the SSM2529 can operate without any I2C control. In this mode, the automatic sample rate detection and smart power-down are always enabled. Volume Control A and Volume Control B can be controlled via the SCL and SDA pins. In standalone mode, the DRC function is disabled. The EQ and HPF are also disabled. When ADDR = 1, the input interface is PDM. Otherwise, I2S and TDM serial interface formats can be selected via MCLK. In standalone mode, the working clock is generated by the internal PLL. Table 39. Standalone Mode Pin Configuration Conventional Operation Pin SCL SDA STDBN ADDR BCLK MCLK SA_MODE = 1 Volume Control A Volume Control B 0: shutdown/mute 1: normal operation 1: PDM 0: I2S/TDM 0: 16 BCLK cycles provided by PLL 1: 32 BCLK cycles provided by PLL Clock: 32 BCLK cycles provided off chip 0: I2S (ADDR = 0) or PDM L channel (ADDR = 1) 1: TDM (ADDR = 0) or PDM R channel (ADDR = 1) I2C PORT The SSM2529 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the SSM2529 and the system I2C master controller. The SSM2529 is always a slave on the bus, meaning that it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address byte format is shown in Table 40. The address resides in the first seven bits of the I2C write. The LSB of this byte either sets a read or write operation. Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation The full byte addresses are shown in Figure 41, where the subaddresses are automatically incremented at word boundaries, and can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically after a singleword write unless a stop condition is encountered. A data transfer is always terminated by a stop condition. Both SDA and SCL must have a 2.2 k pull-up resistor on the lines connected to them. The voltage on these signal lines must not be more than 3.6 V. Table 40. I2C Address Byte Format Bit 0 0 Bit 1 1 Bit 2 1 Bit 3 0 Bit 4 1 Bit 5 0 Bit 6 0 Bit 7 R/W Addressing Initially, each device on the I2C bus is in an idle state, monitoring the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA, while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. The device address for the SSM2529 is 0x34. The ninth bit is known as the acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master writes information to the peripheral, whereas a Logic 1 means that the master reads information from the peripheral after writing the subaddress and repeating the start address. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. The timing for the I2C port is shown in Figure 3. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the SSM2529 immediately jumps to the idle condition. During an SCL high period, issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued, the SSM2529 does not issue an acknowledge and returns to the idle condition. If the highest subaddress is exceeded while in auto-increment mode, one of two actions is taken. In read mode, the SSM2529 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of the read. When the SDA line is not pulled low on the ninth clock pulse of SCL, a no acknowledge occurs. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM2529, and the part returns to the idle condition. Rev. 0 | Page 22 of 52 Data Sheet SSM2529 I2C Read and Write Operations followed by the chip address byte with the R/W bit set to 1 (read). This causes the SSM2529 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the SSM2529. Table 42 shows the timing of a single-word write operation. Every ninth clock, the SSM2529 issues an acknowledge by pulling SDA low. Table 42 to Table 45 use the abbreviations shown in Table 41. Table 43 shows the timing of a burst mode write sequence as an example where the target destination registers are two bytes. The SSM2529 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. Table 41. Symbols for Table 42 to Table 45 Symbol S P AM AS The timing of a single-word read operation is shown in Table 44. Note that the first R/W bit is 0, indicating a write operation. This is because the subaddress still needs to be written to set up the internal address. After the SSM2529 acknowledges the receipt of the subaddress, the master must issue a repeated start command Meaning Start bit Stop bit Acknowledge by master Acknowledge by slave SCK SDA R/W START BY MASTER ACK ACK FRAME 2 SUBADDRESS BYTE FRAME 1 CHIP ADDRESS BYTE SCK (CONTINUED) ACK ACK FRAME 3 DATA BYTE 1 STOP BY MASTER FRAME 4 DATA BYTE 2 10749-040 SDA (CONTINUED) Figure 41. I2C Read and Write Timing Table 42. Single-Word I2C Write Format S IC Address (7 Bits) R/W = 0 AS Subaddress (8 bits) AS Data Byte 1 (8 Bits) P Table 43. Burst Mode I2C Write Format S Chip address, R/W = 0 AS Subaddress AS Data-Word 1 AS Data-Word 2 AS ... P Table 44. Single-Word I2C Read Format S Chip address, R/W = 0 AS Subaddress AS S Chip address, R/W = 1 AS Data Byte 1 AM Data Byte N P Table 45. Burst Mode I2C Read Format S Chip address, R/W = 0 AS Subaddress AS S Chip address, R/W = 1 Rev. 0 | Page 23 of 52 AS Data-Word 1 AM ... P SSM2529 Data Sheet REGISTER SUMMARY The SSM2529 contains eighteen 8-bit registers that can be accessed via the I2C port. See Table 46 for the control register mapping. The register settings are described in detail in Table 47 through Table 159. Table 46. Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 Name PWR_CTRL SYS_CTRL SAI_FMT1 SAI_FMT2 Channel mapping control VOL_BF_FDSP VOL_AF_FDSP Volume and mute control DPLL_CTRL APLL_CTRL1 APLL_CTRL2 APLL_CTRL3 APLL_CTRL4 APLL_CTRL5 APLL_CTRL6 FAULT_CTRL1 FAULT_CTRL2 DEEMP_CTRL HPF_CTRL EQ1_COEF0_HI EQ1_COEF0_LO EQ1_COEF1_HI EQ1_COEF1_LO EQ1_COEF2_HI EQ1_COEF2_LO EQ1_COEF3_HI EQ1_COEF3_LO EQ1_COEF4_HI EQ1_COEF4_LO EQ2_COEF0_HI EQ2_COEF0_LO EQ2_COEF1_HI EQ2_COEF1_LO EQ2_COEF2_HI EQ2_COEF2_LO EQ2_COEF3_HI EQ2_COEF3_LO EQ2_COEF4_HI EQ2_COEF4_LO EQ3_COEF0_HI EQ3_COEF0_LO EQ3_COEF1_HI EQ3_COEF1_LO EQ3_COEF2_HI EQ3_COEF2_LO EQ3_COEF3_HI EQ3_COEF3_LO EQ3_COEF4_HI EQ3_COEF4_LO EQ4_COEF0_HI EQ4_COEF0_LO EQ4_COEF1_HI Bits [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 Bit 5 SYS_RST APWDN_ANA APWDN_EN PDM_MODE PDM_FS PDB_ADC SDATA_FMT LPST LR_SEL CH_SEL_R [7:0] [7:0] [7:0] CLK_LOSS_DET Bit 4 Bit 3 LP_MODE BCLK_RATE BCLK_GEN SAI LRCLK_MODE LRCLK_POL SR_AUTO DIG_VOL PDP_VOL Reserved Bit 2 MCS Bit 1 EDGE SAI_MSB SR BCLK_TDMC BCLK_EDGE CH_SEL_L PDP_VOL_ DIG_VOL_ FORCE FORCE DPLL_NDIV [7:0] Reserved DPLL_REF_SEL [7:0] M_HI [7:0] M_LO [7:0] N_HI [7:0] N_LO [7:0] Reserved R X [7:0] FSYS_DPLL DPLL_BYPASS APLL_BYPASS DPLL_LOCK APLL_LOCK PLLEN [7:0] Reserved PDB_LINE PDB_ZC CLK_LOSS OC [7:0] Reserved AR_TIME MRCV MAX_AR [7:0] Reserved DEEMP_FS [7:0] Reserved HPFCUT HPFOR [7:0] EQ1_COEF0_HI [7:0] EQ1_COEF0_LO [7:0] EQ1_COEF1_HI [7:0] EQ1_COEF1_LO [7:0] EQ1_COEF2_HI [7:0] EQ1_COEF2_LO [7:0] EQ1_COEF3_HI [7:0] EQ1_COEF3_LO [7:0] EQ1_COEF4_HI [7:0] EQ1_COEF4_LO [7:0] EQ2_COEF0_HI [7:0] EQ2_COEF0_LO [7:0] EQ2_COEF1_HI [7:0] EQ2_COEF1_LO [7:0] EQ2_COEF2_HI [7:0] EQ2_COEF2_LO [7:0] EQ2_COEF3_HI [7:0] EQ2_COEF3_LO [7:0] EQ2_COEF4_HI [7:0] EQ2_COEF4_LO [7:0] EQ3_COEF0_HI [7:0] EQ3_COEF0_LO [7:0] EQ3_COEF1_HI [7:0] EQ3_COEF1_LO [7:0] EQ3_COEF2_HI [7:0] EQ3_COEF2_LO [7:0] EQ3_COEF3_HI [7:0] EQ3_COEF3_LO [7:0] EQ3_COEF4_HI [7:0] EQ3_COEF4_LO [7:0] EQ4_COEF0_HI [7:0] EQ4_COEF0_LO [7:0] EQ4_COEF1_HI Rev. 0 | Page 24 of 52 Bit 0 SPWDN ASR ANA_GAIN Reset 0x23 0x20 0x02 0x00 0x10 RW RW RW RW RW RW 0x40 RW 0x40 RW 0x20 RW 0x00 0x00 0x00 0x00 0x00 Type 0x00 COREN 0x30 OT 0x000 ARCV 0x4C DEEMP_EN 0x00 HPFEN 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Data Sheet Hex 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 80 81 82 83 84 85 86 87 88 89 8A 8B Name EQ4_COEF1_LO EQ4_COEF2_HI EQ4_COEF2_LO EQ4_COEF3_HI EQ4_COEF3_LO EQ4_COEF4_HI EQ4_COEF4_LO EQ5_COEF0_HI EQ5_COEF0_LO EQ5_COEF1_HI EQ5_COEF1_LO EQ5_COEF2_HI EQ5_COEF2_LO EQ5_COEF3_HI EQ5_COEF3_LO EQ5_COEF4_HI EQ5_COEF4_LO EQ6_COEF0_HI EQ6_COEF0_LO EQ6_COEF1_HI EQ6_COEF1_LO EQ6_COEF2_HI EQ6_COEF2_LO EQ7_COEF0_HI EQ7_COEF0_LO EQ7_COEF1_HI EQ7_COEF1_LO EQ7_COEF2_HI EQ7_COEF2_LO EQ_CTRL1 EQ_CTRL2 DRC_CTRL1 DRC_CTRL2 DRC_CTRL3 DRC_CURVE1 DRC_CURVE2 DRC_CURVE3 DRC_CURVE4 DRC_CURVE5 DRC_HOLD_TIME DRC_RIPPLE_CTRL DRC mode control FDSP_EN SPK_PROT_EN TEMP_AMBIENT SPKR_DCR SPKR_TC SP_CF1_H SP_CF1_L SP_CF2_H SP_CF2_L SP_CF3_H SP_CF3_L SP_CF4_H SP_CF4_L SSM2529 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 EQEN EQBP7 Bit 5 EQ_RESERVED EQBP6 Reserved PEAK_ATT DRC_ATT Bit 4 Bit 3 EQ4_COEF1_LO EQ4_COEF2_HI EQ4_COEF2_LO EQ4_COEF3_HI EQ4_COEF3_LO EQ4_COEF4_HI EQ4_COEF4_LO EQ5_COEF0_HI EQ5_COEF0_LO EQ5_COEF1_HI EQ5_COEF1_LO EQ5_COEF2_HI EQ5_COEF2_LO EQ5_COEF3_HI EQ5_COEF3_LO EQ5_COEF4_HI EQ5_COEF4_LO EQ6_COEF0_HI EQ6_COEF0_LO EQ6_COEF1_HI EQ6_COEF1_LO EQ6_COEF2_HI EQ6_COEF2_LO EQ7_COEF0_HI EQ7_COEF0_LO EQ7_COEF1_HI EQ7_COEF1_LO EQ7_COEF2_HI EQ7_COEF2_LO EQ_UPDING EQBP5 EQBP4 Reserved Reserved Reserved Bit 2 Bit 0 EQ_UPD_CLR EQ_FORMAT EQ_UPD EQBP3 EQBP2 EQBP1 DRCLELTAV PEAK_REL DRC_DEC DRC_LT DRC_CT DRC_SMAX DRC_NT RESERVED DRCHTNG VBAT_EN Bit 1 LIM_SRC LIM_EN DRC_ET DRC_SMIN DRCHTNOR Reserved COMP_EN EXP_EN Reserved Reserved TEMP_AMBIENT SPKR_DCR SPKR_TC SP_CF1_H SP_CF1_L SP_CF2_H SP_CF2_L SP_CF3_H SP_CF3_L SP_CF4_H SP_CF4_L Rev. 0 | Page 25 of 52 NG_EN DRCRRH DRC_EN FDSP_EN SP_EN Reset 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x88 0x00 0x00 0x00 0x3C 0x00 0x00 0x19 0x40 0x08 0x3F 0x81 0x00 0x55 0x01 0x22 0x02 0x09 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SSM2529 Hex 8C 8D 8E 8F FF Name SPKR_TEMP SPKR_TEMP_MAG MAX_SPKR_TEMP SPK_GAIN SOFT_RST Data Sheet Bits Bit 7 [7:0] [7:0] [7:0] [7:0] [7:0] Bit 6 Bit 5 Bit 4 Bit 3 SPKR_TEMP SPKR_TEMP_MAG MAX_SPKR_TEMP SP_RR Bit 2 Bit 1 SP_AR SOFT_RST Rev. 0 | Page 26 of 52 Bit 0 Reset 0x00 0x00 0x64 0x44 0x00 RW R R RW RW W Data Sheet SSM2529 REGISTER DETAILS SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL (PWR_CTRL) REGISTER Table 47. Address: 0x00, Reset: 0x23, Name: PWR_CTRL Bits 7 Bit Name SYS_RST Settings 0 1 6 APWDN_ANA 0 1 5 APWDN_EN 0 1 4 LP_MODE 0 1 [3:1] MCS 000 001 010 011 100 101 110 111 0 SPWDN 0 1 Description Software reset Normal operation Software reset Auto power-down mode Only digital Both analog and digital Auto power-down enable Auto power-down disabled Auto power-down enabled Low power mode Normal operation Low power operation mode; DAC runs at half speed Master clock rate selection Refer to Table 48 Refer to Table 48 Refer to Table 48 Refer to Table 48 Refer to Table 48 Refer to Table 48 Not applicable Not applicable Master software power-down Normal operation Software master power-down Reset 0x0 Access RW 0x0 RW 0x1 RW 0x0 RW 0x1 RW 0x1 RW Table 48 shows the MCS bit settings available with the possible input sample rates vs. the required master clock frequency, as well as the master clock to bit clock ratio. The b110 thru b111 settings are reserved and not available to the user. MCLK RATIO AND FREQUENCY Table 48. MCS Bit Field Setting--MCLK Ratio and Frequency (N/A = Not Applicable) Input Sample Frequency, fS (kHz) 8 11.025 12 16 22.05 24 32 44.1 Ratio MCLK Ratio MCLK Ratio MCLK Ratio MCLK Ratio MCLK Ratio MCLK Ratio MCLK Ratio MCLK Setting 0 b000 768 fS 6.144 MHz N/A N/A 384 fS 6.144 MHz N/A N/A 192 fS 6.144 MHz N/A Setting 1 b001 1024 fS 8.192 MHz 512 fS 5.6448 MHz 512 fS 6.144 MHz 512 fS 8.192 MHz 256 fS 5.6448 MHz 256 fS 6.144 MHz 256 fS 8.192 MHz 128 fS 5.6448 MHz Setting 2 b010 1536 fS 12.288 MHz 1024 fS 11.2896 MHz 1024 fS 12.288 MHz 768 fS 12.288 MHz 512 fS 11.2896 MHz 512 fS 12.288 MHz 384 fS 12.288 MHz 256 fS 11.2896 MHz Setting 3 b011 2048 fS 16.384 MHz 1536 fS 16.9344 MHz 1536 fS 18.432 MHz 1024 fS 16.384 MHz 768 fS 16.9344 MHz 768 fS 18.432 MHz 512 fS 16.384 MHz 384 fS 16.9344 MHz Rev. 0 | Page 27 of 52 Setting 4 b100 3072 fS 24.576 MHz 2048 fS 22.5792 MHz 2048 fS 24.576 MHz 1536 fS 24.576 MHz 1024 fS 22.5792 MHz 1024 fS 24.576 MHz 768 fS 24.576 MHz 512 fS 22.5792 MHz Setting 5 b101 4096 fS 32.768 MHz 3072 fS 33.8688 MHz 3072 fS 38.864 MHz 2048 fS 32.768 MHz 1536 fS 33.8688 MHz 1536 fS 38.864 MHz 1024 fS 32.768 MHz 768 fS 33.8688 MHz Setting 6 b110 thru b111 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SSM2529 Input Sample Frequency, fS (kHz) 48 88.2 96 Data Sheet Ratio MCLK Ratio MCLK Ratio MCLK Setting 0 b000 N/A N/A N/A Setting 1 b001 128 fS 6.144 MHz 64 fS 5.6448 MHz 64 fS 6.144 MHz Setting 2 b010 256 fS 12.288 MHz 128 fS 11.2896 MHz 128 fS 12.288 MHz Setting 3 b011 384 fS 18.432 MHz 192 fS 16.9344 MHz 192 fS 18.432 MHz Setting 4 b100 512 fS 24.576 MHz 256 fS 22.5792 MHz 256 fS 24.576 MHz Setting 5 b101 768 fS 36.864 MHz 384 fS 33.8688 MHz 384 fS 36.864 MHz Setting 6 b110 thru b111 Reserved Reserved Reserved When using MCS = 0/64fS mode, the chip automatically operates in low power mode. EDGE SPEED AND CLOCKING CONTROL (SYS_CTRL) REGISTER Table 49. Address: 0x01, Reset: 0x20, Name: SYS_CTRL Bits 7 Bit Name PDM_MODE Settings 0 1 6 PDM_FS 0 1 5 PDB_ADC 0 1 4 BCLK_RATE 0 1 3 BCLK_GEN 0 1 [2:1] EDGE 00 01 0 ASR 0 1 Description PDM input enable Disable PDM input Enable PDM input PDM input sample rate About 3 MHz sample rate About 6 MHz sample rate ADC power down Power down Power on BCLK cycles per channel frame 32 cycles per channel 16 cycles per channel Generate BCLK internally Disabled Enabled Edge rate control Normal operation Low EMI mode operation Auto sample rate Sample rate setting determined by MCS register (Register 0x00, Bits[3:1]) Automatic sample rate detection Reset 0x0 Access RW 0x0 RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL (SAI_FMT1) REGISTER Table 50. Address: 0x02, Reset: 0x02, Name: SAI_FMT1 Bits [7:6] Bit Name SDATA_FMT Settings 00 01 10 11 [5:3] SAI 000 001 010 011 100 101 110 111 Description Serial data format I2S, BCLK delay by 1 Left justified Right justified, 24-bit data Right justified, 16-bit data Serial audio interface format Stereo I2S, left justified, right justified TDM2 TDM4 TDM8 TDM16 Mono PCM Reserved Reserved Rev. 0 | Page 28 of 52 Reset 0x0 Access RW 0x0 RW Data Sheet Bits [2:0] Bit Name SR SSM2529 Settings 000 001 010 011 100 101 110 111 Description Sample rate selection 11.025 kHz, 12 kHz 22.05 kHz, 24 kHz 44.1 kHz, 48 kHz 96 kHz 8 kHz 16 kHz 32 kHz Reserved Reset 0x2 Access RW Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW SERIAL AUDIO INTERFACE CONTROL (SAI_FMT2) REGISTER Table 51. Address: 0x03, Reset: 0x00, Name: SAI_FMT2 Bits 7 Bit Name LPST Settings 0 1 [6:5] LR_SEL 00 01 10 11 4 LRCLK_MODE 0 1 3 LRCLK_POL 0 1 2 SAI_MSB 0 1 1 BCLK_TDMC 0 1 0 BCLK_EDGE 0 1 Description Small power stage enable Disabled Enabled L/R channel selector Select left channel Select right channel Select (left + right)/2 Select (left - right)/2 LRCLK mode selection for TDM operation 50% duty cycle LRCLK Pulse mode LRCLK LRCLK polarity control Normal LRCLK operation Inverted LRCLK operation SDATA bit stream order MSB first SDATA LSB first SDATA BCLK cycles per frame in TDM modes select 32 BCLK cycles per slot 16 BCLK cycles per slot BCLK active edge select Rising BCLK edge used (if PDM_MODE = 1, L data is registered on the rising edge, and R data is registered on the falling edge) Falling BCLK edge used (if PDM_MODE = 1, R data is registered on the rising edge, and L data is registered on the falling edge) Rev. 0 | Page 29 of 52 SSM2529 Data Sheet CHANNEL MAPPING CONTROL REGISTER Table 52. Address: 0x04, Reset: 0x10, Name: Channel Mapping Control Bits [7:4] Bit Name CH_SEL_R Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] CH_SEL_L 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Right channel mapping select Channel 0 from SAI to right output Channel 1 from SAI to right output Channel 2 from SAI to right output Channel 3 from SAI to right output Channel 4 from SAI to right output Channel 5 from SAI to right output Channel 6 from SAI to right output Channel 7 from SAI to right output Channel 8 from SAI to right output Channel 9 from SAI to right output Channel 10 from SAI to right output Channel 11 from SAI to right output Channel 12 from SAI to right output Channel 13 from SAI to right output Channel 14 from SAI to right output Channel 15 from SAI to right output Left channel mapping select Channel 0 from SAI to left output Channel 1 from SAI to left output Channel 2 from SAI to left output Channel 3 from SAI to left output Channel 4 from SAI to left output Channel 5 from SAI to left output Channel 6 from SAI to left output Channel 7 from SAI to left output Channel 8 from SAI to left output Channel 9 from SAI to left output Channel 10 from SAI to left output Channel 11 from SAI to left output Channel 12 from SAI to left output Channel 13 from SAI to left output Channel 14 from SAI to left output Channel 15 from SAI to left output Rev. 0 | Page 30 of 52 Reset 0x1 Access RW 0x0 RW Data Sheet SSM2529 VOLUME CONTROL BEFORE FDSP (VOL_BF_FDSP) REGISTER Table 53. Address: 0x05, Reset: 0x40, Name: VOL_BF_FDSP Bits [7:0] Bit Name DIG_VOL Settings 00000000 00000001 00000010 00000011 00000100 00000101 00111111 01000000 01000001 01000010 11111101 11111110 11111111 Description Volume control before FDSP +24 dB +23.625 dB +23.35 dB +22.875 dB +22.5 dB ... +0.375 dB 0 dB -0.375 dB ... -70.875 dB -71.25 dB Mute Reset 0x40 Access RW Reset 0x40 Access RW VOLUME CONTROL AFTER FDSP (VOL_AF_FDSP) REGISTER Table 54. Address: 0x06, Reset: 0x40, Name: VOL_AF_FDSP Bits [7:0] Bit Name PDP_VOL Settings 00000000 00000001 00000010 00000011 00000100 00000101 00111111 01000000 01000001 01000010 11111101 11111110 11111111 Description Volume control after FDSP +24 dB +23.625 dB +23.35 dB +22.875 dB +22.5 dB ... +0.375 dB 0 dB -0.375 dB ... -70.875 dB -71.25 dB Mute VOLUME AND MUTE CONTROL REGISTER Table 55. Address: 0x07, Reset: 0x20, Name: Volume and Mute Control Bits 7 Bit Name CLK_LOSS_DET Settings 0 1 [6:4] SR_AUTO 000 001 010 011 100 101 110 111 3 Reserved Description Clock loss detect enable Clock loss detect disabled Clock loss detect enabled Auto detected sample rate 11.025 kHz/12 kHz 22.05 kHz/24 kHz 44.1 kHz/48 kHz 96 kHz 8 kHz 16 kHz 32 kHz Wrong sample rate Reserved Reset 0x0 Access RW 0x2 R 0x0 RW Rev. 0 | Page 31 of 52 SSM2529 Bits 2 Bit Name PDP_VOL_FORCE Data Sheet Settings 0 1 1 DIG_VOL_FORCE 0 1 0 ANA_GAIN 0 1 Description PDP volume fade enable Soft (default) Force DIG volume fade enable Soft (default) Force Analog gain control 3.6 V gain 5 V gain Reset 0x0 Access RW 0x0 RW 0x0 RW DPLL_CTRL REGISTER Table 56. Address: 0x08, Reset: 0x00, Name: DPLL_CTRL Bits 7 [6:4] Bit Name Reserved DPLL_REF_SEL Settings 000 001 010 [3:0] DPLL_NDIV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Description Reserved DPLL source clock selection Select MCLK as DPLL reference clock Select BCLK as DPLL reference clock Select LRCLK as DPLL reference clock DPLL output clock frequency Reference clock frequency x 1 Reference clock frequency x 1024 Reference clock frequency x 512 Reference clock frequency x 256 Reference clock frequency x 128 Reference clock frequency x 64 Reference clock frequency x 32 Reference clock frequency x 16 Reference clock frequency x 8 Reference clock frequency x 4 Reference clock frequency x 2 Reset 0x0 0x0 Access RW RW 0x0 RW APLL_CTRL1 REGISTER Table 57. Address: 0x09, Reset: 0x00, Name: APLL_CTRL1 Bits [7:0] Bit Name M_HI Description Denominator (M) of the fractional APLL upper byte Reset 0x00 Access RW Reset 0x00 Access RW APLL_CTRL2 REGISTER Table 58. Address: 0x0A, Reset: 0x00, Name: APLL_CTRL2 Bits [7:0] Bit Name M_LO Description Denominator (M) of the fractional APLL lower byte APLL_CTRL3 REGISTER Table 59. Address: 0x0B, Reset: 0x00, Name: APLL_CTRL3 Bits [7:0] Bit Name N_HI Description Numerator (N) of the fractional APLL upper byte Reset 0x00 Access RW Reset 0x00 Access RW APLL_CTRL4 REGISTER Table 60. Address: 0x0C, Reset: 0x00, Name: APLL_CTRL4 Bits [7:0] Bit Name N_LO Description Numerator (N) of the fractional APLL lower byte Rev. 0 | Page 32 of 52 Data Sheet SSM2529 APLL_CTRL5 REGISTER Table 61. Address: 0x0D, Reset: 0x00, Name: APLL_CTRL5 Bits 7 [6:3] Bit Name Reserved R Settings 0010 0011 0100 0101 0110 0111 1000 [2:1] X 00 01 10 11 0 Type 0 1 Description Reserved Integer part of APLL R=2 R=3 R=4 R=5 R=6 R=7 R=8 APLL input clock divider X=1 X=2 X=3 X=4 APLL operation mode Integer Fractional APLL_CTRL6 REGISTER Table 62. Address: 0x0E, Reset: 0x30, Name: APLL_CTRL6 Bits [7:6] 5 4 3 2 1 0 Bit Name FSYS_DPLL Settings Description 00 01 10 11 Analog OSC Clock Rate 1 Analog OSC Clock Rate 2 Analog OSC Clock Rate 3 Analog OSC Clock Rate 4 0 1 Enable DPLL Bypass DPLL (default) 0 1 Enable APLL Bypass APLL (default) 0 1 DPLL not locked DPLL locked 0 1 APLL not locked APLL locked 0 1 Disable internal PLL (default) Enable internal PLL Core clock enable Core clock disable (default) Core clock enable DPLL_BYPASS APLL_BYPASS DPLL_LOCK APLL_LOCK PLLEN COREN 0 1 Reset 0x0 Access RW 0x1 RW 0x1 RW 0x0 R 0x0 R 0x0 RW 0x0 RW Rev. 0 | Page 33 of 52 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW SSM2529 Data Sheet FAULT_CTRL1 REGISTER Table 63. Address: 0x0F, Reset: 0x00, Name: FAULT_CTRL1 Bits [7:5] 4 Bit Name Reserved PDB_LINE Settings Single end lineout enable Disabled Enabled Lineout calibration enable Disabled Enabled Clock for DAC and Class-D lost Normal operation Loss of clock signal Right channel overcurrent fault Normal operation Right channel overcurrent fault Overtemperture fault status Normal operation Overtemperature fault 0 1 3 PDB_ZC 0 1 2 CLK_LOSS 0 1 1 OC 0 1 0 Description OT 0 1 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 R 0x0 R 0x0 R FAULT_CTRL2 REGISTER Table 64. Address: 0x10, Reset: 0x4C, Name: FAULT_CTRL2 Bits 7 [6:5] Bit Name Reserved AR_TIME Settings 00 01 10 11 4 MRCV [3:2] MAX_AR 1 00 01 10 11 [1:0] ARCV 00 01 10 11 Description Auto recovery time 10 ms auto fault recovery delay 20 ms auto fault recovery delay 40 ms auto fault recovery delay 80 ms auto fault recovery delay Manual fault recovery Writing of 1 causes a manual fault recovery attempt when ARCV = 11 Maximum fault recovery attempts 1 auto recovery attempt 3 auto recovery attempts 7 auto recovery attempts Unlimited auto recovery attempts Auto fault recovery control Auto fault recovery for overtemperature and overcurrent faults Auto fault recovery for overtemperature fault only Auto fault recovery for overcurrent fault only No auto fault recovery Reset 0x0 0x2 Access RW RW 0x0 RW 0x3 RW 0x0 RW Reset 0x00 0x0 Access RW RW 0x0 RW DEEMP_CTRL REGISTER Table 65. Address: 0x14, Reset: 0x00, Name: DEEMP_CTRL Bits [7:3] [2:1] Bit Name Reserved DEEMP_FS Settings 00 01 10 11 0 DEEMP_EN 1 0 Description De-emphasis sample rate selection Set coefficients to all zero 48 kHz 44.1 kHz 32 kHz De-emphasis enable De-emphasis filter enable De-emphasis filter disable Rev. 0 | Page 34 of 52 Data Sheet SSM2529 HPF_CTRL REGISTER Table 66. Address: 0x15, Reset: 0x00, Name: HPF_CTRL Bits [7:6] [5:2] Bit Name Reserved HPFCUT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 HPFOR 0 1 0 HPFEN 0 1 Description High-pass filter 3 dB cutoff frequency 3.7 Hz (default) 50 Hz 100 Hz 150 Hz 200 Hz 250 Hz 300 Hz 350 Hz 400 Hz 450 Hz 500 Hz 550 Hz 600 Hz 650 Hz 700 Hz 750 Hz Store/clear high-pass filter dc value when HPF disabled Clear dc value Store dc value High-pass filter enabled HPF disabled (default) HPF enabled Reset 0x0 0x00 Access RW RW 0x0 RW 0x0 RW EQ1_COEF0_HI REGISTER Table 67. Address: 0x16, Reset: 0x00, Name: EQ1_COEF0_HI Bits [7:0] Bit Name EQ1_COEF0_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ1_COEF0_LO REGISTER Table 68. Address: 0x17, Reset: 0x00, Name: EQ1_COEF0_LO Bits [7:0] Bit Name EQ1_COEF0_LO Description EQ coefficient EQ1_COEF1_HI REGISTER Table 69. Address: 0x18, Reset: 0x00, Name: EQ1_COEF1_HI Bits [7:0] Bit Name EQ1_COEF1_HI Description EQ coefficient EQ1_COEF1_LO REGISTER Table 70. Address: 0x19, Reset: 0x00, Name: EQ1_COEF1_LO Bits [7:0] Bit Name EQ1_COEF1_LO Description EQ coefficient Rev. 0 | Page 35 of 52 SSM2529 Data Sheet EQ1_COEF2_HI REGISTER Table 71. Address: 0x1A, Reset: 0x00, Name: EQ1_COEF2_HI Bits [7:0] Bit Name EQ1_COEF2_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ1_COEF2_LO REGISTER Table 72. Address: 0x1B, Reset: 0x00, Name: EQ1_COEF2_LO Bits [7:0] Bit Name EQ1_COEF2_LO Description EQ coefficient EQ1_COEF3_HI REGISTER Table 73. Address: 0x1C, Reset: 0x00, Name: EQ1_COEF3_HI Bits [7:0] Bit Name EQ1_COEF3_HI Description EQ coefficient EQ1_COEF3_LO REGISTER Table 74. Address: 0x1D, Reset: 0x00, Name: EQ1_COEF3_LO Bits [7:0] Bit Name EQ1_COEF3_LO Description EQ coefficient EQ1_COEF4_HI REGISTER Table 75. Address: 0x1E, Reset: 0x00, Name: EQ1_COEF4_HI Bits [7:0] Bit Name EQ1_COEF4_HI Description EQ coefficient EQ1_COEF4_LO REGISTER Table 76. Address: 0x1F, Reset: 0x00, Name: EQ1_COEF4_LO Bits [7:0] Bit Name EQ1_COEF4_LO Description EQ coefficient EQ2_COEF0_HI REGISTER Table 77. Address: 0x20, Reset: 0x00, Name: EQ2_COEF0_HI Bits [7:0] Bit Name EQ2_COEF0_HI Description EQ coefficient EQ2_COEF0_LO REGISTER Table 78. Address: 0x21, Reset: 0x00, Name: EQ2_COEF0_LO Bits [7:0] Bit Name EQ2_COEF0_LO Description EQ coefficient EQ2_COEF1_HI REGISTER Table 79. Address: 0x22, Reset: 0x00, Name: EQ2_COEF1_HI Bits [7:0] Bit Name EQ2_COEF1_HI Description EQ coefficient EQ2_COEF1_LO REGISTER Table 80. Address: 0x23, Reset: 0x00, Name: EQ2_COEF1_LO Bits [7:0] Bit Name EQ2_COEF1_LO Description EQ coefficient Rev. 0 | Page 36 of 52 Data Sheet SSM2529 EQ2_COEF2_HI REGISTER Table 81. Address: 0x24, Reset: 0x00, Name: EQ2_COEF2_HI Bits [7:0] Bit Name EQ2_COEF2_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ2_COEF2_LO REGISTER Table 82. Address: 0x25, Reset: 0x00, Name: EQ2_COEF2_LO Bits [7:0] Bit Name EQ2_COEF2_LO Description EQ coefficient EQ2_COEF3_HI REGISTER Table 83. Address: 0x26, Reset: 0x00, Name: EQ2_COEF3_HI Bits [7:0] Bit Name EQ2_COEF3_HI Description EQ coefficient EQ2_COEF3_LO REGISTER Table 84. Address: 0x27, Reset: 0x00, Name: EQ2_COEF3_LO Bits [7:0] Bit Name EQ2_COEF3_LO Description EQ coefficient EQ2_COEF4_HI REGISTER Table 85. Address: 0x28, Reset: 0x00, Name: EQ2_COEF4_HI Bits [7:0] Bit Name EQ2_COEF4_HI Description EQ coefficient EQ2_COEF4_LO REGISTER Table 86. Address: 0x29, Reset: 0x00, Name: EQ2_COEF4_LO Bits [7:0] Bit Name EQ2_COEF4_LO Description EQ coefficient EQ3_COEF0_HI REGISTER Table 87. Address: 0x2A, Reset: 0x00, Name: EQ3_COEF0_HI Bits [7:0] Bit Name EQ3_COEF0_HI Description EQ coefficient EQ3_COEF0_LO REGISTER Table 88. Address: 0x2B, Reset: 0x00, Name: EQ3_COEF0_LO Bits [7:0] Bit Name EQ3_COEF0_LO Description EQ coefficient EQ3_COEF1_HI REGISTER Table 89. Address: 0x2C, Reset: 0x00, Name: EQ3_COEF1_HI Bits [7:0] Bit Name EQ3_COEF1_HI Description EQ coefficient EQ3_COEF1_LO REGISTER Table 90. Address: 0x2D, Reset: 0x00, Name: EQ3_COEF1_LO Bits [7:0] Bit Name EQ3_COEF1_LO Description EQ coefficient Rev. 0 | Page 37 of 52 SSM2529 Data Sheet EQ3_COEF2_HI REGISTER Table 91. Address: 0x2E, Reset: 0x00, Name: EQ3_COEF2_HI Bits [7:0] Bit Name EQ3_COEF2_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ3_COEF2_LO REGISTER Table 92. Address: 0x2F, Reset: 0x00, Name: EQ3_COEF2_LO Bits [7:0] Bit Name EQ3_COEF2_LO Description EQ coefficient EQ3_COEF3_HI REGISTER Table 93. Address: 0x30, Reset: 0x00, Name: EQ3_COEF3_HI Bits [7:0] Bit Name EQ3_COEF3_HI Description EQ coefficient EQ3_COEF3_LO REGISTER Table 94. Address: 0x31, Reset: 0x00, Name: EQ3_COEF3_LO Bits [7:0] Bit Name EQ3_COEF3_LO Description EQ coefficient EQ3_COEF4_HI REGISTER Table 95. Address: 0x32, Reset: 0x00, Name: EQ3_COEF4_HI Bits [7:0] Bit Name EQ3_COEF4_HI Description EQ coefficient EQ3_COEF4_LO REGISTER Table 96. Address: 0x33, Reset: 0x00, Name: EQ3_COEF4_LO Bits [7:0] Bit Name EQ3_COEF4_LO Description EQ coefficient EQ4_COEF0_HI REGISTER Table 97. Address: 0x34, Reset: 0x00, Name: EQ4_COEF0_HI Bits [7:0] Bit Name EQ4_COEF0_HI Description EQ coefficient EQ4_COEF0_LO REGISTER Table 98. Address: 0x35, Reset: 0x00, Name: EQ4_COEF0_LO Bits [7:0] Bit Name EQ4_COEF0_LO Description EQ coefficient EQ4_COEF1_HI REGISTER Table 99. Address: 0x36, Reset: 0x00, Name: EQ4_COEF1_HI Bits [7:0] Bit Name EQ4_COEF1_HI Description EQ coefficient EQ4_COEF1_LO REGISTER Table 100. Address: 0x37, Reset: 0x00, Name: EQ4_COEF1_LO Bits [7:0] Bit Name EQ4_COEF1_LO Description EQ coefficient Rev. 0 | Page 38 of 52 Data Sheet SSM2529 EQ4_COEF2_HI REGISTER Table 101. Address: 0x38, Reset: 0x00, Name: EQ4_COEF2_HI Bits [7:0] Bit Name EQ4_COEF2_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ4_COEF2_LO REGISTER Table 102. Address: 0x39, Reset: 0x00, Name: EQ4_COEF2_LO Bits [7:0] Bit Name EQ4_COEF2_LO Description EQ coefficient EQ4_COEF3_HI REGISTER Table 103. Address: 0x3A, Reset: 0x00, Name: EQ4_COEF3_HI Bits [7:0] Bit Name EQ4_COEF3_HI Description EQ coefficient EQ4_COEF3_LO REGISTER Table 104. Address: 0x3B, Reset: 0x00, Name: EQ4_COEF3_LO Bits [7:0] Bit Name EQ4_COEF3_LO Description EQ coefficient EQ4_COEF4_HI REGISTER Table 105. Address: 0x3C, Reset: 0x00, Name: EQ4_COEF4_HI Bits [7:0] Bit Name EQ4_COEF4_HI Description EQ coefficient EQ4_COEF4_LO REGISTER Table 106. Address: 0x3D, Reset: 0x00, Name: EQ4_COEF4_LO Bits [7:0] Bit Name EQ4_COEF4_LO Description EQ coefficient EQ5_COEF0_HI REGISTER Table 107. Address: 0x3E, Reset: 0x00, Name: EQ5_COEF0_HI Bits [7:0] Bit Name EQ5_COEF0_HI Description EQ coefficient EQ5_COEF0_LO REGISTER Table 108. Address: 0x3F, Reset: 0x00, Name: EQ5_COEF0_LO Bits [7:0] Bit Name EQ5_COEF0_LO Description EQ coefficient EQ5_COEF1_HI REGISTER Table 109. Address: 0x40, Reset: 0x00, Name: EQ5_COEF1_HI Bits [7:0] Bit Name EQ5_COEF1_HI Description EQ coefficient EQ5_COEF1_LO REGISTER Table 110. Address: 0x41, Reset: 0x00, Name: EQ5_COEF1_LO Bits [7:0] Bit Name EQ5_COEF1_LO Description EQ coefficient Rev. 0 | Page 39 of 52 SSM2529 Data Sheet EQ5_COEF2_HI REGISTER Table 111. Address: 0x42, Reset: 0x00, Name: EQ5_COEF2_HI Bits [7:0] Bit Name EQ5_COEF2_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ5_COEF2_LO REGISTER Table 112. Address: 0x43, Reset: 0x00, Name: EQ5_COEF2_LO Bits [7:0] Bit Name EQ5_COEF2_LO Description EQ coefficient EQ5_COEF3_HI REGISTER Table 113. Address: 0x44, Reset: 0x00, Name: EQ5_COEF3_HI Bits [7:0] Bit Name EQ5_COEF3_HI Description EQ coefficient EQ5_COEF3_LO REGISTER Table 114. Address: 0x45, Reset: 0x00, Name: EQ5_COEF3_LO Bits [7:0] Bit Name EQ5_COEF3_LO Description EQ coefficient EQ5_COEF4_HI REGISTER Table 115. Address: 0x46, Reset: 0x00, Name: EQ5_COEF4_HI Bits [7:0] Bit Name EQ5_COEF4_HI Description EQ coefficient EQ5_COEF4_LO REGISTER Table 116. Address: 0x47, Reset: 0x00, Name: EQ5_COEF4_LO Bits [7:0] Bit Name EQ5_COEF4_LO Description EQ coefficient EQ6_COEF0_HI REGISTER Table 117. Address: 0x48, Reset: 0x00, Name: EQ6_COEF0_HI Bits [7:0] Bit Name EQ6_COEF0_HI Description EQ coefficient EQ6_COEF0_LO REGISTER Table 118. Address: 0x49, Reset: 0x00, Name: EQ6_COEF0_LO Bits [7:0] Bit Name EQ6_COEF0_LO Description EQ coefficient EQ6_COEF1_HI REGISTER Table 119. Address: 0x4A, Reset: 0x00, Name: EQ6_COEF1_HI Bits [7:0] Bit Name EQ6_COEF1_HI Description EQ coefficient EQ6_COEF1_LO REGISTER Table 120. Address: 0x4B, Reset: 0x00, Name: EQ6_COEF1_LO Bits [7:0] Bit Name EQ6_COEF1_LO Description EQ coefficient Rev. 0 | Page 40 of 52 Data Sheet SSM2529 EQ6_COEF2_HI REGISTER Table 121. Address: 0x4C, Reset: 0x00, Name: EQ6_COEF2_HI Bits [7:0] Bit Name EQ6_COEF2_HI Description EQ coefficient Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ6_COEF2_LO REGISTER Table 122. Address: 0x4D, Reset: 0x00, Name: EQ6_COEF2_LO Bits [7:0] Bit Name EQ6_COEF2_LO Description EQ coefficient EQ7_COEF0_HI REGISTER Table 123. Address: 0x4E, Reset: 0x00, Name: EQ7_COEF0_HI Bits [7:0] Bit Name EQ7_COEF0_HI Description EQ coefficient EQ7_COEF0_LO REGISTER Table 124. Address: 0x4F, Reset: 0x00, Name: EQ7_COEF0_LO Bits [7:0] Bit Name EQ7_COEF0_LO Description EQ coefficient EQ7_COEF1_HI REGISTER Table 125. Address: 0x50, Reset: 0x00, Name: EQ7_COEF1_HI Bits [7:0] Bit Name EQ7_COEF1_HI Description EQ coefficient EQ7_COEF1_LO REGISTER Table 126. Address: 0x51, Reset: 0x00, Name: EQ7_COEF1_LO Bits [7:0] Bit Name EQ7_COEF1_LO Description EQ coefficient EQ7_COEF2_HI REGISTER Table 127. Address: 0x52, Reset: 0x00, Name: EQ7_COEF2_HI Bits [7:0] Bit Name EQ7_COEF2_HI Description EQ coefficient EQ7_COEF2_LO REGISTER Table 128. Address: 0x53, Reset: 0x00, Name: EQ7_COEF2_LO Bits [7:0] Bit Name EQ7_COEF2_LO Description EQ coefficient Rev. 0 | Page 41 of 52 SSM2529 Data Sheet EQ_CTRL1 REGISTER Table 129. Address: 0x54, Reset: 0x00, Name: EQ_CTRL1 Bits [7:4] 3 Bit Name EQ_RESERVED EQ_UPDING Settings Description Reserved EQ coefficient updating flag None EQ coefficients updating EQ coefficient update clear Normal operation Interrupt coefficient update EQ coefficient format selection Normal Large gain EQ coefficient registers update flag Update None 0 1 2 EQ_UPD_CLR 0 1 1 EQ_FORMAT 0 1 0 EQ_UPD 1 0 Reset 0x0 0x0 Access RW R 0x0 W 0x0 RW 0x0 R EQ_CTRL2 REGISTER Table 130. Address: 0x55, Reset: 0x00, Name: EQ_CTRL2 Bits 7 Bit Name EQEN Settings 0 1 6 EQBP7 0 1 5 EQBP6 0 1 4 EQBP5 0 1 3 EQBP4 0 1 2 EQBP3 0 1 1 EQBP2 0 1 0 EQBP1 0 1 Description EQ enable EQ disable EQ enable EQ Band 7 bypass when EQ enabled No bypass Bypass EQ Band 7 EQ Band 6 bypass when EQ enabled No bypass Bypass EQ Band 6 EQ Band 5 bypass when EQ enabled No bypass Bypass EQ Band 5 EQ Band 4 bypass when EQ enabled No bypass Bypass EQ Band 4 EQ Band 3 bypass when EQ enabled No bypass Bypass EQ Band 3 EQ Band 2 bypass when EQ enabled No bypass Bypass EQ Band 2 EQ Band 1 bypass when EQ enabled No bypass Bypass EQ Band 1 Rev. 0 | Page 42 of 52 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet SSM2529 DRC_CTRL1 REGISTER Table 131. Address: 0x56, Reset: 0x00, Name: DRC_CTRL1 Bits [7:4] [3:0] Bit Name Reserved DRCLELTAV Settings Description 0000 0001 0011 1111 DRC rms detector average time 0 ms(default) 0.075 ms 0.30 ms 24.576 sec Reset 0x0 0x0 Access RW RW DRC_CTRL2 REGISTER Table 132. Address: 0x57, Reset: 0x00, Name: DRC_CTRL2 Bits [7:4] Bit Name PEAK_ATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] PEAK_REL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC peak detector attack time setting; 16 possible values 0 ms 0.09 ms 0.19 ms 0.37 ms 0.75 ms 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC peak detector decay time setting; 16 possible values 0 ms 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Rev. 0 | Page 43 of 52 Reset 0x0 Access RW 0x0 RW SSM2529 Data Sheet DRC_CTRL3 REGISTER Table 133. Address: 0x58, Reset: 0x00, Name: DRC_CTRL3 Bits [7:4] Bit Name DRC_ATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRC_DEC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC attack time setting; 16 possible settings 0 ms 0.1 ms 0.19 ms 0.37 ms 0.75 ms 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC decay time setting; 16 possible settings 0 ms 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset 0x0 Access RW 0x0 RW Reset 0x0 0x00 Access RW RW DRC_CURVE1 REGISTER Table 134. Address: 0x59, Reset: 0x00, Name: DRC_CURVE1 Bits 7 [6:0] Bit Name Reserved DRC_LT Settings Description 0000000 0000001 xxxxxxx 1010000 DRC limiter threshold setting, relative to input, in 0.5 dB steps +6 dB +5.5 dB -0.5 dB step -35 dB Rev. 0 | Page 44 of 52 Data Sheet SSM2529 DRC_CURVE2 REGISTER Table 135. Address: 0x5A, Reset: 0x00, Name: DRC_CURVE2 Bits 7 [6:0] Bit Name Reserved DRC_CT Settings Description 0000000 0000001 xxxxxxx 1010000 DRC compressor threshold setting, relative to input in 0.5 dB steps +6 dB +5.5 dB -0.5 dB step -35 dB Reset 0x0 0x00 Access RW RW DRC_CURVE3 REGISTER Table 136. Address: 0x5B, Reset: 0x00, Name: DRC_CURVE3 Bits 7 [6:0] Bit Name Reserved DRC_SMAX Settings Description 0000000 0000001 xxxxxxx 1010000 This is the DRC maximum output signal amplitude setting. This is the maximum output level produced by the DRC and is used to indicate the upper compressor threshold. The possible settings are in 0.5 dB steps. +6 dB +5.5 dB -0.5 dB step -35 dB Reset 0x0 0x00 Access RW RW Reset 0x8 Access RW 0x8 RW DRC_CURVE4 REGISTER Table 137. Address: 0x5C, Reset: 0x88, Name: DRC_CURVE4 Bits [7:4] Bit Name DRC_NT Settings 0000 0001 xxxx 1111 [3:0] DRC_ET 0000 0001 xxxx 1111 Description DRC noise gating threshold setting, relative to input; 16 possible values in 3 dB steps -51 dB -54 dB -3 dB step -96 dB DRC expander threshold setting, relative to input; 16 possible values in 3 dB steps -36 dB -39 dB -3 dB step -81 dB DRC_CURVE5 REGISTER Table 138. Address: 0x5D, Reset: 0x00, Name: DRC_CURVE5 Bits [7:4] [3:0] Bit Name Reserved DRC_SMIN Settings Description 0000 0001 xxxx 1011 1111 DRC minimum output signal level -51 dB(default) -54 dB -3 dB step -84 dB -96 dB Rev. 0 | Page 45 of 52 Reset 0x0 0x0 Access RW RW SSM2529 Data Sheet DRC_HOLD_TIME REGISTER Table 139. Address: 0x5E, Reset: 0x00, Name: DRC_HOLD_TIME Bits [7:4] Bit Name DRCHTNG Settings 0000 0001 xxxx 0111 1111 [3:0] DRCHTNOR 0000 0001 xxxx 0111 1111 Description DRC hold time for noise gating 0 ms(default) 0.67 ms Double time 42.67 ms 43.7 sec DRC hold time for normal operation 0 ms(default) 0.67 ms Double time 42.67 ms 43.7 sec Reset 0x0 Access RW 0x0 RW DRC_RIPPLE_CTRL REGISTER Table 140. Address: 0x5F, Reset: 0x00, Name: DRC_RIPPLE_CTRL Bits [7:2] [1:0] Bit Name Reserved DRCRRH Settings Description 00 01 10 11 DRC ripple remove threshold 0 dB (default) 0.28 dB 0.47 dB 0.75 dB Reset 0x0 0x0 Access RW RW DRC MODE CONTROL REGISTER Table 141. Address: 0x60, Reset: 0x3C, Name: DRC Mode Control Bits 7 Bit Name VBAT_EN Settings 0 1 6 LIM_SRC 0 1 5 LIM_EN 0 1 4 COMP_EN 0 1 3 EXP_EN 0 1 2 NG_EN 0 1 [1:0] DRC_EN 0 1 Description VBAT tracking enable VBAT tracking disable VBAT tracking enable Limiter source selection RMS Peak Limiter enable Limiter function disabled Limiter function enabled Compressor enable Compressor function disabled Compressor function enabled Expander enable Expander function disabled Expander function enabled Noise gate enable Noise gate function disabled Noise gate function enabled DRC enable DRC disabled DRC enabled Rev. 0 | Page 46 of 52 Reset 0x0 Access RW 0x0 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x0 RW Data Sheet SSM2529 FDSP_EN REGISTER Table 142. Address: 0x61, Reset: 0x00, Name: FDSP_EN Bits [7:1] 0 Bit Name Reserved FDSP_EN Settings Description 0 1 FDSP enable Disable FDSP Enable FDSP Reset 0x00 0x0 Access RW RW Reset 0x00 0x0 Access RW RW Reset 0x19 Access RW Reset 0x40 Access RW SPK_PROT_EN REGISTER Table 143. Address: 0x80, Reset: 0x00, Name: SPK_PROT_EN Bits [7:1] 0 Bit Name Reserved SP_EN Settings Description 0 1 Speaker protection enable Speaker protection disabled (default) Speaker protection enabled TEMP_AMBIENT REGISTER Table 144. Address: 0x81, Reset: 0x19, Name: TEMP_AMBIENT Bits [7:0] Bit Name TEMP_AMBIENT Settings 0x19 0x20 Description Ambient temperature in degrees Celsius (8.0 integer format) 25C (default) 32C SPKR_DCR REGISTER Table 145. Address: 0x82, Reset: 0x40, Name: SPKR_DCR Bits [7:0] Bit Name SPKR_DCR Settings 0x34 0x40 Description Nominal speaker dc resistance in ohms (5.3 unsigned format) 6.5 8 (default) SPKR_TC REGISTER Table 146. Address: 0x83, Reset: 0x08, Name: SPKR_TC Bits [7:0] Bit Name SPKR_TC Settings 0x08 0x0A Description Nominal speaker temperature coefficient, rise in ohms per degrees Celsius (0.8 fractional format). 0.033 /C (default) 0.04 /C Reset 0x08 Access RW SP_CF1_H REGISTER Table 147. Address: 0x84, Reset: 0x3F, Name: SP_CF1_H Bits [7:0] Bit Name SP_CF1_H Settings Default Description Speaker Temperature Model Coefficient 1, Bits[15:8] in 0.8 fractional format Reset 0x3F Access RW Reset 0x81 Access RW Reset 0x00 Access RW SP_CF1_L REGISTER Table 148. Address: 0x85, Reset: 0x81, Name: SP_CF1_L Bits [7:0] Bit Name SP_CF1_L Settings Default Description Speaker Temperature Model Coefficient 1, Bits[7:0] in 0.8 fractional format SP_CF2_H REGISTER Table 149. Address: 0x86, Reset: 0x00, Name: SP_CF2_H Bits [7:0] Bit Name SP_CF2_H Settings Default Description Speaker Temperature Model Coefficient 2, Bits[15:8] in 0.8 fractional format Rev. 0 | Page 47 of 52 SSM2529 Data Sheet SP_CF2_L REGISTER Table 150. Address: 0x87, Reset: 0x55, Name: SP_CF2_L Bits [7:0] Bit Name SP_CF2_L Settings Default Description Speaker Temperature Model Coefficient 2, Bits[7:0] in 0.8 fractional format Reset 0x55 Access RW Reset 0x01 Access RW Reset 0x22 Access RW Reset 0x02 Access RW Reset 0x09 Access RW Reset 0x00 Access R Reset 0x00 Access R Reset 0x64 Access RW SP_CF3_H REGISTER Table 151. Address: 0x88, Reset: 0x01, Name: SP_CF3_H Bits [7:0] Bit Name SP_CF3_H Settings Default Description Speaker Temperature Model Coefficient 3, Bits[15:8] in 0.8 fractional format SP_CF3_L REGISTER Table 152. Address: 0x89, Reset: 0x22, Name: SP_CF3_L Bits [7:0] Bit Name SP_CF3_L Settings Default Description Speaker Temperature Model Coefficient 3, Bits[7:0] in 0.8 fractional format SP_CF4_H REGISTER Table 153. Address: 0x8A, Reset: 0x02, Name: SP_CF4_H Bits [7:0] Bit Name SP_CF4_H Settings Default Description Speaker Temperature Model Coefficient 4, Bits[15:8] in 0.8 fractional format SP_CF4_L REGISTER Table 154. Address: 0x8B, Reset: 0x09, Name: SP_CF4_L Bits [7:0] Bit Name SP_CF4_L Settings Default Description Speaker Temperature Model Coefficient 4, Bits[7:0] in 0.8 fractional format SPKR_TEMP REGISTER Table 155. Address: 0x8C, Reset: 0x00, Name: SPKR_TEMP Bits [7:0] Bit Name SPKR_TEMP Settings 0x20 Description Speaker voice coil temperature status (8.0 integer format) 32C SPKR_TEMP_MAG REGISTER Table 156. Address: 0x8D, Reset: 0x00, Name: SPKR_TEMP_MAG Bits [7:0] Bit Name SPKR_TEMP_MAG Settings 0x20 Description Speaker magnet temperature status (8.0 integer format) 32C MAX_SPKR_TEMP REGISTER Table 157. Address: 0x8E, Reset: 0x64, Name: MAX_SPKR_TEMP Bits [7:0] Bit Name MAX_SPKR_TEMP Settings 0x64 Description Maximum speaker voice coil temperature before gain reduction occurs, 8.0 integer format 100C Rev. 0 | Page 48 of 52 Data Sheet SSM2529 SPK_GAIN REGISTER Table 158. Address: 0x8F, Reset: 0x44, Name: SPK_GAIN Bits [7:4] Bit Name SP_RR Settings 0000 0001 0010 0011 0100 0101 0110 0111 [3:0] SP_AR 0000 0001 0010 0011 0100 0101 0110 0111 Description Speaker protection gain reduction release rate 0.549 dB/s 0.275 dB/s 0.137 dB/s 0.092 dB/s 0.069 dB/s (default) 0.034 dB/s 0.017 dB/s 0.008 dB/s Speaker protection gain reduction attack rate 0.070 dB/ms 0.035 dB/ms 0.017 dB/ms 0.012 dB/ms 0.009 dB/ms (default) 0.006 dB/ms 0.004 dB/ms 0.003 dB/ms Reset 0x4 Access RW 0x4 RW SOFT_RST REGISTER Table 159. Address: 0xFF, Reset: 0x00, Name: SOFT_RST Bits [7:0] Bit Name SOFT_RST Description Write 0x00 to reset all registers Rev. 0 | Page 49 of 52 Reset 0x00 Access W SSM2529 Data Sheet APPLICATIONS INFORMATION LDO_OUT DVDD SPKVDD (1.8V) (1.08V TO 1.98V) (2.5V TO 5.5V) 100nF 10F 100nF SPKVDD DVDD LDO_OUT 1F BCLK LRCLK AUDIO PROCESSOR SDATA MCLK OUTP IOVDD (1.8V TO 3.6V) 2.2k SSM2529 2.2k OUTN SCL SYSTEM CONTROLLER SDA STDBN ADDR GND SPKGND 10749-041 SA_MODE Figure 42. Software Mode (with I2C Interface) DVDD (1.08V TO 1.98V) 100nF DVDD LDO_OUT 1F SPKVDD (2.5V TO 5.5V) 10F 100nF SPKVDD LDO_OUT (1.8V) BCLK LRCLK SDATA MCLK OUTP SSM2529 OUTN SCL SDA STDBN ADDR GND SPKGND 10749-042 SA_MODE SPKVDD Figure 43. Hardware Standalone Mode Rev. 0 | Page 50 of 52 Data Sheet SSM2529 OUTLINE DIMENSIONS 1.960 1.920 1.880 4 3 2 1 A BALL A1 IDENTIFIER 1.980 1.940 1.900 B 1.20 REF C D 0.40 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) SEATING PLANE SIDE VIEW COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 02-03-2012-A 0.560 0.500 0.440 Figure 44. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 SSM2529ACBZ-RL SSM2529ACBZ-R7 EVAL-SSM2529Z 1 Temperature Range -40C to +85C -40C to +85C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 51 of 52 Package Option CB-16-12 CB-16-12 Branding Y4D Y4D SSM2529 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10749-0-7/12(0) Rev. 0 | Page 52 of 52 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: SSM2529ACBZ-R7 SSM2529ACBZ-RL EVAL-SSM2529Z