MTK-40131 SH POTS chipset MTC-20232 CODSP MTC-30132 SH LIC Data Sheet and User Manual Rev. 1.31 - December 1998 Key features Applications Digitally programmed transmission and signalling characteristics meets world-wide specification requirements Integrated ringing, sine or trapezoid Metering injection Battery reversal Tone generators for signalling and test Minimal external components CODEC and SLIC functions for 2 lines Low-cost POTS interface for short range Standard GCI interface Advanced ISDN NT (NTplus) Analog / Digital PABX Cable Telephone systems (set-top box) Remote telephone access systems Fibre to the curb Radio in the loop Internet telephones Fig. 1: Application Sketch / Block Diagram Ordering Information Part number MTK-40131-C Includ.MTC-20232PQ-C 2x MTC-30132SO-C MTK-40131-I Includ.MTC-20232PQ-I 2x MTC-30132SO-I Package 44 pinPQFP 28 pinSO 44 pinPQFP 28 pinSO Code General Description The MTK-40131 chipset provides all the functions necessary to connect analog telephone sets or other analog terminals (telefax, answering machines, modems etc...) into digital communication systems. It provides an economical solution for the traditional `BORSHT' functions found in central-office exchanges, but optimised for shortrange communication (e.g. up to 500m with 4 RENs attached). Virtually all system-dependent parameters can be set under software control, giving a hitherto unprecedented flexibility to the system integrator, as well as optimising the system cost. The digital interface to the SH POTS chipset uses the industry-standard "GCI"* interface. The system architecture has been designed to offer the most cost-effective solution for shorthaul systems, yet offers the full flexibility required to meet world-wide analog telephony standards. Suitable for Q.552 applications. The MTK-40131 chipset comprises three devices (see fig 1.): A pair of high-voltage device, the Short-Haul Line Interface Circuit (SH LIC) which provides the signal and power interface to the analog lines (one per line) and a low-voltage CMOS, DSP-based dual CODEC/control device (CODSP) which provides all signal processing and control functions for up to two lines. Temp PQ44 0 to -70C SO28 0 to -70C PQ44 -40/+85C SO28 -40/+85C (* The General Circuit Interface (GCI) is an interface specification, developed jointly by Alcatel, Italtel, GPT and Siemens; date March 1989; issue 1.0) MTK-40131 43 42 41 40 39 38 37 36 35 ZOUT TEST TST[0] BR[0] RNG[0] PU[0] SPDI SPICS SPICK PWRS 44 JTDO SPIDO Package / Pinout GNDB 33 RX[0] 28 AW BW 2 27 SA 26 SB BAT 3 JTCK 2 32 TX[0] BATS 4 25 SSB JTMS 3 31 DCC[0] BATR 5 24 DCO JTDI 4 30 DCO[0] PU 6 23 DCI JTRS 5 29 DCC[1] NC 7 22 NC V3VD 6 28 DCO[1] NC 8 21 NC DU 7 27 GNDA RNG 9 20 DCC DD 8 26 VAG BR 10 19 TX DCL 9 25 V3VA TST 11 18 RX FSC 10 24 TX[1] VAG 12 17 DCLF1 GNDD 11 RX[1] VDDA 13 16 DCLF2 GNDA 14 15 V3V 20 SCLK 19 21 PLLCK 18 PU[1] 17 BR[1] 16 RNG[1] 15 TST[1] AD0 14 GCIM 13 AD1 AD2 44 PQFP 22 CPLL MTC-20232 CODSP Fig. 2: Device Pinouts 2 MTC-30132 SH LIC 28 PSOP MTK-40131 Table of Content Key features ...................................................................... 1 Applications ...................................................................... 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Note on Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional Characteristics of the SH POTS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-hook Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ringing Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery Voltage and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Transmission Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transmit and Receive Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Source Impedance (Zco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Balance Impedance (Echo Canceller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Off-hook Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Metering Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CODSP Clock Recovery PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 User-Defined I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Thermal Shutdown SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Transient Energy Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC Characteristics (MTC-30132 SHLIC, unless otherwise noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V3V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AW, BW DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RX, TX DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DCO DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VAG Analog Ground Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SA,SB Sense Bridge Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DCC Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Characteristics for the Digital I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Test Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Battery Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC Characteristics (SHLIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Overpower and Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 MTK-40131 Quality / Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Detailed Programming Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 C/I Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 C/I Bit Allocation:C/I Bit Allocation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ID Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory Map of the CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Global Memory Map and MemID Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CoProcessor Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SHARED Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 General dimensions of the MTC-20232PQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 General dimensions of the MTC-30132SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4 MTK-40131 List of Figures Fig. 1: Application Sketch / Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Fig. 2: Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Fig. 3: Application schematic for 2 analog lines (see Table 3 for component values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Fig. 4: MTC-20132 CODSP Recommended Power-Supply Decoupling Arrangements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Fig. 5: Recommended overvoltage protection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Fig. 6: SH POTS Line voltages - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Fig. 7: Nominal hook-switch detection thresholds (default values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Fig. 8: DC Feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Fig. 9: Transmit and receive frequency response (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Fig. 10: Relative Group delay, transmit and receive paths (Digital to Digital) refered to 1kHz . . . . . . . . . . . . . . . . . . . . . . 18 Fig. 11: 3-element Zco model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Fig. 12: Metering pulse timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Fig. 13: Application suggestion for Semi-unbalanced ringing injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Fig. 14: Block diagram showing the gains in the various signal paths in the SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Fig. 15: Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Fig. 16: GCI data exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fig. 17: GCI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 MTK-40131 List of Tables Table 1: Pin description for MTC-20232PQ CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2: Pin description for MTC-30132SO SH LIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3: Recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4: MTC-20232 CODSP unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5: MTC-30132 SH LIC unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6: Table 6: On-hook Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7: Ringing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8: DC Feed Characteristics (Rfeed = 60 total (50+10 protection) x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9: Examples of ZCO Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10: Off-hook Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11: Metering Characteristics (Determinized by MTC-20232 CODSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12: Tone signal levels (common values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13: Tone Generator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14: Tone generator division values for common frequencies from ETS-300-001, and DTMF tones . . . . . . . . . . . . . . . 24 Table 15: Required frequency setting values (N) for a melody generator (western equal-tempered scale) . . . . . . . . . . . . . . 25 Table 16: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 18: SHLIC Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19: Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 20: Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 21: V3V Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 22: Voltage Characteristics A Wire, B Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 23: Impedance Characteristics A Wire, B Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 24: RX, TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25: DCO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 26: VAG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 27: Sense Bridge Inputs Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 28: DC Loop Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 29: DCC Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 30: Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 31: Test Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 32: Ringing Battery Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 33: Typical Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 34: Short Circuit Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 35: GCI Mode and Timeslot address programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 36: GCI Interface: Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 37: Memory Map for CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 38: Data RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 39: LBO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 40: Data RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 41: Coprocessor Coefficient RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 42: Coprocessor Coefficient RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 43: Shared Memory: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 44: Shared Memory: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 MTK-40131 Pin Description Table 1: Pin description for MTC-20232PQ CODSP Pin Name Description 1 2 3 4 5 6 JTDO JTCK JTMS JTDI JTRS V3VD JTAG Test port data out JTAG Test port clock JTAG Test port mode select JTAG Test port Data In JTAG Test port reset Digital section supply voltage 7 8 9 10 11 DU DD DCL FSC GNDD GCI port upstream data GCI port downstream data GCI port data clock GCI port frame clock Digital ground (0V) 12 13 14 15 AD2 AD1 AD0 GCIM GCI port timeslot select, MSB GCI port timeslot select GCI port timeslot select, LSB GCI port operating mode (0 = 1 timeslot, 1 = 8 timeslots) 16 17 18 19 TST[1] BR[1] RNG[1] PU[1] SH LIC 1 test select SH LIC 1 Bat Reverse control SH LIC 1 Ring control SH LIC 1 Power-up control 20 21 22 SCLK PLLCK CPLL system clock (test only) PLL clock (test only) PLL loop filter capacitor 23 24 RX[1] TX[1] SH LIC 1 RX analog signal SH LIC 1 TX analog signal 25 26 27 V3VA VAG GNDA Analog supply voltage Analog ground reference voltage output Analog ground (0V) 28 29 DCO[1] DCC[1] SH LIC 1 DC loop output SH LIC 1 DC loop control 30 31 DCO[0] DCC[0] SH LIC 0 DC loop output SH LIC 0 DC loop control 32 33 TX[0] RX[0] SH LIC 0 TX analog signal SH LIC 0 RX analog signal 34 35 ZOUT TEST Digital I/O drive control (test only) Test mode select (test only) 36 37 38 39 TST[0] BR[0] RNG[0] PU[0] SH LIC 0 test select SH LIC 0 Bat Reverse control SH LIC 0 Ring control SH LIC 0 Power-up control 40 41 42 43 SPIDI SPICS SPICK SPIDO SPI port data in (User I/O) SPI port chip-select (User I/O) SPI port clock (User I/O) SPI port data out (User I/O) 44 PWRS Reset input 7 MTK-40131 Table 2: Pin description for MTC-30132SO SH LIC Pin Name Description 1 2 GNDB BW Battery ground (0V) B wire output 3 4 5 BAT BATS BATR Battery voltage (output, do not connect) Battery voltage input, SPEECH mode Battery voltage input, RING mode 6 PU Power-up control 7 8 NC NC Do not connect. Thermal conduction pin Do not connect. Thermal conduction pin 9 10 11 RNG BR TST Ring mode control Battery Reverse control Test mode control 12 13 14 15 VAG VDDA GNDA V3V Analog Ground reference input Analog supply voltage Analog Ground, 0V 3V regulator output 16 17 DCLF1 DCLF2 DC bias filter capacitor 1 DC bias filter capacitor 2 18 19 RX TX Analog receive signal Analog transmit signal 20 DCC DC loop control input 21 22 NC NC Do not connect. Thermal conduction pin Do not connect. Thermal conduction pin 23 24 DCI DCO DC loop control separation filter input DC loop control output 25 SSB Loop test resistor switch 26 27 SB SA B-wire sense input A-wire sense input 28 AW A-wire output 8 MTK-40131 Application Schematic V3VD User Outputs (optional) RNG[0] PU[0] FSC DCL 0,1 0,1 0,1 0,1 GCIM AD0 AD1 AD2 0 0 0 1 JTDI JTDO JTCK JTMS JTRS 0 0 0 0 PLLCK TEST ZOUT SCLK RX[0] TX[0] DCC[0] DCO[0] Cdci SB BW SH LIC Ztest RB2 GNDA b Cb2 Rprot BAT BATS Vbats Cs DCI BATR Dp Vbatr Dp VddA Cd GNDB DCLF2 LINE RNG PU VAG Cvag DCLF1 Rf1 Rf2 Cf2 CV3VA CV3VA V3VD D1 SSB VDDA VAG a Cb1 TST BR RX TX DCC DCO RB1 protection TST[0] BR[0] SA AW TST[1] BR[1] Rpwrs VAG PU RX[1] TX[1] RX TX Cpwrs Cdci RB1 a Cb1 SSB RNG PU[1] DCC[1] DCO[1] SA AW TST BR RNG[1] PWRS V3V Cf1 Ztest SB BW SH LIC RB2 b Cb2 Rprot BAT Vbats DCC DCO BATS DCI BATR Vbatr VDDA VddA Dp CODSP GNDB GNDA GNDD CPLL GNDA DCLF2 DCLF1 Rf1 Cpll Rf2 Cf2 Fig. 3: Application schematic for 2 analog lines (see Table 3 for component values). 9 LINE Device test SPICK V3V CV3VD protection JTAG test access V3VD DU DD GCI port GCI mode and timeslot address SPIDI SPIDO SPICS Cf1 MTK-40131 Table 3: Recommended external components Component Function Value Comment RB1, RB2 Rprot Ztest Rf1, Rf2 Feed resistor Protection resistance Test resistor DC bias filter 50 2x10 510 10k 1/4 W 1% * Cb1, Cb2 Cdci Cf1,Cf2 Cvag CV3VA CV3VD Cs, Cd Cpll No-load stabilisation DC feed separation DC bias filter Analog ground decoupling Analog 3,3V regulator decoupling Digital 3,3V decoupling Battery supply decoupling PLL loop filter 1nF 330nF 470nF 100nF 10F+100nF 10F+100nF 100nF 4.7nF 100V ** 5% 100V, 10% Cpwrs Rpws D1 Dp Power-on reset delay Power-on reset delay Power loss reset Battery input protection 100nF 100k BAT46 * 1% results in a maximum longitudinal balance of 40dB. For higher values, more precise matching is required (e.g. 0.1% for 46dB). ** Capacitors are generally not required. They are foreseen to stabilise the line driver outputs when active but driving no load (test condition only). 10 1/4 W, optional 100V Any small signal diode Required depending on the power supplies MTK-40131 Unused Pins CODSP: Pins which are not used in the application should be connected as described here. Failure to do so could result in excessive sensitivity to RFI, or other erratic behaviour. `0' or `1' indicates that the pin should be connected to ground or to the device's digital supply. `-' indicates that the pins is an output and must be left unconnected. SHLIC: The pins NC (7, 8, 21 and 22) are connected to the device substrate, which is at a voltage equal to the VBATR supply pin, and may optionally be electrically connected to this pin. The pin BAT is the internal supply to the line-drivers, and adopts the voltage of VBATR or VBATS, plus the voltage drop across the internal switch, depending on the operating mode. In low-voltage only systems (very short connections, the pins BAT, VBATR and VBATS may all be connected together, and a single supply (e.g. -27V) used for both ringing and speech modes. (In this mode, the voltage drop of the internal switches is avoided). Table 4: MTC-20232 CODSP unused pin connections Pin # Connect to SPDO 43 - GCIM AD0 AD1 AD2 15 14 13 12 0,1 (GCI mode select) 0,1 (GCI timeslot select) 0,1 (GCI timeslot select) 0,1 (GCI timeslot select) JTDI JTDO JTCK JTMS JTRS 4 1 2 3 5 0 0 0 1 SCLK PLLCK ZOUT TEST 20 21 34 35 0 0 0 0 Table 5: MTC-30132 SH LIC unused pin connections Pin # BAT NC NC NC 3 7 8 21 11 Connect to No Connect or see text below No Connect or see text below No Connect or see text below No Connect or see text below MTK-40131 Note on Decoupling As in any system, the PCB layout and supply decoupling can influence the system performance, particularly with respect to noise. CODSP: * It is recommended to connect V3VD and V3VA (digital and analog supply pins) in a star configuration from the supply (either from the SH LIC or an external supply), and each pin be independently decoupled using 10F in parallel with 100nF. In 2-line systems using the SHLIC's regulator to supply the CODSP only (i.e. no other use is made of the regulator), one SHLIC may be used to provide V3VD power and the other V3VA, thus giving improved decoupling between analog and digital supplies. See figure 4. * The VAG line (analog signal reference) must always be properly decoupled using 100nF, placed as close as possible to the CODSP device. V3VA V3V MTC-30132 SH LIC GNDB GNDA MTC-20132 CODSP GNDA Ground star-point VAG GNDA MTC-30132 SH LIC GNDD GNDB V3V V3VD +3.3V Star point MTC-30132 SH LIC GNDB GNDA V3VA MTC-20132 CODSP GNDA Ground star-point VAG MTC-30132 SH LIC GNDA GNDB GNDD V3VD SHLIC: * The SHLIC should use separate 100nF decoupling capacitors between VDD and GNDB and VDD and GNDA. When the on-board regulator of the SHLIC is not used, no capacitor is required at the V3V pin of this device. 10 F Ta 100 nF Cer Fig. 4: MTC-20132 CODSP Recommended Power-Supply Decoupling Arrangements 12 MTK-40131 Overvoltage Protection There are several recommended overvoltage protection options. The application will determine the most appropriate one to chose (e.g. in-house only systems with minimal protection requirements, or systems with loops outside a protected environment requiring more extended protection). The first external protection network to protect the line circuit against foreign voltages consists of the resistors Rpr1 and Rpr2 and an overvoltage protection component, see fig 5. The series resistors Rpr1 and Rpr2 can be PTC, poly-switch or fusible components. Rpr1 GNDB Rpr2 Rpr1 RB1 BATR RB2 RB1 GNDB Rpr2 For further protection, the simplest and cheapest solution is a diode bridge between SA,SB and GNDB, BATR respectively. The diodes must be able to allow current peaks more then 20A. In case the battery BATR cannot accept these high current peaks, one has to add a voltage clamping component to GND or a transient suppresser between each line and GND. The clamp voltage or protection voltage minimum must always be larger then the maximum used ringing battery BATR. The protection components must be dimensioned in such a way that the transient energy on the chip pins AW, BW does not exceed 1mJoule.(energy on chip because of 1 lightning pulse) SA AW Rpr1 MTC-30132 SH LIC GNDB BW SB MTC-30132 SH LIC Rpr2 SA AW RB2 Rpr1 MTC-30132 SH LIC RB2 RB1 BW SB Rpr2 Fig. 5: Recommended overvoltage protection options 13 RB1 Transient Suppressor GNDB SA AW BW SB SA AW MTC-30132 SH LIC RB2 BW SB MTK-40131 Functional Characteristics of the SH POTS System For reference, fig 6 shows the typical voltages on both wires during various stages of operation. For detailed electrical parameters, please refer to the Electrical Characteristics section. (saturation, <0.5V) (bias, 3V) (bias, 3V) 0V VbatS (e.g. -24V) (avg. DC = VbatR/2) (bias, 3V + drop of BAT switch) (bias, 3V + drop of BAT switch) VbatR (e.g. -64V) ON HOOK ON HOOK ADSI RING BURST Fig 6: SH POTS Line voltages - example. 14 OFF HOOK MTK-40131 On-hook Conditions When a line is not in use (on-hook), the designer may select either the speech battery or the ringing battery as the supply to the line drivers. In this mode, most of the internal circuits are put into a low power operating mode, to minimise supply currents. The A and B wire outputs are effectively connected to the supply voltage, thus applying this voltage (minus a small saturation voltage) to the line. The output is current limited in this mode, thus protecting against short circuits, and limiting any inrush current when a set goes off hook. If the SH LIC detects a current in excess of a (programmable) limit, the off-hook condition will be detected (an on-chip debouncer with selectable delay avoids accidental hookswitch detection), and the circuit will be put into active speech mode. The nominal off-hook detection currents, and the hysteresis, are shown in fig 7. When in the on-hook condition, the system designer may select, under program control via the GCI bus, an `on hook active mode', whereby onhook signalling (ADSI, CLI etc..) can be performed in either direction (note, however, that battery reversal is not available in this mode.). off-hook on-hook line current 6.0 6.3 8.8 10.0 10.2 mA 13.6 Fig. 7: Nominal hook-switch detection thresholds (default values) Table 6: On-hook Characteristics Parameter Conditions Min Max Units Note Vfeedo Open-line feed voltage Vbats-1 Vbatr V 4 Ion Ioff Iohyst Line current guaranteeing on-hook state Line current guaranteeing off-hook state Hookswitch detect hysteresis 5.1 8.2 2 11.1 14.2 mA mA mA 1 1 1 Thks Hookswitch detect time 20 ms 2 Ioc Peak over-current limit, on-hook mode 145 mA 3 VbiasH VbiasL Bias voltage during ADSI mode on a (H) and b (L) wires ref. BAT pin 4 V Notes: 1. These are the default values, after reset. The on-hook and off-hook thresholds can be individually programmed in the range 0 to 63mA nominal. 2. Time between off-hook condition and the line current reaching 90% of its final value. 2 3. This is the intrinsic current limit of the output driver. This current can only be seen during on-hook to off-hook transients, or during ringing into a short-circuit load during the ring-trip delay period. The actual value measured will depend on the load resitance used. 4. Iline=0mA, independent of battery reversal mode. This voltage is selected 15 by the user. The output impedance when in the on-hook condition is set by the sense resistors Rfeed. The hook-switch detector has a programmable debounce timer. Times of 8, 16, 24 or 64 ms can be selected (common for both channels). MTK-40131 Ringing Injection The SH POTS chipset is capable of directly injecting a ringing signal of up to 50Vrms (sine wave) without the need for additional external components. The technique of "balanced ringing" is used, which allows this large voltage swing to remain within the technology limits of the SH LIC device. (Balanced ringing requires a specific algorithm for ring-trip detection, which is also implemented by the chipset). The SH POTS chipset allows the user to program a DC offset during ringing as well as a reduced amplitude ringing signal, should the application require this. Ringing waveform, frequency, amplitude and cadence, as well as ringtrip thresholds, are controlled by the CODSP device, and are all programmable. Ringing cadence can be automatic, with independently programmable ring and pause times, or ringing can be controlled directly via the GCI bus. In automatic cadence mode, ringing bursts on both channels can optionally be interleaved if simultaneously active, to avoid peaks in current from the ringing battery supply. Table 7: Ringing Characteristics Parameter Conditions Min Max Units Fr -1 -2 SFNr Ringing frequency 16.66, 20, 25 Hz 50 Hz Single-frequency noise, 10 Hz to 4 kHz +1 +2 -63 Hz Hz dBm Vr Ringing voltage (max), Vbatr=-72V 50 Dr Ringing distortion, sine mode 30Hz to 132 kHz Vrms Note 4 5 % 150 30 ms ms ms 3 2 Trtd Trtdeb Trtzc Ring-trip delay, load = 500+4F Ring-trip de-bounce time Ring-trip detect zero-cross mask time 0 1.75 Tc Ring-cadence times (active and silent) 1 255 n/n 1 IrtH IrtL Hrt Ring-trip current, high threshold Ring-trip current, low threshold Ring-trip hysteresis 6.0 3.5 2 12.0 9.5 mA mA mA 2 2 2 Notes: 1. Units are periods of the selected ringing frequency. The default values are 1s on, 3s off with a ringing frequency of 50Hz. in the range 0 to 63mA(!) nominal. The ring-trip detect mask time is used to bridge the zero-crossings of the ringing signal, and is programmable between 0 and 32 ms in 125s steps. 2. These are the default values, after reset. The max and min ring-trip thresholds can be individually programmed 3. User-selectable 0 or 30ms. Default is 30 ms. 16 4. Ringing voltage is user programmable from 0 to 70Vp(diff) between the a and b wires (NB, the ringing battery voltage must be large enough to encompass this voltage), in 256 steps. The default is the maximum value. Condition: Load = O mA MTK-40131 DC Feed Characteristics As shown in figure 8, the SH POTS chip-set implements a constant-current feed. The limit current and the residual resistance (slope of the characteristic) are both programmable by the user. The DC characteristic falls into three regions. When the combination of line and subset result in a current less than the programmed limit current, the system behaves like a battery with a fixed feed resistance of 120, and a voltage equivalent to the speech supply voltage (VbatS) minus the bias voltage on both lines (6V nominal in total). Should line conditions permit a current which exceeds the programmed limit current, the system enters the constant-current feed mode described above. In order to protect the output stage in the transition region at higher line currents (in excess of 50mA), a third region is defined, where the system synthesises a fixed feed resistance of 200. The slope of the voltage/current characteristic in the constant-current mode can be user programmed to select the effective feedresistance. Note: The SH LIC device includes an over-temperature protection, which activates in case of overheating of the device. Battery Voltage and Reversal The open-line voltage (i.e. the voltage seen on the line when on-hook) is userselectable for each channel via an internal register. It can be either the ringing battery supply (most common use) or the speech battery supply. The speech battery supply is automatically selected when an off-hook condition is detected, independently of these control bits. The selected supply voltage is maintained when the on-hook signalling function (ADSI) is enabled. Iline (mA) The polarity of the line feed can be dynamically controlled by the user. In the `normal' condition, the A-Wire is the most positive. Reversal thus makes the BWire the most positive. Battery reversal is fast (not soft), is controlled by programming an internal register and is independent for both channels. The selected polarity is used in all states (onhook, off-hook, ringing etc...) except onhook signalling which is normal battery mode. Rfeed=200 Rfeed=120 (Programmable) Rfeed 80 60 40 20 VfN Vbats Vline (V) Fig 8: DC Feed characteristics. Table 8: DC Feed Characteristics (Rfeed = 60 total (50+10 protection) x2) Parameter Conditions Min Max Units VbiasH VbiasL Bias voltage, a wire (Iline=0) Bias voltage, b wire (Iline=0) 2.5 2.5 3.5 3.5 V V TOLIcl TRfeedcl Current limit tolerance Tolerance on programmed Rfeed when in current-limit 15 15 % % Icl Current-limit, useful programmed range 70 mA 20 17 Note MTK-40131 AC Transmission Characteristics (MTK-40131 System) Transmit and Receive Filter Characteristics The Short-haul POTS chipset implements transmit and receive filters according to ITU-T (G.712). These filters can be reprogrammed by the user for specific requirements. Please contact Alcatel Microelectronics for further details on this. The default filter characteristics implemented are shown in figures 9 and 10 below. -0.3 receive 12.5 1 - SIN (4000-) dB 1200 0.0 transmit receive / transmit 0.35 0.55 12.5 0.75 1.0 25.0 1.5 200 300 400 600 2400 3000 3600 3400 4000 4600 16000 Fig 9: Transmit and receive frequency response (default). Delay s 1800 1500 1200 900 600 Transmit and Receive Gain 300 frequency 0 500 600 1000 2000 2600 2800 Fig 10: Relative Group delay, transmit and receive paths (Digital to Digital) refered to 1kHz 18 Hz Transmit (from analog subset towards the switching system) and receive gains are user programmable, independently for both lines. The default values are 0dBr in the transmit direction, and 7dBr in the receive direction. MTK-40131 Source Impedance (Zco) The central-office impedance, Zco, is synthesised using digital signal processing techniques. This renders it very stable, and moreover programmable by the user by means of coefficients which are loaded via the GCI. Real or complex Zco's can be synthesised, using the common 3-element model (Rs, Rp, Cp; see fig 11). The Zco setting is common for both lines. Both real and complex Zco's can be programmed to address the local requirements of specifications world-wide, and cover the range: Using the default coefficient values, the return loss when measured against 600 (using 0dBm input signal level) is better than 20dB in the 300 to 3400 Hz band, and better than 10 dB at 10 kHz. Real impedances: 600 to 900 Complex impedances: Rs from 160 to 500 Rp from 300 to 1000 Rp//Cp pole from 725 Hz to 5kHz Cp Rs Rp Fig. 11: 3-element Zco model. Balance Impedance (Echo Canceller) The balance impedance (model of the line+set impedance used to separate the receive and transmit signals in the `hybrid') is independently programmable (though is the same for both channels). Default values offer echo return loss of better than 20dB, though optimization to specific line and set characteristics may yield further improvement. Table 9: Examples of ZCO Coefficients Rs Rp Cp ZcoSh Alfa3 ZcoA2 Rzco 600 0 0 0 Germany 220 820 Europe 750 ZCO850 850 ZCO900 900 Belgium 270 ZcoGamma ZcoAlfa3 Ftx Ap Nan ACG 0 3 0 0 237 0 0 103 115nF 0 40 9 9 5 52 346 512 125 150nF 0 19 7 15 4 122 388 -179 125 0 0 0 0 0 0 0 282 0 0 123 0 0 0 0 0 0 0 290 0 0 126 h0 h1 h2 h3 a0 c5 b0 Dzd0 Dzd1 4 -22 105 95 0 0 0 1 1 Germany -31 48 1 156 0 0 0 0 0 Europe 3 -23 118 88 0 0 0 0 0 ZCO850 4 -22 105 95 0 0 0 1 1 ZCO900 4 -22 105 95 0 0 0 1 1 Belgium 19 MTK-40131 Off-hook Characteristics (MTK-40131 System) Table 10: Off-hook Characteristics (MTK-40131 System) Conditions: see paragraph "operating conditions" Parameter Conditions Min Max Units Note Gtx Relative gain, transmit direction Gain programming step Step accuracy Gain tolerance (ref. programmed value) -6 +1 0.25 0.1 +0.5 dB dB dB dB 1 Relative gain, receive direction Gain programming step Step accuracy Gain tolerance (ref. programmed value) -12 dB dB dB dB 1 -0.5 +1 0.25 0.05 +0.5 dGlt Long-term gain stability -0.5 +0.5 dB 2 Gttx Gain tracking, TX path +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Gain tracking, RX path +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0.3 0.6 1.6 dB dB dB 3 3 3 0.3 0.6 1.6 dB dB dB 3 3 3 Grx Gtrx -0.5 IMDtx Intermodulation distortion, TX path -45 dBm0 4 IMDrx Intermodulation distortion, RX path -50 dBm0 4 Sdtx Signal to total distortion ratio, TX (gain= 0 dB) -0 to -10 dBm0 -20 dBm0 -30 dBm0 -40 dBm0 -45 dBm0 Signal to total distortion ratio, RX (gain= - 7 dB) -0 to -10 dBm0 -20 dBm0 -30 dBm0 -40 dBm0 -45 dBm0 35 34.7 32.9 24.9 19.9 dB dB dB dB dB 5 35 33.8 28.8 19.5 14.5 dB dB dB dB dB 5 Sdrx SFNrx Single frequency noise 300 to 3400 Hz, all out of band freqs. 700 to 1100 Hz in band 300 to 3400Hz Longitudinal balance Resistor matching Notes: 1. User programmable. 2. Covers variations within the permitted ranges of supply voltage and temperature during any one year. 3. Referred to the gain at 1020 Hz applied to the input at a level -10dBm0. -40 -49 1% 0.1% 40 46 4. Intermodulation distortion measured for all intermodulation products of any non-harmonically related frequencies in the range 300 to 3400 Hz for levels between -4 and -21 dBm0. 20 dB dB dB dB 5. Intermodulation distortion measured for all intermodulation products of a frequency in the range 300 to 3400 Hz at -9dBm0 and 50Hz at -23dBm0. MTK-40131 Metering Injection Metering pulses of selectable frequency (12 or 16 kHz) and programmable amplitude can be injected into either analog channel independently. The width of the injected pulse is determined by the user ("on/off mode"), or by an internal timer ("burst mode") which can be set by the user from 2ms to 510 ms in steps of 2ms. The metering signal is always a multiple of half metering periods. See fig. 12. Metering is initiated on a channel by an active low state on the corresponding /MPI bit in the GCI C/I byte. on/off mode /MPI metering burst mode /MPI tmburst metering Fig. 12: Metering pulse timing diagrams. The metering level on the line is set by: Vlm = (Vgen . Zm)/(Zm + Zcom) where: Vlm = metering pulse level on the line Vgen = set level of the metering generator Zm = impedance of the metering load Zcom = CO impedance at the metering frequency. 21 The metering level Vgen is selectable from 0 to a maximum level of 230mVrms (500m line with Zco=900) in 15 linear steps. The internal tolerance on the metering signal level is 10%. MTK-40131 Metering Characteristics (Determinized by MTC-20232 CODSP) Table 11: Metering Characteristics (Determinized by MTC-20232 CODSP) Conditions: see paragraph "operating conditions" Parameter Conditions Min Max Units Note Fml Fmh Metering frequency, 12kHz Metering frequency, 16kHz -60 -80 +60 +80 Hz Hz ( 0.5%) ( 0.5%) SFN1 Single-frequency noise, subharmonics for 12kHz, 30Hz to 12 kHz for 16kHz, 30Hz to 12 kHz Single-frequency noise, mixed products 12kHz, 12kHz to 20kHz 12kHz, 20kHz to 132kHz 16kHz -69 -69 dBm0 dBm0 -51 -69 -69 dBm0 dBm0 dBm0 Nmc Nmt In-band noise due to metering signal Transient noise due to metering pulse -60 -35 dBmp dBm0 THDm Metering total harmonic distortion, 30 Hz to 132 kHz, out of CODSP 0.5 % Dm Metering signal distortion at load 5 % on 200 Vlm Metering pulse amplitude, maximum level with Zco=900, Rline=130 207 253 mVrms ( 10%) SYMm Metering symmetry, a and b wires 24 dB ( max 6%) SFNtx Single frequency noise, mixed products, 10Hz to 4 kHz, TX path SFN2 -63 Note: Measured in accordance to ITU-T specification 071 (Blue Book) 22 dBm 1 1 MTK-40131 Tone Generation The SH POTS system allows the injection of user programmable tones, independently per channel, for signalling or user test purposes. Per channel, a tone comprising two programmable (sinewave) frequencies and programmable amplitudes can be generated (in this The amplitude of each frequency within the tone can be independently set from 0 to the maximum level in 256 linear amplitude steps (8 bit value), with n=63 corresponding to 0dBm on the line. From this, the line signal level Vtl for a given gain factor n is given by: Vtl = 20 log(n/63) in dBm. or n = int(63*10^(Vtl/20) + 0.5) Table 11 lists values for n for a range of tone signal levels. way, the most common call-progress and information tones, melody notes or DTMF tones, can be synthesised). The tone signal is added to the speech signal (the user must be aware of possible clipping which may occur if high signal levels are programmed), or the speech signal can also be muted during a tone burst. The tone burst duration is under user control only (the control bits for mute and tone insertion occupy the same register, which simplifies the generation of tone bursts). Table 12: Tone signal levels (common values) dBm 3 1.5 0 -1.5 -3 -6 -8 -10 -15 -20 -30 -36 n Actual err (dB) 89 75 63 53 45 32 25 20 11 6 2 1 3.00 1.51 0.00 -1.50 -2.92 -5.88 -8.03 -9.97 -15.16 -20.42 -29.97 -35.99 0.00 0.01 0.00 0.00 0.08 0.12 -0.03 0.03 -0.16 -0.42 0.03 0.01 Note that it is possible to generate tones of very high amplitude. The user must ensure that the amplitude parameter is The tone frequency is given by: Fout = 250 * N / 256 Hz, where N is a 16 bit value (thus, N=1024 yields a tone of 1 kHz) or N = int(Fout*256/250 + 0.5) The tone generated has continuous phase if the programmed frequency is changed during the course of a tone (this is not so if the generator is stopped and restarted). Tables 2 and 3 list the values of N required to generate commonly occurring frequencies, and the resulting error. 23 programmed before the tone is enabled. MTK-40131 Table 13: Tone Generator Characteristics Parameter Conditions Min SFNtx Single frequency noise, mixed products, 10Hz to 4 kHz, TX path Table 14: Tone generator division values for common frequencies from ETS-300-001, and DTMF tones Common signalling frequencies Freq. (Hz) N Actual Freq. error (%) 300.00 320.00 325.00 340.00 350.00 375.00 380.00 382.50 400.00 410.00 420.00 440.00 450.00 455.00 475.00 490.00 500.00 525.00 550.00 307 328 333 348 358 384 389 392 410 420 430 451 461 466 486 502 512 538 563 299.805 320.313 325.195 339.844 349.609 375.000 379.883 382.813 400.391 410.156 419.922 440.430 450.195 455.078 474.609 490.234 500.000 525.391 549.805 -0.07 0.10 0.06 -0.05 -0.11 0.00 -0.03 0.08 0.10 0.04 -0.02 0.10 0.04 0.02 -0.08 0.05 0.00 0.07 -0.04 N Actual Freq. error (%) 697.266 769.531 851.563 941.406 1208.984 1335.938 1476.563 1632.813 0.04 -0.06 -0.05 0.04 0.00 0.00 -0.03 -0.01 DTMF tones Freq. (Hz) 697.00 770.00 852.00 941.00 1209.00 1336.00 1477.00 1633.00 714 788 872 964 1238 1368 1512 1672 24 Max Units -63 dBm Note MTK-40131 Table 15: Required frequency setting values (N) for a melody generator (western equal-tempered scale) Octave Note Freq. (Hz) N Actual error (%) 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 C C# D Eb E F F# G Ab A Bb B C C# D Eb E F F# G Ab A Bb B C C# D Eb E F F# G Ab A Bb B C C# D Eb E F F# G Ab A Bb B 261.626 277.183 293.665 311.127 329.628 349.228 369.994 391.995 415.305 440.000 466.164 493.883 523.251 554.365 587.330 622.254 659.255 698.456 739.989 783.991 830.609 880.000 932.328 987.767 1046.502 1108.731 1174.659 1244.508 1318.510 1396.913 1479.978 1567.982 1661.219 1760.000 1864.655 1975.533 2093.005 2217.461 2349.318 2489.016 2637.020 2793.826 2959.955 3135.963 3322.438 3520.000 3729.310 3951.066 268 284 301 319 338 358 379 401 425 451 477 506 536 568 601 637 675 715 758 803 851 901 955 1011 1072 1135 1203 1274 1350 1430 1515 1606 1701 1802 1909 2023 2143 2271 2406 2549 2700 2861 3031 3211 3402 3604 3819 4046 261.719 277.344 293.945 311.523 330.078 349.609 370.117 391.602 415.039 440.430 465.820 494.141 523.438 554.688 586.914 622.070 659.180 698.242 740.234 784.180 831.055 879.883 932.617 987.305 1046.875 1108.398 1174.805 1244.141 1318.359 1396.484 1479.492 1568.359 1661.133 1759.766 1864.258 1975.586 2092.773 2217.773 2349.609 2489.258 2636.719 2793.945 2959.961 3135.742 3322.266 3519.531 3729.492 3951.172 0.04 0.06 0.10 0.13 0.14 0.11 0.03 -0.10 -0.06 0.10 -0.07 0.05 0.04 0.06 -0.07 -0.03 -0.01 -0.03 0.03 0.02 0.05 -0.01 0.03 -0.05 0.04 -0.03 0.01 -0.03 -0.01 -0.03 -0.03 0.02 -0.01 -0.01 -0.02 0.00 -0.01 0.01 0.01 0.01 -0.01 0.00 0.00 -0.01 -0.01 -0.01 0.00 0.00 25 (middle-C) MTK-40131 CODSP Clock Recovery PLL User-Defined I/O Pins The CODSP device derives its internal clocks from the GCI's DCL input by means of a PLL. The PLL automatically detects the clock mode in use, and sets the multiplication factor accordingly. The PLL loop filter requires an external capacitor as shown in the application schematic. AW BW The pins SPIDI, SPICS and SPICK are part of an SPI port which is used by Alcatel Microelectronics during product evaluation and testing. They are available to the user, via the GCI, as output bits (e.g. for driving small indicator LEDs). The pin SPIDO is used as part of the power-up and testing routines, and the behaviour during power-up cannot be guaranteed. It is therefore advised not to make use of this pin for any other purposes. The outputs can source or sink a maximum of 4mA each. protection Rfeed nc Rfeed nc rly +5V SPICK (Line 0) or SPICS (Line 1) Note: In order to support "semi-unbalanced ringing" (DC bias equal to VbatR superimposed on the differential ringing signal), two of these outputs will be active high during the active ringing period on each channel (SPICK for channel 0 and SPICS for channel 1). This can be used to drive a relay via an external NPN transistor as shown in fig 13. line rly 47F -VbatR rly Fig 13: Application suggestion for Semi-unbalanced ringing injection. Test functions Please contact Alcatel Microelectronics. 26 MTK-40131 Electrical Characteristics Absolute Maximum Ratings Operation of the device at or near these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability. Table 16: Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Battery voltage BATR (ref. To GNDB) of SHLIC BATR -75 +0.5 V Battery voltage BATS (ref. To GNDB) of SHLIC BATS -35 +0.5 V Difference between the batteries BATR and BATS, BATR-BATS of SHLIC DBAT -40 +0.5 V VDDA (ref. to GNDA) of SHLIC VDDA -0.5 +7 V GNDB (ref. to GNDA) of SHLIC GNDB -0.5 +0.5 V -40 +85 Ambient temperaure under bias of SHLIC Maximum absolute power dissipation, Tamb. = 85C 1.3 W V3VA,V3VD to CODSP V3V VSS-0.3 4 V Voltage on any device pin * of CODSP Vin VSS-0.3 V3V+0.3 V Function temperature under bias of CODSP -55 +150 C Storage temperature -65 Lead temperature (soldering 10 sec.) +150 W +300 C * except special 5V tolerant I/O's of CODSP Operating Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device as described in this documents, and for the reliability specifications. Correct functioning outside of these limits is not implied. Total cumulative exposure outside the normal power supply voltage range or the ambient temperature under bias, must be less than 0.1 % of the normal useful life as defined in the Reliability section. Table 17: Operating Conditions Symbol BATR BATS DBAT VDDA Trange V3VD V3VA Trange Parameter Limits Unit Min. Typ. Max. Ringing battery voltage Speech battery voltage Difference between the batteries BATR and BATS, BATR-BATS Supply voltage SHLIC Operating temperature range - I SHLIC -C -72 -35 -65 -32 -18 -18 V V -40 4.75 -40 0 -35 5 0 5.5 85 70 V V C(*) C VDD of CODSP (3.3V 8%) Operating temperature range - I CODSP -C 3.036 -40 0 3.3 3.564 85 70 V C C All voltages referenced to GNDA = GNDB or VSS = GNDA, as appropriate. see paragraph Thermal shutdown: Max power dissipation is depending on Max Ambiant temperature (*) 27 MTK-40131 Thermal Shutdown SHLIC Thermal limiting circuitry on chip of the SHLIC will shut down the circuit at a junction temperature of about 165 C. The device should never see this temperature and operation above 145 C junction temperature might degrade device reliability. Table 18: SHLIC Dissipation Parameter Symbol Value Unit Maximum operating power dissipation, Tamb. = 70 C Pmax_op 1.2 W Thermal resistance = 55C/w typ. The specifications for power dissipation imply that in ring mode the active ring phase must at least be 4 times shorter than the non active ring phase. The maximum duration of the active ring phase must be below 2 s. Transient Energy Capability During testing, each device termination withstands being shorted to the supply voltages or ground as specified below. The shorting must be limited to one second. Shorted to GNDA, VDDA or GNDB: VAG, PU, RNG, BR, TST, TA, DCC, DCO, DCI, TX to RX Shorted to GNDA, GNDB or BATS: AW, BW, SA to SB 28 MTK-40131 DC Characteristics (MTC-30132 SHLIC, unless otherwise noted) Unless otherwise stated, these characteristics apply for the operating conditions specified above. All parameters are explicitly or implicitly tested during production at the operating conditions unless they are marked with a *, where they are guaranteed by design. Parameters marked with ** are meant as user information only. Tests are performed using an equivalent of the application schematic. Power Supply Currents Table 19: Power Supply Currents Symbol Parameter Test Conditions Limits Min. Unit Typ. Max. Power Up Power Down RNG=0 RNG=1 RNG=0 RNG=1 0.35 3.5 0.35 2.5 0.5 5.0 0.5 3.5 mA mA mA mA Power Up Power Down RNG=0 RNG=1 RNG=0 RNG=1 3.5 3.5 1.5 5 5 2.5 0.5 mA mA mA mA 3 2.5 5.5 4 mA mA 30 140 180 mW mW mW Ibatr BATR current (IL = 0) Ibats BATS current (IL = 0) Ivdd VDD current (IV3V=0) PowerUp PowerDown Pcc Power dissipation of CODSP (@ 3,45V V3VA and V3VD) PowerDown PowerUp PowerUp 1 line active 2 lines active Notes: IL is the line current, i.e. these parameters are measured without line current. IV3V is the load current in pin V3V The maximum values in the table are valid for the full battery voltage ranges : -18V to -72V for ringing battery BATR -18V to -35V for battery BATS. (BATR must be always the most negative one) In case of sleep mode activation. See tables "Data Ram: Memory Map, description and default values" for programing values. 29 MTK-40131 Power-on Reset The table shows the power reset threshold for VDD of the SHLIC. As long as VDD is below the reset threshold, the SHLIC is held in power down, and the output pins AW and BW are high impedance. The CODSP uses a separate input pin PWRS for system reset at power-up. Table 20: Power-on Reset Characteristics Symbol Parameter Test Conditions Limits Unit Min. Typ. Max. 3.5 4.0 VDDPWR Threshold voltage for power reset on VDD of SHLIC 3.0 TPWRS Active low pulse width on PWRS of CODSP 10 VPWRS Threshold voltage for reset on PWRS of CODSP 1.6 V ms 1.7 V V3V Regulator This series regulator of the SHLIC can be used to provide the supply voltage for the CODSP or other 3.3V devices. Table 21: V3V Regulator Characteristics Symbol Parameter Test Conditions load current Iv3v between 0 and 50mA Limits Unit Min. Typ. Max. 3.05 3.3 3.55 V 50 mA Vv3v V3V output voltage Iload load current range PSRR signal rejection VDD to V3V frequency range 0 to 10KHz 20 Lreg load regulation load current range from 5 to 50mA -1 Cload (**) maximum load capacitance load current range from 0 to 50mA Icc(*) current limitation shorted output V3V shorted to AGND 0 30 dB 1 100 70 ohm nF 200 mA MTK-40131 A-wire, B-wire DC- Levels, Impedances Table 22: Voltage Characteristics A Wire (Aw), B Wire (Bw) Symbol Parameter Test Conditions Limits Unit PU BR RNG Min. Typ. Max. Vawn Normal DC-bias on AW(ref. GNDB) 1 0 0 -3.5 -3.1 -2.7 V Vbwn Normal DC-bias on BW(ref. BAT) 1 0 0 2.5 3 3.5 V Vawr Reverse polarity DC-bias on AW (ref BAT) 1 1 0 2.5 3 3.5 V Vbwr Reverse polarity DC-bias on BW (ref. GNDB) 1 1 0 -3.5 -3.1 -2.7 V Vaw_h DC bias on AW in Act_H mode (TST=1, ref. GNDB) 1 x 1 -4 -3 -2 V Vbw_h DC bias on BW in Act_H mode (TST=1, ref. BAT) 1 x 1 2 3 4 V Vhwpd Voltage level high wire (IL<5mA) 0 x 0 -0.8 -0.5 Vlwpd Voltage level low wire (IL<5mA), ref BAT 0 x 0 Vawring Vbwring DC-level both wires in ringing mode (TST=0) 1 0 1 V 0.5 BAT/2 BAT/2 -2% 0.8 V BAT/2 +2% V Note: These BIAS values are only valid if both DCC and RX are biased at VAG voltage level. Table 23: Impedance Characteristics A Wire (Aw), B Wire (Bw) Symbol Parameter Test Conditions Limits Min. Unit Typ. Max. Za(b)wo (*) Output impedance at AW (BW) (power up) 0mA<IL<70mA 0<f<16 kHz 1.5 ohm Za-bwo (*) Tracking of the output impedance onAW and BW 0mA<IL<70mA 0<f<16 kHz 0.3 ohm Zhwod Output impedance on high wire (power down) PU=0 5 130 ohm Zlwod Output impedance on low wire (power down) PU=0 5 130 ohm Zomd Matching output impedance low vs high wire (power down) PU=0 -70 70 ohm Ia(b)OC Ia(b)HIMP Output current in and out AW (BW) with OT (over-temperature) detected A(B)W_GNDB and A(B)W_BATS -700 +700 A 31 MTK-40131 RX, TX DC- Levels, Impedances Table 24: RX, TX Characteristics Symbol Parameter Test Conditions Limits Min. Ztx (*) Output impedance at TX f = 1 kHz Votx Offset voltage on TX (PU=1) (ref VAG) SA shorted to AW and SB to BW, DCI to V3V, DCO to VAG Iouttx TX output current capability Vrx(*) Rx input voltage range(ref. VAG) Zrx Rx input impedance Unit Typ. Max. 10 ohm 20 mV -1 0.05 mA -1 1 V -20 0 f = 1kHz 20 kohm Test Conditions Limits Unit DCO DC- Levels, Impedances These limits are generally transparent to the user, but are given here for information. Table 25: DCO Characteristics Symbol Parameter Min. Zdco (*) Output impedance at DCO Vodco Offset voltage on DCO(ref. VAG) Ioutdco (*) DCO output current capability Zdci Input impedance at DCI SA shorted to AW and SB to BW -20 Typ. 0 -1 f=1kHz Max. 10 ohm 20 mV 0.05 mA 210 Kohm Limits Unit VAG Analog Ground Input The analog ground is typical half the voltage of the V3V output voltage. It is the reference for all the analog interfacing between SHLIC and the CODSP. VAG is provided by the CODSP. Table 26: VAG Characteristics Symbol Parameter Vvag (**) Voltage level at VAG pin CODSP Ivag VAG input current SH LIC Test Conditions VAG=1.65V 32 Min. Typ. Max. 1.53 1.65 1.77 V 0.5 mA MTK-40131 SA,SB Sense Bridge Inputs Table 27: Sense Bridge Inputs Characteristics Symbol Parameter Test Conditions Limits Unit Min. Typ. Max. Raw-sb bridge resistance from AW to SB VDD, VAG=0V, 25C 205 257 309 Kohm Rsa-bw bridge resistance from BW to SA VDD, VAG=0V, 25C 205 257 309 Kohm DC loop filter These limits are generally transparent to the user, but are given here for information. Table 28: DC Loop Filter Characteristics Symbol Parameter Test Conditions Limits Unit Min. Typ. Max. VDCLF1 DCLF1 output voltage(ref. GNDB) RNG=0, PU=1 -3.5 -3.1 -2.7 V VDCLF2 DCLF2 output voltage(ref. BAT) RNG=0, PU=1 2.5 3.0 3.5 V ZDCLF1s Output impedance at DCLF, VDCLFVDCLF1< 0.5V RNG=0, PU=1 0.6 1 1.4 Mohm ZDCLF2s Output impedance at DCLF, VDCLF2VDCLF< 0.5V RNG=0, PU=1 0.6 1 1.4 Mohm Test Conditions Limits DCC Input Pin These limits are generally transparent to the user, but are given here for information. Table 29: DCC Input Characteristics Symbol Parameter Min. VDCC DCC input voltage range (ref. VAG) RNG=0, PU=1 IinDCC DCC input current, VDCC=VAG+1V RNG=0, PU=1 Note: Forcing DCC positive (ref. VAG) will result in a smaller voltage between A- and Bwire. It a too large signal is applied at DCC, both wires are clamped at the same voltage (only a small residual voltage remains on the line). 33 Unit Typ. -1 4 Max. 1 V 10 uA MTK-40131 Characteristics for the Digital I/O pins CODSP, plus TST, PU, BR, RNG of SHLIC Table 30: Digital I/O Characteristics Symbol Parameter Test Conditions Limits Min. Unit Typ. Max. Vil Low level input voltage 0.3*V3VD V Vih High level input voltage Iil Low level input current (except PU, see below RPD) VDD = 5.25 V -1 +1 A Iih High level input current (except PU, see below RPD) VDD = 5.25 V -1 +1 A Cinp (*) Input capacitance 7 pF RPD Pull down resistance at pin PU 40 kohm VOL output level PU pin, driven low 0.5 V VIL Low-level input voltage, CODSP VIH High-level input voltage, CODSP VOL Low-level output voltage, CODSP VOH High-level output voltage, CODSP CIN Input pin capacitance, CODSP 1 pF COUT Load capacitance, CODSP 100 pF 0.7*V3VD 18 Overtemperature OT activated, Ipu=0.2mA, Tested at high temp. only. V 30 0.2*V3VD 3V3D 0.8*V3VD 3V3D 0.4 0.8*V3VD Test Switch The internal test switch is between the pins SB and SSB. Connecting an external load between SSB and SA allows test of the transmission characteristics in (simulated) off- and on hook conditions. The typical on-resistance of the test switch is around 75 ohms, and has to be taken into account when defining the external load. The test switch is on when RNG=0, PU=1, TST=1, BR=0 34 V 3V3D MTK-40131 Table 31: Test Switch Characteristics Symbol Parameter Test Conditions Limits Min. Iswoff switch leakage current |Vssb-Vsb| < 72V Vswon voltage drop over testswitch Isw=80mA Isw=20mA (VSSB-VSB > 0V) Unit Typ. 4 1 Max. 5 uA 9 3 V V Note: The test switch is normally off when VDD is below the reset level. If the battery voltages are sufficient, the switch remains on when it was on before VDD went below the reset level. Battery Switch This switch is activated during ringing or when the higher on-hook voltage is selected (RNG=1). When active, BATR is connected to the internal battery supply line VBAT. In other cases (RNG=0), the switch is open; VBAT is now connected to BATS via an internal diode. Table 32: Ringing Battery Switch Characteristics Symbol Parameter Test Conditions Limits Min. Unit Typ. Max. Ibswoff(*) leakage current battery switch (RNG=0) BATR=-72V, BATS=-32V 5 uA Irevbats(*) reverse current BATS diode (RNG=1) BATR=-72V, BATS=-32V 5 uA Vdrbats forward drop BATS diode load current < 80mA 1.2 V Ibson current capability battery switch 80 mA Vbswon voltage drop over battery switch (RNG=1) 2 V 0.85 0 load current < 80mA 35 1 MTK-40131 AC Characteristics (SHLIC) (0 dBm : 1 mW in 600 ohm) Unless otherwise stated, the characteristic limits apply over the operating conditions specified above, and each combination of the drive bits unless otherwise stated. All parameters are specified in the presence of a longitudinal current of max. 5 mAp and a DC current of between 0 mA and the current limit. The behaviour of the chip in presence of longitudinal voltages is not tested in production. The different gains in the signal paths are shown in fig 14. The values of the gains are in the following table. Table 33: Typical Gains AWBIAS Rprot ZL RB VL AW G2 RX GR Vab DCC G4 BW Rprot G3 RB I/O to ADSP (Ref. VAG) Gain G1 G1' G2 G3 G4 G5 GR GR' Factor + 1.66 0.079 2 -2 15 - 1/8 1 35/2 BWBIAS TX G1 Sense Bridge DCO G5 The gains in the table above are not tested. They are mentioned for information only. The pin-to-pin gains as listed in the tables below (Grx, Gtx, ...) are tested and guaranteed In case of Ringing, the receive gain is changed from GR to GR', the transmit gain factor G1 is changed to G1'. Fig. 14: Block diagram showing the gains in the various signal paths in the SHLIC. Receive Path Transmit Path Equation : Equation : Grx = Vab = GR( G3 - G2 ) Vrx This equation is valid for an open loop configuration. This does not incorporate the Zco synthesis, which is defined by the feedback from TX to RX. This function is performed in the CODSP. Gtx = Vx 2RB = G VL ZL This equation is valid under open loop conditions. 36 The default test condition of the input bits is: PU=1, RNG=0, BR=0/1. DCC is shorted to VAG. MTK-40131 Overpower and Short Circuit Protection In power down, the DC-loop current limitation is not active. The line current is limited directly through the line drivers. The AW and BW outputs are fully protected against short circuits to a voltage between GNDA/GNDB and BATR (see fig. 15). RS1=RS2 0.3 GNDB RS1 AW BATR GNDB Vaw RS2 BW + Vbw Vsb BATR GNDB Fig. 15: Short circuit protection 37 + Vsa MTK-40131 The current flowing from (or into) AW and/or BW is limited to a value ILW/IHW as long as the junction temperature Tj < 165C (electronic current limitation). The values for ILW/IHW for different conditions are given in the table below. If Tj rises above 165C ( 15 %) the output drivers outputs are made high impedant. Current can only flow in or out the internal protection diodes, in case Vsa and/or Vsb exceeds the range between GND and BATR. The currents should however be limited externally (internal clamping diodes protection): see section overvoltage protection. Table 34: Short Circuit Protection Characteristics Parameter ILW IHW Short circuit peak current, power up, sink current Short circuit peak current, power down, sink current Short circuit peak current, power up, source current Short circuit peak current, power down, source current Test Conditions Limits Unit Min. Typ. Max. PU=1 -145 -120 -95 mA PU=0 -65 -45 -20 mA PU=1 95 120 145 mA PU=0 20 45 65 mA 38 MTK-40131 Detailed Programming Description GCI Interface The SH POTS system uses the GCI standard interface to exchange B channel data (PCM coded voice) and control information with the controlling system. GCI data is exchanged in both directions (downstream, towards the analog line, and upstream, from the analog line) in 4-byte frames at a rate of 8000 frames per second (the standard PCM sampling rate). Voice information or data is transmitted via the "Bearer" channels B1 and B2. Real-time signalling information for the two channels are communicated via the 6 C/I bits (the 2 least significant bits of the C/I byte are used to manage communication via the Monitor channel). Programming and status information is communicated by means of commands over the Monitor channel. SH POTS GCI Interface: Modes ONE TIMESLOT B1 DU/DD 7 6 5 4 Monitor B2 3 2 1 0 C/I 7 6 5 4 3 2 A 8 kHZ GCI Frame CLock FSC DCL SINGLE TIMESLOT MODE : FSC = 8 kHz DCL = 512 kHz ; data rate = 256 k bit/sec DU/DD TIMESLOT 1 FSC TIMESLOT 2 TIMESLOT 8 8 kHZ GCI Frame CLock DCL MULTIPLEXED TIMESLOT MODE : FSC = 8 kHz DCL = 4096 kHz ; data rate = 2048 k bit/sec Fig 16: GCI data exchange. SH POTS GCI Interface: Timing 39 E MTK-40131 Timeslot Address Frames can be formatted singly (4 bytes per frame), or in a multiplexed mode whereby up to 8 GCI compatible devices can be connected to the same bus. In the multiplexed mode, the frames of 4 bytes are transmitted in one of 8 timeslots - the mode and the timeslot address of a particular GCI terminal is set by means of strapping a code on 3 device pins GCIM, AD0 to AD2 on the CODSP (see table 35). The CODSP uses the GCI standard format for analog terminals (see fig. 16). GCIM AD2 AD1 AD0 Time DCL Timeslot slot frequency address mode (kHz) 0 0 0 0 1 512 0 1 0 0 0 8 4096 0 1 0 0 1 8 4096 1 1 0 1 0 8 4096 2 1 0 1 1 8 4096 3 1 1 0 0 8 4096 4 1 1 0 1 8 4096 5 1 1 1 0 8 4096 6 1 1 1 1 8 4096 7 Table 35: GCI mode and Timeslot address programming 40 MTK-40131 SH POTS GCI Interface: Timing tr twH tf tDCL twL DCL FSC tsF thF twFH twFL tdDF DU tdDC DD tsD thD Fig 17: GCI Timing Diagram Table 36: GCI Interface: Timing Characteristics Signal Parameter Description Min inputs inputs DU DU ViL ViH VoL VoH input level Low input level High output level Low output level High DCL(2) DCL(2) DCL(2) DCL(3) DCL(3) tDCL tr,tf twH,twH tDCL twL,twH Clock Period Clock Rize/Fall Pulse Width Clock Period Pulse Width 1952 FSC FSC FSC FSC FSC tsF tr,tf twFH twFL thF Frame Setup Frame rize/Fall Frame Width H Frame Width L Frame Hold 70 DU(1) DU(1) tdDC tdDF Data delay/Clock Data delay/Frame DD DD tsD thD Data setup Data hold (1) (2) (3) Condition CL = 150pF 256 k bit/sec Transmission 2048 kbit/sec Transmission Max Unit 0.8 V V V V 2.0 0.4 2.4 800 243.9 90 1955 60 244.3 DCL-60 60 ns ns ns ns ns 100 150 ns ns 130 tDCL 60 twH+20 60 41 ns ns ns ns ns ns ns MTK-40131 C/I Bits The C/I bits are used to transfer signalling information for both channels simultaneously. The C/I bits must be stable for at least 2 consecutive GCI frames before they will be recognised. The bit allocations for both downstream and upstream directions are shown in the table. Note that the signals are active low, meaning that the idle condition is a logic `1'. C/I Bit Allocation: Direction C/I 7 C/I 6 C/I 5 C/I 4 C/I 3 C/I 2 Downstream /RNG0 /MPI0 /ADSI0 /RNG1 /MPI1 /ADSI1 Upstream /LS0 /AL0 /RPH0 /LS1 /AL1 /RPH1 /RNG /MPI /ADSI /LS /AL /RPH Activate ringing Activate metering pulse Activate on-hook signalling Off-hook condition detected (Loop Stable) Alarm (indicates any of the possible alarm conditions: initrequest, overpower detected) Ring phase. Indicates that ADSI data can NOT be sent. Monitor Channel The CODSP acts as a slave device on the GCI - commands received in the downstream direction are responded to in the upstream direction. The E and A bits in the C/I byte are used to synchronise and acknowledge the correct transfer of a monitor channel byte. Valid commands are: ID Request 10000000 Write request 10001BBB Read request 10011BBB (BBB is the memory block identifier or "MemID" - see below) Other commands should not be used. ID Request The IDrequest command returns 2 bytes: byte 1 10000000 Command confirmation byte 2 10RRRRRR Revision code This command returns a unique code for each device revision. 42 MTK-40131 Read Command A read request command comprises 3 bytes: Read request Address high Address low 10011BBB nnnnnnnn nnnnnnnn The response is a 5 byte stream: Command conf. Address high Address low Data high Data low 10011BBB nnnnnnnn nnnnnnnn dddddddd dddddddd Write Command The write command comprises 5 bytes: Command conf. Address high Address low Data high Data low 10001BBB nnnnnnnn nnnnnnnn dddddddd ddddddd No bytes are returned Memory Map of the CODSP Global Memory Map and MemID Definitions * All addresses can be read and written, though writing to locations or individual bit which are not described here may result in unpredictable, though possibly interesting, behaviour. * The memory block to be accessed is given as part of the READ or WRITE command (see above) as the `B' bits in the command byte. * The default parameter and coefficient values that are used at start-up and after reset, are listed in the following tables. * The control registers of the SH POTS system, accessed via the GCI, are organised in a number of memory blocks. Within each block, a number of addresses are used directly to control the operation of specific functions of the SH POTS system. 43 MTK-40131 Table 37: Memory Map for CODSP MemID Memory Start Address Memory Contents 2 Data RAM 0x 02 0000 C-code Read/Write Data C-code Stack region C-code IRQ Stack region 4 CoProcessor Coef RAM 0x 04 0000 Filter coefficients 5 SHARED RAM 0x 05 0000 Data Packet buffers Label vectors, Fifo control Data RAM MemID = 2 Table 38: Data RAM: Memory Map Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 (0x0000) Bbs0 Bsa0 Bs0 Br0 Tst0 Sh0 01 (0x0001) Bbs1 Bsa1 Bs1 Br1 Tst1 Sh1 02 (0x0002) 03 (0x0003) TX Gain 0 04 (0x0004) TX Gain 1 05 (0x0005) RX Gain 0 06 (0x0006) RX Gain 1 07 (0x0007) Dzd1 Dzd0 08 (0x0008) 09 (0x0009) Td1 CurLim_Rlarge Td0 CurLim_Threshold 10 (0x000A) RW RIL 11 (0x000B) Ringing_DC_Offset Ringing_Amplitude 12 (0x000C) Ringing_Off_Period Ringing_On_Period 13 (0x000D) RM RF LBO 14 (0x000E) RTDAC_ThresholdLow RTDAC_ThresholdHigh 15 (0x000F) RTDAC_Debouncetime RTDAC_GapTime 16 (0x0010) AlarmReg 17 (0x0011) IDC0 18 (0x0012) 19 (0x0013) IAC1 IDC1 IAC0 20 (0x0014) TG1 TG0 MS1 MS0 21 (0x0015) TestTone_Ampl1_L0 22 (0x0016) TestTone_Ampl1_L1 23 (0x0017) TestTone_Ampl2_L0 44 MTK-40131 Address 15 14 13 12 11 10 9 8 7 6 24 (0x0018) 4 3 2 1 0 TestTone_Ampl2_L1 25 (0x0019) TestTone_Freq1_L0 26 (0x001A) TestTone_Freq1_L1 27 (0x001B) TestTone_Freq2_L0 28 (0x001C) TestTone_Freq2_L1 29 (0x001D) 30 (0x001E) 5 ACG Sleep2 Pd1 Pd0 Rzd1 31 (0x001F) DialP_SatTxLevel 32 (0x0020) DialP_DebTime Note: Bit positions and memory locations not documented must not be changed. 45 Rzd0 Sleep1 MTK-40131 LBO register This register controls various loop-back modes, as well as the routing of the GCI B channels to/from the physical line analog channels. The bits are codes as follows: Table 39: LBO Register Description Mode D2 D1 D0 GCI side Analog side Normal 0 0 0 TX(0) -> B1Up TX(1) -> B2Up B1Down -> RX(0) B2Down -> RX(1) Simplex loop B2 0 0 1 TX(0) -> B1Up B2Down -> B2Up B1Down -> RX(0) TX(1) -> RX(1) Simplex loop B1 0 1 0 B1Down -> B1Up TX(1) -> B2Up TX(0) -> RX(0) B2Down -> RX(1) Simplex loop B1 and B2 0 1 1 B1Down -> B1Up B2Down -> B2Up TX(0) -> RX(0) TX(1) -> RX(1) Duplex loopback 1 0 0 B2Down -> B1Up B1Down -> B2Up TX(0) -> RX(1) TX(1) -> RX(0) Reserved 1 0 1 Reserved 1 1 0 Swap mode 1 1 1 TX(0) -> B2Up TX(1) -> B1Up B1Down -> RX(1) B2Down -> RX(0) BnDown BnUp TX(m) RX(m) : GCI B channel n, Downstream direction : GCI B channel n, Upstream direction : Analog `transmit' signal (upstream direction), line m : Analog `receive' signal (downstream direction), line m Alarm Bits - After initialisation (e.g. due to a hardware reset), the CODSP itself will make the upstream CI/Alarm bit active, and set the AlarmReg with an InitRequest value (i.e. "1xx"); the CI/Alarm bit will remain active until the InitRequest is cleared by the GCI supervisor (indicating that the supervisor has done the necessary re-initialisation of system parameters). - In order to check the contents of the AlarmReg, execute the following GCI command: ReadRequest ( MemId=2, Add=0x0010 ); This results in a 4 nibble value, e.g. "0xabgd", read by the supervisor. - In order to clear the InitRequest alarm, in principle one must only clear one bit. Therefore the supervisor should execute the following commands: NewValue = "0xabgd" AND "0xFFFB"; WriteRequest ( MemId=2, Add=0x0010, NewValue ); - Note that the other bits in the alarm register are updated by the DSP at a 8kHz rate, and that they are only used by the GCI supervisor; therefore the other bits might also be overwritten for one cycle, clearing all bits (inclusive the InitRequest bit) in one command: WriteRequest ( MemId=2, Add=0x0010, 0x0000 ); 46 MTK-40131 Meaning and Default Values of the Parameters Table 40: Data RAM: Description and Default Values Name Address Position Description Mapping Default Sh0, Sh1 00, 01 0 SHLIC test mode control bit 0: normal mode 1: test mode 0 (normal) Tst0, Tst1 00, 01 1 SHLIC test switch control bit 0: open switch 1: closed switch 0 (open) Br0, Br1 00, 01 2 SHLIC battery reversal control bit 0: non reversed 1: reversed 0 (non rev.) Bs0, Bs1 00, 01 3 SHLIC battery selection control bit for NonAct_X variant 0: BATS selection L 1: BATR selection H 0 (NonAct_L) Bsa0, Bsa1 00, 01 4 SHLIC battery selection control bit for ActAdsi_X variant 0: BATS selection L 1: BATR selection H 0 (ActAdsi_L) Bbs0, Bbs1 00, 01 6:5 SHLIC battery selection control bit for ActRng_Sph_X variant 0='00':BATS L 1='01':BATR H 2='10':BATS+bias LA 3='11':BATR+bias HA 0 (ActRng_Sph_L) TX_Gain_0 TX_Gain_1 03 04 15:0 Gain factor in TX direction for Line0 and Line1 20 log TX-Gain_* 320 320 (0dB) RX_Gain_0 05 15:0 Gain factor in RX direction RX_Gain_1 06 Dzd1, Dzd0 07 1:0 Disable digital zco path 0: enable 1: disable 1 (disabled) Td1, Td0 08 1:0 Disable Tx path at pdm level 0: enable 1: disable 0 (enabled) CurLim_Threshold 09 7:0 Current limitation threshold parameter val = 0 .. 127 unit = 0.63 mA (eq = 0 .. 80 mA) 51 (32 mA) CurLim_RLarge 09 15:8 Current limitation RLarge resistance parameter (Internal Resistance) val = 0 .. 210 unit = 47 (eq = 0 .. 10 k) 64 (3 k) RF 10 1:0 Ringing frequency 0='00': 16Hz 1='01': 20Hz 2='10': 25Hz 3='11': 50 Hz 3 (50Hz) RM 10 2 Ringing mode 0: onoff mode 1: burst mode 0 (onoff) RIL 10 3 Enable interleaved ringing 0: non interleaved 1: interleaved 1 (interl.) RW 10 5 Ringing waveform 0: sine wave 1: trapezoidal wave 0 (sine) Ringing_Amplitude 11 7:0 Amplitude of ringing signal val = 0 .. 255 unit = 194 mV rms 255 (max ampl) for Line0 and Line1 47 -7+20 log RX-Gain_* 384 384 ( -7dB) MTK-40131 Name Address Position Description Mapping Default Ringing_DC_Offset 11 15:8 DC offset of ringing signal (Between A&B-wire) val = 0 .. 255 unit = 250 mV 0 (no offset) Ringing_On_Period 12 7:0 Length of active ringing phase to be used in burst mode val = 0 .. 255 unit 32 msec 32 (1 sec) Ringing_Off_Period 12 15:8 Length of silent ringing phase to be used in burst mode val = 0 .. 255 unit 32 msec 96 (3 sec) LBO 13 3:0 GCI loopback register (encoding see below) val = 0 .. 15 0 (noloop) RTDAC_ThresholdHigh 14 7:0 Threshold Level high during ringing val = 0 .. 255 unit = 1,6 mA 27 (43,2 mA) RTDAC_ThresholdLow 14 15:8 Threshold Level low during ringing val = 0 .. 255 unit = 1,6 mA 7 (11,2 mA) RTDAC_GapTime 15 7:0 Gaptime during RTDAC Peak Detection val = 0 .. 255 unit = 125s 10 (1,25 ms) RTDAC_Debouncetime 15 15:8 Deb.Time during RTDAC 240 (30ms) AlarmReg 16 2:0 Alarm Status register (encoding see Table) val = 0 .. 255 unit=125s val = 0 .. 7 IDC1 17 7:0 DC line current of Line1, sampled at 2kHz val = " 0 ... 127 unit = 0.63 mA 0 IDC0 17 15:8 DC line current of Line0, sampled at 2kHz val = " 0 ... 127 unit = 0.63 mA 0 IAC0 18 15:0 AC line current of Line0, sampled at 8kHz unit = 215/1.6V @ Tx 0 IAC1 19 15:0 AC line current of Line1, sampled at 8kHz unit = 215/1.6V @ Tx 0 TG1, TG0 20 3,2 Tone Generator control bit for Line1 and Line0 0 : do not add tone 1 : add tone 0 (no tone) MS1, MS0 20 1,0 Mute Speech control bit for Line1 and Line0 0 : pass speech 1 : mute speech 0 (no mute) TestTone_Ampl1_L0 TestTone_Ampl1_L1 21 22 7:0 Amplitude of first sine for Line0 and Line1 val = 0 ... 255 63 (0dBm) TestTone_Ampl2_L0 TestTone_Ampl2_L1 23 24 7:0 Amplitude of second sine for Line0 and Line1 val = 0 ... 255 63 (0dBm) TestTone_Freq1_L0 TestTone_Freq1_L1 25 26 15:0 Frequency of first sine for Line0 and Line1 unit = 250 Hz / 256 1024/256 (1kHz) TestTone_Freq2_L0 TestTone_Freq2_L1 27 28 15:0 Frequency of second sine for Line0 and Line1 unit = 250 Hz / 256 512/256 (500Hz) ACG 29 7:0 Rx Amplitude correction for ZCO synthesis val = 0 ... 255 /128 103/128 (600 Ohm) 48 4(InitReq'st) MTK-40131 Name Address Position Pd1, Pd0 30 11:10 Sleep2 (2) 30 13:12 Sleep1 (2) 30 2:0 Rzd1, Rzd0 30 4:3 DialP_SatTxLevel 31 15:0 DialP_DebTime 32 15:0 Description Mapping Default Power denial mode line 1 Low power activation 1 = enable 0 = disable 00 = inactive 11 = active val = 0 ... 7 eq = 0 ... 70% sleepy 0: enable 1: disable 0 (disable) 00 active 0 (0% sleep) 0 (enabled) Tx Saturation level to be used for dial pulse detection unit = 48,83V @ Tx 8192 (400mV) Debounce time to be used for dial pulse detection unit = 125us 40 (5 ms) Sleep factor to be used when one line inactive Disable analog zco path Note : (1) parameter names with figure 0 or 1 at the end reffer to the analog line 0 or line 1 (2) In low power applications: recommended program value is sleep 1 = 5 combined with sleep 2 = 3 will save power consumption when only 1 line off-hock. 49 MTK-40131 CoProcessor Coefficient RAM MemID = 4 Table 41: Coprocessor Coefficient RAM: Memory Map Address 00 (0x0000) 11 10 9 8 7 6 Rx32KFilter coefficient : r0 01 (0x0001) r1 02 (0x0002) r4 03 (0x0003) s1 04 (0x0004) s2 05 (0x0005) r2 06 (0x0006) r3 07 (0x0007) r5 08 (0x0008) s3 09 (0x0009) s4 10 (0x000A) m0 11 (0x000B) m1 12 (0x000C) u0 13 (0x000D) u1 14 (0x000E) Hyb16KFilter coefficient : h0 15 (0x000F) h1 16 (0x0010) h2 17 (0x0011) h3 18 (0x0012) a0 19 (0x0013) c5 20 (0x0014) b0 21 (0x0015) Tx32KFilter coefficient : t0 22 (0x0016) t1 23 (0x0017) t8 24 (0x0018) q1 25 (0x0019) q2 26 (0x001A) t2 27 (0x001B) t3 28 (0x001C) t9 29 (0x001D) q3 30 (0x001E) q4 31 (0x001F) t4 32 (0x0020) t5 50 5 4 3 2 1 0 MTK-40131 Address 11 10 9 8 7 6 33 (0x0021) t10 34 (0x0022) q5 35 (0x0023) t6 36 (0x0024) t7 37 (0x0025) t11 38 (0x0026) q6 39 (0x0027) q7 40 (0x0028) c2 41 (0x0029) c3 42 (0x002A) ZcoTxFilter coefficient : Ftx 43 (0x002B) Ap 44 (0x002C) NAn 45 (0x002C) 46 (0x002C) Access is similar to that of the Data RAM parameters. Note however that the GCI commands work with 2-byte values whereas the memory contains only 3-nibble values; because all values are <12,0>, the most significant nibble 5 Constants : HLF ONE_EIGHT of the 2-byte GCI value will be a signextension of the 12-bit value, in the case of a ReadRequest; the most significant nibble of a WriteRequest will be neglected. 51 4 3 2 1 0 MTK-40131 Meaning and Default Values of the Parameters Table 42: Coprocessor Coefficient RAM: Description and Default Values Name Address Position Description Mapping Default r0 00 11:0 Rx filter coefficient unit = intval / 512 int96 r1 01 11:0 Rx filter coefficient unit = intval / 512 int-78 r4 02 11:0 Rx filter coefficient unit = intval / 512 int96 s1 03 11:0 Rx filter coefficient unit = intval / 512 int642 s2 04 11:0 Rx filter coefficient unit = intval / 512 int-263 r2 05 11:0 Rx filter coefficient unit = intval / 512 int256 r3 06 11:0 Rx filter coefficient unit = intval / 512 int-303 r5 07 11:0 Rx filter coefficient unit = intval / 512 int256 s3 08 11:0 Rx filter coefficient unit = intval / 512 int746 s4 09 11:0 Rx filter coefficient unit = intval / 512 int-450 m0 10 11:0 Rx filter coefficient unit = intval / 512 int512 m1 11 11:0 Rx filter coefficient unit = intval / 512 int512 u0 12 11:0 Rx filter coefficient unit = intval / 512 int0 u1 13 11:0 Rx filter coefficient unit = intval / 512 int0 h0 14 11:0 Echo Cancelling coefficient unit = intval / 512 int-109 h1 15 11:0 Echo Cancelling coefficient unit = intval / 512 int2 h2 16 11:0 Echo Cancelling coefficient unit = intval / 512 int8 h3 17 11:0 Echo Cancelling coefficient unit = intval / 512 int32 a0 18 11:0 Echo Cancelling coefficient unit = intval / 512 int127 c5 19 11:0 Echo Cancelling coefficient unit = intval / 512 int512 b0 20 11:0 Echo Cancelling coefficient unit = intval / 512 int157 t0 21 11:0 Tx filter coefficient unit = intval / 512 int48 t1 22 11:0 Tx filter coefficient unit = intval / 512 int-37 t8 23 11:0 Tx filter coefficient unit = intval / 512 int48 q1 24 11:0 Tx filter coefficient unit = intval / 512 int728 q2 25 11:0 Tx filter coefficient unit = intval / 512 int-439 t2 26 11:0 Tx filter coefficient unit = intval / 512 int390 t3 27 11:0 Tx filter coefficient unit = intval / 512 int-492 t9 28 11:0 Tx filter coefficient unit = intval / 512 int390 q3 29 11:0 Tx filter coefficient unit = intval / 512 int573 q4 30 11:0 Tx filter coefficient unit = intval / 512 int-227 t4 31 11:0 Tx filter coefficient unit = intval / 512 int64 t5 32 11:0 Tx filter coefficient unit = intval / 512 int128 t10 33 11:0 Tx filter coefficient unit = intval / 512 int64 52 MTK-40131 Name Address Position Description Mapping Default q5 34 11:0 Tx filter coefficient unit = intval / 512 int442 t6 35 11:0 Tx filter coefficient unit = intval / 512 int384 t7 36 11:0 Tx filter coefficient unit = intval / 512 int-768 t11 37 11:0 Tx filter coefficient unit = intval / 512 int384 q6 38 11:0 Tx filter coefficient unit = intval / 512 int962 q7 39 11:0 Tx filter coefficient unit = intval / 512 int-458 c2 40 11:0 Tx filter coefficient unit = intval / 512 int512 c3 41 11:0 Tx filter coefficient unit = intval / 512 int-512 Ftx 42 11:0 ZcoTx filter coefficient unit = intval / 512 int237 Ap 43 11:0 ZcoTx filter coefficient unit = intval / 512 int0 NAn 44 11:0 ZcoTx filter coefficient unit = intval / 512 int0 HLF 45 11:0 Constant definition unit = intval / 512 int256 46 11:0 Constant definition unit = intval / 512 int64 ONE_EIGHT SHARED Memory MemID = 5 Table 43: Shared Memory: Memory Map Address 15 14 85 (0x0055) 86 (0x0056) 13 12 11 10 VLM 9 8 HT 7 6 5 Deb SpiDo SpiDi SpiSk SpiCs SpiSe RBD SR* 4 3 MF MM SR* 87 (0x0057) HSD_ThresholdHigh HSD_ThresholdLow 88 (0x0058) RTD_ThresholdHigh RTD_ThresholdLow 89 (0x0059) MeteringDutyCycle 90 (0x005A) 91 (0x005B) ZcoShAlfa3 ZcoA2 Rxd* RZco ZcoGamma 94 (0x005E) Alo* 2 1 0 SR* SR* Sleep * ZcoAlfa3 TL Note : Bit positions and memory locations not described here must not be changed. 53 MTK-40131 Meaning and Default Values of the Parameters Table 44: Shared Memory: Description and Default Values Name Address Position Description Mapping Default VLM 85 14:11 Metering amplitude (unit value = dependin on Zco) val = 0 .. 15 3 HT 85 10:9 HSD debounce time 0 = '00' : 8ms 1 = '01' : 24ms 2 = '10' : 16ms 3 = '11' : 64ms 2 (16ms) DEB 85 8 RTD debounce time 0 : 0 ms 1 : 30 ms 1 (30ms) MF 85 4 Metering frequency 0 : 12kHz 1 : 16kHz 1 (16kHz ) MM 85 3 Metering mode 0 : burst mode 1 : onoff mode 1 (onoff) SPIDO 86 15 SPI Dout port 0 SPIDI 86 14 SPI Din port 0 SPISK 86 13 SPI SK port 0 SPICS 86 12 SPI CS port 0 SPISE RBD 86 86 11 10 SR (1) 86 5:4 1:0 SPI port selection Disable automatic ring activation of Spick and Spick software resets of SID1, SID0, CP, GCI Soft Resets (2) 86 5:0 HSD_ThresholdHigh 87 HSD_ThresholdLow 1 = disabled 0 = enabled 0 0 (enabled) 1 = reset block 0 = no reset 0 Reset ability of HW blocks (SID0, SID1, MRT, LS, CP, GCI) 0: no reset 1: reset block 0 (no reset) 13:7 HSD high threshold val = 0 .. 127 unit = 0.63mA = 0 .. 80 mA) 16 (10mA) 87 6:0 HSD low threshold val = 0 .. 127 unit = 0.63mA = 0 .. 80 mA) 10 (6.3mA) RTD_ThresholdHigh 88 13:7 RTD high threshold val = 0 .. 127 unit = 0.63mA = 0 .. 80 mA) 16 (10mA) RTD_ThresholdLow 88 6:0 RTD low threshold val = 0 .. 127 unit = 0.63mA = 0 .. 80 mA) 10 (6.3mA) MeteringDutyCycle 89 15:8 Length of the metering burst to be used in "burst" metering mode val = 0 .. 255 unit = 2ms = 0 .. 510ms) 150 (300ms) ZcoShAlfa3 90 15:1 Central office Impedance parameter (1) 0 (600) 54 MTK-40131 Name Address Position Description Mapping Default Central office Impedance parameter (1) ZcoA2 90 13:7 0 (600 ) RxD (1) 90 6 RxDisable at input of analog part Analog loopback at pdm 0: enabled rx path 1: disable rx path 0: disabled loop 1: enable loop 0 (enabled) 0 (disabled) ALO (2) 90 4 Sleep (2) 90 2:0 Sleep factor actually used by the processor val = 0 ... 7 = 0 ... 70% sleepy 0 (0% sleep) RZco 91 11:8 Central office Impedance parameter (1) 3 (600) ZcoGamma 91 7:4 Central office Impedance parameter (1) 0 (600) ZcoAlfa3 91 3:0 (1) TL 94 1:0 Central office Impedance parameter Transcode Law selection 0 (600) 0 (A-Law) Notes : (1) Examples of other Zco parameters are listed on page 19 ` Examples Zco Coefficient' in this manual. Else: contact Alcatel Microelectronics for assistance. (2) Do not change these values. Package :General Dimensions of the MTC-20232PQ 55 0 = `00': A Law 1 = `01': N Law 2 = `10': Linear MTK-40131 Package: General Dimensions of the MTC-30132SO .299(7.60) .291(7.40) .420(10.65) .393(10.00) .030(0.75) .009(0.25) .020(0.49) .013(0.35) 0 - 8 .713(18.10) .696(17.70) .050 TYP x 45 .105(2.65) .092(2.35) .010TYP) .050(1.27) .015(0.40) .012(0.30) .003(0.10) 28 lead small outline plastic DWG.NR 87-0038 Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document. This document contains information on a new product. Alcatel Microelectronics reserves the right to make changes in specifications at any time and without notice. The information furnished by Alcatel Microelectronics in this document is believed to be accurate and reliable. However, no responsibility is assumed by Alcatel Microelectronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No licence is granted under any patents or patent rights of Alcatel Microelectronics. Alcatel Microelectronics info@mie.alcatel.be http://www.alcatel.com/telecom/micro Sales Offices Sales & Design Centres Central Europe Arabellastrae 4 81925 Munchen Germany Stuttgart Office Schwieberdingerstrae 9 70435 Stuttgart Germany Benelux & Nordic Countries Excelsiorlaan 44-46 1930 Zaventem Belgium Southern Europe 10, rue Latecoere, B.P.57 78140 Velizy Cedex France Italy & Mediter.area Via Trento 30 20059 Vimercate MI Italy USA M/S 412-115 1225 N. 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