MTC-30132SO-I - Alcatel - Datasheet.Directory

Key features

▼Digitally programmed

transmission and signalling

characteristics meets

world-wide specification

requirements

▼Integrated ringing, sine or

trapezoid

▼Metering injection

▼Battery reversal

▼Tone generators for signalling

and test

▼Minimal external components

▼CODEC and SLIC functions for

2 lines

▼Low-cost POTS interface for

short range

▼Standard GCI interface

Applications

▼Advanced ISDN NT (NTplus)

▼Analog / Digital PABX

▼Cable Telephone systems

(set-top box)

▼Remote telephone access

systems

Fibre to the curb

Radio in the loop

▼Internet telephones

MTC-20232 CODSP

MTC-30132 SH LIC

MTK-40131

SH POTS chipset

Rev. 1.31 - December 1998

Data Sheet and

User Manual

Fig. 1: Application Sketch / Block Diagram

General Description

The MTK-40131 chipset provides all

the functions necessary to connect ana-

log telephone sets or other analog ter-

minals (telefax, answering machines,

modems etc...) into digital communica-

tion systems. It provides an economical

solution for the traditional ‘BORSHT’

functions found in central-office

exchanges, but optimised for short-

range communication (e.g. up to 500m

with 4 RENs attached). Virtually all sys-

tem-dependent parameters can be set

under software control, giving a hither-

to unprecedented flexibility to the sys-

tem integrator, as well as optimising the

system cost. The digital interface to the

SH POTS chipset uses the industry-stan-

dard “GCI”* interface. The system

architecture has been designed to offer

the most cost-effective solution for short-

haul systems, yet offers the full flexibility

required to meet world-wide analog

telephony standards. Suitable for

Q.552 applications.

The MTK-40131 chipset comprises three

devices (see fig 1.): A pair of high-volt-

age device, the Short-Haul Line Interface

Circuit (SH LIC) which provides the sig-

nal and power interface to the analog

lines (one per line) and a low-voltage

CMOS, DSP-based dual CODEC/con-

trol device (CODSP) which provides all

signal processing and control functions

for up to two lines.

(* The General Circuit Interface (GCI) is an interface specification,

developed jointly by Alcatel, Italtel, GPT and Siemens;

date March 1989; issue 1.0)

Ordering Information

Part number Package Code Temp

MTK-40131-C Includ.MTC-20232PQ-C 44 pinPQFP PQ44 0 to -70°C

2x MTC-30132SO-C 28 pinSO SO28 0 to -70°C

MTK-40131-I Includ.MTC-20232PQ-I 44 pinPQFP PQ44 -40/+85°C

2x MTC-30132SO-I 28 pinSO SO28 -40/+85°C

MTK-40131

MTC-30132

SH LIC

28 PSOP

GNDB

BAT

BATS

SSB

BATR

DCO

DCI

RNG

DCC

TST

VAG

DCLF1

VDDA

DCLF2

GNDA

V3V

Package / Pinout

Fig. 2: Device Pinouts

MTC-20232

CODSP

44 PQFP

PU[0]

SPDI

SPICS

SPICK

SPIDO

PWRS

RNG[0]

TST[0]

BR[0]

TEST

ZOUT

JTDO

JTCK

JTMS

JTDI

JTRS

V3VD

DCL

FSC

GNDD

AD2

AD1

AD0

GCIM

TST[1]

BR[1]

RNG[1]

PU[1]

SCLK

PLLCK

CPLL

RX[0]

TX[0]

DCC[0]

DCO[0]

DCC[1]

DCO[1]

GNDA

VAG

V3VA

TX[1]

RX[1]

MTK-40131

Table of Content

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Note on Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional Characteristics of the SH POTS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

On-hook Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ringing Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Battery Voltage and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AC Transmission Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Transmit and Receive Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Source Impedance (Zco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Balance Impedance (Echo Canceller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Off-hook Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Metering Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CODSP Clock Recovery PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

User-Defined I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Thermal Shutdown SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Transient Energy Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC Characteristics (MTC-30132 SHLIC, unless otherwise noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

V3V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AW, BW DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

RX, TX DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DCO DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

VAG Analog Ground Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SA,SB Sense Bridge Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DC loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DCC Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Characteristics for the Digital I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Test Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Battery Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC Characteristics (SHLIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Overpower and Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MTK-40131

Quality / Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Detailed Programming Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

C/I Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

C/I Bit Allocation:C/I Bit Allocation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

ID Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Memory Map of the CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Global Memory Map and MemID Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

CoProcessor Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

SHARED Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

General dimensions of the MTC-20232PQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

General dimensions of the MTC-30132SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

MTK-40131

List of Figures

Fig. 1: Application Sketch / Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Fig. 2: Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Fig. 3: Application schematic for 2 analog lines (see Table 3 for component values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Fig. 4: MTC-20132 CODSP Recommended Power-Supply Decoupling Arrangements . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Fig. 5: Recommended overvoltage protection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Fig. 6: SH POTS Line voltages - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Fig. 7: Nominal hook-switch detection thresholds (default values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Fig. 8: DC Feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Fig. 9: Transmit and receive frequency response (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Fig. 10: Relative Group delay, transmit and receive paths (Digital to Digital) refered to 1kHz . . . . . . . . . . . . . . . . . . . . . . 18

Fig. 11: 3-element Zco model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Fig. 12: Metering pulse timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Fig. 13: Application suggestion for Semi-unbalanced ringing injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Fig. 14: Block diagram showing the gains in the various signal paths in the SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Fig. 15: Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Fig. 16: GCI data exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Fig. 17: GCI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MTK-40131

List of Tables

Table 1: Pin description for MTC-20232PQ CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2: Pin description for MTC-30132SO SH LIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3: Recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4: MTC-20232 CODSP unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5: MTC-30132 SH LIC unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6: Table 6: On-hook Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7: Ringing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8: DC Feed Characteristics (Rfeed = 60Ωtotal (50Ω+10Ωprotection) x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9: Examples of ZCO Coëfficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10: Off-hook Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11: Metering Characteristics (Determinized by MTC-20232 CODSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12: Tone signal levels (common values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13: Tone Generator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14: Tone generator division values for common frequencies from ETS-300-001, and DTMF tones . . . . . . . . . . . . . . . 24

Table 15: Required frequency setting values (N) for a melody generator (western equal-tempered scale) . . . . . . . . . . . . . . 25

Table 16: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18: SHLIC Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 19: Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20: Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21: V3V Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22: Voltage Characteristics A Wire, B Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23: Impedance Characteristics A Wire, B Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 24: RX, TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25: DCO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26: VAG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 27: Sense Bridge Inputs Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 28: DC Loop Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 29: DCC Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 30: Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 31: Test Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 32: Ringing Battery Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 33: Typical Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 34: Short Circuit Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 35: GCI Mode and Timeslot address programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 36: GCI Interface: Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 37: Memory Map for CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 38: Data RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 39: LBO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 40: Data RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 41: Coprocessor Coefficient RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 42: Coprocessor Coefficient RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 43: Shared Memory: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 44: Shared Memory: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

MTK-40131

Pin Description

Pin Name Description

1 JTDO JTAG Test port data out

2 JTCK JTAG Test port clock

3 JTMS JTAG Test port mode select

4 JTDI JTAG Test port Data In

5 JTRS JTAG Test port reset

6 V3VD Digital section supply voltage

7 DU GCI port upstream data

8 DD GCI port downstream data

9 DCL GCI port data clock

10 FSC GCI port frame clock

11 GNDD Digital ground (0V)

12 AD2 GCI port timeslot select, MSB

13 AD1 GCI port timeslot select

14 AD0 GCI port timeslot select, LSB

15 GCIM GCI port operating mode (0 = 1 timeslot, 1 = 8 timeslots)

16 TST[1] SH LIC 1 test select

17 BR[1] SH LIC 1 Bat Reverse control

18 RNG[1] SH LIC 1 Ring control

19 PU[1] SH LIC 1 Power-up control

20 SCLK system clock (test only)

21 PLLCK PLL clock (test only)

22 CPLL PLL loop filter capacitor

23 RX[1] SH LIC 1 RX analog signal

24 TX[1] SH LIC 1 TX analog signal

25 V3VA Analog supply voltage

26 VAG Analog ground reference voltage output

27 GNDA Analog ground (0V)

28 DCO[1] SH LIC 1 DC loop output

29 DCC[1] SH LIC 1 DC loop control

30 DCO[0] SH LIC 0 DC loop output

31 DCC[0] SH LIC 0 DC loop control

32 TX[0] SH LIC 0 TX analog signal

33 RX[0] SH LIC 0 RX analog signal

34 ZOUT Digital I/O drive control (test only)

35 TEST Test mode select (test only)

36 TST[0] SH LIC 0 test select

37 BR[0] SH LIC 0 Bat Reverse control

38 RNG[0] SH LIC 0 Ring control

39 PU[0] SH LIC 0 Power-up control

40 SPIDI SPI port data in (User I/O)

41 SPICS SPI port chip-select (User I/O)

42 SPICK SPI port clock (User I/O)

43 SPIDO SPI port data out (User I/O)

44 PWRS Reset input

Table 1: Pin description for MTC-20232PQ CODSP

MTK-40131

Table 2: Pin description for MTC-30132SO SH LIC

Pin Name Description

1 GNDB Battery ground (0V)

2 BW B wire output

3 BAT Battery voltage (output, do not connect)

4 BATS Battery voltage input, SPEECH mode

5 BATR Battery voltage input, RING mode

6 PU Power-up control

7 NC Do not connect. Thermal conduction pin

8 NC Do not connect. Thermal conduction pin

9 RNG Ring mode control

10 BR Battery Reverse control

11 TST Test mode control

12 VAG Analog Ground reference input

13 VDDA Analog supply voltage

14 GNDA Analog Ground, 0V

15 V3V 3V regulator output

16 DCLF1 DC bias filter capacitor 1

17 DCLF2 DC bias filter capacitor 2

18 RX Analog receive signal

19 TX Analog transmit signal

20 DCC DC loop control input

21 NC Do not connect. Thermal conduction pin

22 NC Do not connect. Thermal conduction pin

23 DCI DC loop control separation filter input

24 DCO DC loop control output

25 SSB Loop test resistor switch

26 SB B-wire sense input

27 SA A-wire sense input

28 AW A-wire output

MTK-40131

Application Schematic

CODSP

SH LIC

SSB

BATS

BATR

VDDA

GNDB

DCLF1

DCLF2

GNDA

V3V

TST[0]

BR[0]

RNG[0]

PU[0]

DCC

DCO

DCI

VAG

Vbats

Vbatr

VddA

Cvag

Cdci

CV3VD

Cb1

Cb2

RB2

RB1

Ztest

Cf1

Cf2

protection

LINE

RX[0]

TX[0]

DCC[0]

DCO[0]

VAG

TST

RNG

SH LIC

SSB

BATS

BATR

VDDA

GNDB

DCLF1

DCLF2

GNDA

V3V

TST[1]

BR[1]

RNG[1]

PU[1]

DCC

DCO

DCI

VAG

Vbats

Vbatr

VddA

Cdci

CV3VA

Cb1

Cb2

RB2

RB1

Ztest

protection

LINE

RX[1]

TX[1]

DCC[1]

DCO[1]

TST

RNG

CPLL

Cpll

GNDD

GNDA

V3VD

SPIDI

SPIDO

SPICS

SPICK

PLLCK

GCIM

FSC

DCL

AD0

AD1

AD2

GCI mode

and timeslot

address

GCI port

User

Outputs

(optional)

JTDI

JTDO

JTCK

JTMS

JTRS

TEST

ZOUT

JTAG test

access

Device

test

Cpwrs

PWRS

V3VD

Rpwrs

0,1

V3VD

BAT

SCLK

Rf1

Rf2

Cf1

Cf2

Rf1

Rf2

Rprot

CV3VA

Fig. 3: Application schematic for 2 analog lines (see Table 3 for component values).

MTK-40131

Table 3: Recommended external components

Component Function Value Comment

RB1, RB2 Feed resistor 50Ω1/4 W ±1% *

Rprot Protection resistance 2x10Ω

Ztest Test resistor 510Ω1/4 W, optional

Rf1, Rf2 DC bias filter 10kΩ

Cb1, Cb2 No-load stabilisation 1nF 100V **

Cdci DC feed separation 330nF 5%

Cf1,Cf2 DC bias filter 470nF 100V, 10%

Cvag Analog ground decoupling 100nF

CV3VA Analog 3,3V regulator decoupling 10µF+100nF

CV3VD Digital 3,3V decoupling 10µF+100nF

Cs, Cd Battery supply decoupling 100nF 100V

Cpll PLL loop filter 4.7nF

Cpwrs Power-on reset delay 100nF

Rpws Power-on reset delay 100kΩ

D1 Power loss reset Any small signal diode

Dp Battery input protection BAT46 Required depending on

the power supplies

* ±1% results in a maximum longitudinal balance of 40dB. For higher values, more

precise matching is required (e.g. ±0.1% for 46dB).

** Capacitors are generally not required. They are foreseen to stabilise the line dri-

ver outputs when active but driving no load (test condition only).

MTK-40131

Table 4: MTC-20232 CODSP unused pin connectionsUnused Pins

CODSP:

Pins which are not used in the applica-

tion should be connected as described

here. Failure to do so could result in

excessive sensitivity to RFI, or other

erratic behaviour. ‘0’ or ‘1’ indicates

that the pin should be connected to

ground or to the device’s digital supply.

‘-’ indicates that the pins is an output

and must be left unconnected.

Pin # Connect to

SPDO 43 -

GCIM 15 0,1 (GCI mode select)

AD0 14 0,1 (GCI timeslot select)

AD1 13 0,1 (GCI timeslot select)

AD2 12 0,1 (GCI timeslot select)

JTDI 4 0

JTDO 1 -

JTCK 2 0

JTMS 3 0

JTRS 5 1

SCLK 20 0

PLLCK 21 0

ZOUT 34 0

TEST 35 0

Table 5: MTC-30132 SH LIC unused pin connections

Pin # Connect to

BAT 3 No Connect or see text below

NC 7 No Connect or see text below

NC 8 No Connect or see text below

NC 21 No Connect or see text below

SHLIC:

The pins NC (7, 8, 21 and 22) are

connected to the device substrate,

which is at a voltage equal to the

VBATR supply pin, and may optionally

be electrically connected to this pin.

The pin BAT is the internal supply to the

line-drivers, and adopts the voltage of

VBATR or VBATS, plus the voltage drop

across the internal switch, depending

on the operating mode. In low-voltage

only systems (very short connections,

the pins BAT, VBATR and VBATS may

all be connected together, and a single

supply (e.g. -27V) used for both ringing

and speech modes. (In this mode, the

voltage drop of the internal switches is

avoided).

MTK-40131

Note on Decoupling

As in any system, the PCB layout and

supply decoupling can influence the

system performance, particularly with

respect to noise.

CODSP:

• It is recommended to connect V3VD

and V3VA (digital and analog sup-

ply pins) in a star configuration from

the supply (either from the SH LIC or

an external supply), and each pin be

independently decoupled using 10µF

in parallel with 100nF.

In 2-line systems using the SHLIC’s

regulator to supply the CODSP only

(i.e. no other use is made of the regu-

lator), one SHLIC may be used to

provide V3VD power and the other

V3VA, thus giving improved decou-

pling between analog and digital

supplies. See figure 4.

• The VAG line (analog signal refer-

ence) must always be properly

decoupled using 100nF, placed as

close as possible to the CODSP

device.

SHLIC:

• The SHLIC should use separate

100nF decoupling capacitors

between VDD and GNDB and VDD

and GNDA. When the on-board reg-

ulator of the SHLIC is not used, no

capacitor is required at the V3V pin

of this device.

MTC-30132

SH LIC

MTC-30132

SH LIC

MTC-20132

CODSP

GNDD

V3VD

GNDA

V3VA

VAG

+3.3V Star point

Ground

star-point

GNDA

GNDB

GNDA

GNDB

MTC-30132

SH LIC

MTC-30132

SH LIC

MTC-20132

CODSP

GNDD

V3VD

GNDA

V3VA

VAG

Ground

star-point

GNDA

GNDB

GNDA

GNDB

V3V

10 µF Ta

100 nF Cer

Fig. 4: MTC-20132 CODSP Recommended Power-Supply

Decoupling Arrangements

RB1

Rpr1

RB2

Rpr2

BATR

GNDB

MTC-30132

SH LIC

RB1

Rpr1

RB2

Rpr2

GNDB

MTC-30132

SH LIC

RB1

Rpr1

RB2

Rpr2

GNDB

MTC-30132

SH LIC

RB1

Rpr1

RB2

Rpr2

GNDB

MTC-30132

SH LIC

Transient

Suppressor

MTK-40131

Overvoltage Protection

There are several recommended over-

voltage protection options. The applica-

tion will determine the most appropriate

one to chose (e.g. in-house only systems

with minimal protection requirements,

or systems with loops outside a protect-

ed environment requiring more extend-

ed protection).

The first external protection network to

protect the line circuit against foreign

voltages consists of the resistors Rpr1

and Rpr2 and an overvoltage protec-

tion component, see fig 5. The series

resistors Rpr1 and Rpr2 can be PTC,

poly-switch or fusible components.

For further protection, the simplest and

cheapest solution is a diode bridge

between SA,SB and GNDB, BATR

respectively. The diodes must be able to

allow current peaks more then 20A.

In case the battery BATR cannot accept

these high current peaks, one has to

add a voltage clamping component to

GND or a transient suppresser between

each line and GND. The clamp voltage

or protection voltage minimum must

always be larger then the maximum

used ringing battery BATR.

The protection components must be

dimensioned in such a way that the

transient energy on the chip pins AW,

BW does not exceed 1mJoule.(energy

on chip because of 1 lightning pulse)

Fig. 5: Recommended overvoltage protection options

VbatS

VbatR

(avg. DC = VbatR/2)

ON HOOK

ON HOOK ADSI

RING BURST

OFF HOOK

(saturation, <0.5V)

(bias, 3V)

(e.g. -24V)

(e.g. -64V)

(bias, 3V + drop

of BAT switch)

(bias, 3V + drop of BAT switch)

MTK-40131

Fig 6: SH POTS Line voltages - example.

Functional Characteristics of the SH POTS System

For reference, fig 6 shows the typical

voltages on both wires during various

stages of operation. For detailed electri-

cal parameters, please refer to the Elec-

trical Characteristics section.

On-hook Conditions

When a line is not in use (on-hook), the

designer may select either the speech

battery or the ringing battery as the sup-

ply to the line drivers. In this mode, most

of the internal circuits are put into a low

power operating mode, to minimise

supply currents. The A and B wire out-

puts are effectively connected to the

supply voltage, thus applying this volt-

age (minus a small saturation voltage)

to the line. The output is current limited

in this mode, thus protecting against

short circuits, and limiting any inrush

current when a set goes off hook. If the

SH LIC detects a current in excess of a

(programmable) limit, the off-hook con-

dition will be detected (an on-chip

debouncer with selectable delay avoids

accidental hookswitch detection), and

the circuit will be put into active speech

mode. The nominal off-hook detection

currents, and the hysteresis, are shown

in fig 7. When in the on-hook condi-

tion, the system designer may select,

under program control via the GCI bus,

an ‘on hook active mode’, whereby on-

hook signalling (ADSI, CLI etc..) can be

performed in either direction (note, how-

ever, that battery reversal is not avail-

able in this mode.).

MTK-40131

off-hook

on-hook

6.0

8.8

10.2

13.6

line current

Fig. 7: Nominal hook-switch detection thresholds (default values)

Parameter Conditions Min Max Units Note

Vfeedo Open-line feed voltage Vbats-1 Vbatr V 4

Ion Line current guaranteeing on-hook state 5.1 11.1 mA 1

Ioff Line current guaranteeing off-hook state 8.2 14.2 mA 1

Iohyst Hookswitch detect hysteresis 2 mA 1

Thks Hookswitch detect time 20 ms 2

Ioc Peak over-current limit, on-hook mode 145 mA 3

VbiasH Bias voltage during ADSI mode 2 4 V

VbiasL on a (H) and b (L) wires ref. BAT pin

Notes:

1. These are the default values, after

reset. The on-hook and off-hook thresh-

olds can be individually programmed in

the range 0 to 63mA nominal.

2. Time between off-hook condition and

the line current reaching 90% of its final

value.

3. This is the intrinsic current limit of the

output driver. This current can only be

seen during on-hook to off-hook tran-

sients, or during ringing into a short-cir-

cuit load during the ring-trip delay peri-

od. The actual value measured will

depend on the load resitance used.

4. Iline=0mA, independent of battery

reversal mode. This voltage is selected

by the user. The output impedance

when in the on-hook condition is set by

the sense resistors Rfeed.

The hook-switch detector has a pro-

grammable debounce timer. Times of 8,

16, 24 or 64 ms can be selected (com-

mon for both channels).

Table 6: On-hook Characteristics

6.3 10.0

MTK-40131

Parameter Conditions Min Max Units Note

Fr Ringing frequency

16.66, 20, 25 Hz -1 +1 Hz

50 Hz -2 +2 Hz

SFNr Single-frequency noise, 10 Hz to 4 kHz -63 dBm

Vr Ringing voltage (max), Vbatr=-72V 50 Vrms 4

Dr Ringing distortion, sine mode

30Hz to 132 kHz 5 %

Trtd Ring-trip delay, load = 500Ω+4µF 150 ms

Trtdeb Ring-trip de-bounce time 0 30 ms 3

Trtzc Ring-trip detect zero-cross mask time 1.75 ms 2

Tc Ring-cadence times (active and silent) 1 255 n/n 1

IrtH Ring-trip current, high threshold 6.0 12.0 mA 2

IrtL Ring-trip current, low threshold 3.5 9.5 mA 2

Hrt Ring-trip hysteresis 2 mA 2

Notes:

1. Units are periods of the selected ring-

ing frequency. The default values are 1s

on, 3s off with a ringing frequency of

50Hz.

2. These are the default values, after

reset. The max and min ring-trip thresh-

olds can be individually programmed

in the range 0 to 63mA(!) nominal. The

ring-trip detect mask time is used to

bridge the zero-crossings of the ringing

signal, and is programmable between

0 and 32 ms in 125µs steps.

3. User-selectable 0 or 30ms. Default is

30 ms.

4. Ringing voltage is user programma-

ble from 0 to 70Vp(diff) between the a

and b wires (NB, the ringing battery

voltage must be large enough to encom-

pass this voltage), in 256 steps. The

default is the maximum value. Condi-

tion: Load = Ø mA

Ringing Injection

The SH POTS chipset is capable of

directly injecting a ringing signal of up

to 50Vrms (sine wave) without the need

for additional external components. The

technique of “balanced ringing” is

used, which allows this large voltage

swing to remain within the technology

limits of the SH LIC device. (Balanced

ringing requires a specific algorithm for

ring-trip detection, which is also imple-

mented by the chipset). The SH POTS

chipset allows the user to program a

DC offset during ringing as well as a

reduced amplitude ringing signal,

should the application require

this. Ringing waveform, frequency,

amplitude and cadence, as well as ring-

trip thresholds, are controlled by the

CODSP device, and are all program-

mable. Ringing cadence can be auto-

matic, with independently programma-

ble ring and pause times, or ringing

can be controlled directly via the GCI

bus. In automatic cadence mode, ring-

ing bursts on both channels can option-

ally be interleaved if simultaneously

active, to avoid peaks in current from

the ringing battery supply.

Table 7: Ringing Characteristics

DC Feed Characteristics

As shown in figure 8, the SH POTS

chip-set implements a constant-current

feed. The limit current and the residual

resistance (slope of the characteristic)

are both programmable by the user.

The DC characteristic falls into three

regions. When the combination of line

and subset result in a current less than

the programmed limit current, the sys-

tem behaves like a battery with a fixed

feed resistance of 120Ω, and a voltage

equivalent to the speech supply voltage

(VbatS) minus the bias voltage on both

lines (6V nominal in total). Should line

conditions permit a current which

exceeds the programmed limit current,

the system enters the constant-current

feed mode described above. In order to

protect the output stage in the transition

region at higher line currents (in excess

of 50mA), a third region is defined,

where the system synthesises a fixed

feed resistance of 200Ω. The slope of

the voltage/current characteristic in the

constant-current mode can be user pro-

grammed to select the effective feed-

resistance.

Note: The SH LIC device includes an

over-temperature protection, which acti-

vates in case of overheating of the

device.

Battery Voltage and Rever-

sal

The open-line voltage (i.e. the voltage

seen on the line when on-hook) is user-

selectable for each channel via an inter-

nal register. It can be either the ringing

battery supply (most common use) or

the speech battery supply. The speech

battery supply is automatically selected

when an off-hook condition is detected,

independently of these control bits. The

selected supply voltage is maintained

when the on-hook signalling function

(ADSI) is enabled.

The polarity of the line feed can be

dynamically controlled by the user. In

the ‘normal’ condition, the A-Wire is the

most positive. Reversal thus makes the B-

Wire the most positive. Battery reversal

is fast (not soft), is controlled by pro-

gramming an internal register and is

independent for both channels. The

selected polarity is used in all states (on-

hook, off-hook, ringing etc...) except on-

hook signalling which is normal battery

mode.

MTK-40131

Iline (mA)

Vline (V)

Vbats

VfN

(Programmable)

Rfeed

Rfeed=200Ω

Rfeed=120Ω

Fig 8: DC Feed characteristics.

Parameter Conditions Min Max Units Note

VbiasH Bias voltage, a wire (Iline=0) 2.5 3.5 V

VbiasL Bias voltage, b wire (Iline=0) 2.5 3.5 V

TOLIcl Current limit tolerance ±15 %

TRfeedcl Tolerance on programmed Rfeed ±15 %

when in current-limit

Icl Current-limit, useful programmed range 20 70 mA

Table 8: DC Feed Characteristics (Rfeed = 60Ωtotal (50Ω+10Ωprotection) x2)

MTK-40131

1500

1200

900

600

300

1800

500

600

1000

2000

2600

2800

frequency

µs

Delay

Fig 10: Relative Group delay, transmit and receive paths

(Digital to Digital) refered to 1kHz

16000

4600

3600

3400

3000

2400

600

400

300

200

receive

transmit

receive / transmit

-0.3

0.0

0.35

0.55

0.75

1.0

1.5

12.5

25.0

4000

Fig 9: Transmit and receive frequency response (default).

Transmit and Receive

Filter Characteristics

The Short-haul POTS chipset implements

transmit and receive filters according to

ITU-T (G.712). These filters can be

reprogrammed by the user for specific

requirements. Please contact Alcatel

Microelectronics for further details on

this. The default filter characteristics

implemented are shown in figures 9

and 10 below.

AC Transmission Characteristics (MTK-40131 System)

Transmit and Receive Gain

Transmit (from analog subset towards

the switching system) and receive gains

are user programmable, independently

for both lines. The default values are

0dBr in the transmit direction, and -

7dBr in the receive direction.

12.5 1 - SIN dB

π(4000-ƒ)

1200

MTK-40131

Source Impedance (Zco)

The central-office impedance, Zco, is

synthesised using digital signal proces-

sing techniques. This renders it very sta-

ble, and moreover programmable by

the user by means of coefficients which

are loaded via the GCI. Real or com-

plex Zco’s can be synthesised, using the

common 3-element model (Rs, Rp, Cp;

see fig 11). The Zco setting is common

for both lines. Both real and complex

Zco’s can be programmed to address

the local requirements of specifications

world-wide, and cover the range:

Using the default coefficient values, the

return loss when measured against

600Ω(using 0dBm input signal level) is

better than 20dB in the 300 to 3400

Hz band, and better than 10 dB at 10

kHz.

Real impedances: 600Ωto 900Ω

Complex impedances:

Rs from 160Ωto 500Ω

Rp from 300Ωto 1000Ω

Rp//Cp pole from 725 Hz to 5kHz

Fig. 11: 3-element Zco model.

Balance Impedance

(Echo Canceller)

The balance impedance (model of the

line+set impedance used to separate

the receive and transmit signals in the

‘hybrid’) is independently programma-

ble (though is the same for both

channels). Default values offer echo

return loss of better than 20dB, though

optimization to specific line and set

characteristics may yield further

improvement.

Rs Rp Cp ZcoSh Alfa3 ZcoA2 Rzco ZcoGamma ZcoAlfa3 Ftx Ap Nan ACG

Belgium 600 0 0 0 0 3 0 0 237 0 0 103

Germany 220 820 115nF 0 40 9 9 5 52 346 512 125

Europe 270 750 150nF 0 19 7 15 4 122 388 -179 125

ZCO850 850 0 0 0 0 0 0 0 282 0 0 123

ZCO900 900 0 0 0 0 0 0 0 290 0 0 126

Table 9: Examples of ZCO Coefficients

h0 h1 h2 h3 a0 c5 b0 Dzd0 Dzd1

Belgium 4 -22 105 95 0 0 0 1 1

Germany -31 48 1 156 0 0 0 0 0

Europe 3 -23 118 88 0 0 0 0 0

ZCO850 4 -22 105 95 0 0 0 1 1

ZCO900 4 -22 105 95 0 0 0 1 1

MTK-40131

Off-hook Characteristics (MTK-40131 System)

Parameter Conditions Min Max Units Note

Gtx Relative gain, transmit direction -6 +1 dB 1

Gain programming step 0.25 dB

Step accuracy 0.1 dB

Gain tolerance (ref. programmed value) -0.5 +0.5 dB

Grx Relative gain, receive direction -12 +1 dB 1

Gain programming step 0.25 dB

Step accuracy 0.05 dB

Gain tolerance (ref. programmed value) -0.5 +0.5 dB

dGlt Long-term gain stability -0.5 +0.5 dB 2

Gttx Gain tracking, TX path

+3 to -40 dBm0 ±0.3 dB 3

-40 to -50 dBm0 ±0.6 dB 3

-50 to -55 dBm0 ±1.6 dB 3

Gtrx Gain tracking, RX path

+3 to -40 dBm0 ±0.3 dB 3

-40 to -50 dBm0 ±0.6 dB 3

-50 to -55 dBm0 ±1.6 dB 3

IMDtx Intermodulation distortion, TX path -45 dBm0 4

IMDrx Intermodulation distortion, RX path -50 dBm0 4

Sdtx Signal to total distortion ratio, TX (gain= 0 dB)

-0 to -10 dBm0 35 dB 5

-20 dBm0 34.7 dB

-30 dBm0 32.9 dB

-40 dBm0 24.9 dB

-45 dBm0 19.9 dB

Sdrx Signal to total distortion ratio, RX (gain= - 7 dB)

-0 to -10 dBm0 35 dB 5

-20 dBm0 33.8 dB

-30 dBm0 28.8 dB

-40 dBm0 19.5 dB

-45 dBm0 14.5 dB

SFNrx Single frequency noise

300 to 3400 Hz, all out of band freqs. -40 dB

700 to 1100 Hz in band 300 to 3400Hz -49 dB

Longitudinal balance

Resistor matching 1% 40 dB

0.1% 46 dB

Notes:

1. User programmable.

2. Covers variations within the permit-

ted ranges of supply voltage and tem-

perature during any one year.

3. Referred to the gain at 1020 Hz

applied to the input at a level -10dBm0.

4. Intermodulation distortion measured

for all intermodulation products of any

non-harmonically related frequencies in

the range 300 to 3400 Hz for levels

between -4 and -21 dBm0.

5. Intermodulation distortion measured

for all intermodulation products of a fre-

quency in the range 300 to 3400 Hz at

-9dBm0 and 50Hz at -23dBm0.

Table 10: Off-hook Characteristics (MTK-40131 System)

Conditions: see paragraph "operating conditions"

MTK-40131

Metering Injection

Metering pulses of selectable frequency

(12 or 16 kHz) and programmable

amplitude can be injected into either

analog channel independently. The

width of the injected pulse is determi-

ned by the user (“on/off mode”), or by

an internal timer (“burst mode”) which

can be set by the user from 2ms to 510

ms in steps of 2ms. The metering signal

is always a multiple of half metering

periods. See fig. 12.

metering

/MPI

metering

/MPI

on/off mode

burst mode

tmburst

Fig. 12: Metering pulse timing diagrams.

The metering level on the line is set by: Vlm = (Vgen . Zm)/(Zm + Zcom)

where:

Vlm = metering pulse level on the line

Vgen = set level of the metering generator

Zm = impedance of the metering load

Zcom = CO impedance at the metering frequency.

The metering level Vgen is selectable

from 0 to a maximum level of

230mVrms (500m line with

Zco=900Ω) in 15 linear steps. The

internal tolerance on the metering sig-

nal level is ±10%.

Metering is initiated on a channel by

an active low state on the correspond-

ing /MPI bit in the GCI C/I byte.

MTK-40131

Metering Characteristics (Determinized by MTC-20232 CODSP)

Parameter Conditions Min Max Units Note

Fml Metering frequency, 12kHz -60 +60 Hz (≈±0.5%)

Fmh Metering frequency, 16kHz -80 +80 Hz (≈±0.5%)

SFN1 Single-frequency noise, subharmonics

for 12kHz, 30Hz to 12 kHz -69 dBm0

for 16kHz, 30Hz to 12 kHz -69 dBm0

SFN2 Single-frequency noise, mixed products

12kHz, 12kHz to 20kHz -51 dBm0

12kHz, 20kHz to 132kHz -69 dBm0

16kHz -69 dBm0

Nmc In-band noise due to metering signal -60 dBmp 1

Nmt Transient noise due to metering pulse -35 dBm0 1

THDm Metering total harmonic distortion,

30 Hz to 132 kHz, out of CODSP 0.5 %

Dm Metering signal distortion at load 5 % on 200Ω

Vlm Metering pulse amplitude, maximum 207 253 mVrms (≈±10%)

level with Zco=900Ω, Rline=130Ω

SYMm Metering symmetry, a and b wires 24 dB (≈max 6%)

SFNtx Single frequency noise, mixed products,

10Hz to 4 kHz, TX path -63 dBm

Note:

Measured in accordance to ITU-T speci-

fication 071 (Blue Book)

Table 11: Metering Characteristics (Determinized by MTC-20232 CODSP)

Conditions: see paragraph "operating conditions"

MTK-40131

Tone Generation

The SH POTS system allows the injection

of user programmable tones, inde-

pendently per channel, for signalling or

user test purposes. Per channel, a tone

comprising two programmable (sine-

wave) frequencies and programmable

amplitudes can be generated (in this

way, the most common call-progress and

information tones, melody notes or DTMF

tones, can be synthesised). The tone sig-

nal is added to the speech signal (the

user must be aware of possible clipping

which may occur if high signal levels are

programmed), or the speech

signal can also be muted during a tone

burst. The tone burst duration is under

user control only (the control bits for mute

and tone insertion occupy the same reg-

ister, which simplifies the generation of

tone bursts).

dBm n Actual err (dB)

3 89 3.00 0.00

1.5 75 1.51 0.01

0 63 0.00 0.00

-1.5 53 -1.50 0.00

-3 45 -2.92 0.08

-6 32 -5.88 0.12

-8 25 -8.03 -0.03

-10 20 -9.97 0.03

-15 11 -15.16 -0.16

-20 6 -20.42 -0.42

-30 2 -29.97 0.03

-36 1 -35.99 0.01

Note that it is possible to generate tones

of very high amplitude. The user must

ensure that the amplitude parameter is

programmed before the tone is

enabled.

Table 12: Tone signal levels (common values)

The tone frequency is given by:

Fout = 250 * N / 256 Hz, where N is a 16 bit value

(thus, N=1024 yields a tone of 1 kHz)

N = int(Fout*256/250 + 0.5)

The tone generated has continuous

phase if the programmed frequency is

changed during the course of a tone

(this is not so if the generator is stopped

and restarted). Tables 2 and 3 list the

values of N required to generate com-

monly occurring frequencies, and the

resulting error.

The amplitude of each frequency within

the tone can be independently set from

0 to the maximum level in 256 linear

amplitude steps (8 bit value), with

n=63 corresponding to 0dBm on the

line. From this, the line signal level Vtl

for a given gain factor n is given by:

Vtl = 20 log(n/63) in dBm.

n = int(63*10^(Vtl/20) + 0.5)

Table 11 lists values for n for a range

of tone signal levels.

Common signalling frequencies

Freq. (Hz) N Actual Freq. error (%)

300.00 307 299.805 -0.07

320.00 328 320.313 0.10

325.00 333 325.195 0.06

340.00 348 339.844 -0.05

350.00 358 349.609 -0.11

375.00 384 375.000 0.00

380.00 389 379.883 -0.03

382.50 392 382.813 0.08

400.00 410 400.391 0.10

410.00 420 410.156 0.04

420.00 430 419.922 -0.02

440.00 451 440.430 0.10

450.00 461 450.195 0.04

455.00 466 455.078 0.02

475.00 486 474.609 -0.08

490.00 502 490.234 0.05

500.00 512 500.000 0.00

525.00 538 525.391 0.07

550.00 563 549.805 -0.04

DTMF tones

Freq. (Hz) N Actual Freq. error (%)

697.00 714 697.266 0.04

770.00 788 769.531 -0.06

852.00 872 851.563 -0.05

941.00 964 941.406 0.04

1209.00 1238 1208.984 0.00

1336.00 1368 1335.938 0.00

1477.00 1512 1476.563 -0.03

1633.00 1672 1632.813 -0.01

MTK-40131

Table 14: Tone generator division values for common frequencies

from ETS-300-001, and DTMF tones

Parameter Conditions Min Max Units Note

SFNtx Single frequency noise, mixed products,

10Hz to 4 kHz, TX path -63 dBm

Table 13: Tone Generator Characteristics

MTK-40131

Octave Note Freq. (Hz) N Actual error (%)

2 C 261.626 268 261.719 0.04 (middle-C)

2 C# 277.183 284 277.344 0.06

2 D 293.665 301 293.945 0.10

2 Eb 311.127 319 311.523 0.13

2 E 329.628 338 330.078 0.14

2 F 349.228 358 349.609 0.11

2 F# 369.994 379 370.117 0.03

2 G 391.995 401 391.602 -0.10

2 Ab 415.305 425 415.039 -0.06

2 A 440.000 451 440.430 0.10

2 Bb 466.164 477 465.820 -0.07

2 B 493.883 506 494.141 0.05

3 C 523.251 536 523.438 0.04

3 C# 554.365 568 554.688 0.06

3 D 587.330 601 586.914 -0.07

3 Eb 622.254 637 622.070 -0.03

3 E 659.255 675 659.180 -0.01

3 F 698.456 715 698.242 -0.03

3 F# 739.989 758 740.234 0.03

3 G 783.991 803 784.180 0.02

3 Ab 830.609 851 831.055 0.05

3 A 880.000 901 879.883 -0.01

3 Bb 932.328 955 932.617 0.03

3 B 987.767 1011 987.305 -0.05

4 C 1046.502 1072 1046.875 0.04

4 C# 1108.731 1135 1108.398 -0.03

4 D 1174.659 1203 1174.805 0.01

4 Eb 1244.508 1274 1244.141 -0.03

4 E 1318.510 1350 1318.359 -0.01

4 F 1396.913 1430 1396.484 -0.03

4 F# 1479.978 1515 1479.492 -0.03

4 G 1567.982 1606 1568.359 0.02

4 Ab 1661.219 1701 1661.133 -0.01

4 A 1760.000 1802 1759.766 -0.01

4 Bb 1864.655 1909 1864.258 -0.02

4 B 1975.533 2023 1975.586 0.00

5 C 2093.005 2143 2092.773 -0.01

5 C# 2217.461 2271 2217.773 0.01

5 D 2349.318 2406 2349.609 0.01

5 Eb 2489.016 2549 2489.258 0.01

5 E 2637.020 2700 2636.719 -0.01

5 F 2793.826 2861 2793.945 0.00

5 F# 2959.955 3031 2959.961 0.00

5 G 3135.963 3211 3135.742 -0.01

5 Ab 3322.438 3402 3322.266 -0.01

5 A 3520.000 3604 3519.531 -0.01

5 Bb 3729.310 3819 3729.492 0.00

5 B 3951.066 4046 3951.172 0.00

Table 15: Required frequency setting values (N) for a melody generator (western equal-tempered scale)

MTK-40131

Rfeed

line

protection

-VbatR

47µF

rly

+5V

SPICK

(Line 0)

SPICS

(Line 1)

Fig 13: Application suggestion for Semi-unbalanced ringing injection.

CODSP Clock Recovery

PLL

The CODSP device derives its internal

clocks from the GCI’s DCL input by

means of a PLL. The PLL automatically

detects the clock mode in use, and sets

the multiplication factor accordingly.

The PLL loop filter requires an external

capacitor as shown in the application

schematic.

User-Defined I/O Pins

The pins SPIDI, SPICS and SPICK are

part of an SPI port which is used by Alca-

tel Microelectronics during product evalu-

ation and testing. They are available to

the user, via the GCI, as output bits (e.g.

for driving small indicator LEDs). The pin

SPIDO is used as part of the power-up

and testing routines, and the behaviour

during power-up cannot be guaranteed.

It is therefore advised not to make use of

this pin for any other purposes. The out-

puts can source or sink a maximum of

4mA each.

Note: In order to support “semi-unba-

lanced ringing” (DC bias equal to VbatR

superimposed on the differential ringing

signal), two of these outputs will be

active high during the active ringing

period on each channel (SPICK for chan-

nel 0 and SPICS for channel 1). This can

be used to drive a relay via an external

NPN transistor as shown in fig 13.

Test functions

Please contact Alcatel Microelectronics.

MTK-40131

Electrical Characteristics

Absolute Maximum Ratings

Operation of the device at or near

these conditions is not guaranteed. Sustained exposure to these limits will

adversely affect device reliability.

Parameter Symbol Min. Max. Unit

Battery voltage BATR (ref. To GNDB) of SHLIC BATR -75 +0.5 V

Battery voltage BATS (ref. To GNDB) of SHLIC BATS -35 +0.5 V

Difference between the batteries BATR and BATS, BATR-BATS of SHLIC DBAT -40 +0.5 V

VDDA (ref. to GNDA) of SHLIC VDDA -0.5 +7 V

GNDB (ref. to GNDA) of SHLIC GNDB -0.5 +0.5 V

Ambient temperaure under bias of SHLIC -40 +85

Maximum absolute power dissipation, Tamb. = 85°C 1.3 W

V3VA,V3VD to CODSP V3V VSS-0.3 4 V

Voltage on any device pin * of CODSP Vin VSS-0.3 V3V+0.3 V

Function temperature under bias of CODSP -55 +150 °C

Storage temperature -65 +150 W

Lead temperature (soldering 10 sec.) +300 °C

* except special 5V tolerant I/O’s of CODSP

All voltages referenced to GNDA = GNDB or VSS = GNDA, as appropriate.

(*)

see paragraph Thermal shutdown: Max power dissipation is depending on

Max Ambiant temperature

Operating Conditions

Operating ranges define the limits for

functional operation and parametric

characteristics of the device as descri-

bed in this documents, and for

the reliability specifications. Correct

functioning outside of these limits is not

implied. Total cumulative exposure out-

side the normal power supply

voltage range or the ambient tempera-

ture under bias, must be less than 0.1 %

of the normal useful life as defined in

the Reliability section.

Symbol Parameter Limits Unit

Min. Typ. Max.

BATR Ringing battery voltage -72 -65 -18 V

BATS Speech battery voltage -35 -32 -18 V

DBAT Difference between the batteries

BATR and BATS, BATR-BATS -40 -35 0 V

VDDA Supply voltage SHLIC 4.75 5 5.5 V

Trange Operating temperature range - I -40 85 °C(*)

SHLIC - C 0 70 °C

V3VD

V3VA VDD of CODSP (3.3V± 8%) 3.036 3.3 3.564 V

Trange Operating temperature range - I -40 85 °C

CODSP - C 0 70 °C

Table 17: Operating Conditions

Table 16: Absolute Maximum Ratings

MTK-40131

Thermal Shutdown

SHLIC

Thermal limiting circuitry on chip of the

SHLIC will shut down the circuit at a

junction temperature of about 165 °C.

The device should never see this tem-

perature and operation above 145 °C

junction temperature might degrade

device reliability.

Parameter Symbol Value Unit

Maximum operating power dissipation, Tamb. = 70 °C Pmax_op 1.2 W

Thermal resistance = 55°C/w typ.

The specifications for power dissipation

imply that in ring mode the active ring

phase must at least be 4 times shorter

than the non active ring phase. The

maximum duration of the active ring

phase must be below 2 s.

Transient Energy Capability

During testing, each device termination

withstands being shorted to the supply

voltages or ground as specified below.

The shorting must be limited to one sec-

ond.

Shorted to GNDA, VDDA or GNDB:

VAG, PU, RNG, BR, TST, TA, DCC, DCO, DCI, TX to RX

Shorted to GNDA, GNDB or BATS:

AW, BW, SA to SB

Table 18: SHLIC Dissipation

MTK-40131

DC Characteristics

(MTC-30132 SHLIC,

unless otherwise noted)

Unless otherwise stated, these charac-

teristics apply for the operating condi-

tions specified above. All parameters

are explicitly or implicitly tested during

production at the operating conditions

unless they are marked with a *, where

they are guaranteed by design. Para-

meters marked with ** are meant as

user information only. Tests are per-

formed using an equivalent of the appli-

cation schematic.

Power Supply Currents

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Power RNG=0 0.35 0.5 mA

Ibatr BATR current (IL = 0) Up RNG=1 3.5 5.0 mA

Power RNG=0 0.35 0.5 mA

Down RNG=1 2.5 3.5 mA

Power RNG=0 3.5 5 mA

Ibats BATS current (IL = 0) Up RNG=1 3.5 5 mA

Power RNG=0 1.5 2.5 mA

Down RNG=1 0.5 mA

Ivdd VDD current (IV3V=0) PowerUp 3 5.5 mA

PowerDown 2.5 4 mA

Pcc Power dissipation of CODSP PowerDown 30 mW

(@ 3,45V V3VA and V3VD) PowerUp 1 line active ✝140 mW

PowerUp 2 lines active 180 mW

Notes:

IL is the line current, i.e. these parameters are measured without line current.

IV3V is the load current in pin V3V

The maximum values in the table are valid for the full battery voltage ranges :

-18V to -72V for ringing battery BATR

-18V to -35V for battery BATS. (BATR must be always the most negative one)

✝

In case of sleep mode activation. See tables "Data Ram: Memory Map, description and default val-

ues" for programing values.

Table 19: Power Supply Currents

MTK-40131

Power-on Reset

The table shows the power reset thresh-

old for VDD of the SHLIC. As long as

VDD is below the reset threshold, the

SHLIC is held in power down, and the

output pins AW and BW are high

impedance.

The CODSP uses a separate input pin

PWRS for system reset at power-up.

V3V Regulator

This series regulator of the SHLIC can

be used to provide the supply voltage

for the CODSP or other 3.3V devices.

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

VDDPWR Threshold voltage for power 3.0 3.5 4.0 V

reset on VDD of SHLIC

TPWRS Active low pulse width on 10 ms

PWRS of CODSP

VPWRS Threshold voltage for reset 1.6 1.7 V

on PWRS of CODSP

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Vv3v V3V output voltage load current Iv3v 3.05 3.3 3.55 V

between 0 and 50mA

Iload load current range 0 50 mA

PSRR signal rejection VDD to frequency range 0 to 20 dB

V3V 10KHz

Lreg load regulation load current range from -1 1 ohm

5 to 50mA

Cload (**) maximum load load current range from 100 nF

capacitance 0 to 50mA

Icc(*) current limitation shorted V3V shorted to AGND 70 200 mA

output

Table 20: Power-on Reset Characteristics

Table 21: V3V Regulator Characteristics

MTK-40131

A-wire, B-wire DC- Levels, Impedances

Symbol Parameter Test Conditions Limits Unit

PU BR RNG Min. Typ. Max.

Vawn Normal DC-bias on AW(ref. GNDB) 1 0 0 -3.5 -3.1 -2.7 V

Vbwn Normal DC-bias on BW(ref. BAT) 1 0 0 2.5 3 3.5 V

Vawr Reverse polarity DC-bias on AW (ref BAT) 1 1 0 2.5 3 3.5 V

Vbwr Reverse polarity DC-bias on BW (ref. GNDB) 1 1 0 -3.5 -3.1 -2.7 V

Vaw_h DC bias on AW in Act_H mode (TST=1, ref. GNDB) 1 x 1 -4 -3 -2 V

Vbw_h DC bias on BW in Act_H mode (TST=1, ref. BAT) 1 x 1 2 3 4 V

Vhwpd Voltage level high wire (IL<5mA) 0 x 0 -0.8 -0.5 V

Vlwpd Voltage level low wire (IL<5mA), ref BAT 0 x 0 0.5 0.8 V

Vawring DC-level both wires in ringing mode (TST=0) 1 0 1 BAT/2 BAT/2 BAT/2 V

Vbwring -2% +2%

Note:

These BIAS values are only valid if both DCC and RX are biased at VAG voltage level.

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Za(b)wo Output impedance at AW (BW) 0mA<IL<70mA 1.5 ohm

(*) (power up) 0<f<16 kHz

Za-bwo Tracking of the output impedance 0mA<IL<70mA 0.3 ohm

(*) onAW and BW 0<f<16 kHz

Zhwod Output impedance on high wire PU=0 5 130 ohm

(power down)

Zlwod Output impedance on low wire PU=0 5 130 ohm

(power down)

Zomd Matching output impedance low vs PU=0 -70 70 ohm

high wire (power down)

Ia(b)OC Output current in and out AW (BW) A(B)W_GNDB -700 +700 µA

Ia(b)HIMP with OT (over-temperature) detected and

A(B)W_BATS

Table 22: Voltage Characteristics A Wire (Aw), B Wire (Bw)

Table 23: Impedance Characteristics A Wire (Aw), B Wire (Bw)

MTK-40131

RX, TX DC- Levels, Impedances

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Ztx (*) Output impedance at TX f = 1 kHz 10 ohm

Votx Offset voltage on TX (PU=1) SA shorted to -20 0 20 mV

(ref VAG) AW and SB to

BW, DCI to V3V,

DCO to VAG

Iouttx TX output current capability -1 0.05 mA

Vrx(*) Rx input voltage range(ref. VAG) -1 1 V

Zrx Rx input impedance f = 1kHz 20 kohm

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Zdco (*) Output impedance at DCO 10 ohm

Vodco Offset voltage on DCO(ref. VAG) SA shorted to -20 0 20 mV

AW and SB to

Ioutdco (*) DCO output current capability -1 0.05 mA

Zdci Input impedance at DCI f=1kHz 210 Kohm

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Vvag (**) Voltage level at VAG pin CODSP 1.53 1.65 1.77 V

Ivag VAG input current SH LIC VAG=1.65V 0.5 mA

DCO DC- Levels, Impedances

These limits are generally transparent

to the user, but are given here for infor-

mation.

VAG Analog Ground Input

The analog ground is typical half the

voltage of the V3V output voltage. It is the reference for all the analog

interfacing between SHLIC and the

CODSP. VAG is provided by the

CODSP.

Table 24: RX, TX Characteristics

Table 25: DCO Characteristics

Table 26: VAG Characteristics

MTK-40131

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

VDCLF1 DCLF1 output voltage(ref. GNDB) RNG=0, PU=1 -3.5 -3.1 -2.7 V

VDCLF2 DCLF2 output voltage(ref. BAT) RNG=0, PU=1 2.5 3.0 3.5 V

ZDCLF1s Output impedance at DCLF, VDCLF- RNG=0, PU=1 0.6 1 1.4 Mohm

VDCLF1< 0.5V

ZDCLF2s Output impedance at DCLF, VDCLF2- RNG=0, PU=1 0.6 1 1.4 Mohm

VDCLF< 0.5V

DC loop filter

These limits are generally transparent

to the user, but are given here for

information.

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

VDCC DCC input voltage range (ref. VAG) RNG=0, PU=1 -1 1 V

IinDCC DCC input current, VDCC=VAG+1V RNG=0, PU=1 4 10 uA

DCC Input Pin

These limits are generally transparent

to the user, but are given here for

information.

Note:

Forcing DCC positive (ref. VAG) will result in a smaller voltage between A- and B-

wire. It a too large signal is applied at DCC, both wires are clamped at the same

voltage (only a small residual voltage remains on the line).

SA,SB Sense Bridge Inputs

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Raw-sb bridge resistance from AW to SB VDD, VAG=0V, 25°C 205 257 309 Kohm

Rsa-bw bridge resistance from BW to SA VDD, VAG=0V, 25°C 205 257 309 Kohm

Table 27: Sense Bridge Inputs Characteristics

Table 28: DC Loop Filter Characteristics

Table 29: DCC Input Characteristics

MTK-40131

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Vil Low level input voltage 0.3*V3VD V

Vih High level input voltage 0.7*V3VD V

Iil Low level input current VDD = 5.25 V -1 +1 µA

(except PU, see below RPD)

Iih High level input current VDD = 5.25 V -1 +1 µA

(except PU, see below RPD)

Cinp (*) Input capacitance 7 pF

RPD Pull down resistance at pin PU 18 30 40 kohm

VOL output level PU pin, driven low Overtemperature OT 0.5 V

activated, Ipu=0.2mA,

Tested at high temp.

only.

VIL Low-level input voltage, CODSP 0.2*V3VD 3V3D

VIH High-level input voltage, CODSP 0.8*V3VD 3V3D

VOL Low-level output voltage, CODSP 0.4 V

VOH High-level output voltage, CODSP 0.8*V3VD 3V3D

CIN Input pin capacitance, CODSP 1 pF

COUT Load capacitance, CODSP 100 pF

Characteristics for the Digi-

tal I/O pins

CODSP, plus TST, PU, BR, RNG of

SHLIC

Test Switch

The internal test switch is between the

pins SB and SSB. Connecting an exter-

nal load between SSB and SA allows

test of the transmission characteristics in

(simulated) off- and on hook conditions.

The typical on-resistance of the test

switch is around 75 ohms, and has to

be taken into account when defining the

external load. The test switch is on

when RNG=0, PU=1, TST=1, BR=0

Table 30: Digital I/O Characteristics

MTK-40131

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Ibswoff(*) leakage current battery switch BATR=-72V, BATS=-32V 5 uA

(RNG=0)

Irevbats(*) reverse current BATS diode BATR=-72V, BATS=-32V 5 uA

(RNG=1)

Vdrbats forward drop BATS diode load current < 80mA 0.85 1.2 V

Ibson current capability battery switch 0 80 mA

Vbswon voltage drop over load current < 80mA 1 2 V

battery switch (RNG=1)

Battery Switch

This switch is activated during ringing

or when the higher on-hook voltage is

selected (RNG=1). When active, BATR

is connected to the internal battery

supply line VBAT. In other cases

(RNG=0), the switch is open; VBAT is

now connected to BATS via an internal

diode.

Symbol Parameter Test Conditions Limits Unit

Min. Typ. Max.

Iswoff switch leakage current |Vssb-Vsb| < 72V 5 uA

Vswon voltage drop over testswitch Isw=80mA 4 9 V

Isw=20mA 1 3 V

(VSSB-VSB > 0V)

Note:

The test switch is normally off when VDD is below the reset level.

If the battery voltages are sufficient, the switch remains on when it was

on before VDD went below the reset level.

Table 31: Test Switch Characteristics

Table 32: Ringing Battery Switch Characteristics

MTK-40131

AC Characteristics

(SHLIC)

(0 dBm : 1 mW in 600 ohm)

Unless otherwise stated, the characteris-

tic limits apply over the operating condi-

tions specified above, and each combi-

nation of the drive bits unless otherwise

stated.

All parameters are specified in the pres-

ence of a longitudinal current of max. 5

mAp and a DC current of between 0

mA and the current limit. The behaviour

of the chip in presence of longitudinal

voltages is not tested in production.

The different gains in the signal paths

are shown in fig 14. The values of the

gains are in the following table.

BWBIAS

VabVLZL

Sense

Bridge

AWBIAS

RB I/O to ADSP

(Ref. VAG)

DCC

DCO

Fig. 14: Block diagram showing the gains in the various signal

paths in the SHLIC.

Gain Factor

G1 + 1.66

G1’ 0.079

G2 2

G3 -2

G4 15

G5 - 1/8

GR 1

GR’ 35/2

The gains in the table above are not

tested. They are mentioned for informa-

tion only. The pin-to-pin gains as listed

in the tables below (Grx, Gtx, …) are

tested and guaranteed

In case of Ringing, the receive gain is

changed from GR to GR’, the transmit

gain factor G1 is changed to G1’.

The default test condition of the input

bits is: PU=1, RNG=0, BR=0/1. DCC

is shorted to VAG.

Rprot

Receive Path

Equation :

Grx Vab

Vrx GR G G== −()32

This equation is valid for an open loop

configuration. This does not incorporate

the Zco synthesis, which is defined by

the feedback from TX to RX. This func-

tion is performed in the CODSP.

Transmit Path

Equation :

Gtx Vx

VL RB

ZL G==

This equation is valid under open loop

conditions.

Table 33: Typical Gains

MTK-40131

Overpower and Short Circuit

Protection

In power down, the DC-loop current lim-

itation is not active. The line current is

limited directly through the line

drivers.

The AW and BW outputs are fully pro-

tected against short circuits to a voltage

between GNDA/GNDB and BATR (see

fig. 15).

GNDB

BATR

GNDB

Vbw

Vaw

RS1

RS2

Vsb

Vsa

RS1=RS2 ≥ 0.3Ω

Fig. 15: Short circuit protection

MTK-40131

The current flowing from (or into) AW

and/or BW is limited to a value

ILW/IHW as long as the junction tem-

perature Tj < 165°C (electronic current

limitation). The values for ILW/IHW for

different conditions are given in the

table below. If Tj rises above 165°C (±

15 %) the output drivers outputs are

made high impedant. Current can only

flow in or out the internal protection

diodes, in case Vsa and/or Vsb

exceeds the range between GND and

BATR. The currents should however be

limited externally (internal clamping

diodes protection): see section over-

voltage protection.

Parameter Test Conditions Limits Unit

Min. Typ. Max.

ILW Short circuit peak current, PU=1 -145 -120 -95 mA

power up, sink current

Short circuit peak current, PU=0 -65 -45 -20 mA

power down, sink current

IHW Short circuit peak current, PU=1 95 120 145 mA

power up, source current

Short circuit peak current, PU=0 20 45 65 mA

power down, source current

Table 34: Short Circuit Protection Characteristics

MTK-40131

Detailed Programming Description

GCI Interface

The SH POTS system uses the GCI stan-

dard interface to exchange B channel

data (PCM coded voice) and control

information with the controlling system.

GCI data is exchanged in both direc-

tions (downstream, towards the analog

line, and upstream, from the analog

line) in 4-byte frames at a rate of 8000

frames per second (the standard PCM

sampling rate).

SH POTS GCI Interface: Modes

DCL

FSC

DU/DD

ONE TIMESLOT

Monitor

C/I

8 kHZ GCI Frame CLock

SINGLE TIMESLOT MODE : FSC = 8 kHz

DCL = 512 kHz ; data rate = 256 k

bit/sec

DCL

FSC

DU/DD

8 kHZ GCI Frame CLock

TIMESLOT 1

TIMESLOT 2

TIMESLOT 8

MULTIPLEXED TIMESLOT MODE : FSC = 8

kHz DCL = 4096 kHz ; data rate = 2048 k

bit/sec

SH POTS GCI Interface: Timing

Fig 16: GCI data exchange.

Voice information or data is transmitted

via the “Bearer” channels B1 and B2.

Real-time signalling information for the

two channels are communicated via the

6 C/I bits (the 2 least significant bits of

the C/I byte are used to manage com-

munication via the Monitor channel).

Programming and status information is

communicated by means of commands

over the Monitor channel.

MTK-40131

Table 35: GCI mode and Timeslot address programming

GCIM AD2 AD1 AD0 Time DCL Timeslot

slot frequency address

mode (kHz)

0 0 0 0 1 512 0

1 0 0 0 8 4096 0

1 0 0 1 8 4096 1

1 0 1 0 8 4096 2

1 0 1 1 8 4096 3

1 1 0 0 8 4096 4

1 1 0 1 8 4096 5

1 1 1 0 8 4096 6

1 1 1 1 8 4096 7

Timeslot Address

Frames can be formatted singly

(4 bytes per frame), or in a multi-

plexed mode whereby up to

8 GCI compatible devices can be

connected to the same bus. In the mul-

tiplexed mode, the frames of

4 bytes are transmitted in one of

8 timeslots - the mode and the timeslot

address of a particular GCI terminal

is set by means of strapping a code

on 3 device pins GCIM, AD0 to AD2

on the CODSP (see table 35). The

CODSP uses the GCI standard format

for analog terminals (see fig. 16).

MTK-40131

Signal Parameter Description Min Max Unit

inputs ViL input level Low 0.8 V

inputs ViH input level High 2.0 V

DU VoL output level Low 0.4 V

DU VoH output level High 2.4 V

DCL(2) tDCL Clock Period 1952 1955 ns

DCL(2) tr,tf Clock Rize/Fall 60 ns

DCL(2) twH,twH Pulse Width 800 ns

DCL(3) tDCL Clock Period 243.9 244.3 ns

DCL(3) twL,twH Pulse Width 90 ns

FSC tsF Frame Setup 70 DCL-60 ns

FSC tr,tf Frame rize/Fall 60 ns

FSC twFH Frame Width H 130 ns

FSC twFL Frame Width L tDCL ns

FSC thF Frame Hold 60 ns

DU(1) tdDC Data delay/Clock 100 ns

DU(1) tdDF Data delay/Frame 150 ns

DD tsD Data setup twH+20 ns

DD thD Data hold 60 ns

(1) Condition CL = 150pF

(2) 256 k bit/sec Transmission

(3) 2048 kbit/sec Transmission

twH

tDCL

twL

DCL

FSC

tsF

thF

twFH

tdDF

tdDC

tsD

thD

twFL

SH POTS GCI Interface: Timing

Fig 17: GCI Timing Diagram

Table 36: GCI Interface: Timing Characteristics

MTK-40131

C/I Bits

The C/I bits are used to transfer sig-

nalling information for both channels

simultaneously. The C/I bits must be sta-

ble for at least 2 consecutive GCI

frames before they will be recognised.

The bit allocations for both downstream

and upstream directions are shown in

the table. Note that the signals are

active low, meaning that the idle condi-

tion is a logic ‘1’.

Monitor Channel

The CODSP acts as a slave device on

the GCI - commands received in the

downstream direction are responded to

in the upstream direction.

The E and A bits in the C/I byte are

used to synchronise and acknowledge

the correct transfer of a monitor

channel byte.

/RNG Activate ringing

/MPI Activate metering pulse

/ADSI Activate on-hook signalling

/LS Off-hook condition detected (Loop Stable)

/AL Alarm (indicates any of the possible alarm conditions: initrequest, overpower detected)

/RPH Ring phase. Indicates that ADSI data can NOT be sent.

C/I Bit Allocation:

Direction C/I 7 C/I 6 C/I 5 C/I 4 C/I 3 C/I 2

Downstream /RNG0 /MPI0 /ADSI0 /RNG1 /MPI1 /ADSI1

Upstream /LS0 /AL0 /RPH0 /LS1 /AL1 /RPH1

ID Request

The IDrequest command returns 2 bytes:

(BBB is the memory block identifier or “MemID” - see below)

Other commands should not be used.

ID Request 1 0 0 0 0 0 0 0

Write request 1 0 0 0 1 B B B

Read request 1 0 0 1 1 B B B

Valid commands are:

byte 1 1 0 0 0 0 0 0 0 Command confirmation

byte 2 1 0 R R R R R R Revision code

This command returns a unique code for each device revision.

MTK-40131

Read Command

A read request command comprises 3 bytes:

Write Command

The write command comprises 5 bytes:

Command conf. Address high Address low Data high Data low

1 0 0 1 1 B B B n n n n n n n n n n n n n n n n d d d d d d d d d d d d d d d d

Command conf. Address high Address low Data high Data low

1 0 0 0 1 B B B n n n n n n n n n n n n n n n n d d d d d d d d d d d d d d d

The response is a 5 byte stream:

Read request Address high Address low

1 0 0 1 1 B B B n n n n n n n n n n n n n n n n

Global Memory Map and

MemID Definitions

• All addresses can be read and writ-

ten, though writing to locations or

individual bit which are not described

here may result in unpredictable,

though possibly interesting, behav-

iour.

• The memory block to be accessed is

given as part of the READ or WRITE

command (see above) as the ‘B’ bits

in the command byte.

• The default parameter and coefficient

values that are used at start-up and

after reset, are listed in the following

tables.

• The control registers of the SH POTS

system, accessed via the GCI, are

organised in a number of memory

blocks. Within each block, a number

of addresses are used directly to con-

trol the operation of specific functions

of the SH POTS system.

Memory Map of the CODSP

No bytes are returned

MTK-40131

Data RAM

MemID = 2

Address 15 14 13 12 11 10 987654321 0

00 (0x0000) Bbs0 Bsa0 Bs0 Br0 Tst0 Sh0

01 (0x0001) Bbs1 Bsa1 Bs1 Br1 Tst1 Sh1

02 (0x0002)

03 (0x0003) TX Gain 0

04 (0x0004) TX Gain 1

05 (0x0005) RX Gain 0

06 (0x0006) RX Gain 1

07 (0x0007) Dzd1 Dzd0

08 (0x0008) Td1 Td0

09 (0x0009) CurLim_Rlarge CurLim_Threshold

10 (0x000A) RW RIL RM RF

11 (0x000B) Ringing_DC_Offset Ringing_Amplitude

12 (0x000C) Ringing_Off_Period Ringing_On_Period

13 (0x000D) LBO

14 (0x000E) RTDAC_ThresholdLow RTDAC_ThresholdHigh

15 (0x000F) RTDAC_Debouncetime RTDAC_GapTime

16 (0x0010) AlarmReg

17 (0x0011) IDC0 IDC1

18 (0x0012) IAC0

19 (0x0013) IAC1

20 (0x0014) TG1 TG0 MS1 MS0

21 (0x0015) TestTone_Ampl1_L0

22 (0x0016) TestTone_Ampl1_L1

23 (0x0017) TestTone_Ampl2_L0

MemID Memory Start Address Memory Contents

2 Data RAM 0x 02 0000 C-code Read/Write Data

C-code Stack region

C-code IRQ Stack region

4 CoProcessor Coef RAM 0x 04 0000 Filter coefficients

5 SHARED RAM 0x 05 0000 Data Packet buffers

Label vectors, Fifo control

Table 37: Memory Map for CODSP

Table 38: Data RAM: Memory Map

MTK-40131

Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

24 (0x0018) TestTone_Ampl2_L1

25 (0x0019) TestTone_Freq1_L0

26 (0x001A) TestTone_Freq1_L1

27 (0x001B) TestTone_Freq2_L0

28 (0x001C) TestTone_Freq2_L1

29 (0x001D) ACG

30 (0x001E) Sleep2 Pd1 Pd0 Rzd1 Rzd0 Sleep1

31 (0x001F) DialP_SatTxLevel

32 (0x0020) DialP_DebTime

Note:

Bit positions and memory locations not documented must not be changed.

MTK-40131

LBO register

This register controls various loop-back

modes, as well as the routing of the

GCI B channels to/from the physical

line analog channels. The bits are

codes as follows:

BnDown : GCI B channel n, Downstream direction

BnUp : GCI B channel n, Upstream direction

TX(m) : Analog ‘transmit’ signal (upstream direction), line m

RX(m) : Analog ‘receive’ signal (downstream direction), line m

Alarm Bits

- After initialisation (e.g. due to a hardware reset), the CODSP itself will make the upstream CI/Alarm bit

active, and set the AlarmReg with an InitRequest value (i.e. ”1xx”); the CI/Alarm bit will remain active

until the InitRequest is cleared by the GCI supervisor (indicating that the supervisor has done the necessary

re-initialisation of system parameters).

Mode D2 D1 D0 GCI side Analog side

Normal 0 0 0 TX(0) -> B1Up B1Down -> RX(0)

TX(1) -> B2Up B2Down -> RX(1)

Simplex loop B2 0 0 1 TX(0) -> B1Up B1Down -> RX(0)

B2Down -> B2Up TX(1) -> RX(1)

Simplex loop B1 0 1 0 B1Down -> B1Up TX(0) -> RX(0)

TX(1) -> B2Up B2Down -> RX(1)

Simplex loop B1 and B2 0 1 1 B1Down -> B1Up TX(0) -> RX(0)

B2Down -> B2Up TX(1) -> RX(1)

Duplex loopback 1 0 0 B2Down -> B1Up TX(0) -> RX(1)

B1Down -> B2Up TX(1) -> RX(0)

Reserved 1 0 1

Reserved 1 1 0

Swap mode 1 1 1 TX(0) -> B2Up B1Down -> RX(1)

TX(1) -> B1Up B2Down -> RX(0)

- In order to check the contents of the AlarmReg, execute the following GCI command:

ReadRequest ( MemId=2, Add=0x0010 );

This results in a 4 nibble value, e.g. ”0xabgd”, read by the supervisor.

- In order to clear the InitRequest alarm, in principle one must only clear one bit.

Therefore the supervisor should execute the following commands:

NewValue = ”0xabgd” AND ”0xFFFB”;

WriteRequest ( MemId=2, Add=0x0010, NewValue );

- Note that the other bits in the alarm register are updated by the DSP at a 8kHz rate, and that they

are only used by the GCI supervisor; therefore the other bits might also be overwritten for one cycle,

clearing all bits (inclusive the InitRequest bit) in one command:

WriteRequest ( MemId=2, Add=0x0010, 0x0000 );

Table 39: LBO Register Description

MTK-40131

Meaning and Default Values of the Parameters

Name Address Position Description Mapping Default

Sh0, Sh1 00, 01 0 SHLIC test mode control bit 0: normal mode 0

1: test mode (normal)

Tst0, Tst1 00, 01 1 SHLIC test switch control bit 0: open switch 0

1: closed switch (open)

Br0, Br1 00, 01 2 SHLIC battery reversal control 0: non reversed 0

bit 1: reversed (non rev.)

Bs0, Bs1 00, 01 3 SHLIC battery selection control 0: BATS selection L 0

bit for NonAct_X variant 1: BATR selection H (NonAct_L)

Bsa0, Bsa1 00, 01 4 SHLIC battery selection control 0: BATS selection L 0

bit for ActAdsi_X variant 1: BATR selection H (ActAdsi_L)

Bbs0, Bbs1 00, 01 6:5 SHLIC battery selection control 0=’00’:BATS L 0

bit for ActRng_Sph_X variant 1=’01’:BATR H (ActRng_Sph_L)

2=’10’:BATS+bias LA

3=’11’:BATR+bias HA

TX_Gain_0 TX_Gain_1 03 15:0 Gain factor in TX direction 320

04 for Line0 and Line1 (0dB)

RX_Gain_0 05 15:0 Gain factor in RX direction 384

RX_Gain_1 06 for Line0 and Line1 ( -7dB)

Dzd1, Dzd0 07 1:0 Disable digital zco path 0: enable 1

1: disable (disabled)

Td1, Td0 08 1:0 Disable Tx path at 0: enable 0

pdm level 1: disable (enabled)

CurLim_Threshold 09 7:0 Current limitation val = 0 .. 127 51

threshold parameter unit = 0.63 mA (32 mA)

(eq = 0 .. 80 mA)

CurLim_RLarge 09 15:8 Current limitation val = 0 .. 210 64

RLarge resistance parameter unit = 47 (3 kΩ)

(Internal Resistance) (eq = 0 .. 10 kΩ)

RF 10 1:0 Ringing frequency 0=’00’: 16Hz 3

1=’01’: 20Hz (50Hz)

2=’10’: 25Hz

3=’11’: 50 Hz

RM 10 2 Ringing mode 0: onoff mode 0

1: burst mode (onoff)

RIL 10 3 Enable interleaved ringing 0: non interleaved 1

1: interleaved (interl.)

RW 10 5 Ringing waveform 0: sine wave 0

1: trapezoidal wave (sine)

Ringing_Amplitude 11 7:0 Amplitude of ringing signal val = 0 .. 255 255

unit = 194 mV rms (max ampl)

Table 40: Data RAM: Description and Default Values

20 log TX-Gain_*

320

-7+20 logRX-Gain_*

384

MTK-40131

Name Address Position Description Mapping Default

Ringing_DC_Offset 11 15:8 DC offset of ringing signal val = 0 .. 255 0

(Between A&B-wire) unit = 250 mV (no offset)

Ringing_On_Period 12 7:0 Length of active ringing val = 0 .. 255 32

phase unit ≈32 msec (1 sec)

to be used in burst mode

Ringing_Off_Period 12 15:8 Length of silent ringing phase val = 0 .. 255 96

to be used in burst mode unit ≈32 msec (3 sec)

LBO 13 3:0 GCI loopback register val = 0 .. 15 0

(encoding see below) (noloop)

RTDAC_ThresholdHigh 14 7:0 Threshold Level high val = 0 .. 255 27

during ringing unit = 1,6 mA (43,2 mA)

RTDAC_ThresholdLow 14 15:8 Threshold Level low val = 0 .. 255 7

during ringing unit = 1,6 mA (11,2 mA)

RTDAC_GapTime 15 7:0 Gaptime during val = 0 .. 255 10

RTDAC Peak Detection unit = 125µs (1,25 ms)

RTDAC_Debouncetime 15 15:8 Deb.Time during RTDAC val = 0 .. 255 240 (30ms)

unit=125µs

AlarmReg 16 2:0 Alarm Status register val = 0 .. 7 4(InitReq’st)

(encoding see Table)

IDC1 17 7:0 DC line current of Line1, val = ” 0 ... 127 0

sampled at 2kHz unit = 0.63 mA

IDC0 17 15:8 DC line current of Line0, val = ” 0 ... 127 0

sampled at 2kHz unit = 0.63 mA

IAC0 18 15:0 AC line current of Line0, unit = 215/1.6V @ Tx 0

sampled at 8kHz

IAC1 19 15:0 AC line current of Line1, unit = 215/1.6V @ Tx 0

sampled at 8kHz

TG1, TG0 20 3,2 Tone Generator control bit 0 : do not add tone 0

for Line1 and Line0 1 : add tone (no tone)

MS1, MS0 20 1,0 Mute Speech control bit 0 : pass speech 0

for Line1 and Line0 1 : mute speech (no mute)

TestTone_Ampl1_L0 21 7:0 Amplitude of first sine val = 0 ... 255 63

TestTone_Ampl1_L1 22 for Line0 and Line1 (0dBm)

TestTone_Ampl2_L0 23 7:0 Amplitude of second sine val = 0 ... 255 63

TestTone_Ampl2_L1 24 for Line0 and Line1 (0dBm)

TestTone_Freq1_L0 25 15:0 Frequency of first sine unit = 250 Hz / 256 1024/256

TestTone_Freq1_L1 26 for Line0 and Line1 (1kHz)

TestTone_Freq2_L0 27 15:0 Frequency of second sine unit = 250 Hz / 256 512/256

TestTone_Freq2_L1 28 for Line0 and Line1 (500Hz)

ACG 29 7:0 Rx Amplitude correction for val = 0 ... 255 /128 103/128

ZCO synthesis (600 Ohm)

MTK-40131

Name Address Position Description Mapping Default

Pd1, Pd0 30 11:10 Power denial mode 1 = enable 0

line 1 0 = disable (disable)

Sleep2 (2) 30 13:12 Low power activation 00 = inactive 00

11 = active active

Sleep1 (2) 30 2:0 Sleep factor to be used when val = 0 ... 7 0

one line inactive eq = 0 ... 70% sleepy (0% sleep)

Rzd1, Rzd0 30 4:3 Disable analog zco path 0: enable 0

1: disable (enabled)

DialP_SatTxLevel 31 15:0 Tx Saturation level to be used unit = 48,83µV @ Tx 8192

for dial pulse detection (400mV)

DialP_DebTime 32 15:0 Debounce time to be used for unit = 125us 40

dial pulse detection (5 ms)

Note :

(1)

parameter names with figure 0 or 1 at the end reffer to the analog line 0 or line 1

(2)

In low power applications: recommended program value is sleep 1 = 5 combined

with sleep 2 = 3 will save power consumption when only 1 line off-hock.

MTK-40131

CoProcessor Coefficient RAM

MemID = 4

Address 11 10 9 8 7 6 5 4 3 2 1 0

00 (0x0000) Rx32KFilter coefficient : r0

01 (0x0001) r1

02 (0x0002) r4

03 (0x0003) s1

04 (0x0004) s2

05 (0x0005) r2

06 (0x0006) r3

07 (0x0007) r5

08 (0x0008) s3

09 (0x0009) s4

10 (0x000A) m0

11 (0x000B) m1

12 (0x000C) u0

13 (0x000D) u1

14 (0x000E) Hyb16KFilter coefficient : h0

15 (0x000F) h1

16 (0x0010) h2

17 (0x0011) h3

18 (0x0012) a0

19 (0x0013) c5

20 (0x0014) b0

21 (0x0015) Tx32KFilter coefficient : t0

22 (0x0016) t1

23 (0x0017) t8

24 (0x0018) q1

25 (0x0019) q2

26 (0x001A) t2

27 (0x001B) t3

28 (0x001C) t9

29 (0x001D) q3

30 (0x001E) q4

31 (0x001F) t4

32 (0x0020) t5

Table 41: Coprocessor Coefficient RAM: Memory Map

MTK-40131

Address 11 10 9 8 7 6 5 4 3 2 1 0

33 (0x0021) t10

34 (0x0022) q5

35 (0x0023) t6

36 (0x0024) t7

37 (0x0025) t11

38 (0x0026) q6

39 (0x0027) q7

40 (0x0028) c2

41 (0x0029) c3

42 (0x002A) ZcoTxFilter coefficient : Ftx

43 (0x002B) Ap

44 (0x002C) NAn

45 (0x002C) Constants : HLF

46 (0x002C) ONE_EIGHT

Access is similar to that of the Data

RAM parameters. Note however that

the GCI commands work with 2-byte

values whereas the memory contains

only 3-nibble values; because all values

are <12,0>, the most significant nibble

of the 2-byte GCI value will be a sign-

extension of the 12-bit value, in the

case of a ReadRequest; the most signifi-

cant nibble of a WriteRequest will be

neglected.

MTK-40131

Meaning and Default Values of the Parameters

Name Address Position Description Mapping Default

r0 00 11:0 Rx filter coefficient unit = intval / 512 int96

r1 01 11:0 Rx filter coefficient unit = intval / 512 int-78

r4 02 11:0 Rx filter coefficient unit = intval / 512 int96

s1 03 11:0 Rx filter coefficient unit = intval / 512 int642

s2 04 11:0 Rx filter coefficient unit = intval / 512 int-263

r2 05 11:0 Rx filter coefficient unit = intval / 512 int256

r3 06 11:0 Rx filter coefficient unit = intval / 512 int-303

r5 07 11:0 Rx filter coefficient unit = intval / 512 int256

s3 08 11:0 Rx filter coefficient unit = intval / 512 int746

s4 09 11:0 Rx filter coefficient unit = intval / 512 int-450

m0 10 11:0 Rx filter coefficient unit = intval / 512 int512

m1 11 11:0 Rx filter coefficient unit = intval / 512 int512

u0 12 11:0 Rx filter coefficient unit = intval / 512 int0

u1 13 11:0 Rx filter coefficient unit = intval / 512 int0

h0 14 11:0 Echo Cancelling coefficient unit = intval / 512 int-109

h1 15 11:0 Echo Cancelling coefficient unit = intval / 512 int2

h2 16 11:0 Echo Cancelling coefficient unit = intval / 512 int8

h3 17 11:0 Echo Cancelling coefficient unit = intval / 512 int32

a0 18 11:0 Echo Cancelling coefficient unit = intval / 512 int127

c5 19 11:0 Echo Cancelling coefficient unit = intval / 512 int512

b0 20 11:0 Echo Cancelling coefficient unit = intval / 512 int157

t0 21 11:0 Tx filter coefficient unit = intval / 512 int48

t1 22 11:0 Tx filter coefficient unit = intval / 512 int-37

t8 23 11:0 Tx filter coefficient unit = intval / 512 int48

q1 24 11:0 Tx filter coefficient unit = intval / 512 int728

q2 25 11:0 Tx filter coefficient unit = intval / 512 int-439

t2 26 11:0 Tx filter coefficient unit = intval / 512 int390

t3 27 11:0 Tx filter coefficient unit = intval / 512 int-492

t9 28 11:0 Tx filter coefficient unit = intval / 512 int390

q3 29 11:0 Tx filter coefficient unit = intval / 512 int573

q4 30 11:0 Tx filter coefficient unit = intval / 512 int-227

t4 31 11:0 Tx filter coefficient unit = intval / 512 int64

t5 32 11:0 Tx filter coefficient unit = intval / 512 int128

t10 33 11:0 Tx filter coefficient unit = intval / 512 int64

Table 42: Coprocessor Coefficient RAM: Description and Default Values

MTK-40131

Name Address Position Description Mapping Default

q5 34 11:0 Tx filter coefficient unit = intval / 512 int442

t6 35 11:0 Tx filter coefficient unit = intval / 512 int384

t7 36 11:0 Tx filter coefficient unit = intval / 512 int-768

t11 37 11:0 Tx filter coefficient unit = intval / 512 int384

q6 38 11:0 Tx filter coefficient unit = intval / 512 int962

q7 39 11:0 Tx filter coefficient unit = intval / 512 int-458

c2 40 11:0 Tx filter coefficient unit = intval / 512 int512

c3 41 11:0 Tx filter coefficient unit = intval / 512 int-512

Ftx 42 11:0 ZcoTx filter coefficient unit = intval / 512 int237

Ap 43 11:0 ZcoTx filter coefficient unit = intval / 512 int0

NAn 44 11:0 ZcoTx filter coefficient unit = intval / 512 int0

HLF 45 11:0 Constant definition unit = intval / 512 int256

ONE_EIGHT 46 11:0 Constant definition unit = intval / 512 int64

SHARED Memory

MemID = 5

Address 15 14 13 12 11 10 987654321 0

85 (0x0055) VLM HT Deb MF MM

86 (0x0056) SpiDo SpiDi SpiSk SpiCs SpiSe RBD SR* SR* SR* SR*

87 (0x0057) HSD_ThresholdHigh HSD_ThresholdLow

88 (0x0058) RTD_ThresholdHigh RTD_ThresholdLow

89 (0x0059) MeteringDutyCycle

90 (0x005A) ZcoShAlfa3 ZcoA2 Rxd* Alo* Sleep *

91 (0x005B) RZco ZcoGamma ZcoAlfa3

94 (0x005E) TL

Note :

Bit positions and memory locations not described here must not be changed.

Table 43: Shared Memory: Memory Map

MTK-40131

Meaning and Default Values of the Parameters

Name Address Position Description Mapping Default

VLM 85 14:11 Metering amplitude val = 0 .. 15 3

(unit value = dependin on Zco)

HT 85 10:9 HSD debounce time 0 = ’00’ : 8ms 2

1 = ’01’ : 24ms (16ms)

2 = ’10’ : 16ms

3 = ’11’ : 64ms

DEB 85 8 RTD debounce time 0 : 0 ms 1

1 : 30 ms (30ms)

MF 85 4 Metering frequency 0 : 12kHz 1

1 : 16kHz (16kHz )

MM 85 3 Metering mode 0 : burst mode 1

1 : onoff mode (onoff)

SPIDO 86 15 SPI Dout port 0

SPIDI 86 14 SPI Din port 0

SPISK 86 13 SPI SK port 0

SPICS 86 12 SPI CS port 0

SPISE 86 11 SPI port selection 0

RBD 86 10 Disable 1 = disabled 0

automatic ring activation 0 = enabled (enabled)

of Spick and Spick

SR (1) 86 5:4 software resets of 1 = reset block 0

1:0 SID1, SID0, CP, GCI 0 = no reset

Soft Resets (2) 86 5:0 Reset ability of HW blocks 0: no reset 0

(SID0, SID1, MRT, LS, CP, GCI) 1: reset block (no reset)

HSD_ThresholdHigh 87 13:7 HSD high threshold val = 0 .. 127 16

unit = 0.63mA (10mA)

= 0 .. 80 mA)

HSD_ThresholdLow 87 6:0 HSD low threshold val = 0 .. 127 10

unit = 0.63mA (6.3mA)

= 0 .. 80 mA)

RTD_ThresholdHigh 88 13:7 RTD high threshold val = 0 .. 127 16

unit = 0.63mA (10mA)

= 0 .. 80 mA)

RTD_ThresholdLow 88 6:0 RTD low threshold val = 0 .. 127 10

unit = 0.63mA (6.3mA)

= 0 .. 80 mA)

MeteringDutyCycle 89 15:8 Length of the metering burst val = 0 .. 255 150

to be used in ”burst” metering unit = 2ms (300ms)

mode = 0 .. 510ms)

ZcoShAlfa3 90 15:1 Central office (1) 0

Impedance parameter (600Ω)

Table 44: Shared Memory: Description and Default Values

MTK-40131

Name Address Position Description Mapping Default

ZcoA2 90 13:7 Central office (1) 0

Impedance parameter (600Ω)

RxD (1) 90 6 RxDisable at input of analog 0: enabled rx path 0

part 1: disable rx path (enabled)

ALO (2) 90 4 Analog loopback at pdm 0: disabled loop 0

1: enable loop (disabled)

Sleep (2) 90 2:0 Sleep factor actually used by val = 0 ... 7 0

the processor = 0 ... 70% sleepy (0% sleep)

RZco 91 11:8 Central office (1) 3

Impedance parameter (600Ω)

ZcoGamma 91 7:4 Central office (1) 0

Impedance parameter (600Ω)

ZcoAlfa3 91 3:0 Central office (1) 0

Impedance parameter (600Ω)

TL 94 1:0 Transcode Law selection 0 = ‘00’: A Law 0

1 = ‘01’: N Law (A-Law)

2 = ‘10’: Linear

Notes:

(1) Examples of other Zco parameters are listed on page 19 ‘ Examples Zco Coëfficient’

in this manual.

Else: contact Alcatel Microelectronics for assistance.

(2) Do not change these values.

Package :General Dimensions of the MTC-20232PQ

MTK-40131

DS 0256b 12/98

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changes in specifications at any time and without notice.

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other rights of third parties resulting from its use.

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Package: General Dimensions

of the MTC-30132SO

28 lead small outline

plastic DWG.NR 87-0038

.299(7.60)

.291(7.40) .420(10.65)

.393(10.00)

.020(0.49)

.013(0.35)

.713(18.10)

.696(17.70)

.050 TYP

.012(0.30)

.003(0.10)

.105(2.65)

.092(2.35)

.030(0.75)

.009(0.25)

0° - 8°

.010TYP) .050(1.27)

.015(0.40)

x 45°