March 2010 Doc ID 12933 Rev 4 1/34
34
L6727
Single phase PWM controller
Feature
■Flexible power supply from 5 V to 12 V
■Power conversion input as low as 1.5 V
■1 % output voltage accuracy
■High-current integrated drivers
■Adjustable output voltage
■0.8 V internal reference
■Simple voltage mode control loop
■Sensorless and programmable OCP across
Low-side RdsON
■Oscillator internally fixed at 300 kHz
■Internal Soft-start
■LS-LESS to manage pre-bias start-up
■Disable function
■OV / UV protection
■FB disconnection protection
■SO-8 package
Applications
■Subsystem power supply (MCH, IOCH, PCI...)
■Memory and termination supply
■CPU and DSP power supply
■Distributed power supply
■General DC / DC converters
Description
L6727 is a single-phase step-down controller with
integrated high-current drivers that provides
complete control logic, protections and reference
voltage to realize in an easy and simple way
general DC-DC converters by using a compact
SO-8 package.
Device flexibility allows managing conversions
with power input VIN as low as 1.5 V and device
supply voltage in the range of 5 V to 12 V.
L6727 provides simple control loop with voltage-
mode error-amplifier. The integrated 0.8 V
reference allows regulating output voltages with
±1 % accuracy over line and temperature
variations. Oscillator is internally fixed to 300 kHz.
L6727 provides programmable over current
protection as well as over and under voltage
protection. Current information is monitored
across the low-side MOSFET RdsON saving the
use of expensive and space-consuming sense
resistors while output voltage is monitored
through FB pin.
FB disconnection protection prevents excessive
and dangerous output voltages in case of floating
FB pin.
SO-8
Table 1. Device summary
Order codes Package Packaging
L6727 SO-8 Tu b e
L6727TR Tape and reel
www.st.com
Contents L6727
2/34 Doc ID 12933 Rev 4
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Soft-start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 Enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.2 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.3 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.4 Undervoltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.1 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.2 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L6727 Contents
Doc ID 12933 Rev 4 3/34
9.3 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.4 Embedding L6727-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.1 Output inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11 20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1.1 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1.2 Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1.3 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1.5 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12 5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.1.1 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.1.2 Power iutput (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.1.3 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.1.5 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical application circuit and block diagram L6727
4/34 Doc ID 12933 Rev 4
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
HS
LS
V
IN
= 1.5V to 19V (**)
L
C
OUT
Vout
LOAD
C
HF C
BULK
R
D
C
SN
R
SN
C
BOOT
R
gHS
R
gLS
D
1
2
8
BOOT
UGATE
PHASE
LGATE 4
C
DEC
FB
6
R
FB
COMP /
DIS / OC
7
RF
CF
CP
GND
VCC
ROS
V
CC
= 5V to 12V
R
OCSET
(*)
5
3
L6727 Reference Schematic
(*) R
OCSET
not to be connected when VCC > 5V
L6727
(**) Up to 12V with Vcc > 5V
VCC
BOOT
LGATE
FB
UGATE
COMP
/ DIS / OC
GND
ADAPTIVE ANTI
CROSS CONDUCTION
HS
LS
VCC
ERROR
AMPLIFIER
+
-0.8V
300 kHz
OSCILLATOR
PWM PHASE
CONTROL LOGIC
& PROTECTIONS
CURRENT READ
& OCP
DISABLE
Vout Monitor
IOCSET
L6727
L6727 Pins description and connection diagrams
Doc ID 12933 Rev 4 5/34
2 Pins description and connection diagrams
Figure 3. Pins connection (top view)
2.1 Pin descriptions
Table 2. Pins descriptions
1
2
3
4VCC
FB
COMP / DIS / OC
PHASE
LGATE
GND
UGATE
BOOT
5
6
7
8
L6727
Pin # Name Function
1BOOT
HS driver supply.
Connect through a capacitor (100 nF) to the floating node (LS-drain) pin
and provide necessary bootstrap diode from VCC.
2 UGATE HS driver output. Connect to HS MOSFET gate.
3GND
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
4 LGATE LS driver output. Connect to LS MOSFET gate.
5VCC
Device and LS driver power supply.
Operative range from 4.1 V to 13.2 V. Filter with at least 1μF MLCC to GND.
6FB
Error Amplifier Inverting Input.
Connect with a resistor RFB to the output regulated voltage. Additional
resistor ROS to GND may be used to regulate voltages higher than the
reference.
7COMP / DIS
/ OC
COMP. Error amplifier output. Connect with an RF - CF // CP to FB to
compensate the control-loop.
DIS. The device can be disabled by forcing this pin lower than 0.5V(typ). To
disable the device, the external pull-down need to overcome 10mA of
COMP output current for about 15 μs. Once disabled, COMP output current
drops to 20 μA.
OC. Over current threshold set. Connect with an ROCSET resistor to VCC
(ONLY IF VCC is supplied by 5 V bus) to program OC threshold. When
VCC > 5V, ROCSET need to be not-connected.
8 PHASE
HS driver return path, current-reading and adaptive-dead-time monitor.
Connect to the LS drain to sense RdsON drop to measure the output current.
This pin is also used by the adaptive-dead-time control circuitry to monitor
when HS MOSFET is OFF.
Electrical specifications L6727
6/34 Doc ID 12933 Rev 4
2.2 Thermal data
Table 3. Thermal data
3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction to ambient (1)
1. Measured with the component mounted on a 2S2P board in free air (6.7cm x 6.7cm, 35μm (P) and
17.5 μm (S) copper thickness).
85 °C/W
T
MAX
Maximum junction temperature 150 °C
T
STG
Storage temperature range -40 to 150 °C
T
J
Junction temperature range -20 to 150 °C
Symbol Parameter Value Unit
VCC to GND -0.3 to 15 V
V
BOOT
to PHASE
to GND
15
45 V
V
UGATE
to PHASE
to PHASE; t < 50 ns
to GND
-0.3 to (VBOOT - V
PHASE
)
+ 0.3
-1
VBOOT + 0.3
V
V
PHASE
to GND -8 to 30 V
V
LGATE
to GND
to GND; t < 50 ns
-0.3 to VCC + 0.3
-1 V
COMP to GND -0.3 to 7 V
FB to GND -0.3 to 3.6 V
L6727 Electrical specifications
Doc ID 12933 Rev 4 7/34
3.2 Electrical characteristics
VCC = 12 V; TA = -20 °C to +85 °C, unless otherwise specified.
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Recommended operating conditions
VCC Device supply voltage See Figure 1 4.1 13.2 V
VIN Conversion input voltage 13.2 V
VCC < 7.0 V 19.0 V
Supply current and power-ON
ICC VCC supply current UGATE and LGATE = OPEN 6 mA
IBOOT BOOT supply current UGATE = OPEN; PHASE to GND 0.5 mA
UVLO VCC turn-ON VCC rising 4.1 V
Hysteresis 0.2 V
Oscillator
FSW Main oscillator accuracy 0 °C to +70 °C 270 300 330 kHz
250 300 350 kHz
ΔVOSC PWM ramp amplitude 1.5 V
dMAX Maximum duty cycle 80 %
Reference
Output voltage accuracy VOUT = 0.8 V, TA = 0 °C to 70 °C -1 - 1 %
VOUT = 0.8 V -1.5 1.5 %
Error amplifier
A0DC gain(1) 120 dB
GBWP Gain-bandwidth product(1) 15 MHz
SR Slew-rate(1) 8V/μs
IFB Input bias current Sourced from FB 100 nA
DIS Disable threshold COMP falling 0.43 0.5 V
Gate drivers
IUGATE HS source current BOOT - PHASE = 5 V to 12 V 1.5 A
RUGATE HS sink resistance BOOT - PHASE = 5 V to 12 V 1.1 Ω
ILGATE LS source current VCC = 5 V to 12 V 1.5 A
RLGATE LS sink resistance VCC = 5 V to 12 V 0.65 Ω
Overcurrent protection
IOCSET OCSET current source Sunk from COMP pin, before SS 55 60 65 μA
Electrical specifications L6727
8/34 Doc ID 12933 Rev 4
VCC_OC OC Switch-over threshold VCC rising 8 V
VOCTH Fixed OC threshold VPHASE to GND, VCC > VCC_OC -400 mV
Over and undervoltage protections
OVP OVP threshold FB rising 1 V
UVP UVP threshold FB falling 0.6 V
1. Guaranteed by design, not subject to test.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
L6727 Device description
Doc ID 12933 Rev 4 9/34
4 Device description
L6727 is a single-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections to realize in an easy and simple way a general DC-
DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck
topology, with its high level of integration this 8-pin device allows reducing cost and size of
the power supply solution.
L6727 is designed to operate from a 5 V or 12 V supply bus. Thanks to the high precision
0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8 V with
±1 % accuracy over line and temperature variations (between 0 °C and +70 °C).
The switching frequency is internally set to 300 kHz.
This device provides a simple control loop with a voltage-mode error-amplifier. The error-
amplifier features a 15 MHz gain-bandwidth product and 8V/µs slew rate, allowing high
regulator bandwidth for fast transient response.
To avoid load damages, L6727 provides over current protection as well as over voltage,
under voltage and feedback disconnection protection. When the device is supplied from 5 V,
over current trip threshold is programmable by a simple resistor. Output current is monitored
across Low-side MOSFET RdsON, saving the use of expensive and space-consuming sense
resistor. Output voltage and feedback disconnection are monitored through FB pin.
L6727 implements soft-start increasing the internal reference from 0 V to 0.8 V in 5.1 ms
(typ) in closed loop regulation. Low-side-less feature allows the device to perform soft-start
over pre-biased output avoiding high current return through the output inductor and
dangerous negative spike at the load side.
Driver section L6727
10/34 Doc ID 12933 Rev 4
5 Driver section
The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition.
The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return.
The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.
The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:
●to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at
PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
●to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE
has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See
maximum duty cycle limitation and recommended operating conditions, in Ta bl e 5 ) can be
chosen freely.
5.1 Power dissipation
L6727 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
●Device bias power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):
●Drivers power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency and total gate charge of
the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs (easy calculable) is dissipated by three main
factors: external gate resistance (when present), intrinsic MOSFET resistance and
intrinsic driver resistance. This last term is the important one to be determined to
calculate the device power dissipation. The total power dissipated to switch the
MOSFETs results:
where VBOOT - VPHASE is the voltage across the bootstrap capacitor. External gate
resistors helps the device to dissipate the switching power since the same power PSW
will be shared between the internal driver impedance and the external resistor resulting
in a general cooling of the device.
PDC VCC ICC IBOOT
+()⋅=
PSW FSW QgHS VBOOT VPHASE
–()QgLS VCC
⋅+⋅[]⋅=
L6727 Soft-start and disable
Doc ID 12933 Rev 4 11/34
6 Soft-start and disable
L6727 implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device progressively increases the
internal reference from 0 V to 0.8 V in about 5.1 ms, in closed loop regulation, gradually
charging the output capacitors to the final regulation voltage.
In the event of an overcurrent triggering during soft start, the over current logic will override
the soft start sequence and will shut down both the high side and low side gates for the
internal soft start residual time (up to 2048 clock cycles) plus 2048 clock cycles, then it will
begin a new soft start.
The device begins soft start phase only when VCC power supply is above UVLO threshold
and overcurrent threshold setting phase has been completed.
6.1 Low-side-less start up (LSLess)
In order to manage start up over pre-biased output, L6727 performs a special sequence in
enabling LS driver to switch: during the soft-start phase, LS driver results disabled
(LS = OFF) until HS starts to switch. This avoids the dangerous negative spike on the output
voltage that can happen if starting over a pre-biased output.
If the output voltage is pre-biased to a voltage lower than the programmed one, neither HS
nor LS will turn on until the soft start ramp exceeds the output pre-bias voltage; then VOUT
will ramp up from there, without any drop or current return.
If the output voltage is pre-biased to a voltage higher than the programmed one, HS would
never start to switch. In this case, at the end of soft start time, LS is enabled and discharges
the output to the final regulation value.
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections by-pass LSLESS, turning ON the LS MOSFET in case of need.
Figure 4. LSless startup (left) vs non-lsless startup (right)
Soft-start and disable L6727
12/34 Doc ID 12933 Rev 4
6.2 Enable / disable
The device can be disabled by externally pushing COMP / DIS pin under 0.5 V (typ). In
disable condition HS and LS MOSFETs are turned off, and a 20 μA current is sourced from
COMP / DIS pin. Setting free the pin, this current pulls it over the threshold and the device
enables again performing a new SS.
To disable the device, the external pull-down needs to overcome 10 mA of COMP output
current for about 15 μs. Once disabled, COMP output current drops to 20μA.
Figure 5. Start up sequence; VCC = 5V (Left) overcurrent hiccup (Right)
L6727 Overcurrent protection
Doc ID 12933 Rev 4 13/34
7 Overcurrent protection
The overcurrent feature protects the converter from a shorted output or overload, by sensing
the output current information across the low side MOSFET drain-source on-resistance,
RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of
expensive and space-consuming sense resistors.
The low side RdsON current sense is implemented by comparing the voltage at the PHASE
node when LS MOSFET is turned on with the programmed OCP threshold voltage,
internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an
overcurrent event is detected. If two overcurrent events are detected in two consecutive
switching cycles, the protection will be triggered and the device will turn off both LS and HS
MOSFETs for 2048 clock cycles (plus internal SS remaining time, if triggered during a SS
phase); then it will begin a new soft-start.
If the overcurrent condition is not removed, the continuous fault will cause L6727 to go into a
hiccup mode with a typical period of 13.6 ms (Figure 5), guaranteeing safe load protection
and very low power dissipation.
7.1 Overcurrent threshold setting
When supplied with VCC = 5 V, L6727 allows to easily program an overcurrent threshold
ranging from 50 mV to 500 mV, simply by adding a resistor (ROCSET) between COMP and
VCC.
During a short period of time (5.5 ms - 6.5 ms) following the first enable (given VCC over
UVLO threshold), an internal 60µA current (IOCSET) is sunk from COMP pin, determining a
voltage drop across ROCSET
. This voltage drop, differentially sensed between VCC and
COMP, divided by a factor 3, will be sampled and internally held by the device as Over
Current Threshold until next VCC cycling. Differential sensing versus VCC allows OCSET
procedure to be fully independent from VIN rail. The OC setting procedure overall time
length ranges from 5.5 ms to 6.5 ms, proportionally to the threshold being set.
Connecting an ROCSET resistor between COMP and VCC, the programmed threshold will
be:
ROCSET values range from 2.5 kΩ to 25 kΩ.
If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up
inrush current and noise. This can result in a continuous OCP triggering and hiccup mode.
In this case, consider to increase ROCSET value.
In case ROCSET is not connected (and VCC = 5 V), the device will set the maximum
threshold.
If the device is supplied with a VCC higher than 7 V, ROCSET must be not connected. In this
case, as soon as VCC rises over VCC_OC (8 V typ.), L6727 switches OC threshold to 400mV
(internally fixed value).
See Figure 5 for OC threshold setting and soft start oscilloscope sample waveforms.
IOCth
1
3
---
IOCSET ROCSET
⋅
RdsON
--------------------------------------------
⋅=
Output voltage monitor and protections L6727
14/34 Doc ID 12933 Rev 4
8 Output voltage monitor and protections
L6727 monitors the voltage at FB pin and compares it to internal reference voltage in order
to provide Under Voltage and Over Voltage protections.
8.1 Undervoltage protection
If the voltage at FB pin drops below UV threshold (0.6 V typ), the device turns off both HS
and LS MOSFETs, waits for 2048 clock cycles and then performs a new soft start. If under
voltage condition is not removed, the device enters a hiccup mode with a typical period of
13.6 ms.
UVP is active from the end of soft start.
8.2 Overvoltage protection
If the voltage at FB pin rises over OV threshold (1 V typ), over voltage protection turns off HS
MOSFET and turns on LS MOSFET overriding PWM logic as long as over voltage is
detected.
OVP is always active with top priority as soon as over current threshold setting phase has
been completed.
8.3 Feedback disconnection protection
In order to provide load protection even if FB pin is not connected, a 100 nA bias current is
always sourced from this pin. If FB pin is not connected, this current will permanently pull up
FB over OVP threshold: thus LS will be latched on preventing output voltage from rising out
of control.
8.4 Undervoltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to
support its internal rails, UVLO is provided: the device will start up when VCC reaches
UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold.
The 4.1 V maximum UVLO upper threshold allows L6727 to be supplied from 5 V and 12 V
busses in or-ing diode configuration.
L6727 Application details
Doc ID 12933 Rev 4 15/34
9 Application details
9.1 Output voltage selection
L6727 is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to
be within ±1 % tolerance over line and temperature variations between 0 °C and +70 °C
(excluding output resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be easily achieved by adding a resistor ROS between
FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
where VREF is 0.8V.
9.2 Compensation network
The control loop showed in Figure 6 is a voltage mode control loop. The error amplifier is a
voltage mode type. The output voltage is regulated to the internal reference (when present,
offset resistor between FB node and GND can be neglected in control loop calculation).
Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with VIN
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and VOUT
. This function has a double pole at frequency FLC depending on the L-COUT
resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage
ΔVOSC.
The compensation network closes the loop joining VOUT and EA output with transfer
function ideally equal to -ZF/ZFB.
Figure 6. PWM control loop
VOUT VREF 1RFB
ROS
-----------+
⎝⎠
⎛⎞
⋅=
L R
C
OUT
ESR
R
F
C
F
C
P
R
FB
C
S
OSC
V
IN
ΔV
OSC
+
+
_
_
V
OUT
V
REF
Z
F
Z
FB
PWM
COMPARATOR
ERROR
AMPLIFIER
R
S
Application details L6727
16/34 Doc ID 12933 Rev 4
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for
stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain
has to cross 0dB axis with -20 dB/decade slope.
As an example, Figure 7 shows an asymptotic bode plot of a type III compensation.
Figure 7. Example of type III compensation.
●Open loop converter singularities:
a)
b)
●Compensation Network singularities frequencies:
a)
b)
c)
d)
Gain
[dB]
Log (Freq)
0dB
open loop
EA gain
closed
loop gain
compensation
gain
open loop
converter gain
F
LC
F
ESR
F
Z1
F
Z2
F
P1
F
P2
20log (R
F
/R
FB
)
20log (V
IN
/ΔV
OSC
)
F
0dB
FLC
1
2πLC
OUT
⋅
----------------------------------=
FESR
1
2πCOUT ESR⋅⋅
--------------------------------------------=
FZ1
1
2πRFCF
⋅⋅
------------------------------=
FZ2
1
2πRFB RS
+()CS
⋅⋅
-----------------------------------------------------=
FP1
1
2πRF
CFCP
⋅
CFCP
+
---------------------
⎝⎠
⎛⎞
⋅⋅
--------------------------------------------------=
FP2
1
2πRSCS
⋅⋅
-------------------------------=
L6727 Application details
Doc ID 12933 Rev 4 17/34
To place the poles and zeroes of the compensation network, the following suggestions may
be followed:
a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth
according to the approximated formula (suggested values for RFB range from 2 kΩ
to 5 kΩ):
b) Place FZ1 below FLC (typically 0.5*FLC):
c) Place FP1 at FESR:
d) Place FZ2 at FLC and FP2 at half of the switching frequency:
e) Check that compensation network gain is lower than open loop EA gain;
f) Estimate phase margin obtained (it should be greater than 45 °) and repeat,
modifying parameters, if necessary.
9.3 Layout guidelines
L6727 provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 8) must be part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
The input capacitance (C
IN
), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
RF
RFB
----------
F0dB
FLC
------------
ΔVOSC
VIN
-------------------
⋅=
CF
1
πRFFLC
⋅⋅
-----------------------------=
CP
CF
2πRFCFFESR 1–⋅⋅⋅
----------------------------------------------------------=
RS
RFB
FSW
2F⋅LC
------------------1–
---------------------------=
CS
1
πRSFSW
⋅⋅
-------------------------------=
Application details L6727
18/34 Doc ID 12933 Rev 4
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitors (C
OUT
) as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
Figure 8. Power connections (heavy lines)
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
recommended to minimize the distance between controller and power section. See Figure 9
for drivers current paths.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC
and Bootstrap capacitor) and loop compensation components as close to the device as
practical. For over current programmability, place ROCSET close to the device and avoid
leakage current paths on COMP / OC pin, since the internal current source is only 60μA.
Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big
negative spikes on the phase pin. This spike must be limited within the absolute maximum
ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase
resistor in series to PHASE pin), as well as the positive spike, but has an additional
consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can
cause, in the worst case condition of maximum input voltage and during particular
transients, that boot-to-phase voltage overcomes the absolute maximum ratings also
causing device failures. It is then suggested in this cases to limit this extra-charge by adding
a small resistor in series to the bootstrap diode (RD in Figure 1).
Figure 9. Drivers turn-on and turn-off paths
L
C
IN
V
IN
UGATE
PHASE
LGATE
GND
LOAD
L6727
C
OUT
R
GATE
R
INT
C
GD
C
GS
C
DS
VCC
LS DRIVER LS MOSFET
GND
LGATE
R
GATE
R
INT
C
GD
C
GS
C
DS
BOOT
HS DRIVER HS MOSFET
PHASE
UGATE
R
PHASE
L6727 Application details
Doc ID 12933 Rev 4 19/34
9.4 Embedding L6727-based VRs
When embedding the VR into the application, additional care must be taken since the whole
VR is a switching DC/DC regulator and the most common system in which it has to work is a
digital system such as MB or similar. In fact, latest MBs have become faster and more
powerful: high speed data busses are more and more common and switching-induced noise
produced by the VR can affect data integrity if additional layout guidelines are not followed.
Few easy points must be considered mainly when routing traces in which switching high
currents flow (switching high currents cause voltage spikes across the stray inductance of
the traces causing noise that can affect the near traces):
When reproducing high current path on internal layers, keep all layers the same size in order
to avoid "surrounding" effects that increase noise coupling.
Keep safe guard distance between high current switching VR traces and data busses,
especially if high-speed data busses, to minimize noise coupling.
Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that
must walk near the VR.
Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive
and Input voltage path (from input bulk capacitors and HS drain). Also GND connection
must be considered if not insisting on a power ground plane. These connections must be
carefully kept far away from noise-sensitive data busses.
Since the generated noise is mainly due to the switching activity of the VR, noise emissions
depend on how fast the current switches. To reduce noise emission levels, it is also possible,
in addition to the previous guidelines, to reduce the current slope and thus to increase the
switching times: this will cause, as a consequence of the higher switching time, an increase
in switching losses that must be considered in the thermal design of the system.
Application information L6727
20/34 Doc ID 12933 Rev 4
10 Application information
10.1 Output inductor
Inductor value is defined by a compromise between dynamic response, ripple, efficiency,
cost and size. Usually, inductance is calculated to maintain inductor ripple current (ΔIL)
between 20 % and 30 % of maximum output current. Given the switching frequency (FSW),
the input voltage (VIN), the output voltage (VOUT) and the desired ripple current (ΔIL),
inductance can be calculated as follows:
Figure 1 shows the ripple current vs. the output voltage for different inductance, with
VIN = 5 V and VIN = 12 V.
Increasing inductance reduces inductor ripple current (and output voltage ripple
accordingly) but, at the same time, increases the converter response time to load transients.
Higher inductance means that the inductor needs more time to change its current from initial
to final value. Until the inductor has not finished its charging, the additional output current is
supplied by output capacitors. Minimizing the response time lead to minimize the output
capacitance required. If the compensation network is designed with high bandwidth, during
an heavy load transient the device is able to saturate duty cycle (0 % or 80 %). When this
condition is reached, the response time is limited only by the time required to charge the
inductor.
Figure 10. Inductor current ripple vs output voltage
LVIN VOUT
–
FSW ΔIL
⋅
------------------------------
VOUT
VIN
--------------
⋅=
L6727 Application information
Doc ID 12933 Rev 4 21/34
10.2 Output capacitors
Output capacitors choice depends on the application constraints in point of output voltage
ripple and output voltage deviation during a load transient.
During steady-state conditions, the output voltage ripple is influenced by ESR and
capacitance of the output capacitors as follows:
Where ΔIL is the inductor current ripple. These contribution are not in phase, so total ripple
will be lower than the sum of their moduli. Even ESL and board parasitic inductance can
contribute significantly to output ripple.
During a load variation, the output capacitors supply to the load the additional current or
absorb the current in excess delivered by the inductor until converter reaction is completed.
In fact, even if the controller react immediately to the load transient saturating the duty cycle
to 80 % or 0 %, the current slew rate is limited by the inductance. At first approximation,
output voltage drop, based on ESR and capacitor charge/discharge and considering an
ideal load-step, can be estimated as follows:
Where ΔVL is the voltage applied to the inductor during the transient ( for
the load appliance or VOUT for the load removal).
MLCC capacitors typically have low ESR to minimize the ripple but also have low
capacitance that do not minimize the capacitive voltage deviation during load transient. On
the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive
voltage deviation during load transient, but also higher ESR value resulting in higher ripple
voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC
capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in
dynamic conditions.
10.3 Input capacitors
The input capacitor bank is designed mainly to stand input rms current, which depends on
output current (IOUT) and duty-cycle (D) for the regulation as follows:
The equation reaches its maximum value, IOUT/2, when D = 0.5. Losses depend on input
capacitor ESR:
ΔVOUT_ESR ΔILESR⋅=
ΔVOUT_C ΔIL
1
8C
OUT FSW
⋅⋅
---------------------------------------
⋅=
ΔVOUT_ESR ΔIOUT ESR⋅=
ΔVOUT_C
LΔIOUT
2
⋅
2C
OUT ΔVL
⋅⋅
--------------------------------------=
DMAX VIN VOUT
–⋅
Irms IOUT D1D–()⋅⋅=
PESRI
rms
2
⋅=
20 A demonstration board L6727
22/34 Doc ID 12933 Rev 4
11 20 A demonstration board
L6727 demonstration board realizes on a four-layer PCB a step-down DC/DC converter and
shows the operation of the device in a general purpose application. Input voltage can range
from 5 V to 12 V bus (when VCC > 5 V, R6 need to be removed). Output voltage is
programmed to 1.25 V. The voltage regulator can deliver up to 20 A output current. The
switching frequency is 300 kHz.
Figure 11. 20 A demonstration board (left) and components placement (right)
Figure 12. 20 A demonstration board top (left) and bottom (right) layers
L6727 20 A demonstration board
Doc ID 12933 Rev 4 23/34
Figure 13. 20 A demonstration board inner layers
20 A demonstration board L6727
24/34 Doc ID 12933 Rev 4
Figure 14. 20 A demonstration board schematic
HSDHSD
VIN_POWER
LSG1
UGATE
BOOT
BOOT PHASE
GND
VCC
GND
COMP
FB
COMP
VCC_PIN
FB
OUT
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
PHASE
OUT
LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2
UGATE HSG
LGATELGATE
VCCVCC_PINLGATE
PHASE OUT
HSG
PHASE
HSD
GND
LSG1
PHASE
GND
LSG2
PHASE
0
0 0 0
0 0
0
VIN_POWER
GNDIN_POWER
0
VCC
GNDCC
00
0 0 0 0 0 0 0 0 0
VOUT
0
GNDOUT
0
0 0 0 0 0 0 0 0 0 0
0 0 00 0 00
0
0
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C33
NC
C33
NC
R14
NC
R14
NC
COMPCOMP
12
L2
T60-18 6Ts
L2
T60-18 6Ts
1
3 2
Q6
NC
Q6
NC
FBFB
GNDGND
VOUT1VOUT1
C21
NC
C21
NC
R4
1.8
R4
1.8
UGATEUGATE
C13
4.7uF
C13
4.7uF
4
51
6
7
8
2
3
Q1
NC
Q1
NC
C34
NC
C34
NC
R13
3.9k
R13
3.9k
4
51
6
7
8
2
3
Q2
NC
Q2
NC
C37
NC
C37
NC
R8
0
R8
0
C23
6.8nF
C23
6.8nF
R3
2.2
R3
2.2
C36
NC
C36
NC
R11
0
R11
0
C15
NC
C15
NC
C22
NC
C22
NC
C27
NC
C27
NC
GNDOUT1GNDOUT1
GNDIN1GNDIN1
1
3 2
Q4
STD55NH2LL
Q4
STD55NH2LL
C16
NC
C16
NC
C3
NC
C3
NC
R9
2.2k
R9
2.2k
C381uF C381uF
R17
2.2
R17
2.2
C5
NC
C5
NC
C14
1uF
C14
1uF
VIN1VIN1
C28
NC
C28
NC
PHASEPHASE
C19
NC
C19
NC
C10
100nF
C10
100nF
C4
NC
C4
NC
C35
33pF
C35
33pF
C17
NC
C17
NC
C11
4.7uF
C11
4.7uF
R6
12k
R6
12k
R12
NC
R12
NC
1
3 2
Q5
STD90NH2LL
Q5
STD90NH2LL
C7
NC
C7
NC
C31
NC
C31
NC
R10
NC
R10
NC
C29
NC
C29
NC
C6
NC
C6
NC
R18
NC
R18
NC
C18
2200uF
C18
2200uF
C25
2200uF
C25
2200uF
R7
33k
R7
33k
R5
0
R5
0
1 2
L1
NC
L1
NC
R15
NC
R15
NC
C2
1800uF
C2
1800uF
C1
1800uF
C1
1800uF
R1
3.3
R1
3.3
LGATELGATE
C9
NC
C9
NC
C32
NC
C32
NC
C20
NC
C20
NC
C24
10nF
C24
10nF
D1
1N4148
D1
1N4148
C12
4.7uF
C12
4.7uF
R16
0
R16
0
VCC 5
GND
3FB 6
UGATE
2
BOOT
1
COMP 7
PHASE 8
LGATE
4
L6726A/27
U1
L6726A/27
U1
4
51
6
7
8
2
3
Q3
NC
Q3
NC
VCCVCC
C30
NC
C30
NC
C26
NC
C26
NC
C8
NC
C8
NC
R2
3.3
R2
3.3
L6727 20 A demonstration board
Doc ID 12933 Rev 4 25/34
Table 6. 20 A demonstration board - bill of material
Qty Reference Description Package
Capacitors
2C1, C2 Electrolytic Cap 1800 μF 16 V
Nippon chemi-con KZJ or KZG Radial 10 x 25 mm
1 C10 MLCC, 100 nF, 25 V, X7R SMD0603
3 C11 to C13 MLCC, 4.7 μF, 1 6 V, X 5 R
Murata GRM31CR61C475MA01 SMD1206
2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805
2 C18, C25 Electrolytic Cap 2200 μF 6.3 V
Nippon chemi-con KZJ or KZG Radial 10 x 20 mm
1 C23 MLCC, 6.8 nF, X7R
SMD06031 C24 MLCC, 10 nF, X7R
1 C35 MLCC, 33 pF, X7R
Resistors
2 R1, R2 Resistor, 3R3, 1/16 W, 1 % SMD0603
1 R17 Resistor, 2R2, 1/16 W, 1 %
2 R5, R16 Resistor, 0R, 1/8 W, 1 %
SMD08051 R3 Resistor, 2R2, 1/8 W, 1 %
1 R4 Resistor, 1R8, 1/8 W, 1 %
2 R11, R8 Resistor, 0R, 1/16 W, 1 %
SMD0603
1 R9 Resistor, 2K2, 1/16 W, 1 %
1 R13 Resistor, 3K9, 1/16 W, 1 %
1 R7 Resistor, 33K, 1/16 W, 1 %
1 R6 Resistor, 12K, 1/16 W, 1 %
Inductor
1L1 Inductor, 1.25 μH, T60-18, 6Turns
Easymagnet AP106019006P-1R1M na
Active components
1 D1 Diode, 1N4148 or BAT54 SOT23
1 Q5 STD55NH2LL DPACK
1 Q6 STD90NH2LL
1 U1 Controller, L6727 SO8
20 A demonstration board L6727
26/34 Doc ID 12933 Rev 4
11.1 Board description
11.1.1 Power input (VIN)
This is the input voltage for the power conversion. The high-side MOSFET drain is
connected to this input. Supply must be compliant with VIN recommended operating
conditions and capacitors rating.
If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it
can supply also the device through R16 resistor. When VCC > 5 V, R6 need to be removed.
11.1.2 Power output (VOUT)
This is the output voltage of the power conversion. The output voltage is programmed to
1.25 V. It can be changed by replacing R13. R6 allows to adjust OCP threshold when
VCC = 5 V.
11.1.3 IC additional supply (VCC)
The controller can be supplied separately from the power conversion through VCC input. In
this case, to separate VCC from VIN, R16 resistor must be removed. When VCC > 5 V, R6
need to be removed.
11.1.4 Test points
The following test points are provided to allow easy probing of important signals:
– COMP: output of the error amplifier;
– FB: inverting input of the error amplifier;
– PH: Phase pin of the device;
– LG: Low-Side gate pin of the device;
– UG: High-Side gate pin of the device.
11.1.5 Demonstration board efficiency
Figure 15. 20 A demonstration board efficiency
L6727 5 A demonstration board
Doc ID 12933 Rev 4 27/34
12 5 A demonstration board
L6727 demonstration board realizes on a two-layer PCB a step-down DC/DC converter and
shows the operation of the device in a general-purpose low-current application. Input
voltage can range from 5 V to 12 V bus. Output voltage is programmed at 1.25 V. The
application can deliver an output current in excess of 5 A. The switching frequency is 300
kHz.
Figure 16. 5 A demonstration board (left) and components placement (right)
Figure 17. 5 A demonstration board top (left) and bottom (right) layers
5 A demonstration board L6727
28/34 Doc ID 12933 Rev 4
Figure 18. 5 A demonstration board schematic
PHASE PIN
BOOT
BOOT
GND
FB
COMP
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
UGATE HSG1
LGATELGATE
VCCVCC_PIN
GND
LGATE
UGATE
PHASE PIN
COMP
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
OUTOUT
LSG1LSG1LSG1
VCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
OUTOUTOUTOUTOUTOUTOUTOUT OUTOUT
VIN_POWER
FBFBFB
PHASE
HSD
0
0
0
VIN_POWER
GNDIN_POWER
0
VCC
GNDCC
0
0 0
VOUT
0
GNDOUT
0
0
0
0 0
0
0
0
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R14
15
R14
15
COMPCOMP
12
L2
2.2uH
L2
2.2uH
FBFB
GNDGND
VOUT1VOUT1
3
4
65
U5B
STS9D8NH3LL
U5B
STS9D8NH3LL
R4
1.8
R4
1.8
UGATEUGATE
C30
330uF
C30
330uF
R13
3.9K
R13
3.9K
R8
0
R8
0
12
L3 NCL3 NC
C23
6.8nF
C23
6.8nF
R3 0R3 0
C36
6.8nF
C36
6.8nF
GNDOUT1GNDOUT1
GNDIN1GNDIN1
R9
2.2k
R9
2.2k
C38
1uF
C38
1uF
R17 3.3R17 3.3
C29A
NC
C29A
NC
C51
10uF
C51
10uF
VIN1VIN1
R10
NC
R10
NC
R16
0
R16
0
PHASEPHASE
C10
100nF
C10
100nF
D1
BAT54
D1
BAT54
C35
220pF
C35
220pF
C40
NC
C40
NC
C14
1uF
C14
1uF
C29
NC
C29
NC
R18
NC
R18
NC
C18
NC
C18
NC
R7
4.7k
R7
4.7k
R5 0R5 0
1
2
87
U5A
STS9D8NH3LL
U5A
STS9D8NH3LL
LGATELGATE
C24
68nF
C24
68nF
R1
3.3
R1
3.3
C12
10uF
C12
10uF
BOOT
1
UGATE
2
GND
3
LGATE/OC
4VCC 5
FB 6
COMP 7
PHASE 8
L6727
U1
L6727
L6727
U1
L6727
VCCVCC
C39
22uF
C39
22uF
R2 3.3R2 3.3
L6727 5 A demonstration board
Doc ID 12933 Rev 4 29/34
Table 7. 5 A demonstration board - bill of material
Qty Reference Description Package
Capacitors
2C12, C51 10 μF, 2 5 V, X 5 R
Murata GRM31CR61E106KA12 SMD1206
1 C10 MLCC, 100 nF, 25 V, X7R SMD0603
2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805
1C39 MLCC, 22 μF, 6.3 V, X5R
Murata GRM31CR60J226ME19 SMD1206
1C30 330 μF, 6.3 V, 9 mΩ
Sanyo 6TPF330M9L SMD7343
2 C23, C36 MLCC, 6.8 nF, X7R
SMD06031 C24 MLCC, 68 nF, X7R
1 C35 MLCC, 220 pF, X7R
Resistors
1 R4 Resistor, 1R8, 1/8 W, 1 % SMD0805
4 R3, R5, R8, R16 Resistor, 0R, 1/16 W, 1 %
SMD06033 R1, R2, R17 Resistor, 3R3, 1/16 W, 1 %
1 R14 Resistor, 15R, 1/16 W, 1 %
1 R9 Resistor, 2K2, 1/16 W, 1 %
SMD06031 R13 Resistor, 3K9, 1/16 W, 1 %
1 R7 Resistor, 4K7, 1/16 W, 1 %
Inductor
1L1 Inductor, 2.20 μH,
Wurth 744324220LF na
Active Components
1 D1 Diode, BAT54 SOT23
1 Q5 Mosfet, STS9D8NH3LL SO8
1 U1 Controller, L6727 SO8
5 A demonstration board L6727
30/34 Doc ID 12933 Rev 4
12.1 Board description
12.1.1 Power input (VIN)
This is the input voltage for the power conversion. The high-side MOSFET drain is
connected to this input. Supply must be compliant with VIN recommended operating
conditions and capacitors rating.
If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it
can supply also the device through R16 resistor.
12.1.2 Power iutput (VOUT)
This is the output voltage of the power conversion. The output voltage is programmed to
1.25 V. It can be changed by replacing R13.
12.1.3 IC additional supply (VCC)
The controller can be supplied separately from the power conversion through VCC input. In
this case, to separate VCC from VIN, R16 resistor must be removed.
12.1.4 Test points
The following test points are provided to allow easy probing of important signals:
– COMP: output of the error amplifier;
– FB: inverting input of the error amplifier;
– PH: Phase pin of the device;
– LG: Low-Side gate pin of the device;
– UG: High-Side gate pin of the device.
12.1.5 Demonstration board efficiency
Figure 19. 5 A demonstration board efficiency
L6727 Package mechanical data
Doc ID 12933 Rev 4 31/34
13 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 8. SO-8 mechanical data
Dim.
mm. inch
Min Typ Max Min Typ Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D (1)
1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004
Package mechanical data L6727
32/34 Doc ID 12933 Rev 4
Figure 20. Package dimensions
L6727 Revision history
Doc ID 12933 Rev 4 33/34
14 Revision history
Table 9. Revision history
Date Revision Changes
04-Dec-2006 1Initial release.
28-Feb-2007 2 Updated VOCTH values in Table 5 on page 7
06-Jun-2007 3 Updated Figure 1: Typical application circuit on page 4,
Tabl e 3 and Table 4 on page 6
23-Mar-2010 4
Added Section 10: Application information on page 20, Section 11:
20 A demonstration board on page 22, Section 12: 5 A
demonstration board on page 27
Updated: Table 5 on page 7
L6727
34/34 Doc ID 12933 Rev 4
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