1
LTC1698
1698f
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
The LTC
®
1698 is a precision secondary-side forward
converter controller that synchronously drives external
N-channel MOSFETs. It is designed for use with the
LT
®
3781 primary-side synchronous forward converter
controller to create a completely isolated power supply.
The LT3781 synchronizes the LTC1698 through a small
pulse transformer and the LTC1698 drives a feedback
optocoupler to close the feedback loop. Output accuracy
of ±0.8% and high efficiency over a wide range of load
currents are obtained.
The LTC1698 provides accurate secondary-side current
limit using an external current sense resistor. The input
voltage at the MARGIN pin provides ±5% output voltage
adjustment. A power good flag and overvoltage input are
provided to ensure proper power supply conditions. An
auxiliary 3.3V logic supply is included that supplies up to
10mA of output current.
Isolated Secondary
Synchronous Rectifier Controller
■
High Efficiency Over Wide Load Current Range
■
±0.8% Output Voltage Accuracy
■
Dual N-Channel MOSFET Synchronous Drivers
■
Pulse Transformer Synchronization
■
Optocoupler Feedback Driver
■
Programmable Current Limit Protection
■
±5% Margin Output Voltage Adjustment
■
Adjustable Overvoltage Fault Protection
■
Power Good Flag
■
Auxiliary 3.3V Logic Supply
■
Available in 16-Lead SSOP and SO Packages
■
48V Input Isolated DC/DC Converters
■
Isolated Telecommunication Power Systems
■
Distributed Power Step-Down Converters
■
Industrial Control Systems
■
Automotive and Heavy Equipment
Figure 1. Simplified 2-Transistor Isolated Forward Converter
, LTC and LT are registered trademarks of Linear Technology Corporation.
+
+
CG
V
DD
PWRGD
LTC1698
PGND GND
28
C
FB
C
C
C
CILM
R
C
V
OUT
R
CILM
R2
R5
R4
R1
L1
6
13
9
7
14
C
OUT
110
Q4
V
IN
36V to 72V
Q3
T1
•
•
Q1
D1
Q2
R
PRISEN
T2
FG
16
I
SNS
R
SECSEN
12
I
SNSGND
11
SYNC
V
FB
V
COMP
V
AUX
I
COMP
OVPIN
MARGIN V
MARGIN
O.1µF
1681 F01
V
AUX
3.3V
10mA
15
OPTODRV
PLEASE REFER TO FIGURE 12 IN THE TYPICAL APPLICATIONS
SECTION FOR THE COMPLETE 3.3V/15A APPLICATION SCHEMATIC
5
34
R
SYNC
R
K
R
E
ISOLATION
BOUNDARY
R
F
REF
V
FB
SG
TG BG
LT3781
V
C
C
SYNC
C
K
C
F
V
DD
BIAS
C
SG
+
–
D2
•
•
2
LTC1698
1698f
(Note 1)
V
DD
, PWRGD ....................................................... 13.2V
Input Voltage
MARGIN, V
FB
, OVPIN, I
SNSGND
, I
SNS
... –0.3V to 5.3V
SYNC ..................................................... –14V to 14V
Output Voltage
V
COMP
, I
COMP
(Note 2)......................... –0.3V to 5.3V
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1698E (Note 3)............................ – 40°C to 85°C
LTC1698I........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
ORDER PART
NUMBER
LTC1698EGN
LTC1698ES
LTC1698IGN
LTC1698IS
T
JMAX
= 125°C, θ
JA
= 130°C/W (GN)
T
JMAX
= 125°C, θ
JA
= 110°C/W (SO)
GN PACKAGE
16-LEAD PLASTIC SSOP S PACKAGE
16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
V
DD
CG
PGND
GND
OPTODRV
V
COMP
MARGIN
V
FB
FG
SYNC
V
AUX
I
COMP
I
SNS
I
SNSGND
PWRGD
OVPIN
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 8V, unless otherwise noted. (Note 4)
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Supply Voltage ●6 8 12.6 V
V
UVLO
Undervoltage Lockout 4V
I
VDD
V
DD
Supply Current V
FB
, OVPIN, V
ISNS
, V
ISNSGND
= 0V,
C
FG
= C
CG
= 1000pF, C
VAUX
= 0.1µF,
V
SYNC
= 0V ●1.8 4 mA
f
SYNC
= 100kHz (Note 5) 5.0 mA
MARGIN and Error Amplifier
V
FB
Feedback Voltage MARGIN = Open, V
COMP
= 1V (Note 7) 1.223 1.233 1.243 V
●1.215 1.233 1.251 V
I
VFB
Feedback Input Current V
FB
= 1.233V ●0.05 1 µA
V
MARGIN
MARGIN Voltage MARGIN = Open 1.65 V
R
MARGIN
MARGIN Input Resistance 16.5 kΩ
∆V
FB
Feedback Voltage Adjustment V
MARGIN
= 3.3V ●456 %
V
MARGIN
= 0V ●–6 –5 –4 %
G
ERR
Error Amplifier Open-Loop DC Gain V
COMP
= 0.8V to 1.2V, Load = 2kΩ, 100pF ●65 90 dB
BW
ERR
Error Amplifier Unity-Gain Bandwidth No Load (Note 6) 2 MHz
V
CLAMP
Error Amplifier Output Clamp Voltage V
FB
= 0V 2 V
I
VCOMP
Error Amplifier Source Current V
FB
= 0V ●–25 –10 mA
Error Amplifier Sink Current V
FB
= 5V, V
COMP
= 1.233V ●37 mA
OPTODRV
G
OPTO
Opto Driver DC Gain OVPIN, V
ISNS
, V
ISNSGND
= 0V ●4.75 5 5.25 V/V
BW
OPTO
Opto Driver Unity-Gain Bandwidth No Load (Note 6) 1 MHz
V
OPTOHIGH
Opto Driver Output High Voltage V
FB
, OVPIN, V
ISNSGND
= 0V, V
ISNS
= –50mV,
I
OPTODRV
= –10mA ●45 V
I
OPTOSC
Opto Driver Output Short-Circuit Current OVPIN, V
ISNSGND
, V
ISNS
= 0V, V
FB
= 1.233V ●–50 –25 –10 mA
GN PART MARKING
1698
1698I
3
LTC1698
1698f
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 8V, unless otherwise noted. (Note 4)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired. All voltages refer to GND.
Note 2: The LTC1698 incorporates a 5V linear regulator to power internal
circuitry. Driving these pins above 5.3V may cause excessive current flow.
Guaranteed by design and not subject to test.
Note 3: The LTC1698E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. For guaranteed performance to
specifications over the –40°C to 85°C range, the LTC1698I is available.
Note 4: All currents into device pins are positive; all currents out of the
device pins are negative. All voltages are referenced to ground unless
otherwise specified. For applications with V
DD
< 7V, refer to the Typical
Performance Characteristics.
Note 5: Supply current in active operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC1698 operating frequency, supply voltage and the external FETs
used.
Note 6: This parameter is guaranteed by correlation and is not tested.
Note 7: V
FB
is tested in an op amp feedback loop which servos V
FB
to the
internal bandgap voltage.
Note 8: The current comparator output current varies linearly with
temperature.
Note 9: The PWRGD and OVP comparators incorporate 10mV of
hysteresis.
Note 10: The driver disable time-out is proportional to the SYNC period
within the frequency synchronization range.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
AUX
V
AUX
Auxiliary Supply Voltage C
VAUX
= 0.1µF, I
LOAD
= 0mA to 10mA, V
DD
= 7V to 12.6V ●3.135 3.320 3.465 V
Current Limit Amplifier
I
ISNSGND
I
SNSGND
Input Current V
ISNSGND
= 0V ●0.05 1 µA
I
ISNS
I
SNS
Input Current V
ISNS
= 0V ●0.05 1 µA
V
ILIMTH
Current Limit Threshold V
ICOMP
= 2.5V, V
ISNSGND
= 0V –27.0 –25 –23.0 mV
(V
ISNS
– V
ISNSGND
)●–27.5 –25 –22.5 mV
I
ICOMP
I
COMP
Source Current V
ISNSGND
= 0V, V
ISNS
= –0.3V, V
ICOMP
= 2.5V (Note 8) –280 –200 –120 µA
●–370 –200 –80 µA
I
COMP
Sink Current V
ISNSGND
= 0V, V
ISNS
= 0.3V, V
ICOMP
= 2.5V (Note 8) 120 200 280 µA
●80 200 370 µA
g
mILIM
Current Limit Amplifier V
ISNSGND
= 0V, V
ICOMP
= 2.5V, I
ICOMP
= ±10µA●2.2 3.5 5 millimho
Transconductance
G
ICOMP
Current Limit Amplifier V
ICOMP
= 2.5V, No Load ●48 60 dB
Open-Loop DC Gain
PWRGD and OVP Comparators
V
PWRGD
Percent Below V
FB
V
FB
↓, MARGIN = Open (Note 9) ●–9 –6 –3 %
I
PWRGD
Power Good Sink Current V
FB
= 2V ●10 µA
V
FB
= 0V ●10 mA
V
OL
Power Good Output Low Voltage I
PWRGD
= 3mA, V
FB
= 0V ●0.4 V
V
OVPREF
OVPIN Threshold V
FB
= V
ISNS
= V
ISNSGND
= 0V, OVPIN ↑ (Note 9) ●1.18 1.233 1.28 V
I
OVPIN
OVPIN Input Bias Current V
OVPIN
= 1.233V ●0.1 1 µA
t
PWRGD
Power Good Response Time V
FB
↑●125 ms
Power Bad Response Time V
FB
↓●0.5 1 2.5 ms
t
OVP
Overvoltage Response Time V
OVPIN
↑, C
OPTODRV
= 0.1µF●520 µs
SYNC and Drivers
V
PT
SYNC Input Positive Threshold ●1 1.6 2.2 V
V
NT
SYNC Input Negative Threshold ●–2.2 –1.6 –1 V
I
SYNC
SYNC Input Current V
SYNC
= ±10V ●150 µA
f
SYNC
SYNC Frequency Range C
FG
= C
CG
= 1000pF, V
SYNC
= ±5V ●50 400 kHz
t
d
SYNC Input to Driver Output Delay C
FG
= C
CG
= 1000pF, f
SYNC
= 100kHz, V
SYNC
= ±5V ●40 90 ns
t
SYNC
Minimum SYNC Pulse Width f
SYNC
= 100kHz, V
SYNC
= ±10V (Note 6) ●75 ns
t
r
, t
f
Driver Rise and Fall Time C
FG
= C
CG
= 1000pF, f
SYNC
= 100kHz, V
SYNC
= ±5V, ●10 40 ns
10% to 90%
t
DDIS
Driver Disable Time-Out C
FG
= C
CG
= 1000pF, f
SYNC
= 100kHz, V
SYNC
= ±5V
Measured from CG ↑ (Note 10) ●10 15 20 µs
4
LTC1698
1698f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VFB vs Temperature
TEMPERATURE (°C)
–50
V
FB
(V)
1.236
1.242
1.248
25 75 150
1698 G01
1.230
1.224
1.218 –25 0 50 100 125
V
DD
= 8V
V
DD
(V)
5
1.218
V
FB
(V)
1.224
1.236
1.242
1.248
7910 14
1698 G02
1.230
68 11 12 13
T
A
= 25°C
V
MARGIN
(V)
0
V
FB
(V)
∆V
FB
(%)
1.245
1.270
1.295
2.64
1698 G03
1.221
1.196
1.233
1.258
1.282
1.208
1.184
1.171
1
3
5
–1
–3
0
2
4
–2
–4
–5
0.660.33 1.320.99 1.98 2.31 2.97
1.65 3.3
V
DD
= 8V
T
A
= 25°C
VFB vs VDD VFB vs VMARGIN
ISNS Threshold vs Temperature ISNS Threshold vs VDD
Current Limit Amplifier gm
vs Temperature
TEMPERATURE (°C)
–50
–27.5
I
SNS
THRESHOLD (mV)
–27.0
–26.0
–25.5
–25.0
–22.5
–24.0
050 75
1698 G04
–26.5
–23.5
–23.0
–24.5
–25 25 100 125 150
V
DD
= 8V
V
DD
(V)
5
–27.5
I
SNS
THRESHOLD (mV)
–27.0
–26.0
–25.5
–25.0
–22.5
–24.0
87 10 11
1698 G05
–26.5
–23.5
–23.0
–24.5
69
12 13 14
T
A
= 25°C
TEMPERATURE (°C)
–50
g
mILIM
(millimho)
3.8
4.2
4.6
100 125
1698 G06
3.4
3.0
–25 250 50 75 150
2.6
2.2
5.0 V
DD
= 8V
OVPIN Threshold vs Temperature OVPIN Threshold vs VDD
Power Good Threshold
vs Temperature
TEMPERATURE (°C)
–50
OVPIN THRESHOLD (V)
1.24
1.26
1.28
25 75 150
1698 G07
1.22
1.20
1.18 –25 0 50 100 125
V
DD
= 8V
V
DD
(V)
5
1.18
OVPIN THRESHOLD (V)
1.20
1.24
1.26
1.28
7910 14
1698 G08
1.22
68 11 12 13
T
A
= 25°C
TEMPERATURE (°C)
–50
POWER GOOD THRESHOLD (V)
∆V
FB
(%)
1.166
1.181
1.196
25 75 150
1698 G09
1.152
1.137
1.122
–5.4
–4.2
–3.0
–6.6
–7.8
–9.0
–25 0 50 100 125
V
DD
= 8V
5
LTC1698
1698f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VAUX vs Temperature VAUX vs Line Voltage VAUX vs Load Current
VAUX Short-Circuit Current
vs Temperature VAUX Short-Circuit Current
vs VDD Opto Driver Load Regulation
Opto Driver Short-Circuit Current
vs Temperature
TEMPERATURE (°C)
–50
V
AUX
(V)
3.300
3.383
150
1698 G10
3.218
3.135 050 100
–25 25 75 125
3.465
3.259
3.341
3.176
3.424
V
DD
= 8V
I
LOAD
= 0mA
V
DD
(V)
5
V
AUX
(V)
3.300
3.383
14
1698 G11
3.218
3.135 78 10 12
6911 13
3.465
3.259
3.341
3.176
3.424
V
DD
= 8V
I
LOAD
= 0mA
LOAD CURRENT (mA)
0
V
AUX
(V)
3.300
3.383
109
1698 G12
3.218
3.135 23 57
1468
3.465
3.259
3.341
3.176
3.424
V
DD
= 8V
T
A
= 25°C
TEMPERATURE (°C)
–50
V
AUX
SHORT-CIRCUIT CURRENT (mA)
–20
–10
0
25 75 150
1698 G13
–30
–40
–50 –25 0 50 100 125
V
DD
= 8V
V
DD
(V)
5
V
AUX
SHORT-CIRCUIT CURRENT (mA)
–20
–10
0
810 14
1698 G14
–30
–40
–50 67 911 12 13
T
A
= 25°C
LOAD CURRENT (mA)
0
OPTO DRIVER OUTPUT VOLTAGE (V)
PERCENT (%)
3.006
3.018
3.030
8
1698 G15
2.994
2.982
3.000
3.012
3.024
2.988
2.976
2.970
0.2
0.6
1.0
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0
21 43 67 9
510
V
DD
= 8V
T
A
= 25°C
TEMPERATURE (°C)
–50
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
–30
–20
150
1698 G16
–40
–50 050 100
–25 25 75 125
–10
–35
–25
–45
–15
V
DD
= 8V
V
OPTODRV
= 1.233V
Maximum OPTO Driver Output
Voltage vs Load Current Maximum OPTO Driver Output
Voltage vs Temperature
LOAD CURRENT (mA)
0
MAXIMUM OPTO DRIVER OUTPUT VOLTAGE (V)
4
6
8
1698 G22
2
024510
8
6
139
7
V
DD
= 10V
V
DD
= 8V
V
DD
= 7V
V
DD
= 6V
V
DD
= 5V
T
A
= 25°C
V
COMP
= 0V
TEMPERATURE (°C)
–50
0
MAXIMUM OPTO DRIVER OUTPUT VOLTAGE (V)
2
4
6
8
–25 0 25 50
1698 G23
75 100 125 150
V
DD
= 10V
V
DD
= 8V
V
DD
= 6V
V
DD
= 5V
V
COMP
= 0V
I
OPTODRV
= –10mA
V
DD
= 7V
6
LTC1698
1698f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
IVDD vs SYNC Frequency
f
SYNC
(kHz)
50
I
VDD
(mA)
30
40
50
450
1698 G19
20
10
25
35
45
15
5
0150100 250200 350 400
300 500
V
DD
= 8V
T
A
= 25°CC
FG
= C
CG
= 4700pF
C
FG
= C
CG
= 3300pF
C
FG
= C
CG
= 2200pF
C
FG
= C
CG
= 1000pF
TEMPERATURE (°C)
–50
SYNC POSITIVE THRESHOLD (V)
2.00
2.25
25 75 150
1698 G20
1.75
1.50
1.25
1.00 –25 0 50 100 125
V
DD
= 8V
V
DD
(V)
5
1.00
SYNC POSITIVE THRESHOLD (V)
1.24
1.72
1.96
2.20
7910 14
1698 G21
1.48
68 11 12 13
T
A
= 25°C
SYNC Positive Threshold
vs Temperature SYNC Positive Threshold
vs VDD
Undervoltage Lockout Threshold
vs Temperature
TEMPERATURE (°C)
–50
V
UVLO
(V)
3
4
5
25 75 150
1698 G24
2
1
0–25 0 50 100 125
IVDD vs VDD
Opto Driver Short-Circuit Current
vs VDD
V
DD
(V)
5
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
–20
–10
0
810 14
1698 G17
–30
–40
–50 67 911 12 13
T
A
= 25°C
V
OPTODRV
= 1.233V
V
DD
(V)
5
I
VDD
(mA)
12
16
20
13
1698 G18
8
4
10
14
18
6
2
076 98 11 12
10 14
T
A
= 25°C
f
SYNC
= 100kHz C
FG
= C
CG
= 4700pF
C
FG
= C
CG
= 3300pF
C
FG
= C
CG
= 2200pF
C
FG
= C
CG
= 1000pF
DRIVER LOAD (pF)
0
TIME (ns)
4000 8000 10000
90
80
70
60
50
40
30
20
10
0
1698 G25
2000 6000
VDD = 8V
TA = 25°C
CG, FG tPHL
tftr
CG, FG tPLH
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125 150
t
d
(ns)
90
80
70
60
50
40
30
20
10
0
1698 G26
V
DD
= 8V
C
CG
= C
FG
= 1000pF
f
SYNC
= 100kHz
CG, FG t
PLH
CG, FG t
PHL
f
SYNC
(kHz)
50
DRIVER DISABLE TIME-OUT t
DISS
(µs)
150 250 300 500
1698 G27
100 200 350 400 450
30
25
20
15
10
5
0
NORMALIZED DRIVER DISABLE TIME-OUT
t
DISS
× f
SYNC
2.2
2.0
1.8
1.6
1.4
1.2
1.0
V
DD
= 8V
T
A
= 25°C
t
DISS
× f
SYNC
t
DISS
Driver Rise, Fall and Propagation
Delay vs Driver Load SYNC Input to Driver Output Delay
vs Temperature Driver Disable Time-Out vs SYNC
Frequency
7
LTC1698
1698f
UU
U
PI FU CTIO S
V
DD
(Pin 1): Power Supply Input. For isolated applica-
tions, a simple rectifier from the power transformer is
used to power the chip. This pin powers the opto driver,
the V
AUX
supply and the FG and CG drivers. An internal 5V
regulator powers the remaining circuitry. V
DD
requires an
external 4.7µF bypass capacitor.
CG (Pin 2): Catch Gate Driver. If SYNC slews positive, CG
pulls high to drive an external N-channel MOSFET. CG
draws power from the V
DD
pin and swings between V
DD
and PGND.
PGND (Pin 3): Power Ground. Connect PGND to a low
impedance ground plane in close proximity to the ground
terminal of the external current sensing resistor.
GND (Pin 4): Logic and Signal Ground. GND is referenced
to the internal low power circuitry. Careful board layout
techniques must be used to prevent corruption of signal
ground reference. Connect GND and PGND together di-
rectly at the LTC1698.
OPTODRV (Pin 5): Optocoupler Driver Output. This pin
drives a ground referenced optocoupler through an exter-
nal resistor. If V
FB
is low, OPTODRV pulls low. If V
FB
is
high, OPTODRV pulls high. This optocoupler driver has a
DC gain of 5. During overvoltage or overcurrent condi-
tions, OPTODRV pulls high. The output is capable of
sourcing 10mA of current and will drive an external 0.1µF
capacitive load and is short-circuit protected.
V
COMP
(Pin 6): Error Amplifier Output. This error amplifier
is able to drive more than 2kΩ and 100pF of load. The
internal diode connected from V
FB
to V
COMP
reduces
OPTODRV recovery time under start-up conditions.
MARGIN (Pin 7): Current Input to Adjust the Output
Voltage Linearly. The MARGIN pin connects to an internal
16.5k resistor. The other end of this resistor is regulated
to 1.65V. Connecting MARGIN to a 3.3V logic supply
sources 100µA of current into the chip and moves the
output voltage 5% higher. Connecting MARGIN to 0V
sinks 100µA out of the pin and moves the regulated output
voltage 5% lower. The MARGIN pin voltage does not affect
the PWRGD and OVPIN trip points.
V
FB
(Pin 8): Feedback Voltage. V
FB
senses the regulated
output voltage through an external resistor divider. The
V
FB
pin is servoed to the reference voltage of 1.233V under
closed-loop conditions. An RC network from V
FB
to V
COMP
compensates the feedback loop. If V
FB
goes low, V
COMP
pulls high and OPTODRV goes low.
OVPIN (Pin 9): Overvoltage Input. OVPIN is a high imped-
ance input to an internal comparator. The threshold of this
comparator is set to 1.233V. If the OVPIN potential is
higher than the threshold voltage, OPTODRV pulls high
immediately. Use an external RC lowpass filter to prevent
noisy signals from triggering this comparator.
PWRGD (Pin 10): Power Good Output. This is an open-
drain output. PWRGD floats if V
FB
is above 94% of the
nominal value for more than 2ms. PWRGD pulls low if V
FB
is below 94% of the nominal value for more than 1ms. The
PWRGD threshold is independent of the MARGIN pin
potential.
I
SNSGND
(Pin 11): Current Sense Ground. Connect to the
positive side of the sense resistor, normally grounded.
I
SNS
(Pin 12): Current Sense Input. Connect to the nega-
tive side of the sense resistor through an external RC
lowpass filter. This pin normally sees a negative voltage,
which is proportional to the average load current. If
current limit is exceeded, OPTODRV pulls high.
I
COMP
(Pin 13): Current Amplifier Output. An RC network
at this pin compensates the current limit feedback loop.
Referencing the RC to V
OUT
controls output voltage over-
shoot on start-up. This pin can float if current limit loop
compensation is not required.
V
AUX
(Pin 14): Auxiliary 3.3V Logic Supply. This pin
requires a 0.1µF or greater bypass capacitor. This auxiliary
power supply can power external devices and sources
10mA of current. Internal current limiting is provided.
SYNC (Pin 15): Drivers Synchronization Input. A negative
voltage slew at SYNC forces FG to pull high and CG to pull
low. A positive voltage slew at SYNC resets the FG pin and
CG pulls high. If SYNC loses its synchronization signal for
more than the driver disable time-out interval, both the
forward and catch drivers output are forced low. The SYNC
circuit accepts pulse and square wave signals. The mini-
mum pulse width is 75ns. The synchronization frequency
range is between 50kHz to 400kHz.
FG (Pin 16): Forward Gate Driver. If SYNC slews negative,
FG goes high. FG draws power from V
DD
and swings
between V
DD
and PGND.
8
LTC1698
1698f
BLOCK DIAGRA
W
I-TO-V CONVERTER
RMARGIN
20k
ROVP
3k
100k
VFB 0.94VREF
MPWRGD
RILIM
3k
MILIM
MARGIN
7
SYNC
15
OPTODRV
5
±5% VREF
VREF
BANDGAP
SYNC IN
VCC
VDD
VAUX
14
–
+
–
+
–+
ERR
–
+
ILIM 25mV
–
+
OVP
VREF
1698 BD
+
OPTO
PWRGD
10
OVPIN 9
ICOMP 13
ISNS 12
ISNSGND 11
VCOMP 6
VFB 8
CG 2
FG 16
PWRGD
AUX GEN VCC GEN
1
OPERATIO
U
The LTC1698 is a secondary-side synchronous rectifier
controller designed to work with the LT3781 primary-side
synchronous controller chip to form an isolated synchro-
nous forward converter. This chip set uses a dual transis-
tor forward topology that is predominantly used in distrib-
uted power supply systems where isolated low voltages
are needed to power complex electronic equipment. The
primary stage is a current mode, fixed frequency forward
converter and provides the typical PWM operation. A
power transformer is used to provide the functions of
input/output isolation and voltage step-down to achieve
the required low output voltage. Instead of using typical
Schottky diodes, synchronous rectification on the sec-
ondary offers isolation with high efficiency. It supplies
high power without the need of bulky heat sinks, which is
often a problem in any space constrained application.
The LTC1698 not only provides synchronous drivers for
the external MOSFETs, it comes with other housekeeping
functions performed on the secondary side of the power
supply, all within a single integrated controller. Figure 1
shows the typical chip-set application. Upon power up, the
LTC1698’s V
DD
input is low, the gate drivers TG and BG are
both at the ground potential. The secondary forward and
(Refer to Block Diagram)
9
LTC1698
1698f
catch MOSFETs Q3 and Q4 are off. As soon as transistors
Q1 and Q2 turn on, the flux in the power transformer T1
forces the body diodes of Q3 and Q4 to conduct, and the
whole circuit starts like a conventional forward converter.
At the same time, the LTC1698 V
DD
potential ramps up
quickly through the V
DD
bias circuitry. Once the V
DD
voltage exceeds 4.0V, the LTC1698 enables its drivers and
enters synchronous operation.
The pulse transformer T2 synchronizes the primary and
secondary MOSFET drivers. In a typical conversion cycle,
the primary MOSFETs Q1 and Q2 turn on simultaneously.
SG goes low and generates a negative spike at the LTC1698
SYNC input through the pulse transformer. The LTC1698
forces FG to turn on and CG to turn off. Power is delivered
to the load through the transformer T1 and the inductor L1.
At the beginning of the next phase in which Q1 and Q2 turn
off, SG goes high, SYNC sees a positive spike, the MOSFET
Q3 shuts off, Q4 conducts and allows continuous current
to flow through the inductor L1. The capacitor C
OUT
filters
the switching waveform to provide a steady DC output
voltage for the load.
The LTC1698 error amplifier ERR senses the output volt-
age through an external resistor divider and regulates the
V
FB
pin potential to the 1.233V internal bandgap voltage.
An external RC network across the V
FB
and V
COMP
pins
frequency compensates the error amplifier feedback. The
opto driver amplifies the voltage difference between the
V
COMP
pin and the bandgap potential, driving the external
optocoupler diode with an inverting gain of 5. The
optocoupler feeds the amplified output error signal to the
primary controller and closes the forward converter volt-
age feedback loop. Under start-up conditions, the internal
diode across the LTC1698 error amplifier clamps the
V
COMP
pin. This speeds up the opto driver recovery time by
reducing the negative slew rate excursion at the COMP pin.
The forward converter output voltage can be easily ad-
justed. The potential at the MARGIN pin is capable of
forcing the error amplifier reference voltage to move
linearly by ±5%. The internal R
MARGIN
resistor converts
the MARGIN voltage to a current and linearly controls the
offset of the error amplifier. Connecting the MARGIN pin
to 3.3V increases the V
FB
voltage by 5%, and connecting
the MARGIN pin to 0V reduces V
FB
by 5%. With the
MARGIN pin floating, the VFB voltage is regulated to the
internal bandgap voltage.
The current limit transconductance amplifier I
LIM
provides
the secondary side average current limit function. The
average voltage drops across the R
SECSEN
resistor is
sensed and compared to the –25mV threshold set by the
internal I
LIM
amplifier. Once I
LIM
detects high output
current, the current amplifier output pulls high, overrides
the error amplifier, injects more current into the photo
diode and forces a lower duty cycle. An RC network
connected to the I
COMP
pin is used to stabilize the second-
ary current limit loop. Alternatively, if only overcurrent
fault protection is required, I
COMP
can float.
If under abnormal conditions the feedback path is broken,
OVPIN provides another route for overvoltage fault pro-
tection. If the voltage at OVPIN is higher than the bandgap
voltage, the OVP comparator forces OPTODRV high im-
mediately. A simple external RC filter prevents a momen-
tary overshoot at OVPIN from triggering the OVP
comparator. Short OVPIN to ground if this pin is not used.
The LTC1698 provides an open-drain PWRGD output. If
V
FB
is less than 94% of its nominal value for more than
1ms, the PWRGD comparator pulls the PWRGD pin low.
If V
FB
is higher than 94% of its nominal value for more than
2ms, the transistor M
PWRGD
shuts off, and an external
resistor pulls the PWRGD pin high.
The LTC1698 provides an auxiliary 3.3V logic power
supply. This auxiliary power supply is externally compen-
sated with a minimum 0.1µF bypass capacitor. It supplies
up to 10mA of current to any external devices.
OPERATIO
U
(Refer to Block Diagram)
10
LTC1698
1698f
APPLICATIO S I FOR ATIO
WUUU
Undervoltage Lockout
In UVLO (low V
DD
voltage) the drivers FG and CG are shut
off and the pins OPTODRV, V
AUX
, PWRGD and I
COMP
are
forced low. The LTC1698 allows the bandgap and the
internal bias currents to reach their steady-state values
before releasing UVLO. Typically, this happens when V
DD
reaches approximately 4.0V. Beyond this threshold, the
drivers start switching. The OPTODRV, V
AUX
, PWRGD and
I
COMP
pins return to their normal values and the chip is
fully functional. However, if the V
DD
voltage is less than 7V,
the OPTODRV and V
AUX
current sourcing capabilities are
limited. See the OPTO driver graphs in the Typical Perfor-
mance Characteristics section.
V
DD
Regulator
The bias supply for the LTC1698 is generated by peak
rectifying the isolated transformer secondary winding. As
shown in Figure 2, the zener diode Z1 is connected from
base of Q5 to ground such that the emitter of Q5 is
regulated to one diode drop below the zener voltage. R
Z
is
selected to bring Z1 into conduction and also provide base
current to Q5. A resistor (on the order of a few hundred
ohms), in series with the base of Q5, may be required to
surpress high frequency oscillations depending on Q5’s
selection. A power MOSFET can also be used by increasing
the zener diode value to offset the drop of the gate-to-
source voltage. V
DD
supply current varies linearly with the
supply voltage, driver load and clock frequency. A 4.7µF
bypass capacitor for the V
DD
supply is sufficient for most
applications. This capacitor must be large enough to
provide a stable DC voltage to meet the LTC1698 V
DD
supply requirement. Under start-up conditions, it must be
small enough to power up instantaneously, enabling the
LTC1698 to regulate the feedback loop. Using a larger
capacitor requires evaluation of the start-up performance.
SYNC Input
Figure 3 shows the synchronous forward converter appli-
cation. The primary controller LT3781 runs at a fixed
frequency and controls MOSFETs Q1 and Q2. The second-
ary controller LTC1698 controls MOSFETs Q3 and Q4. An
inexpensive, small-size pulse transformer T2 synchro-
nizes the primary and the secondary controllers. Figure 4
shows the pulse transformer timing waveforms. When the
LT3781 synchronization output SG goes low, MOSFET
V
SECONDARY
1Ω
D3
R
Z
2k R
B
*
*R
B
IS OPTIONAL, SEE TEXT
Z1
10V
Q5
FZT690
0.47µF
4.7µF
1698 F02
V
DD
Figure 2. VDD Regulator
••
••
D2 T1
T2
V
IN
D1
Q1
Q2 Q3
Q4
PRIMARY
CONTROLLER
LT3781
TG
BG
SG
SECONDARY
CONTROLLER
LTC1698
CG
L1
C
OUT
V
OUT
FG SYNC
C
SG
ISOLATION BARRIER
SECONDARYPRIMARY
C
SYNC
R
SYNC
1698 F03
Figure 3. Synchronization Using Pulse Transformer
TG
BG
SG
SYNC
FG
CG
1698 F04
Figure 4. Primary Side and Secondary Side
Synchronization Waveforms
11
LTC1698
1698f
drivers TG and BG go high. The pulse transformer T2
generates a negative slew at the SYNC pin and forces the
secondary MOSFET driver FG to go high and CG to go low.
When TG and BG go low, SG goes high and the secondary
controller forces CG high and FG low.
For a given pulse transformer, a bigger capacitor C
SG
generates a higher and wider SYNC pulse. The peak of this
pulse should be much higher than the SYNC threshold.
Amplitudes greater than ±5V help to speed up the SYNC
comparator and reduce the SYNC to FG and CG drivers
propagation delay. The minimum pulse width is 75ns.
Overshoot during the pulse transformer reset interval
must be minimized and kept below the minimum com-
parator thresholds of ±1V. The amount of overshoot can
be reduced by having a smaller reset resistor R
SYNC
. For
nonisolated applications, the SYNC input can be driven
directly by a square pulse. To reduce the propagation
delay, make the positive and negative magnitude of the
square wave much greater than the ±2.2V maximum
threshold.
In addition to the simple driver synchronization, the sec-
ondary controller requires a driver disable signal. Loss of
synchronization while CG is high will cause Q4 to dis-
charge the output capacitor. This produces a negative
output voltage transient and possible damage to the load
circuitry connected to V
OUT
. To overcome this problem,
the LTC1698 comes with a unique adaptive time-out
circuit. It works well within the 50kHz to 400kHz frequency
range. At every positive SYNC pulse, the internal timer
resets. If the SYNC signal is missing, the internal timer
loses its reset command, and eventually exceeds the
internal time-out limit. This forces both the FG and CG
drivers to go low immediately.
The time-out duration varies linearly with the LT3781
primary controller clocking frequency. Upon power up,
the time-out circuitry takes a few clock cycles to adapt to
the input clock frequency. During this time interval, the
drivers pulse width might be prematurely terminated, and
the inductor current flows through the MOSFETs body
diode. Once the LTC1698 timer locks to the clocking
frequency, the LTC1698 drivers follow the SYNC signal
without fail. Figure 5 shows the SYNC time-out wave-
forms. The time-out circuit guarantees that if the SYNC
pulse is missing for more than one period, both the
drivers will be shut down preventing the output voltage
from going below ground. The wide synchronization
frequency range adds flexibility to the forward converter
and allows this converter chip set to meet different
application requirements.
Under normal operating conditions, the time-out circuitry
adapts to the switching frequency within a few cycles.
Once synchronized, internal circuitry ensures the maxi-
mum time that the Catch FET (Q4) could be left turned on
is typically just over one switching period. This is particu-
larly important with high output voltages that can generate
significant negative output inductor currents if the Catch
FET Q4 is left on. Poor feedback loop performance includ-
ing output voltage overshoot can cause the primary con-
troller to interrupt the synchronization pulse train. While
this generally is not a problem, it is possible that low
frequency interruptions could lead to a time-out period
longer than a switching period, limited only by the internal
timer clamp (50µs typical).
Output Voltage Programming
The switching regulator output voltage is programmed
through a resistor feedback network (R1 and R2 in
Figure 1) connected to V
FB
. If the output is at its nominal
value, the divider output is regulated to the error amplifier
threshold of 1.233V.
The output voltage is thus set according to the relation:
V
OUT
= 1.233 • (1 + R2/R1)
APPLICATIO S I FOR ATIO
WUUU
SG
SYNC
FG
CG
RESET
(INTERNAL)
DISDRI
(INTERNAL)
1698 F05
Figure 5. SYNC Time-Out Waveforms
12
LTC1698
1698f
MARGIN Adjustment
The MARGIN input is used for adjusting the programmed
output voltage linearly by varying the current flowing into
and out of the pin. Forcing 100µA into the pin moves the
output voltage 5% higher. Forcing 100µA out of the pin
moves the output voltage 5% lower. With the MARGIN pin
floating, the V
FB
pin is regulated to the bandgap voltage of
1.233V. The MARGIN pin is a high impedance input. It is
important to keep this pin away from any noise source like
the inductor switching node. Any stray signal coupled to
the MARGIN pin can affect the switching regulator output
voltage.
This pin is internally connected to a 16.5k resistor that
feeds the I-V converter. The I-V converter output linearly
controls the error amplifier offset voltage. The input of the
I-V converter is biased at 1.65V. This allows the ±100µA
current to be obtained by connecting the MARGIN pin to
the V
AUX
3.3V supply (+5%) or GND (–5%). For output
voltage adjustment smaller than ±5%, an external resistor
R
EXT
as shown in Figure 6 is added in series with the
internal resistor to lower the current flowing into or out of
the MARGIN pin. The value of R
EXT
is calculated as follow:
RREQUIRED k
EXT
=
51165
%
%–•.
V
FB
loop causes the error amplifier to drive the OPTODRV
pin low, forcing the primary controller to increase the duty
cycle. This causes the output voltage to increase to a
dangerously high level. To eliminate this fault condition,
the OVP comparator monitors the output voltage with a
resistive divider at OVPIN. A voltage at OVPIN higher than
the V
REF
potential forces the OPTODRV pin high and
reduces the duty cycle, thus preventing the output voltage
from increasing further.
The OVPIN senses the output voltage through a resistor
divider network (R4 and R5 in Figure 1). The divider is
ratioed such that the voltage at OVPIN equals 1.233V when
the output voltage rises to the overvoltage level. The
overvoltage level is set following the relation:
V
OVERVOLTAGE
= 1.233 • (1 + R5/R4)
The OVP comparator is designed to respond quickly to an
overvoltage condition. A small capacitor from OVPIN to
ground keeps any noise spikes from coupling to the OVP
pin. This simple RC filter prevents a momentary overshoot
from triggering the OVP comparator.
The OVP comparator threshold is independent of the
potential at the MARGIN pin. If the OVP function is not
used, connect OVPIN to ground.
Power Good
The PWRGD pin is an open-drain output for power good
indication. PWRGD floats if V
FB
is above 94% of the
nominal value for more than 2ms. An external pull-up
resistor is required for PWRGD to swing high. PWRGD
pulls low if V
FB
drops below 94% of the nominal value for
more than 1ms. The PWRGD threshold is referenced to the
1.233V bandgap voltage, which remains unchanged if the
MARGIN pin is exercised.
Opto Feedback and Frequency Compensation
For a forward converter to obtain good load and line
regulation, the output voltage must be sensed and com-
pared to an accurate reference potential. Any error voltage
must be amplified and fed back to the supply’s control
circuitry where the sensed error can be corrected. In an
isolated supply, the control circuitry is frequently located
on the primary. The output error signal in this type of
7I-V CONVERTER
R
MARGIN
R
EXT
(OPTIONAL)
REDUCE
V
FB
INCREASE
V
FB
MARGIN
14
BANDGAP
AUX GEN
V
DD
V
AUX
3.3V V
AUX
0.1µF
V
REF
±5% V
REF
–
+
ERR V
FB
V
COMP
1698 F06
8
6
APPLICATIO S I FOR ATIO
WUUU
Figure 6. Output Voltage Adjustment
Overvoltage Function
The OVPIN is used for overvoltage protection and is
designed to protect against an open V
FB
loop. Opening the
13
LTC1698
1698f
supply must cross the isolation boundary. Coupling this
signal requires an element that will withstand the isolation
potentials and still transfer the loop error signal.
Optocouplers are widely used for this function due to their
ability to couple DC signals. To properly apply them, a
number of factors must be considered. The gain, or
current transfer ratio (CTR) through an optocoupler is
loosely specified and is a strong function of the input
current through the diode. It changes considerably as a
function of time (aging) and temperature. The amount of
aging accelerates with higher operating current. This
variation directly affects the overall loop gain of the sys-
tem. To be an effective optical detector, the output transis-
tor of the optocoupler must have a large base area to
collect the light energy. This gives it a large collector to
base capacitance which can introduce a pole into the
feedback loop. This pole varies considerably with the
current and interacts with the overall loop frequency
compensation network.
The common collector optocoupler configuration removes
the miller effect due to the parasitic capacitance and
increases the frequency response. Figure 7 shows the
optocoupler feedback circuitry using the common collec-
tor approach. Note that the terms R
D
, CTR, C
DE
and r
π
vary
from part to part. They also change with bias current. The
dominant pole of the opto feedback is due to R
F
and C
F
. The
feedforward capacitor C
K
at the optocoupler creates a low
frequency zero. This zero should be chosen to provide a
phase boost at the loop crossover frequency. The parallel
combination of R
K
and R
D
form a high frequency pole with
C
K
. For most optocouplers, R
D
is 50Ω at a DC bias of 1mA,
and 25Ω at a DC bias of 2mA. The CTR term is the small
signal AC current transfer ratio. For the QT Optoelectron-
ics MOC207 optocoupler used here, the AC CTR is around
1, even though the DC CTR is much lower when biased at
1mA or 2mA. The first denominator term in the V
C
/V
OUT
equation has been simplified and assumes that C
FB
<<C
C
.
The actual term is:
sR C C sR CC
CC
CFB CCFB
CFB
••( )• •• •
21++ +
APPLICATIO S I FOR ATIO
WUUU
V
V
sC R
sR C sR C
sR C
sC RR
RR
R CTR
RR srC sRC
C
OUT
CC
CCFB
KK
KKD
KD
F
DK DE FF
=+++
++
+
++
π
–(••)
(••)•( •• )
•• (••)
•• ••••(••)
•(••)
1
21 51
1
1
1
1
1
wherewhere
R Optocoupler diode equivalent small signal resis ce
CTR Optocoupler current transfer ratio
C Optocoupler nonlinear capacitor across base to emitter
r Optocoupler small signalresis ce across the base emitter
D
DE
:tan
tan
=−
=
=
=−
π
20k
V
REF
V
COMP
C
C
C
FB
R
C
V
REF
R2
V
OUT
LTC1698
V
FB
1698 F07
100k
OPTODRV
R
K
C
K
MOC207
–
+
–
+
V
REF
LT3781
V
FB
V
CC
C
F
V
C
R
F
R1
R
E
–
+
Figure 7. Error Signal Feedback
14
LTC1698
1698f
A series RC network can be added in parallel with R2
(Figure 7) to provide a zero for the feedback loop fre-
quency compensation.
The opto driver will drive a capacitive load up to 0.1µF. For
optocouplers with a base pin, switching signal noise can
get into this high impedance node. Connect a large resis-
tor, 1M or 2M between the base and the emitter. This
increases the diode current and the overall feedback
bandwidth slightly, and decreases the optocoupler gain.
When designing the resistor in series with the optocoupler
diode, it is important to consider the part to part variations
in the current transfer ratio and its reduction over tem-
perature and aging. The bigger the biasing current, the
faster the aging. The LTC1698 opto driver is designed to
source up to 10mA of current and swing between 0.4V to
(V
DD
– 2.5V). This should meet the design consideration
of most optocouplers.
Besides the voltage feedback function, the LTC1698 opto
driver couples fault signals to the primary controller and
prevents catastrophic damage to the circuit. Upon current
limit or an overvoltage fault, the I
LIM
or OVP comparator
overrides the error amplifier output and forces the
OPTODRV pin high. This sources maximum current into
the external optodiode and reduces the forward converter
duty cycle.
Average Current Limit
The secondary current limit function is implemented by
measuring the negative voltage across the current sense
resistor R
SECSEN
. The current limit transconductance
amplifier I
LIM
has a –25mV threshold. As shown in
Figure 8, if the secondary current is small, the I
COMP
pin
goes low and the transistor M
ILIM
shuts off. The potential
at V
COMP
determines the OPTODRV output. If the second-
ary current is large, I
COMP
pulls high and forces the tran-
sistor M
ILIM
to turn on hard. Thus the current limit circuit
overrides the voltage feedback and forces OPTODRV high
and injects maximum current into the external optocoupler.
The R
ILIM
resistor provides a linear relationship between
the current sensed and the OPTODRV output.
The ISNS and ISNSGND pins allow a true Kelvin current
sense measurement and offer true differential measure-
ment across the sense resistor. A differential lowpass
filter formed by R6 and C2 removes the pulse-to-pulse
inductor current ripple and generates the average sec-
ondary current which is equal to the load current. The
lowpass corner frequency is typically set to 1 to 2 orders
of magnitude below the switching frequency and follows
the relationship:
RmV
I
R
Cf
SECSEN LMAX
SW
=
=π
25
61
22
10
•• •
where:
R
SECSEN
= Secondary current sense resistor
I
LMAX
= Maximum allowed secondary current
f
SW
= Forward converter switching frequency
APPLICATIO S I FOR ATIO
WUUU
–
+
–
+
12
11
2
16
OPTO
I
LIM
+
OPTODRV
V
OUT
R
CILM
C
CILM
V
REF
V
COMP
LTC1698
I
SNSGND
I
SNS
FG
CG
DRIVE
25mV
20k
100k
M
ILIM
R
ILIM
3k
5
I
COMP
13 C2
Q4
Q3
T1
R
SECSEN
1698 F08
R6
R6
R
DIV
(OPTIONAL)
Figure 8. Secondary Average Current Limit
15
LTC1698
1698f
If the application generates a bigger current sense voltage,
a potential divider can be easily obtained by adding a
resistor across C2. With this additional resistor, the volt-
age sensed by the current comparator becomes:
R
RR
V
DIV
DIV RSENSE
+(• )
•
26
An RC network formed by R
CILM
and C
CILM
between I
COMP
and V
OUT
can be used to stabilize the current limit loop.
Connecting the compensation network to V
OUT
minimizes
output overshoot during start-up or short-circuit recov-
ery. The R
CILM
and C
CILM
zero should be chosen to be well
within the closed-loop crossover frequency. This pin can
be left floating if current loop compensation is not re-
quired. The forward converter secondary current limit func-
tion can be disabled by shorting I
SNS
and I
SNSGND
to ground.
Auxiliary 3.3V Logic Power Supply
An internal P-channel LDO (low dropout regulator) pro-
duces the 3.3V auxiliary supply that can power external
devices or drive the MARGIN pin. This supply can source
up to 10mA of current and the current limit is provided
internally. The pin requires at least a 0.1µF bypass
capacitor.
MOSFET Selection
Two logic-level N-channel power MOSFETs (Q3 and Q4 in
Figure 1) are required for most LTC1698 circuits. They are
selected based primarily on the on-resistance and body
diode considerations. The required MOSFET R
DS(ON)
should
be determined based on input and output voltage, allow-
able power dissipation and maximum required output
current.
The average inductor (L1) current is equal to the output
load current. This current is always flowing through either
Q3 or Q4 with the power dissipation split up according to
the duty cycle:
DC Q V
V
N
N
DC Q V
V
N
N
OUT
IN
P
S
OUT
IN
P
S
() •
() – •
3
41
=
=
where N
P
/N
S
is the turns ratio of the transformer T1.
The R
DS(ON)
required for a given conduction loss can now
be calculated by rearranging the relation P = I
2
R.
PIRDCQ
RP
IDCQ
PIRDCQ
RP
IDCQ
MAX Q MAX DS ON Q
DS ON Q MAX Q
MAX
MAX Q MAX DS ON Q
DS ON Q MAX Q
MAX
() ()
() ()
() ()
() ()
••()
•()
••()
•()
323
33
2
424
44
2
3
3
4
4
=
⇒=
=
⇒=
where I
MAX
is the maximum load current and P
MAX
is the
allowable conduction loss.
In a typical 2-transistor forward converter circuit, the duty
cycle is less than 50% to prevent the transformer core
from saturating. This results in the duty cycle of Q4 being
greater than that of Q3. Q4 will dissipate more power due
to the higher duty cycle. A lower RDS(ON) MOSFET can be
used for Q4. This will slow down the turn-on time of Q4
since a lower RDS(ON) MOSFET will have a larger gate
capacitance.
The next consideration for the MOSFET is the characteris-
tic of the body diode. The body diodes conduct during the
power-up phase, when the LTC1698 V
DD
supply is ramp-
ing up and the time-out circuit is adapting to the SYNC
input frequency. The CG and FG signals terminate prema-
turely and the inductor current flows through the body
diodes. The body diodes must be able to take the compa-
rable amount of current as the MOSFETs. Most power
MOSFETs have the same current rating for the body diode
and the MOSFET itself.
The LTC1698 CG and FG MOSFET drivers will dissipate
power. This will increase with higher switching frequency,
higher V
DD
or larger MOSFETs. To calculate the driver
dissipation, the total gate charge Qg is used. This param-
eter is found on the MOSFET manufacturers data sheet.
The power dissipated in each LTC1698 MOSFET driver is:
P
DRIVER
= Qg • V
DD
• f
SW
where f
SW
is the switching frequency of the converter.
APPLICATIO S I FOR ATIO
WUUU
16
LTC1698
1698f
Power Transformer Selection
The forward transformer provides DC isolation and deliv-
ers energy from the primary to the secondary. Unlike the
flyback topology, the transformer in the forward converter
is not an energy storage device. As such, ungapped ferrite
material is typically used. Select a power material rated
with low loss at the switching frequency. Many core
manufacturers have selection guides and application notes
for transformer design. A brief overview of the more
important design considerations is presented here.
For operating frequencies greater than 100kHz, the flux
in the core is usually limited by core loss, not saturation.
It is important to review both criteria when selecting the
trans
former. The AC operating flux density for core loss is
given by:
BVDC
NAf
AC IN
PeSW
=••
•••
10
2
8
where:
B
AC
is the AC operating flux density (gauss)
DC is the operating duty cycle
A
e
is the effective cross sectional core area (cm
2
)
f
SW
is the switching frequency
To prevent core saturation during a transient condition,
the peak flux density is:
BV DC MAX
NAf
PK IN MAX
PeSW
=
()
•( )•
••
10
8
The minimum secondary turns count is:
NN
VV
V DC MAX
S MIN P OUT D
IN MIN
() ()
••( )
=+
where:
V
OUT
is the secondary output voltage
V
D
is the voltage drop across the rectifier in the secondary
V
IN(MIN)
is the minimum input voltage
DC(MAX) is the maximum duty cycle
The core must be sized to provide sufficient window area
for the amount of wire and insulation needed. The best
performance is achieved by making each winding a single
layer evenly distributed across the width of the bobbin.
Multiple layers may be used to increase the copper area.
Interleaving the primary and secondary windings will
decrease the leakage inductance.
In a single-ended forward converter, much of the energy
stored in the leakage inductance is dissipated in the
primary-side MOSFET during turn-off. It is good design
practice to sandwich the secondary winding between two
primary windings.
For the 2-transistor forward converter shown in Figure 1,
energy stored in the leakage inductance is returned to the
input by diodes D1 and D2. With this topology, additional
insulation for higher isolation can be used without signifi-
cant penalty.
For a more detailed discussion on transformer core and
winding losses, see Application Note AN19.
Inductor Selection
The output inductor in a typical LTC1698 circuit is chosen
for inductance value and saturation current rating. The
output inductor in a forward converter operates the same
as in a buck regulator. The inductance sets the ripple
current, which is commonly chosen to be 40% of the full
load current. Ripple current is set by:
IVt
L
RIPPLE OUT OFF MAX
=•
()
where:
tDC MIN
f
OFF MAX SW
()
–()
=
()
1
and DC(MIN) is calculated based on the maximum input
voltage.
DC MIN N
N
V
V
P
S
OUT
IN MAX
() •
()
=
APPLICATIO S I FOR ATIO
WUUU
17
LTC1698
1698f
Once the value of the inductor has been determined, an
inductor with sufficient DC current rating is selected. Core
saturation must be avoided under all operating conditions.
Under start-up conditions, the converter sees a short
circuit while charging the output capacitor. If the inductor
saturates, the peak current will dramatically increase. The
current will be limited only by the primary controller
minimum on time and the circuit impedances.
High efficiency converters generally cannot afford the core
loss found in low cost iron powder cores, forcing the use
of more expensive ferrite, molypermalloy, or Kool Mµ
®
cores. As inductance increases, core loss goes down.
Increased inductance requires more turns of wire so
copper losses will increase. The optimum inductor will
have equal core and copper loss.
Ferrite designs have very low core losses and are preferred
at higher switching frequencies. Therefore, design goals
concentrate on minimizing copper loss and preventing
saturation. Kool Mµ is a very good, low-loss powder
material with a “soft” saturation characteristic.
Molypermalloy is more efficient at higher switching fre-
quencies, but is also more expensive. Surface mount
designs are available from many manufacturers using all
of these materials.
Output Capacitor Selection
The output capacitor selection is primarily determined by
the effective series resistance (ESR) to minimize voltage
ripple. In a forward converter application, the inductor
current is constantly flowing to the output capacitor,
therefore, the ripple current at the output capacitor is
small. The output ripple voltage is approximately given by:
V I ESR fC
RIPPLE RIPPLE SW OUT
≈+
•••
1
8
The output ripple is highest at maximum input voltage
since I
RIPPLE
increases with input voltage. Typically, once
the ESR requirement for C
OUT
has been satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
Fast load current transitions at the output will appear as a
voltage across the ESR of the output capacitor until the
feedback loop can change the inductor current to match
the new load current value. As an example: at 3.3V out, a
10A load step with a 0.01Ω ESR output capacitor would
experience a 100mV step at the output, a 3% output
change. In surface mount applications, multiple capaci-
tors may have to be placed in parallel to meet the ESR
requirement.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1698. These items are also illustrated graphically in
Figure 9. Check the following for your layout:
1. Keep the power circuit and the signal circuit segre-
gated. Place the power circuit, shown in bold, so that
the two MOSFET drain connections are made directly at
the transformer. The two MOSFET sources should be as
close together as possible.
2. Connect PGND directly to the sense resistor with as
short a path as possible. The MOSFET gate drive return
currents flow through this connection.
3. Connect the 4.7µF ceramic capacitor directly between
V
DD
and PGND. This supplies the FG and CG drivers and
must supply the gate drive current.
4. Bypass the V
AUX
supply with a 0.1µF ceramic capacitor
returned to GND.
5. Place all signal components in close proximity to their
associated LTC1698 pins. Return all signal component
grounds directly to the GND pin. One common connec-
tion can be made to V
OUT+
from R2, R5 and C
CILM
.
6. Make the connection between GND and PGND right at
the LTC1698 pins.
7. Use a Kelvin-sense connection from the I
SNS
and I
SNSGND
pins to the secondary-side current-limit resistor
R
SECSEN
.
APPLICATIO S I FOR ATIO
WUUU
Kool Mµ is a registered trademark of Magnetics, Inc.
18
LTC1698
1698f
APPLICATIO S I FOR ATIO
WUUU
CG
V
DD
LTC1698
PGND
GND
OPTODRV
V
COMP
MARGIN
C
FB
R1
BOLD LINES INDICATE HIGH CURRENT PATHS
R
C
C
C
V
FB
SYNC
FG
V
AUX
I
COMP
I
SNS
I
SENSGND
PWRGD
OVPIN
2
1
3
4
5
6
7
8
15
16
C
OUT
V
OUT+
V
OUT–
14
13
12
11
10
9
R2R7
D3
R
SECSEN
Q4
C
K
R
K
MOC207
C4
0.1µFR4
1698 F09
1k
0.1µF
4.7µF
T2
T1
0.1µF
C
CILM
R
CILM
R5
1k
+
Q3
1Ω
L1
•
•
•
•
Figure 9. LTC1698 Layout Diagram
Figure 10. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter
V
COMP
V
DD
LTC1698
GND
V
FB
CG
FG
I
SNS
SYNC
OPTODRV
V
CC
BIAS
L1 V
OUT1
3.3V
AT 10A
BG
LT3781
SG
ISOLATION
BOUNDARY
C
OUT2
: POSCAP, 680µF/4V
L2: SUMIDA CEP125-IR8MC-H
Q1, Q2: SILICONIX Si7440DP
1698 F10
V
IN
36V
TO 72V
V
REF
V
C
V
FB
TG
••
GBIAS
4.7µF
CMDSH-3
Q1
Q2 B340A
3.01k
2.32k
L2
1.8µH0.006Ω
V
CC
BOOST
CL
–
CL
+
LT3710
SYNC
TG
CSET
ILCOMP
SS
••
–
+
0.1µF
3.3k
33nF
10pF
C
S
680pF
10k
10k
180pF
0.01µFBGS
PGND
SW
BG
VA
OUT
V
FB
4700pF
V
OUT2
1.8V
AT 10A
C
OUT2
+
220Ω
19
LTC1698
1698f
Figure 11. 36VIN-72VIN to 5V/30A Isolated Synchronous Forward Converter
TYPICAL APPLICATIO S
U
V
CC
13
2
1
5
1µF0.01µF
82pF
OVLO
SHDN
1.24k
1%
10k
4.7µF
16V
1000pF
5V
REF
6
F
SET
0.1µF
8
SS
10
12
T2
PULSE ENG
P2033
BAS21
BAS21
BAT54
BAT54S
ZVN3310F
9
V
C
PGND
14
V
FB
37 4
THERM
LT3781
SYNC SGND
52.3k
1% 10Ω
1k
3k
1k
3.3k
FZT690B 0.22µF
50V
1
10k
220pF
MOC207
143
1
4
8
7
5
14
15
8
5
6
7
2
3300pF
2200pF
4700pF
5V
REF
5V
REF
SG
11
SENSE
15
BG
18
BSTREF
19
TG
20
BAS21
0.1µF
100V
1mH
DO1608C-105
COILCRAFT
V
BST
1.5µF
100V
1.5µF
100V
0.56µH
DO1813P-561HC
0.022µF
1000pF
••
SYNC V
FB
OVPIN
MARGIN
I
COMP
V
DD
OPTODRV
V
AUX
0.1µF
1612 11
I
SNS
I
SNSGND
FG
2
CG
PGND GND
LTC1698
PWRGD
6
8
9
7
13
1.24k
1% 976Ω
1%
4.22k
1% 3.01k
1%
1043
V
COMP
1698 F11
MMBZ5240B
0.008Ω
1%, 1W
1000pF
100V
2200pF
250V
AC
•
•••
T1
PULSE
PA0285
PULSE
PA0265
100Ω
10Ω
V
IN+
36V TO 72V
V
IN–
V
OUT+
5V /30A
V
OUT–
RTN
10Ω
1/4W
1000pF
100V
10Ω
1/4W
330pF
+
+
+
+
3.3Ω
V
IN
V
IN
V
CC
V
CC
V
OUT
V
CC
V
OUT
V
CC
V
IN
V
CC
0Ω
2.43k
1%
RT1
100k
1µF
ON/OFF
V
OUT
TRIM
4.7µF
16V
470Ω
V
OUT
FZT853
B0540W
100Ω
0.25W 2k
0.25W
5241B
11V
20k
FMMT619
FMMT718
Si7456DP
Si7456DP Si7456DP
Si7884DP Si7884DP Si7884DP Si7884DP Si7884DP
Si7456DP
0.047µF
B2100
B2100
470µF
6.3V
POSCAP
470µF
6.3V
POSCAP
470µF
6.3V
POSCAP
470µF
6.3V
POSCAP
22µF
6.3V
1µF
16V
0Ω
B0540W
MMBD4148
0Ω
270k
0.25W 73.2k
1%
1
2
3
4
5
7
20
LTC1698
1698f
Figure 12. LT3781/LTC1698 36VIN-72VIN to 3.3V/15A Isolated Synchronous Forward Converter-Quarter Brick
TYPICAL APPLICATIO S
U
V
CC
13
2
1
5
1µF0.01µF
82pF
OVLO
SHDN
1.24k
1%
10k
270k
1/4W
100µF
20V
1000pF
5V
REF
6
F
SET
4700pF
8
SS
10
BAT54
BAT54
PULSE ENG
PA0184
BAS21
BAS21
BAT54
ZETEX
ZVN3310F
9
V
C
PGND
12
V
FB
37 4
THERM
LT3781
SYNC SGND
52.3k
1% 10Ω
1k
3k
1k
1k
2k
FZT690B
4.7µF
0.22µF
1
10k
5V
REF
MOC207
7143
8
1
5
4
5
14
15
6
5
82
3300pF 4700pF
220pF
5V
REF
14
SG
+
11
SENSEBG
18
BSTREF
19 1617
TG NC NC
15 20
BAS21
0.1µF
1mH
DO1608C-105
COILCRAFT
V
BST
3.3µH
D01608C-332
COILCRAFT
0.022µF
1000pF
••
SYNC V
FB
OVPIN
MARGIN
I
COMP
V
DD
OPTODRV
V
AUX
0.1µF
1612 11
FG
2
CG
PGND GND
LTC1698
PWRGD
6
8
9
7
13
1.78k
1% 1.24k
1%
3.01k
1% 2.43k
1%
3410
V
COMP
1698 F12
1k
0.22µF
MBR0540
0.03Ω
Si7456DP
Si7456DP
1000pF
100V
1000pF
100V
2200pF
250V
MURS120
MURS120
10Ω
•
••
T1
38431
SCHOTT
10Ω
MMBT3906
MMBD914
MMBT3906
V
IN+
V
IN–
0.82µF
100V 0.82µF
100V
×2
V
OUT+
V
OUT–
330pF
+
+
+
330µF
6.3V
KEMET
T520
330µF
6.3V
KEMET
T520
330µF
6.3V
KEMET
T520 330µF
6.3V
KEMET
T520
+
3.3Ω
V
CC
V
IN
V
CC
V
CC
10k
2.43k
1%
RT1
100k
0.1µF
ON/OFF
TRIM
V
OUT+
4.7Ω
10V
MMBZ5240B
470Ω
–
+
3.01k
1% 3.01k
1%
3.01k
1%
3.01k
1%
100Ω
1/4W
100Ω
1/4W
9V
V
OUT
V
OUT+
3
4
2
1LT1783CS5
+SENSE
–SENSE
OPTIONAL DIFFERENTIAL SENSE**
V
CC
V
IN
5V
REF
FQT7N10L
100Ω
1/4W 100Ω
1/4W
47k
62k
1/4W
4.7µF
MMBT3904
OPTIONAL FAST START*
V
IN
18V
MMBZ5248B
•
0.1µF
100Ω
9V
5
I
SNS
I
SNSGND
0.1µF
1k
1k
Si7892DP Si7892DP Si7892DP Si7892DP
10Ω
1/4W
10Ω
1/4W
R
OUT
(OPTIONAL)
73.2k
1%
3300pF
R
IN
(OPTIONAL)
1
2
3
4
5
6
78
21
LTC1698
1698f
TYPICAL APPLICATIO S
U
V
CC
14
2
1
5
1µF
25V 82pF
OVLO
SHDN
1.24k
1%
73.2k
1%
24k
10k
270k
0.25W
68µF
25V
1000pF
56k
5V
REF
6
F
SET
4700pF
8
SS
10
13
BAT54
BAT54
T2
MIDCOM, INC
31264R
BAS21LT1
BAS21LT1
BAT54
ZVN3310F
9
V
C
PGND
12
I
MAX
V
FB
37 4
THERM
LT3781
SYNC SGND
52.3k
1% 10Ω
1k
3k
1k
3.3k
20k
0.25W 100Ω
0.25W FZT603
ZETEX
4.7µF
16V
0.22µF
50V
1
10k
5V
REF
ISO1
MOC207
7143
3
14
6
5
14
15
6
5
82
3300pF
4700pF
47Ω
0.01µF
50V
5V
REF
15
SG
+
11
SENSE
16
BG
18
BSTREF
19
TG
17 20
BAS21LT1
0.1µF
100V
1mH
DO1608C-105
COILCRAFT
BLKSENS
V
BST
220pF
1.5µF
100V
4.7µH
DO1608C-472
COILCRAFT
0.022µF
1000pF
•
•
SYNC V
FB
OVPIN
MARGIN
I
COMP
V
DD
OPTODRV
V
AUX
0.1µF
50V
0.1µF
50V
16
I
SNS
I
SNSGND
FG
2
CG
PGND GND
LTC1698
PWRGD
6
8
9
7
13
909Ω
0.1%
8.25k
0.1%
3411 1012
V
COMP
1698 F13
1k
0.01µF
MURS120T3
0.025Ω
1/2W
3
67
5
4
SUD40N10-25
SUD40N10-25
SUD40N10-25
470pF
100V
470pF
100V
2200pF
250V
MURS120T3
MURS120T3
10Ω
1
8
11
12
10
9
•
••
2
T1
EFD25
10Ω
V
IN+
V
IN–
1.5µF
100V
1.5µF
100V
V
OUT+
V
OUT–
68µF
25V
AVX
68µF
25V
AVX
68µF
25V
AVX
68µF
25V
AVX
22Ω
0.25W
22Ω
0.25W
25µH
MAG INC CORE
55380-A2 18T #18AWG
330pF
+
+
+
+
V
TOP
3.3Ω
V
IN
V
CC
V
IN
V
CC
V
TOP
V
TOP
V
OUT–
V
OUT+
V
CC
15V
MMBZ5245BLT1
20k
0.1µF
50V
0.33µF
50V
V
OUT+
BAT54
10Ω
0.25W
10V
MMBZ5240BLT1
10k
1k
UNLESS NOTED:
ALL PNPs MMBT39O6LT1
NC
0.015Ω
100pF
200Ω
18V
MMBZ5248BLT1
110Ω
0.1µF
T1 EFD25-3F3
LP = 120µH
2mil GAP EACH LEG
2M
POLYESTER
FILM
SQUARE 0.031 INCH
MARGIN TAPE
PINS 9-10 5T BIFILAR 33AWG
PINS 2-5 12T BIFILAR 33AWG
PINS 4-3 7T QUADFILAR 26AWG
PINS 7,8-11,12 12T BIFILAR 24AWG
PINS 6-4 8T QUADFILAR 26AWG
Si4486EY
×2Si4486EY
×2
•
215Ω215Ω
0.033µF
Figure 13. 36VIN-72VIN to 12V/5A Isolated Synchronous Forward Converter
22
LTC1698
1698f
GN16 (SSOP) 0502
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
U
PACKAGE DESCRIPTIO
23
LTC1698
1698f
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
1
N
2345678
N/2
.150 – .157
(3.810 – 3.988)
NOTE 3
16 15 14 13
.386 – .394
(9.804 – 10.008)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
S16 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
123 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
24
LTC1698
1698f
LINEAR TECHNOLOGY CORPORATION 2000
LT/TP 0203 2K • PRINTED IN THE USA
PART NUMBER DESCRIPTION COMMENTS
LT1339 High Power Synchronous DC/DC Controller Operation Up to 60V Maximum
LT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistor
LT1431 Programmable Reference 0.4% Initial Voltage Tolerance
LT1680 High Power DC/DC Step-Up Controller Operation Up to 60V Maximum
LT1681 Dual Transistor Synchronous Forward Controller Operation Up to 72V Maximum
LT1725 General Purpose Isolated Flyback Controller Drives External Power MOSFET with External I
SENSE
Resistor
LT1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding
LT3710 Secondary Side Synchronous Post Regulator Generates a Regulated Auxiliary Output in Isolated DC/DC Converters, Dual
N-Channel MOSFET Synchronous Drivers
LT3781 Dual Transistor Synchronous Forward Controller Operation up to 72V Maximum
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO S
U
LT3781/LTC1698 Isolated 3.3V/15A Converter
LT3781/LTC1698 Isolated 3.3V/15A Converter
LOAD CURRENT (A)
0
EFFICIENCY (%)
95
90
85
80
75
70
65 510 15 20
1698 TA01
25 30
V
IN
= 36V
V
IN
= 72V
V
IN
= 48V
I
OUT
(XX)
0
EFFICIENCY (%)
95
90
85
80
75
70 12
1698 TA02
36915
V
IN
= 36V
V
IN
= 72V
V
IN
= 48V
LT3781/LTC1698 Isolated 3.3V/15A Converter
Efficiency vs Load Current
LT3781/LTC1698 Isolated 5V/30A Converter
Efficiency vs Load Current
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