M28F010 1024K (128K x 8) CMOS FLASH MEMORY Y Y Y Y Y Y Flash Electrical Chip-Erase 5 Second Typical Quick-Pulse Programming Algorithm 10 ms Typical Byte-Program 2 Second Typical Chip-Program Single High Voltage for Writing and Erasing CMOS Low Power Consumption 30 mA Maximum Active Current 100 mA Maximum Standby Current Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface Y Y Y Y ETOX-III Flash-Memory Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience Compatible with JEDEC-Standard Byte-Wide EPROM Pinouts 10,000 Program/Erase Cycles Minimum Available in Three Product Grades: QML: b 55 C to a 125 C (TC) SE2: b 40 C to a 125 C (TC) SE3: b 40 C to a 110 C (TC) Noise Immunity Features g 10% VCC Tolerance Maximum Latch-Up Immunity through EPI Processing Intel's M28F010 is a 1024-Kbit byte-wide, in-system re-writable, CMOS nonvolatile flash memory. It is organized as 131,072 bytes of 8 bits and is available in a 32-pin hermetic CERDIP package. The M28F010 is also available in 32-contact leadless chip carrier, J-lead, and Flatpack surface mount packages. It offers the most cost-effective and reliable alternative for updatable nonvolatile memory. The M28F010 adds electrical chiperasure and reprogramming to EPROM technology. Memory contents of the M28F010 can be erased and reprogrammed 1) in a socket; 2) in a PROM programmer socket; 3) on-board during subassembly test; 4) insystem during final test; and 5) in-system after-sale. The M28F010 increases memory flexibility while contributing to time- and cost-savings. It is targeted for alterable code-, data-storage applications where traditional EEPROM functionality (byte erasure) is either not required or is not cost-effective. Use of the M28F010 is also appropriate where EPROM ultraviolet erasure is impractical or too time consuming. 271111 - 1 Figure 1. M28F010 Block Diagram January 1996 Order Number: 271111-005 M28F010 271111 - 3 271111 - 16 271111 - 2 Figure 2. M28F010 Pin Configurations Table 1. Pin Description Symbol 2 Type Name and Function A0 -A16 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. DQ0 -DQ7 INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data during memory read cycles. The data pins are active high and float to tri-state OFF when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CE INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE is active low; CE high deselects the memory device and reduces power consumption to standby levels. OE INPUT OUTPUT ENABLE: Gates the devices output through the data buffers during a read cycle. OE is active low. WE INPUT WRITE ENABLE: Controls writes to the control register and the array. Write enable is active low. Addresses are latched on the falling edge and data is latched on the rising edge of the WE pulse. Note: With VPP s VCC a 2V, memory contents cannot be altered. VPP ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing the entire array, or programming bytes in the array. VCC DEVICE POWER SUPPLY (5V g 10%) VSS GROUND NC NO INTERNAL CONNECTION to device. Pin may be driven or left floating. M28F010 271111 - 4 Figure 3. M28F010 in a M80C186 System PRINCIPLES OF OPERATION Flash-memory augments EPROM functionality with in-circuit electrical erasure and reprogramming. The M28F010 introduces a command register to manage this new functionality. The command register allows for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility. In the absence of high voltage on the VPP pin, the M28F010 is a read-only memory. Manipulation of the external memory-control pins yields the standard EPROM read, standby, output disable, and intelligent Identifier operations. The same EPROM read, standby, and output disable operations are available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables erasure and programming of the device. All functions associated with altering memory contentsintelligent Identifier, erase, erase verify, program, and program verifyare accessed via the command register. Commands are written to the register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent Identifier codes, or output data for erase and program verification. The command register is only alterable when VPP is at high voltage. Depending upon the application, the system designer may choose to make the VPP power supply switchableavailable only when memory updates are desired. When high voltage is removed, the contents of the register default to the read command, making the M28F010 a read-only memory. Memory contents cannot be altered. 3 M28F010 Table 2. M28F010 Bus Operations Pins VPP(1) A0 A9 CE Read VPPL A0 A9 Output Disable VPPL X X OE WE DQ0 -DQ7 VIL VIL VIH Data Out VIL VIH VIH Tri-State Tri-State Operation READ-ONLY READ/WRITE Standby VPPL X X VIH X X intelligent Identifier (Mfr)(2) VPPL VIL VID(7) VIL VIL VIH Data e 89H VIL VIL VIH Data e B4H VIL VIL VIH Data Out(3) intelligent Identifier (Device)(2) VPPL VIH VID(7) Read VPPH A0 A9 Output Disable VPPH X X VIL VIH VIH Tri-State Standby(4) VPPH X X VIH X X Tri-State Write VPPH A0 A9 VIL VIH VIL Data In(5) NOTES: 1. VPPL may be ground, a no-connect with a resistor tied to ground, or as defined in the Characteristics Section. VPPH is the programming voltage specified for the device. Refer to DC Characteristics. When VPP e VPPL memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other addresses low. 3. Read operations with VPP e VPPH may access array data or the intelligent Identifier codes. 4. With VPP at high voltage, the standby current equals ICC a IPP (standby). 5. Refer to Table 3 for valid Data-In during a write operation. 6. X can be VIL or VIH. 7. VID is the intelligent Identifier high voltage. Refer to DC Characteristics. Or, the system designer may choose to ``hardwire'' VPP, making the high voltage supply constantly available. In this instance, all operations are performed in conjunction with the command register. The M28F010 is designed to accommodate either design practice, and to encourage optimization of the processor-memory interface. Integrated Stop Timer Sucessive command write cycles define the durations of program and erase operations; specifically, the program or erase time durations are normally terminated by associated program or erase verify commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command. Write Protection The command register is only active when VPP is at high voltage. Depending upon the application, the system designer may choose to make the VPP pow- 4 er supply switchableavailable only when memory updates are desired. When VPP e VPPL, the contents of the register default to the read command, making the 28F010 a read-only memory. In this mode, the memory contents cannot be altered. Or, the system designer may choose to ``hardwire'' VPP, making the high voltage supply constantly available. In this case, all Command Register functions are inhibited whenever VCC is below the write lockout voltage VLKO. (See Power Up/Down Protection) The 28F010 is designed to accommodate either design practice, and to encourage optimization of the processor-memory interface. BUS OPERATIONS Read The M28F010 has two control functions, both of which must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data from the output pins, independent of device selection. Figure 6 illustrates read timing waveforms. M28F010 When VPP is high (VPPH), the read operation can be used to access array data, to output the intelligent Identifier codes, and to access data for program/ erase verification. When VPP is low (VPPL), the read operation can only access the array data. Output Disable With Output-Enable at a logic-high level (VIH), output from the device is disabled. Output pins are placed in a high-impedance state. Standby With Chip-Enable at a logic-high level, the standby operation disables most of the M28F010's circuitry and substantially reduces device power consumption. The outputs are placed in a high-impedance state, independent of the Output-Enable signal. If the M28F010 is deselected during erasure, programming, or program/erase verification, the device draws active current until the operation is terminated. intelligent Identifier Operation The intelligent Identifier operation outputs the manufacturer code (89H) and device code (B4H). Programming equipment automatically matches the device with its proper erase and programming algorithms. With Chip-Enable and Output-Enable at a logic low level, raising A9 to high voltage VID activates the operation. Data read from locations 0000H and 0001H represent the manufacturer's code and the device code, respectively. The manufacturer- and device-codes can also be read via the command register, for instances where the M28F010 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location 0000H outputs the manufacturer code (89H). A read from address 0001H outputs the device code (B4H). Write Device erasure and programming are accomplished via the command register, when high voltage is applied to the VPP pin. The contents of the register serve as input to the internal state-machine. The state-machine outputs dictate the function of the device. The command register itself does not occupy an addressable memory location. The register is a latch used to store the command, along with address and data information needed to execute the command. The command register is written by bringing WriteEnable to a logic-low level (VIL), while Chip-Enable is low. Addresses are latched on the falling edge of Write-Enable, while data is latched on the rising edge of the Write-Enable pulse. Standard microprocessor write timings are used. The three high-order register bits (R7, R6, R5) encode the control functions. All other register bits, R4 to R0, must be zero. The only exception is the reset command, when FFH is written to the register. Register bits R7 - R0 correspond to data inputs D7 - D0. Refer to AC Write Characteristics and the Erase/ Programming Waveforms for specific timing parameters. 5 M28F010 COMMAND DEFINITIONS When low voltage is applied to the VPP pin, the contents of the command register default to 00H, enabling read-only operations. Placing high voltage on the VPP pin enables read/ write operations. Device operations are selected by writing specific data patterns into the command register. Table 3 defines these M28F010 register commands. Table 3. Command Definitions Command Bus Cycles First Bus Cycle Second Bus Cycle Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3) Read Memory 1 Write X 00H Read intelligent Identifier Codes(4) 2 Write X 90H Set-up Erase/Erase(5) 2 Write X 20H Write X 20H Erase Verify(5) 2 Write EA A0H Read X EVD Set-up Program/Program(6) 2 Write X 40H Write PA PD Program Verify(6) 2 Write X C0H Read X PVD Reset(7) 2 Write X FFH Write X FFH Read IA NOTES: 1. Bus operations are defined in Table 2. 2. IA e Identifier address: 00H for manufacturer code, 01H for device code. EA e Address of memory location to be read during erase verify. PA e Address of memory location to be programmed. Addresses are latched on the falling edge of the Write-Enable pulse. 3. ID e Data read from location IA during device identification (Mfr e 89H, Device e B4H). EVD e Data read from location EA during erase verify. PD e Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable. PVD e Data read from location PA during program verify. PA is latched on the Program command. 4. Following the Read inteligent ID command, two read operations access manufacturer and device codes. 5. Figure 5 illustrates the Quick-Erase Algorithm. 6. Figure 4 illustrates the Quick-Pulse Programming Algorithm. 7. The second bus cycle must be followed by the desired command register write. 6 ID M28F010 Read Command While VPP is high, for erasure and programming, memory contents can be accessed via the read command. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. The default contents of the register upon VPP power-up is 00H. This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition. Where the VPP supply is hard-wired to the M28F010, the device powers-up and remains enabled for reads until the commandregister contents are changed. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Intelligent Identifier Command Flash-memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice. high voltage is applied to the VPP pin. In the absence of this high voltage, memory contents are protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Erase-Verify Command The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H into the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the Write-Enable pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse. The M28F010 applies an internally-generated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The erase-verify command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. The M28F010 contains an intelligent Identifier operation to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the command register. Following the command write, a read cycle from address 0000H retrieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of B4H. To terminate the operation, it is necessary to write another valid command into the register. In the case where the data read is not FFH, another erase operation is performed. (Refer to Set-up Erase/Erase). Verification then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is complete. The device can be programmed. At this point, the verify operation is terminated by writing a valid command (e.g. Program Set-up) to the command register. Figure 5, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the M28F010. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Set-up Erase/Erase Commands Set-up Program/Program Commands Set-up Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing 20H to the command register. Set-up program is a command-only operation that stages the device for byte programming. Writing 40H into the command register performs the set-up operation. To commence chip-erasure, the erase command (20H) must again be written to the register. The erase operation begins with the rising edge of the Write-Enable pulse and terminates with the rising edge of the next Write-Enable pulse (i.e., Erase-Verify Command). Once the program set-up operation is performed, the next Write-Enable pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising edge of the Write-Enable pulse. The rising edge of Write-Enable also begins the programming operation. The programming operation terminates with the next rising edge of Write-Enable, used to write the program-verify command. Refer to AC Program- This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when 7 M28F010 ming Characteristics and Waveforms for specific timing parameters. Program-Verify Command The M28F010 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at random. Following each programming operation, the byte just programmed must be verified. The program-verify operation is initiated by writing C0H into the command register. The register write terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the byte last programmed. No new address information is latched. The M28F010 applies an internally-generated margin voltage to the byte. A microprocessor read cycle outputs the data. A successful comparison between the programmed byte and true data means that the byte is successfully programmed. Programming then proceeds to the next desired byte location. Figure 4, the M28F010 Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specific timing parameters. Reset Command A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. A valid command must then be written to place the device in the desired state. EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled an expensive solution. Intel has designed extended cycling capability into its ETOX-II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric field is one-tenth that of common EEPROMs, minimizing the probabili8 ty of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 MV/ cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failureincreasing time to wearout by a factor of 100,000,000. The device is programmed and erased using Intel's Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program the device. QUICK-PULSE PROGRAMMING ALGORITHM The Quick-Pulse Programming algorithm uses programming operations of 10 ms duration. Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes verify on the first or second operation. The entire sequence of programming and byte verification is performed with VPP at high voltage. Figure 4 illustrates the Quick-Pulse Programming algorithm. QUICK-ERASE ALGORITHM Intel's Quick-Erase algorithm yields fast and reliable electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array. Erasure begins with a read of memory contents. The M28F010 is erased when shipped from the factory. Reading FFH data from the device would immediately be followed by device programming. For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (Data e 00H). This is accomplished, using the Quick-Pulse Programming algorithm, in approximately two seconds. Erase execution then continues with an initial erase operation. Erase verification (data e FFH) begins at address 0000H and continues through the array to the last address, or until data other than FFH is encountered. With each erase operation, an increasing number of bytes verify to the erased state. Erase efficiency may be improved by storing the address of the last byte verified in a register. Following the next erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 5 illustrates the Quick-Erase algorithm. M28F010 Bus Command Operation Standby Comments Wait for VPP Ramp to VPPH(1) Initialize Pulse-Count Write Set-up Program Data e 40H Write Program Valid Address/Data Standby Write Duration of Program Operation (tWHWH1) Program(2) Verify Data e C0H; Stops Program Operation Standby tWHGL Read Read Byte to Verify Programming Standby Compare Data Output to Data Expected Write Standby Read Data e 00H, Resets the Register for Read Operations Wait for VPP Ramp to VPPL(1) 271111 - 5 NOTES: 1. See DC Characteristics for value of VPPH. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no-connect with a resistor tied to ground, or as defined in Characteristics Section. Refer to Principles of Operation. 2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command. 3. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. Figure 4. M28F010 Quick-Pulse Programming Algorithm 9 M28F010 Bus Command Operation Comments Entire Memory Must e 00H Before Erasure Use Quick-Pulse Programming Algorithm (Figure 4) Wait for VPP Ramp to VPPH(1) Standby Initialize Addresses and Pulse-Count Write Set-up Erase Data e 20H Write Erase Data e 20H Standby Duration of Erase Operation (tWHWH2) Standby Addr e Byte to Verify; Data e A0H; Stops Erase Operation tWHGL Read Read Byte to Verify Erasure Standby Compare Output to FFH Increment Pulse-Count Write Write Erase Verify Read Standby Data e 00H, Resets the Register for Read Operations Wait for VPP Ramp to VPPL(1) 271111 - 6 NOTES: 1. See DC Characteristics for value of VPPH. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no-connect with a resistor tied to ground, or as defined in Characteristics Section. Refer to Principles of Operation. 2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is written with the read command. 3. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. Figure 5. M28F010 Quick-Erase Algorithm 10 M28F010 DESIGN CONSIDERATIONS VPP Trace on Printed Circuit Boards Two-Line Output Control Programming flash-memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and layout considerations given the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line control provides for: a. the lowest possible memory power dissipation and, b. complete assurance that output bus contention will not occur. To efficiently use these two control inputs, an address-decoder output should drive chip-enable, while the system's read signal controls all flashmemories and other parallel memories. This assures that only enabled memory devices have active outputs, while deselected devices maintain the low power standby condition. Power Supply Decoupling Flash-memory power-switching characteristics require careful device decoupling. System designers are interested in three supply current (ICC) issues standby, active, and transient current peaks produced by falling and rising edges of chip-enable. The capacitive and inductive loads on the device outputs determine the rnagnitudes of these peaks. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 mF ceramic capacitor connected between VCC and VSS, and between VPP and VSS. Place the high-frequency, low-inherent-inductance capacitors as close as possible to the devices. Also, for every eight devices, a 4.7 mF electrolytic capacitor should be placed at the array's power supply connection, between VCC and VSS. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply charge to the smaller capacitors as needed. Power Up/Down Protection The M28F010 is designed to offer protection against accidental erasure or programming during power transitions. Upon power-up, the M28F010 is indifferent as to which power supply, VPP or VCC, powers up first Power supply sequencing is not required. Internal circuitry in the M28F010 ensures that the command register is reset to the read mode on power up. A system designer must guard against active writes for VCC voltages above VLKO when VPP is active. Since both WE and CE must be low for a command write, driving either to VIH will inhibit writes. The control register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. M28F010 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases the usable battery life of your system because the M28F010 does not consume any power to retain code or data when the system is off. Table 4 illustrates the power dissipated when updating the M28F010. Table 4. M28F010 Typlcal Update Power Dissipation(4) Operation Notes Power Dissipation (Watt-Seconds) Array Program/Program Verify 1 0.171 Array Erase/Erase Verify 2 0.136 One Complete Cycle 3 0.478 NOTES: 1. Formula to calculate typical Program/Program Verify Power e [VPP c Y Bytes c typical Y Prog Pulses (tWHWH1 c IPP2 typical a tWHGL c IPP4 typical)] a [VCC c Y Bytes c typical Y Prog Pulses (tWHWH1 c ICC2 typical a tWHGL c ICC4 typical]. 2. Formula to calculate typical Erase/Erase Verify Power e [VPP (VPP3 typical c tERASE typical a IPP5 typical c tWHGL c Y Bytes)] a [VCC (ICC3 typical c tERASE typical a ICC5 typical c tWHGL c Y Bytes)]. 3. One Complete Cycle e Array Preprogram a Array Erase a Program. 4. ``Typicals'' are not guaranteed, but based on a limited number of samples from production lots. 11 M28F010 ABSOLUTE MAXIMUM RATINGS* Case Temperature Under BiasAAA b 55 C to a 125 C Storage Temperature AAAAAAAAAA b 65 C to a 150 C Voltage on Any Pin with Respect to Ground AAAAAAAAAA b 2.0V to a 7.0V(1) Voltage on Pin A9 with Respect to Ground AAAAAAA b 2.0V to a 13.5V(1, 2) VPP Supply Voltage with Respect to Ground During Erase/Program AAAA b 2.0V to a 14.0V(1, 2) NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. VCC Supply Voltage with Respect to Ground AAAAAAAAAA b 2.0V to a 7.0V(1) Output Short Circuit CurrentAAAAAAAAAAAAA100 mA(3) NOTES: 1. Minimum DC input voltage is b 0.5V. During transitions, inputs may undershoot to b 2.0V for periods less than 20 ns. Maximum DC voltage on output pins is VCC a 0.5V, which may overshoot to VCC a 2.0V for periods less than 20 ns. 2. Maximum DC voltage on A9 or VPP may overshoot to a 14.0V for periods less than 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. OPERATING CONDITIONS Symbol Description Min Max Units Comments V NOTE: Erase/Program are Inhibited when VPP e VPPL V VPPL VPP during Read-Only Operations 0.00 VCC a 2.0V VPPH VPP during Read/Write Operations 11.40 12.60 MIL-STD-883 Symbol Description Min Max Units TC Operating Temperature (Instant On) b 55 a 125 C VCC Digital Supply Voltage 4.50 5.50 V Extended Temperature Min Max Units TC Symbol Case Temperature (Instant On) Description b 40 a 110 C VCC Digital Supply Voltage 4.50 5.50 V Avionics Grade Symbol 12 Min Max Units TC Case Temperature (Instant On) Description b 40 a 125 C VCC Digital Supply Voltage 4.50 5.50 V M28F010 DC CHARACTERISTICSTTL/NMOS COMPATIBLE Symbol Limits Parameter Min Unit Comments Max ILI Input Leakage Current g 1.0 mA VCC e VCC Max VIN e VCC or VSS ILO Output Leakage Current g 10 mA VCC e VCC Max VOUT e VCC or VSS ICCS VCC Standby Current 1.0 mA VCC e VCC Max CE e VIH ICC1 VCC Active Read Current 30 mA VCC e VCC Max, CE e VIL f e 6 MHz, IOUT e 0 mA ICC2 VCC Programming Current 30 mA Programming in Progress ICC3 VCC Erase Current 30 mA Erasure in Progress IPPS VPP Leakage Current g 10 mA VPP e VPPL IPP1 VPP Read Current 200 mA VPP e VPPH Max g 10 VPP e VPPL IPP2 VPP Programming Current 30 mA VPP e VPPH Max Programming in Progress IPP3 VPP Erase Current 30 mA VPP e VPPH Max Erasure in Progress VIL Input Low Voltage b 0.5 0.8 V VIH Input High Voltage 2.0 VCC a 0.5 V VOL Output Low Voltage 0.45 V IOL e 2.1 mA VCC e VCC Min VOH1 Output High Voltage V IOH e b 2.5 mA VCC e VCC Min VID A9 intelligent Identifer Voltage IID A9 intelligent Identifier Current 2.4 11.50 13.00 V 500 mA A9 e VID 13 M28F010 DC CHARACTERISTICSCMOS COMPATIBLE Symbol (Over Specified Operating Conditions) Limits Parameter Min Unit Comments Max ILI Input Leakage Current g 1.0 mA VCC e VCC Max VIN e VCC or VSS ILO Output Leakage Current g 10 mA VCC e VCC Max VOUT e VCC or VSS ICCS VCC Standby Current 100 mA VCC e VCC Max CE e VCC g 0.2V ICC1 VCC Active Read Current 30 mA VCC e VCC Max, CE e VIL f e 6 MHz, IOUT e 0 mA ICC2 VCC Programming Current 30 mA Programming in Progress ICC3 VCC Erase Current 30 mA Erasure in Progress IPPS VPP Leakage Current g 10 mA VPP e VPPL IPP1 VPP Read Current 200 mA VPP e VPPH Max g 10 VPP e VPPL IPP2 VPP Programming Current 30 mA VPP e VPPH Max Programming in Progress IPP3 VPP Erase Current 30 mA VPP e VPPH Max Erasure in Progress VIL Input Low Voltage b 0.5 0.8 V VIH Input High Voltage 0.7 VCC VCC a 0.5 V VOL Output Low Voltage 0.45 V VOH1 Output High Voltage VOH2 0.85 VCC V VCC b 0.4 VID A9 intelligent Identifer Voltage IID A9 intelligent Identifier Current 11.50 IOL e 2.1 mA VCC e VCC Min IOH e b 2.5 mA, VCC e VCC Min IOH e b 100 mA, VCC e VCC Min 13.00 V 500 mA A9 e VID CAPACITANCE TC e 25 C, f e 1.0 MHz Symbol Limits Parameter Min 14 Unit Conditions Max CIN Address/Control Capacitance 6 pF VIN e 0V COUT Output Capacitance 12 pF VOUT e 0V M28F010 AC TESTING INPUT/OUTPUT WAVEFORM AC LOAD CIRCUIT 271111 - 7 AC Testing: Inputs are driven at VOH1 for a logic ``1'' and VOL for a logic ``0''. Testing measurements are made at VIH for a logic ``1'' and VIL for a logic ``0''. Rise/Fall time s 10 ns. 271111 - 8 CL e 100 pF CL includes Jig Capacitance AC TEST CONDITIONS Input Rise and Fall Times (10% to 90%)AAAAAA10 ns Input Pulse Levels AAAAAAAAAAAAAAAAAVOL and VOH1 Input Timing Reference Level AAAAAAAAAAVIL and VIH Output Timing Reference Level AAAAAAAAVIL and VIH AC CHARACTERISTICSRead-Only Operations Versions M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Symbol Characteristic Min tAVAV/tRC Read Cycle Time 90 tELQV/tCE Chip Enable Access Time Max Min Max 120 Min Max 150 Min Max 200 Min Unit Max 250 ns 90 120 150 200 250 ns tAVQV/tACC Address Access Time 90 120 150 200 250 ns tGLQV/tOE Output Enable Access Time 40 50 55 60 65 ns tELQX/tLZ Chip Enable to Output in Low Z tGLQX/tOLZ Output Enable to Output in Low Z 0 0 0 0 0 ns 0 0 0 0 0 ns tGHQZ/tDF Output Disable to Output in High Z tOH tWHGL Output Hold from Address, CE, or OE Change(1) Write Recovery Time before Read 30 30 35 45 60 ns 0 0 0 0 0 ns 6 6 6 6 6 ms NOTE: 1. Whichever occurs first. 15 271111- 9 M28F010 Figure 6. AC Waveforms for Read Operations 16 M28F010 AC CHARACTERISTICSWrite/Erase/Program Operations(1,2) Versions M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Characteristic Min tAVAV/tWC Write Cycle Time 90 120 150 200 250 ns tAVWL/tAS Address Set-Up Time 0 0 0 0 0 ns tWLAX/tAH Address Hold Time 60 60 60 90 ns tDVWH/tDS Data Set-up Time 50 50 50 50 50 ns tWHDX/tDH Data Hold Time 10 10 10 10 10 ns tWHGL Write Recovery Time before Read 6 6 6 6 6 ms tGHWL Read Recovery Time before Write 0 0 0 0 0 ms tELWL/tCS Chip Enable Set-Up Time before Write 20 20 20 20 20 ns tWHEH/tCH Chip Enable Hold Time 0 0 0 0 0 ns tWLWH/tWP Write Pulse Width 80 80 80 80 80 ns tELEH 80 80 80 80 80 ns tWHWL/tWPH Write Pulse Width High 20 20 20 20 20 ns tWHWH1 Duration of Programming Operation 10 25 10 25 10 25 10 25 10 tWHWH2 Duration of Erase Operation 9.5 10.5 9.5 10.5 9.5 10.5 9.5 10.5 9.5 10.5 ms tVPEL VPP Set-Up Time to Chip Enable Low 100 100 ns Alternative Write Pulse Width Max Min 100 Max Min 100 Max Min 100 Max Min Unit Symbol Max 25 ms NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and inactive Write-Enable times should be measured relative to the Chip-Enable waveform. 17 M28F010 ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min Unit Comments Typ Max Chip Erase Time 5(1) 30 Sec Excludes 00H Programming Prior to Erasure Chip Program Time 2(1) 24(2) Sec Excludes System-Level Overhead Erase/Program Cycles 10,000 100,000 Cycles NOTES: 1. 25 C, 12.0V VPP, 10,000 Cycles. 2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program a 6 msec write recovery), while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 271111 - 10 Figure 7. M28F010 Typical Programming Time vs. Temperature 271111 - 11 Figure 8. M28F010 Typical Programming Time vs. VPP Voltage 18 M28F010 271111 - 12 Figure 9. M28F010 Typical Erase Time vs. Temperature 271111 - 13 Figure 10. M28F010 Typical Erase Time vs. VPP Voltage 19 Alternative Write Timing 271111- 14 M28F010 Figure 11. AC Waveforms for Programming Operations 20 271111- 15 M28F010 Figure 12. AC Waveforms for Erase Operations 21 M28F010 ADDITIONAL INFORMATION Order Number ER-20, ``ETOX II Flash Memory Technology ER-24, ``The Intel 28F010 Flash Memory'' RR-60, ``ETOX II Flash Memory Reliability Data Summary'' AP-316, ``Using Flash Memory for In-System Reprogrammable Nonvolatile Storage'' AP-325, ``Guide to Flash Memory Reprogramming'' 22 294005 294008 293002 292046 292059