1
FEATURES
>155.5 Mbps (77.7 MHz) switching rates
+340mV nominal differential signaling
5 V power supply
Cold Spare LVDS outputs
TTL compatible inputs
Ultra low power CMOS technology
5.0ns maximum, propagation delay
3.0ns maximum, differential skew
Operational environment; total dose irradiati on testi ng to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si)
- Latchup immune (LET > 111 MeV-cm2/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-95833
- QML Q and V compliant part
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 L VDS Standard
INTRODUCTION
The UT54L VDSC031 Quad Driver is a quad CMOS differential
line driver designed for applications requiring ultra low power
dissipation and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Dif ferential Signaling (LVDS) technology.
The UT54LVDSC031 accepts TTL input levels and translates
them to low voltage (340mV) differential output signals. In
addition, the driver supports a three-state function that may be
used to disable the output stage, disabling the load current, and
thus dropping the device to an ultra low idle power state.
The UT54LVDSC031 and companion quad line receiver
UT54LVDSC032 provide new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
All LVDS pins have Cold Spare buffers. These buffers will be
high impedance when V DD is tied to VSS.
D1
D2
D3
D4
DOUT1+
DOUT1-
DOUT2+
DOUT2-
DOUT3+
DOUT3-
DOUT4+
DOUT4-
DIN1
DIN2
DIN4
DIN3
EN
EN
Standard Products
UT54LVDSC031 Quad Driver
Data Sheet
October 27, 2010
www.aeroflex.com/LVDS
Figure 1. UT54LVDSC031 Quad Driver Block Diagram
2
TRUTH TABLE
PIN DESCRIPTION
APPLICATIONS INFORMATION
The UT54LVDSC031 driver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in Figure
3. This configuration provides a clean signaling environment for
quick edge rates of the drivers. The receiver is connected to the
driver through a balanced media such as a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the
characteristic impedance of the media is in the range of 100Ω. A
termination resistor of 100Ω should be selected to match the
media and is located as close to the receiver input pins as possible.
The termination resistor converts the current sourced by the
driver into voltages that are detected by the receiver. Other
configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuiti es, as wel l as groun d
shifting, noise margin limits, and total termination loading must
be taken into account.
The UT54LVDSC031 differential line driver is a balanced current
source design. A current mode driver, has a high output
impedance and supplies a constant current for a range of loads (a
voltage mode driver on the other hand supplies a constant voltage
for a range of loads). Current is switched through the load in one
direction to produce a logic state and in the other direction to
produce the other logic state. The current mode requires (as
discussed above) that a resistive termination be employed to
terminate the signal and to complete the loop as shown in Figure
3. AC or unterminated configurations are not allowed. The 3.4mA
loop curren t will develop a differential voltage of 340mV across
the 100Ω termination resistor which the receiver detects with a
240mV minimum differential noise margin neglecting resistive
line losses (driven signal minus receiver threshold (340mV -
100mV = 240mV)). The signal is centered around +1.2V (Driver
Offs et, VOS) with respect to ground as shown in Figure 4. Note:
The steady-state voltage (VSS) peak-to-peak swing is twice the
differential voltage (VOD) and is typically 680mV.
Enables Input Output
EN EN DIN DOUT+ DOUT-
L H X Z Z
All other combinations
of ENABLE inputs L L H
H H L
Pin No. Name Description
1, 7, 9, 15 DIN Driver input pin, TTL/CMOS
compatible
2, 6, 10, 14 DOUT+ Non-inverting driver output pin,
LVDS levels
3, 5, 1 1, 13 DOUT- Inv erting driver output pin,
LVDS levels
4EN Active high enable pin, OR-ed
with EN
12 EN Active low enable pin, OR-ed
with EN
16 VDD Power supply pin, +5V + 10%
8 VSS Ground pin
Figure 2. UT54LVDSC031 Pinout
UT54LVDSC031
Driver
16
15
14
13
12
11
10
9
VDD
DIN4
DOUT4+
DOUT4-
EN
DOUT3-
DOUT3+
DIN3
1
DIN1
2
DOUT1+ 3
DOUT1-
4
EN 5
DOUT2- 6
DOUT2+ 7
DIN2
8
VSS
ENABLE
DATA
INPUT
1/4 UT54LVDSC031
1/4 UT54LVDSC031
+
-DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 100Ω
3
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases
exponentially in most cases between 20 MHz - 50 MHz. This is
due to the overlap current that flows between the rails of the
device when the internal gates switch. Whereas the current mode
driver switches a fixe d current between its output without any
substantial overlap current. This is similar to some ECL and
PECL devices, but without the heavy static ICC requirements of
the ECL/PECL design. LVDS requires 80% less current th an
similar PECL devices. AC specifications for the driver are a
tenfold improvement over other existing RS-422 drivers.
The Three-State function allows the driver outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.
DIN
DOUT-
DOUT+
SINGLE-ENDED
DOUT+ - DOUT-
DIFFERENTIAL OUTPUT
V0D
3V
0V
VOH
VOS
VOL
+VOD
-VOD
0V
0V (DIFF.) VSS
Figure 4. Driver Output Levels
Note: The footprint of the UT54LVDSC031 is the same as the
industry standard Quad Differential (RS-422) Driver.
4
OPERATIONAL ENVIRONMENT
Notes:
1. Guarnteed but not tested.
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
4. During cold spare, all pins except LVDS outputs should not exceeed ±0.3V.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Ionizing Dose (TID) 1.0E6 rad(Si)
Single Event Latchup (SEL) >100 MeV-cm2/mg
Neutron Fluence11.0E13 n/cm2
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.3V to 6.0V
VI/O4Voltage on any pin during operatio n
Voltage on LVDS outp uts during cold
spare
-0.3V to (VDD + 0.3V)
-0.3V to 6.0V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.25 W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 4.5 to 5.5V
TCCase temperature range -55 to +125°C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS*1, 2
(VDD = 5.0V +10%; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates dir ectio n only.
3. Guaranteed by characterization.
4. Devices are tested @ VDD = 5.5V only.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltag e (TTL) 2.0 VDD V
VIL Low-level input voltage (TTL) VSS 0.8 V
VOL Low-level output voltage RL = 100Ω0.90 V
VOH High-level output voltage RL = 100Ω1.60 V
IIN4Input leakage current VIN = VDD -10 +10 μA
ICSOUT Cold Spare Leakage LVDS Outputs VIN=5.5V, VDD=VSS -10 +10 μΑ
VOD1Differential Output Voltage RL = 100Ω(figure 5) 250 400 mV
ΔVOD1Change in Magnitude of VOD for
Complementary Output States RL = 100Ω(figure 5) 10 mV
VOS Offset Voltage RL = 100Ω, 1.125 1.375 V
ΔVOS Change in Magnitude of VOS for
Complementary Output States RL = 100Ω(figure 5) 25 mV
VCL3Input clamp voltage ICL = -18mA -1.5 V
IOS3Output Short Circuit Current VOUT = 0V25.0 mA
IOZ4Output Three-State Current EN = 0.8V and EN = 2.0 V,
VOUT = 0V or VDD
-10 +10 μΑ
ICCL4Loaded supply current drivers
enabled RL = 100Ω all channels
VIN = VDD or VSS(all inputs) 25.0 mA
ICCZ4Loaded supply current drivers
disabled DIN = VDD or VSS
EN = VSS, EN = VDD 10.0 mA
Vos Voh Vol+
2
---------------------------
=
⎝⎠
⎛⎞
6
Figure 5. Driver VOD and VOS Test Circuit or Equivalent Circuit
Generator Vos VoD
40pF
40pF
50
Ω
50
Ω
50
Ω
7
AC SWITCHING CHARACTERISTICS1, 2, 3, 4
(VDD = +5.0V + 10%, TC = -55 °C to +125 °C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Channel-to-Channel Skew is defined as th e difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests un less otherwise specified: f = 1 MHz, ZO = 50, tr < 6 ns, and tf < 6 ns.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
SYMBOL PARAMETER MIN MAX UNIT
tPHLD Differential Propagation Delay High to Low
(figures 6 and 7) 0.5 5.0 ns
tPLHD Differential Propagation Delay Low to High
(figures 6 and 7) 0.5 5.0 ns
tSKD4Differential Skew (tPHLD - tPLHD) (figures 6 and 7) 03.0 ns
tSK14Channel-to-Channel Skew1 (figures 6 and 7) 03.0 ns
tSK24Chip-to-Chip Skew5 (figure 6 and 7) 4.5 ns
tTLH4Rise Time (figures 6 and 7) 2.0 ns
tTHL4Fall Time (figures 6 and 7) 2.0 ns
tPHZ4Disable Time High to Z (figures 8 and 9) 10 ns
tPLZ4Disable Time Low to Z (figures 8 and 9) 10 ns
tPZH4Enable Time Z to High (figures 8 and 9) 10 ns
tPZL4Enable Time Z to Low (figures 8 and 9) 10 ns
8
D
DIN
DOUT-
DOUT+
Driver Enabled
Generator
50Ω
RL = 100Ω
Figure 6. Driver Propagation Delay and Transition Time Test Circuit or Equivalant Circuit
40pF
40pF
DIN
DOUT-
DOUT+
VDIFF
tPHLD
VDD
0V
VOH
VOL
0V
VDIFF = DOUT+ - DOUT-
0V (Differential)
1.25V
tTHL
20%
80%
0V
20%
80%
tTLH
tPLHD
1.25V
Figure 7. Driver Propagation Delay and Transition Time Waveforms
9
D
VDD
VSS
DIN
EN
Generator
50ΩEN
50Ω
50Ω
DOUT+
DOUT-
VOS
Figure 8. Driver Three-State Delay Test Circuit or Equivalant Circuit
40pF
40pF
EN when EN = VDD
EN when EN = VSS
or
DOUT+ when DIN =VDD
DOUT- when DIN = VSS
DOUT+ when DIN = VSS
DOUT- when DIN = VDD tPLZ tPZL
50% 50%
VOL
1.2V
1.2V
VOH
0V
VDD
0V
VDD
1.25V
1.25V
1.25V
1.25V
50%
tPZH
tPHZ
Figure 9. Driver Three-State Delay Waveform
10
Notes:
1. All exposed metalized areas are gold plated over electrop lated nickel per MIL-PRF-385 35.
2. The lid is electrically connected to VSS.
3. Lead finishes are in ac cor da nce to MIL-P RF -38535.
4. Package dimensions and sym bols are similar to MIL-STD- 1835 variation F-5A.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option.
7. With solder, increase maximum by 0.003.
Figure 10. 16-pin Ceramic Flatpack
PACKAGING
11
ORDERING INFORMATION
UT54LVDSC031 QUAD DRIVER:
UT54LVDSC031 - * * * * *
Device Type:
UT54LVDSC031 LVDS Driver
Access T i me:
Not applicable
Package Type:
(U) = 16-lead Flatpack (dual-in-line)
Screening:
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. T ested at 25°C only . Lead finish is GOLD ONL Y.
Radiation neither tested nor guaranteed.
4. HiRel T emperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room
temp, and 125°C. Radiation neither tested nor guaranteed.
12
UT54LVDSC0 31 QUAD DRIVER: SMD
5962 - ** *
Federal Stoc k Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
Drawing Number: 95833
Device Type
03 = LVDS Driver
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(X) = 16 lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
95833 **
Notes:
1.Lead finish (A,C, or X) must be specifi ed.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
