0.1 GHz to 8 GHz,
GaAs, Nonreflective, SP4T Switch
Data Sheet
HMC344ALP3E
Rev. A Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Broadband frequency range: 0.1 GHz to 8 GHz
Nonreflective 50 Ω design
Low insertion loss: 1.7 dB at 6 GHz
High isolation: 36 dB at 6 GHz
High input linearity at 250 MHz to 8 GHz
P1dB: 28 dBm typical
IP3: 44 dBm typical
Integrated 2 to 4 line decoder
16-lead, 3 mm × 3 mm LFCSP package
ESD HBM rating: 250 V (Class 1A)
APPLICATIONS
Broadband telecommunications systems
Fiber optics
Switched filter banks
Wireless Infrastructure below 8 GHz
FUNCTIONAL BLOCK DIAGRAM
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
RF4
NIC
NIC
RF3 2:4
DECODER
HMC344ALP3E
PACKAGE
BASE
RF1
NIC
GND
RFC
GND
NIC
NIC
RF2
GND
VEE
CTLB
CTLA
14305-001
Figure 1.
GENERAL DESCRIPTION
The HMC344ALP3E is a broadband, nonreflective, single-pole,
four-throw (SP4T) switch manufactured using a gallium arsenide
(GaAs) metal semiconductor field effect transistor (MESFET)
process. This switch offers high isolation, low insertion loss, and
on-chip termination of the isolated ports.
The switch operates with a negative supply voltage (VEE) range
of −5 V to −3 V and requires two negative logic control
voltages.
The HMC344ALP3E includes an on-chip, binary two-line to
four-line decoder that provides logic control from two logic
input lines.
The HMC344ALP3E comes in a 3 mm × 3 mm, 16-lead LFCSP
package and operates from a 0.1 GHz to 8 GHz frequency range.
HMC344ALP3E Data Sheet
Rev. A | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
Typical Performance Charcteristics ................................................6
Insertion Loss, Return Loss, and Isolation ................................6
Input Power Compression and Input IP3 ..................................7
Theory of Operation .........................................................................8
Applications Information .................................................................9
Evaluation Board ...........................................................................9
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
12/2017—Rev. 01.0316 to Rev. A
Changes to Features Section, Figure 1, and General Description
Section ................................................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 2, Table 3, and Figure 4 .................................. 5
Added Figure 3 and Figure 5; Renumbered Sequentially ........... 5
Added Insertion Loss, Return Loss, and Isolation Section and
Figure 8 .............................................................................................. 6
Changes to Figure 6, Figure 7, and Figure 9.................................. 6
Added Input Power Compression and Input 1P3 Section, Figure 12,
and Figure 13 ....................................................................................... 7
Changes to Figure 10 and Figure 11 ............................................... 7
Added Theory of Operation Section ............................................. 8
Changes to Table 4 ............................................................................. 8
Added Figure 14 ................................................................................ 9
Changes to Evaluation Board Section, Figure 15, and Table 5 .... 9
Changes to Figure 16 ...................................................................... 10
Added Figure 17 ............................................................................. 10
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide ......................................................... 11
Data Sheet HMC344ALP3E
Rev. A | Page 3 of 11
SPECIFICATIONS
VEE = −3 V or −5 V, control voltage (VCTL) = 0 V or VEE, case temperature (TCASE) = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 0.1 8 GHz
INSERTION LOSS
Between RFC and RF1 to RF4 (On) 0.1 GHz to 2 GHz 1.4 2.0 dB
2 GHz to 4 GHz 1.4 2.0 dB
4 GHz to 6 GHz 1.7 2.2 dB
6 GHz to 8 GHz 2.1 2.5 dB
ISOLATION
Between RFC and RF1 to RF4 (Off) 0.1 GHz to 2 GHz 39 43 dB
2 GHz to 4 GHz 33 37 dB
4 GHz to 6 GHz 32 36 dB
6 GHz to 8 GHz 28 32 dB
RETURN LOSS
RFC and RF1 to RF4 (On) 0.1 GHz to 2 GHz 12 16 dB
2 GHz to 4 GHz 12 16 dB
4 GHz to 6 GHz 11 16 dB
6 GHz to 8 GHz 6 11 dB
RF1 to RF4 (Off) 0.1 GHz to 8 GHz 11 16 dB
SWITCHING
Rise and Fall Time tRISE, tFAL L 10% to 90% of radio frequency (RF) output 35 ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 75 ns
INPUT LINEARITY1 f = 250 MHz to 8 GHz
1 dB Power Compression P1dB VEE = −5 V 23 28 dBm
VEE = −3 V 25 dBm
Third-Order Intercept IP3 10 dBm per tone, 1 MHz spacing
VEE = −5 V 40 44 dBm
VEE = −3 V 44 dBm
SUPPLY VEE pin
Voltage VEE −5 −3 V
Current IEE 2.5 6 mA
DIGITAL CONTROL INPUTS CTLA and CTLB pins
Voltage VCTL
Low VINL VEE = −5 V −3 0 V
VEE = −3 V −1 0 V
High VINH VEE = −5 V −5 −4.2 V
VEE = −3 V −3 −2.2 V
Current ICTL
Low IINL 40 µA
High
I
INH
0.10
µA
1 Input linearity performance degrades at frequencies less than 250 MHz.
HMC344ALP3E Data Sheet
Rev. A | Page 4 of 11
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Negative Supply Voltage (VEE) −7 V
Digital Control Input Voltage Range VEE − 0.5 V to +1 V
RF Input Power
f = 250 MHz to 8 GHz, TCASE = 85°C
VEE = −5 V
Through Path 28 dBm
Terminated Path
26.5 dBm
Hot Switching 22 dBm
VEE = −3 V
Through Path 25 dBm
Terminated Path 23.5 dBm
Hot Switching 19 dBm
Temperature
Junction, TJ 150°C
Storage −65°C to +150°C
Reflow 260°C
Junction to Case Thermal Resistance, θJC
Through Path 107°C/W
Terminated Path 137°C/W
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC344ALP3E
Rev. A | Page 5 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NIC = N OT INTE RNALLY CONNECT E D. THE S E P INS
ARE NOT CO NNE CTED I NTERNAL LY; HOWE V E R, ALL
DATA S HO WN I N THIS DATA SHEE T IS M E AS URE D
WHE N THESE P INS ARE CONNECT E D TO THE RF /DC
GRO UND E X TERNALLY .
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF /DC GROUND OF THE P CB.
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
RF4
NIC
NIC
RF3
RF1
NIC
GND
RFC
GND
NIC
NIC
RF2
GND
V
EE
CTLB
CTLA
TOP VIEW
Not t o Scal e
HMC344ALP3E
14305-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 RF4 RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential does not equal 0 V dc.
2, 3, 10, 11, 13 NIC Not Internally Connected. These pins are not connected internally; however, all data shown in this data
sheet is measured when these pins are connected to the RF/dc ground externally.
4 RF3 RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential does not equal 0 V dc.
5, 14, 16 GND Ground. These pins connect to the RF/dc ground of the PCB.
6 VEE Negative Supply Voltage Pin.
7
CTLB
Control Input 2 Pin. See Table 4 for the control voltage truth table.
8 CTLA Control Input 1 Pin. See Table 4 for the control voltage truth table.
9 RF2 RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential does not equal 0 V dc.
12 RF1 RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential does not equal 0 V dc.
15 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential does not equal 0 V dc.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
14305-003
Figure 3. RFC and RF1 to RF4 Interface Schematic
600Ω 100kΩ
CTLA,
CTLB
14305-004
Figure 4. CTLA and CTLB Interface Schematic
5Ω
1.6pF
VEE
14305-005
Figure 5. VEE Interface Schematic
HMC344ALP3E Data Sheet
Rev. A | Page 6 of 11
TYPICAL PERFORMANCE CHARCTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
0
–5
–4
–3
–2
–1
0123456 7 89
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
14305-006
Figure 6. Insertion Loss vs. Frequency at Various Temperatures,
Between RFC and RF1
0
–35
–30
–25
–15
–20
–5
–10
0123456789
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
RFC
RF1 TO RF4 ON
RF1 TO RF4 OFF
14305-007
Figure 7. Return Loss vs. Frequency for RFC, RF1 to RF4 On,
and RF1 to RF4 Off
0
–5
–4
–3
–2
–1
01 2 3456 7 89
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
14305-008
Figure 8. Insertion Loss vs. Frequency, Between RFC and RFx
0
–80
–10
–20
–30
–40
–50
–60
–70
0 1 2 3456 7 8 9
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
14305-009
Figure 9. Isolation vs. Frequency, Between RFC and RFx
Data Sheet HMC344ALP3E
Rev. A | Page 7 of 11
INPUT POWER COMPRESSION AND INPUT IP3
30
15
18
21
27
24
01 2 34 5 678
INPUT COMPRESSION (dB)
FRE Q UE NCY ( GHz)
P1d B AT +85° C
P1d B AT +25° C
P1d B AT –40°C
P0.1dB AT + 85°C
P0.1dB AT + 25°C
P0.1dB AT –40°C
14305-010
Figure 10. Input Compression vs. Frequency at Various Temperatures,
VEE = −5 V
47
37
39
41
43
45
0 1 23 4 5678
INPUT I P 3 ( dB)
FRE Q UE NCY ( GHz)
14305-011
Figure 11. Input IP3 vs. Frequency at Room Temperature,
VEE = −5 V
30
15
18
21
27
24
012345 6 7 8
INPUT COMPRESSION (dB)
FRE Q UE NCY ( GHz)
14305-012
P1d B AT +85° C
P1d B AT +25° C
P1d B AT –40°C
P0.1dB AT + 85°C
P0.1dB AT + 25°C
P0.1dB AT –40°C
Figure 12. Input Compression vs. Frequency at Various Temperatures,
VEE = −3 V
47
37
39
41
43
45
0 1 2 3 4 567 8
INPUT I P 3 ( dB)
FRE Q UE NCY ( GHz)
14305-013
Figure 13. Input IP3 vs. Frequency at Room Temperature,
VEE = −3 V
HMC344ALP3E Data Sheet
Rev. A | Page 8 of 11
THEORY OF OPERATION
The HMC344ALP3E requires a negative supply voltage at the
VEE pin and two logic control inputs at the CTLA and CTLB
pins to control the state of the RF paths.
Depending on the logic level applied to the CTLA pin and the
CTLB pin, one RF path is in the insertion loss state, while the other
three paths are in an isolation state (see Table 4). The insertion
loss path conducts the RF signal between the RF throw pin and
the RF common pin, and the isolation paths provide high loss
between the RF throw pins terminated to internal 50 Ω resistors
and the insertion loss path.
The ideal power-up sequence is as follows:
1. Ground to the die bottom.
2. Power up VEE.
3. Power up the digital control inputs. The relative order of the
logic control inputs is not important. However, powering the
digital control inputs before the VEE supply can inadvertently
become forward-biased and damage the internal ESD protec-
tion structures.
4. Apply an RF input signal. The design is bidirectional; the RF
input signal can be applied to the RFC pin while the RF throw
pins are the outputs, or the RF input signal can be applied to
the RF throw pins, while the RFC pin is the output. All of the
RF pins are dc-coupled to 0 V, and no dc blocking is required
at the RF pins when the RF line potential equals 0 V.
The power-down sequence is the reverse of the power-up
sequence.
Table 4. Control Voltage Truth Table
Digital Control Input RF Paths
CTLA CTLB RFC to RF1 RFC to RF2 RFC to RF3 RFC to RF4
High High Insertion loss (on) Isolation (off ) Isolation (off) Isolation (off)
Low High Isolation (off) Insertion loss (on) Isolation (off) Isolation (off)
High
Low
Isolation (off )
Isolation (off )
Insertion loss (on)
Isolation (off )
Low Low Isolation (off ) Isolation (off) Isolation (off) Insertion loss (on)
Data Sheet HMC344ALP3E
Rev. A | Page 9 of 11
APPLICATIONS INFORMATION
EVALUATION BOARD
The EV1HMC344ALP3 is a 4-layer evaluation board. Each
copper layer is 0.5 oz (0.7 mil) and separated by dielectric
materials. Figure 14 shows the stack up for this evaluation board.
RO4350
0.5oz Cu (0. 7m i l )0.5oz Cu (0. 7m i l )
0.5o z Cu (0.7mil)
TOTAL THICKNESS
~62mil
0.5o z Cu (0.7mil)
0.5o z Cu (0.7mil)
0.5oz Cu (0. 7m i l )
W = 16mil G = 13mil
T = 0.7mi l
H = 10mil
FR4
RO4350
14305-014
Figure 14. EV1HMC344ALP3 Evaluation Board (Cross Sectional View)
All RF and dc traces are routed on the top copper layer, and the
inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is a 10 mil Rogers RO4350. The middle and bottom
dielectric materials provide mechanical strength. The overall board
thickness is approximately 62 mil allowing the Subminiature
Version A (SMA) launchers to be connected at the board edges.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 16 mil and a
ground clearance of 13 mil for a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, arrange as many
plated through vias as possible around the transmission lines
and under the exposed pad of the package.
Figure 15 is the external interface circuit recommended for
transistor to transistor level (TTL) compatible control of the
negative voltage controlled switches.
TTL CONTROL A/B
–5
74HCT04 ( 1/6)
TO A/B
5.1V
ZENER 10kΩ
VDC
VEE
VCC
14305-015
Figure 15. TTL Interface Circuit
Figure 16 shows the layout of the EV1HMC344ALP3 evaluation
board with component placement. The power supply port is
connected to the VEE test point, J8. Control voltages, CTLA and
CTLB, are connected to the A and B test points, J9 and J10. The
ground reference is connected to the GND test point, J11. The
NIC pins are connected to the PCB ground to maximize
isolation. Use a 1 nF bypass capacitor on the supply trace, VEE,
to filter high frequency noise.
The RF input and output ports (RFC, RF1 to RF4) connect through
50 Ω transmission lines to the SMA launchers, J1 to J5. These SMA
launchers are soldered onto the board. For connection to the RF
pins, R1 to R5 are populated with 0 Ω resistors. A through cal-
ibration line connects the unpopulated J6 and J7 launchers. This
transmission line estimates the loss of the PCB over the envi-
ronmental conditions being evaluated, as shown in Figure 17.
Table 5 describes the evaluation board components.
Table 5. Evaluation Board Components
Component
Default Value
Description
R1 to R5 0 Ω Resistors, R0402 package
C6 1 nF Capacitor, C0402 package
R7, R8 Do not insert Resistors, R0402 package
J1 to J5 Not applicable PCB mount and SMA
launchers
J6, J7 Do not insert PCB mount and SMA
launchers
J8 to J11 Not applicable DC pins
U1 HMC344ALP3E SP4T switch
PCB 104708-3 Evaluation PCB
HMC344ALP3E Data Sheet
Rev. A | Page 10 of 11
14305-017
R1
R2
R3
R4
R5
Figure 16. EV1HMC344ALP3 Evaluation Board Component Placement
RF1
J1
C6
J5
RF3 RF2
RFC
J9
THRU CAL
J4
B
J10
HMC344ALP3E
RF4
1
NIC
2
NIC
3
RF3
4
12
11
10
9
V
EE
6
CTLB
7
CTLA
8
RF2
NIC
NIC
RF1
NIC 13
GND 14
RFC 15
GND 16
EPAD
GND
5
J8
V
DD
A
J3
J2
J6
RF4
J7
14305-018
R1
R2
R3
R4
R5
R7 R8
Figure 17. EV1HMC344ALP3 Evaluation Board Schematic
Data Sheet HMC344ALP3E
Rev. A | Page 11 of 11
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.70
1.60 SQ
1.50
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
0.05 M AX
0.02 NO M
0.203 REF
0.20 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.90
0.85
0.80
0.45
0.40
0.35
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.
11-22-2016-A
PKG-004831
COM P LIANT TO JEDEC S TANDARDS MO-220-VEED-4
EXPOSED
PAD
PIN 1
INDIC ATOR AREA OPTI ONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
SEATING
PLANE
Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(CP-16-50)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
HMC344ALP3E −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-50
HMC344ALP3ETR −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-50
EV1HMC344ALP3
Evaluation Board
1 All models are RoHS compliant parts.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14305-0-12/17(A)
