General Description
The MAX9723 stereo DirectDrive®headphone amplifier
with BassMax and volume control is ideal for portable
audio applications where space is at a premium and per-
formance is essential. The MAX9723 operates from a sin-
gle 1.8V to 3.6V power supply and includes features that
reduce external component count, system cost, board
space, and improves audio reproduction.
The headphone amplifier uses Maxim’s DirectDrive
architecture that produces a ground-referenced output
from a single supply, eliminating the need for large DC-
blocking capacitors. The headphone amplifiers deliver
62mW into a 16Ωload, feature low 0.006% THD+N, and
high 90dB PSRR. The MAX9723 features Maxim’s indus-
try-leading click-and-pop suppression.
The BassMax feature boosts the bass response of the
amplifier, improving audio reproduction when using
inexpensive headphones. The integrated volume con-
trol features 32 discrete volume levels, eliminating the
need for an external potentiometer. BassMax and the
volume control are enabled through the I2C/SMBus™-
compatible interface. Shutdown is controlled through
either the hardware or software interfaces.
The MAX9723 consumes only 3.7mA of supply current
at 1.8V, provides short-circuit and thermal-overload
protection, and is fully specified over the extended
-40°C to +85°C temperature range. The MAX9723 is
available in a tiny (2mm x 2mm x 0.62mm) 16-bump
chip-scale package (UCSP™) or 16-pin thin QFN (4mm
x 4mm x 0.8mm) package.
Applications
Features
♦62mW, DirectDrive Headphone Amplifier
Eliminates Bulky DC-Blocking Capacitors
♦1.8V to 3.6V Single-Supply Operation
♦Integrated 32-Level Volume Control
♦High 90dB PSRR at 1kHz
♦Low 0.006% THD+N
♦Industry-Leading Click-and-Pop Suppression
♦±8kV HBM ESD-Protected Headphone Outputs
♦Short-Circuit and Thermal-Overload Protection
♦Low-Power Shutdown Mode (5µA)
♦Software-Enabled Bass Boost (BassMax)
♦I2C/SMBus-Compatible Interface
♦Available in Space-Saving, Thermally Efficient
Packages:
16-Bump UCSP (2mm x 2mm x 0.62mm)
16-Pin Thin QFN (4mm x 4mm x 0.8mm)
MAX9723
Stereo DirectDrive Headphone Amplifier
with BassMax, Volume Control, and I2C
________________________________________________________________ Maxim Integrated Products 1
I2C INTERFACE
VOLUME
CONTROL
BassMax
BassMax
1.8V TO 3.6V SUPPLY
SCL
BBL
OUTL
BBR
OUTR
SDA
INL
INR
MAX9723
Σ
Σ
Block Diagram
Ordering Information
19-3509; Rev 2; 8/08
EVALUATION KIT
AVAILABLE
PART**
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX9723_EBE-T*
-40°C to +85°C 16 UCSP-16
B16-1
MAX9723_ETE+
-40°C to +85°C
16 TQFN
T1644-4
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
SMBus is a trademark of Intel Corp.
UCSP is a trademark of Maxim Integrated Products, Inc.
**Replace the ‘_’ with the one-letter code that denotes the
slave address and maximum programmable gain. See the
Selector Guide.
+Denotes a lead-free/RoHS-compliant package.
*Future product—contact factory for availability.
Pin Configurations appear at end of data sheet.
PDA Audio
Portable CD Players
Mini Disc Players
Automotive Multimedia
MP3-Enabled Cellular
Phones
MP3 Players
PART
SLAVE ADDRESS
MAXIMUM GAIN (dB)
MAX9723A
1001100 0
MAX9723B
1001101 0
MAX9723C
1001100 +6
MAX9723D
1001101 +6
Selector Guide
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
GENERAL
Supply Voltage Range VDD 1.8 3.6 V
Quiescent Supply Current IDD No load 4 6.5 mA
Shutdown Supply Current
IDD_SHDN
V SHDN = 0V 5 8.5 µA
Turn-On Time tON
200
µs
Turn-Off Time tOFF 35 µs
Thermal Shutdown Threshold TTHRES
+143
°C
Thermal Shutdown Hysteresis THYST 12 °C
HEADPHONE AMPLIFIER
Gain = 0dB,
MAX9723A/
MAX9723B
±0.7 ±4.5
Output Offset Voltage VOS
M easur ed b etw een
OU T_ and S GN D
( N ote 2) Gain = +6dB,
MAX9723C/
MAX9723D
±0.8
±5
mV
Input Resistance RIN All volume levels 10 17 27 kΩ
BBR, BBL Input Bias Current
IBIAS_BB ±10 ±100
nA
DC, VDD = 1.8V to 3.6V 73 90
f = 217Hz, 100mVP-P ripple,
VDD = 3.0V 87
f = 1kHz, 100mVP-P ripple,
VDD = 3.0V 86
Power-Supply Rejection Ratio PSRR (Note 2)
f = 20kHz, 100mVP-P ripple,
VDD = 3.0V 61
dB
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
RL = 32Ω59
Output Power POUT THD+N = 1%,
fIN = 1kHz RL = 16Ω (Note 5) 38 60 mW
RL = 16Ω, POUT = 35mW, fIN = 1kHz
0.006
Total Harmonic Distortion Plus
Noise
THD+N
RL = 32Ω, POUT = 45mW, fIN = 1kHz
0.004
%
Gain range bit 5 = 1 0
MAX9723A/
MAX9723B Gain range bit 5 = 0 -5 dB
Gain range bit 5 = 1 +6
Maximum Gain AMAX MAX9723C/
MAX9723D Gain range bit 5 = 0 +1 dB
BW = 22Hz to 22kHz 99
Signal-to-Noise Ratio SNR RL = 32Ω,
VOUT = 1VRMS A-weighted
100
dB
Slew Rate SR
0.35
V/µs
Capacitive Drive No sustained oscillations
300
pF
Output Resistance in Shutdown
ROUT_SHDN
VSHDN = 0V, measured from OUT_ to
SGND 20 kΩ
Output Capacitance in Shutdown
COUT_SHDN
VSHDN = 0V, measured from OUT_ to
SGND 60 pF
Into
shutdown -69
MAX9723A/
MAX9723B Out of
shutdown -71
Into
shutdown -70
Click/Pop Level KCP
RL = 32Ω,
peak voltage,
A-weighted,
32 samples
per second
(Notes 2, 4) MAX9723C/
MAX9723D Out of
shutdown -69
dB
Charge-Pump Switching
Frequency fCP
505 600
700 kHz
Crosstalk XTALK
L to R or R to L, f = 10kHz,
VOUT = 1VP-P, RL = 32Ω, both channels
loaded
80 dB
DIGITAL INPUTS (SHDN, SDA, SCL)
Input High Voltage VIH 0.7 x
VDD
V
Input Low Voltage VIL 0.3 x
VDD
V
Input Leakage Current ±1µA
DIGITAL OUTPUTS (SDA)
Output Low Voltage VOL IOL = 3mA 0.4 V
Output High Current IOH VSDA = VDD 1µA
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Serial Clock Frequency fSCL 0
400
kHz
Bus Free Time Between a STOP
and a START Condition tBUF 1.3 µs
START Condition Hold Time
tHD:STA
0.6 µs
Low Period of the SCL Clock tLOW 1.3 µs
High Period of the SCL Clock tHIGH 0.6 µs
Setup Time for a Repeated
START Condition tSU:STA 0.6 µs
Data Hold Time
tHD:DAT
0 0.9 µs
Data Setup Time
tSU:DAT 100
ns
Maximum Rise Time of SDA and
SCL Signals tr
300
ns
Maximum Fall Time of SDA and
SCL Signals tf
300
ns
Setup Time for STOP Condition
tSU:STO
0.6 µs
Pulse Width of Suppressed Spike
tSP
100
ns
Maximum Capacitive Load for
Each Bus Line
CL_BUS 400
pF
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
MAX9723 toc01
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.01
0.1
1
0.001
10 100k
VDD = 2.4V
RL = 16Ω
POUT = 10mW
POUT = 25mW
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
MAX9723 toc02
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.01
0.1
1
0.001
10 100k
VDD = 2.4V
RL = 32Ω
POUT = 23mW
POUT = 10mW
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
MAX9723 toc03
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.01
0.1
1
0.001
10 100k
VDD = 3V
RL = 16Ω
POUT = 37mW
POUT = 20mW
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
MAX9723 toc04
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.01
0.1
1
0.001
10 100k
VDD = 3V
RL = 32Ω
POUT = 30mW
POUT = 10mW
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
MAX9723 toc05
OUTPUT POWER (mW)
THD+N (%)
4020
0.01
0.1
1
10
100
0.001
060
VDD = 2.4V
RL = 16Ω
fIN = 1kHz
fIN = 20Hz fIN = 10kHz
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
MAX9723 toc06
OUTPUT POWER (mW)
THD+N (%)
4020
0.01
0.1
1
10
100
0.001
060
VDD = 2.4V
RL = 32Ω
fIN = 1kHz fIN = 10kHz
fIN = 20Hz
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
MAX9723 toc07
OUTPUT POWER (mW)
THD+N (%)
80604020
0.01
0.1
1
10
100
0.001
0 100
VDD = 3V
RL = 16Ω
fIN = 10kHz
fIN = 1kHz
fIN = 20Hz
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
MAX9723 toc08
OUTPUT POWER (mW)
THD+N (%)
80604020
0.01
0.1
1
10
100
0.001
0100
VDD = 3V
RL = 32Ω
fIN = 10kHz
fIN = 1kHz
fIN = 20Hz
0
40
60
80
100
120
140
160
180
0 20406080
POWER DISSIPATION
vs. OUTPUT POWER
MAX9723 toc09
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
20
VDD = 2.4V
fIN = 1kHz
POUT = POUTL + POUTR
OUTPUTS IN PHASE
RL = 32Ω
RL = 16Ω
0
100
50
200
150
250
300
0406020 80 100 120
POWER DISSIPATION
vs. OUTPUT POWER
MAX9723 toc10
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
RL = 16Ω
VDD = 3V
fIN = 1kHz
POUT = POUTL + POUTR
OUTPUTS IN PHASE
RL = 32Ω
OUTPUT POWER
vs. LOAD RESISTANCE
MAX9723 toc11
LOAD RESISTANCE (Ω)
OUTPUT POWER (mW)
100
10
20
30
40
50
60
70
80
0
10 1k
VDD = 2.4V
fIN = 1kHz
THD+N = 10%
THD+N = 1%
OUTPUT POWER
vs. LOAD RESISTANCE
MAX9723 toc12
LOAD RESISTANCE (Ω)
OUTPUT POWER (mW)
100
10
20
30
40
50
60
70
80
90
100
0
10 1k
VDD = 3V
fIN = 1kHz
THD+N = 10%
THD+N = 1%
OUTPUT POWER
vs. SUPPLY VOLTAGE
MAX9723 toc13
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
3.43.22.8 3.02.2 2.4 2.62.0
10
20
30
40
50
60
70
80
90
100
0
1.8 3.6
THD+N = 10%
THD+N = 1%
fIN = 1kHz
RL = 16Ω
20
40
60
80
100
120
140
0
OUTPUT POWER
vs. SUPPLY VOLTAGE
MAX9723 toc14
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
3.43.22.8 3.02.2 2.4 2.62.01.8 3.6
THD+N = 10%
THD+N = 1%
fIN = 1kHz
RL = 32Ω
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX9723 toc15
FREQUENCY (Hz)
PSRR (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
RL = 32Ω
CROSSTALK
vs. FREQUENCY
-100
-80
-60
-40
-20
0
-120
MAX9723 toc16
FREQUENCY (Hz)
CROSSTALK (dB)
10k1k10010 100k
VIN = 1VP-P
RL = 32Ω
A = 0dB
LEFT TO RIGHT
A = 0dB
RIGHT TO LEFT
A = 0dB
CROSSTALK
vs. FREQUENCY
-100
-80
-60
-40
-20
0
-120
MAX9723 toc17
FREQUENCY (Hz)
CROSSTALK (dB)
10k1k10010 100k
VIN = 1VP-P
RL = 32Ω
A = -10dB
LEFT TO RIGHT
A = -10dB
RIGHT TO LEFT
A = -10dB
BASS BOOST FREQUENCY
RESPONSE
-5
0
5
10
15
20
-10
MAX9723 toc18
FREQUENCY (Hz)
AMPLITUDE (dB)
10k1k10010 100k
NO LOAD
R1 = 47kΩ
BassMax DISABLED
R2 = 36kΩ
C3 = 0.068μF
R2 = 22kΩ
C3 = 0.1μF
R2 = 10kΩ
C3 = 0.22μF
GAIN FLATNESS
vs. FREQUENCY
-6
-5
-4
-3
-2
-1
0
1
-7
MAX9723 toc19
FREQUENCY (Hz)
AMPLITUDE (dB)
10k1k10010 100k
OUTPUT SPECTRUM
vs. FREQUENCY
MAX9723 toc20
FREQUENCY (kHz)
AMPLITUDE (dBV)
15105
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-140
020
RL = 32Ω
VDD = 3V
fIN = 1kHz
CHARGE-PUMP OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX9723 toc21
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
175150125100755025
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
-3.5
0200
NO HEADPHONE LOAD
CHARGE-PUMP LOAD
CONNECTED
BETWEEN PVSS AND PGND
OUTPUT POWER vs. CHARGE-PUMP
CAPACITANCE AND LOAD RESISTANCE
MAX9723 toc22
LOAD RESISTANCE (Ω)
OUTPUT POWER (mW)
403020
40
45
50
55
60
65
70
75
35
10 50
C1 = C2 = 2.2μF
C1 = C2 = 0.68μF
C1 = C2 = 1μF
VDD = 3V
fIN = 1kHz
THD+N = 1%
POWER-UP/POWER-DOWN
WAVEFORM
MAX9723 toc23
20ms/div
VDD
2V/div
VOUT
10mV/div
EXITING SHUTDOWN
MAX9723 toc24
40μs/div
VOUT_
200mV/div
VSHDN
2V/div
ENTERING SHUTDOWN
MAX9723 toc25
20μs/div
VOUT_
200mV/div
VSHDN
2V/div
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9723 toc26
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.43.23.02.82.62.42.22.0
2.5
3.0
3.5
4.0
4.5
2.0
1.8 3.6
NO LOAD
INPUTS GROUNDED
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT (μA)
1
2
3
4
5
6
7
8
0
MAX9723 toc27
SUPPLY VOLTAGE (V)
3.43.23.02.82.62.42.22.01.8 3.6
NO LOAD
INPUTS GROUNDED
Detailed Description
The MAX9723 stereo headphone amplifier features
Maxim’s DirectDrive architecture, eliminating the large
output-coupling capacitors required by conventional sin-
gle-supply headphone amplifiers. The MAX9723 consists
of two 62mW Class AB headphone amplifiers, hard-
ware/software shutdown control, inverting charge pump,
integrated 32-level volume control, BassMax circuitry,
comprehensive click-and-pop suppression circuitry, and
an I2C-compatible interface (see the Functional
Diagram/Typical Operating Circuit). A negative power
supply (PVSS) is created internally by inverting the posi-
tive supply (VDD). Powering the amplifiers from VDD and
PVSS increases the dynamic range of the amplifiers to
almost twice that of other single-supply amplifiers,
increasing the total available output power.
The MAX9723 DirectDrive outputs are biased at SGND
(see Figure 1). The benefit of this 0V bias is that the
amplifier outputs do not have a DC component, elimi-
nating the need for large DC-blocking capacitors.
Eliminating the DC-blocking capacitors on the output
saves board space, system cost, and improves low-fre-
quency response.
An I2C-compatible interface allows serial communica-
tion between the MAX9723 and a microcontroller. The
MAX9723 is available with two different I2C addresses
allowing two MAX9723 ICs to share the same bus (see
Table 1). The internal command register controls the
shutdown status of the MAX9723, enables the BassMax
circuitry, sets the maximum gain of the amplifier, and
sets the volume level (see Table 2). The MAX9723’s
BassMax circuitry improves audio reproduction by
boosting the bass response of the amplifier, compen-
sating for any low-frequency attenuation introduced by
MAX9723
Stereo DirectDrive Headphone Amplifier
with BassMax, Volume Control, and I2C
_______________________________________________________________________________________ 9
Pin Description
PIN BUMP
THIN QFN
UCSP NAME FUNCTION
1D1V
DD Power-Supply Input. Bypass VDD to PGND with a 1µF capacitor.
2 C1 C1P Charge-Pump Flying Capacitor Positive Terminal
3 B1 PGND Power Ground. Connect to SGND.
4 A1 C1N Charge-Pump Flying Capacitor Negative Terminal
5 B2 SCL Serial Clock Input. Connect a 10kΩ pullup resistor from SCL to VDD.
6A2PV
SS Charge-Pump Output. Connect to SVSS. Bypass PVSS with a 1µF capacitor
to PGND.
7 A3 SDA Serial-Data Input. Connect a 10kΩ pullup resistor from SDA to VDD.
8B3SHDN Shutdown. Drive SHDN low to disable the MAX9723. Connect SHDN to VDD while bit 7
is high for normal operation (see the Command Register section).
9 A4 SGND Signal Ground. Connect to PGND.
10 B4 INL Left-Channel Input
11 C4 INR Right-Channel Input
12 D4 SVSS Headphone Amplifier Negative Power-Supply Input. Connect to PVSS.
13 C3 BBR
Right BassMax Input. Connect an external lowpass filter between OUTR and BBR to
apply bass boost to the right-channel output. Connect BBR to SGND if BassMax is not
used (see the BassMax (Bass Boost) section).
14 D3 OUTR Right Headphone Output
15 D2 OUTL Left Headphone Output
16 C2 BBL
Left BassMax Input. Connect an external lowpass filter between OUTL and BBL to
apply bass boost to the left-channel output. Connect BBL to SGND if BassMax is not
used (see the BassMax (Bass Boost) section).
EP — EP Exposed Paddle. Connect EP to SVSS or leave unconnected.
MAX9723
the headphone. The MAX9723A and MAX9723B have a
maximum amplifier gain of 0dB while the MAX9723C
and MAX9723D have a maximum gain of +6dB.
Amplifier volume is digitally programmable to any one
of 32 levels.
DirectDrive
Traditional single-supply headphone amplifiers have
their outputs biased at a nominal DC voltage, typically
half the supply, for maximum dynamic range. Large cou-
pling capacitors are needed to block this DC bias from
the headphone. Without these capacitors, a significant
amount of DC current flows to the headphone, resulting
in unnecessary power dissipation and possible damage
to both headphone and headphone amplifier.
Maxim’s DirectDrive architecture uses a charge pump to
create an internal negative supply voltage. This allows
the MAX9723 headphone amplifier outputs to be biased
at 0V, almost doubling the dynamic range while operat-
ing from a single supply. With no DC component, there is
no need for the large DC-blocking capacitors. Instead of
two large (typically 220µF) tantalum capacitors, the
MAX9723 charge pump requires only two small 1µF
ceramic capacitors, thereby conserving board space,
reducing cost, and improving the low-frequency
response of the headphone amplifier. See the Output
Power vs. Charge-Pump Capacitance and Load
Resistance graph in the Typical Operating Characteris-
tics for details of the possible capacitor sizes.
In addition to the cost and size disadvantages, the DC-
blocking capacitors required by conventional head-
phone amplifiers limit low-frequency response and can
distort the audio signal.
Previous attempts at eliminating the output-coupling
capacitors involved biasing the headphone return
(sleeve) to the DC bias voltage of the headphone
amplifiers. This method raises some issues:
1) The sleeve is typically grounded to the chassis.
Using the midrail biasing approach, the sleeve must
be isolated from system ground, complicating prod-
uct design. The DirectDrive output biasing scheme
allows the sleeve to be grounded.
2) During an ESD strike, the amplifier’s ESD structure is
the only path to system ground. The amplifier must
be able to withstand the full ESD strike. The
MAX9723 headphone outputs can withstand an
±8kV ESD strike (HBM).
3) When using the headphone jack as a line out to
other equipment, the bias voltage on the sleeve may
conflict with the ground potential from other equip-
ment, resulting in possible damage to the amplifiers.
The DirectDrive outputs of the MAX9723 can be
directly coupled to other ground-biased equipment.
Charge Pump
The MAX9723 features a low-noise charge pump. The
600kHz switching frequency is well beyond the audio
range, and does not interfere with the audio signals.
This enables the MAX9723 to achieve a 99dB SNR. The
switch drivers feature a controlled switching speed that
minimizes noise generated by turn-on and turn-off tran-
sients. Limiting the switching speed of the charge
pump minimizes di/dt noise caused by the parasitic
bond wire and trace inductance. Although not typically
required, additional high-frequency noise attenuation
can be achieved by increasing the size of C2 (see the
Functional Diagram/Typical Operating Circuit).
Shutdown
The MAX9723 features a 5µA, low-power shutdown
mode that reduces quiescent current consumption and
extends battery life. Shutdown is controlled by a hard-
ware or software interface. Driving SHDN low disables
the drive amplifiers, bias circuitry, charge pump, and
sets the headphone amplifier output impedance to
20kΩ. Similarly, the MAX9723 enters shutdown when bit
seven (B7) in the control register is reset. SHDN and B7
must be high to enable the MAX9723. The I2C interface
is active and the contents of the command register are
not affected when in shutdown. This allows the master
to write to the MAX9723 while in shutdown.
Stereo DirectDrive Headphone Amplifier
with BassMax, Volume Control, and I2C
10 ______________________________________________________________________________________
VDD
+VDD
-VDD
VDD/2
GND
SGND
CONVENTIONAL AMPLIFIER BIASING SCHEME
DirectDrive BIASING SCHEME
Figure 1. Traditional Amplifier Output vs. MAX9723 DirectDrive
Output
C3
R2
R1
R
R
OUT_
BB_
AUDIO
INPUT
MAX9723
BassMax
ENABLE
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tSU, STA tHD, STA tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tRtF
SCL
SDA
SSrP
1
SCL
START
CONDITION
SDA
289
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
MAX9723 SLAVE ADDRESS
PART
A6 A5 A4 A3 A2 A1 A0
R/W
MAX9723A
1001100
0
MAX9723B
1001101
0
MAX9723C
1001100
0
MAX9723D
1001101
0
B7 B6 B5
B4 B3 B2 B1
B0
SHUTDOWN
BassMax
ENABLE
MAXIMUM
GAIN VOLUME
MODE B7
MAX9723 Disabled 0
MAX9723 Enabled 1
MODE B6
BassMax Disabled 0
BassMax Enabled 1
VV
IN P P OUT P P
AV
_( ) _( )
−−
⎛
⎝
⎜⎞
⎠
⎟
=
10 20
VPR
OUT P P OUT L_( ) _ %
()
−=×22 1
PTT
D MAX J MAX A
JA
() ()
=−
θ
S
ACK
0
ACKNOWLEDGE FROM MAX9723
R/W ACKNOWLEDGE
FROM MAX9723
B7 B6 B5 B4 B3 B2
COMMAND BYTE IS STORED ON
RECEIPT OF STOP CONDITION
ACK
P
B1 B0
SLAVE ADDRESS COMMAND BYTE
MAXIMUM GAIN (dB) B5
-5 0
01
MAXIMUM GAIN (dB) B5
+1 0
+6 1
B4 B3
B2
B1 B0
(LSB)
GAIN
(dB)
11111 0
11110 -0.5
11101 -1
11100 -1.5
11011 -2
11010 -2.5
11001 -3
11000 -4
10111 -5
10110 -6
10101 -7
10100 -9
1 0 0 1 1 -11
1 0 0 1 0 -13
1 0 0 0 1 -15
1 0 0 0 0 -17
0 1 1 1 1 -19
0 1 1 1 0 -21
0 1 1 0 1 -23
0 1 1 0 0 -25
0 1 0 1 1 -27
0 1 0 1 0 -29
0 1 0 0 1 -31
0 1 0 0 0 -33
0 0 1 1 1 -35
0 0 1 1 0 -37
0 0 1 0 1 -39
0 0 1 0 0 -41
0 0 0 1 1 -43
0 0 0 1 0 -45
0 0 0 0 1 -47
0 0 0 0 0 MUTE
B4 B3 B2 B1 B0
(LSB)
GAIN
(dB)
1
1111
-5
1
1110
-6
1
1101
-7
1
1100
-9
1
1011
-11
11010-13
1
1001
-15
11000-17
1
0111
-19
1
0110
-21
1
0101
-23
1
0100
-25
1
0011
-27
1
0010
-29
1
0001
-31
1
0000
-33
0
1111
-35
0
1110
-37
01101-39
0
1100
-41
01011-43
0
1010
-45
0
1001
-47
0
1000
-51
0
0111
-55
0
0110
-59
0
0101
-63
0
0100
-67
0
0011
-71
00010-75
0
0001
-79
00000
MUTE
fRC
dB IN IN
−=××
3
1
2π
B4 B3 B2 B1 B0
(LSB)
GAIN
(dB)
111111
111100
11101-1
11100-3
11011-5
11010-7
11001-9
11000-11
10111-13
10110-15
10101-17
10100-19
10011-21
10010-23
10001-25
10000-27
01111-29
01110-31
01101-33
01100-35
01011-37
01010-39
01001-41
01000-45
00111-49
00110-53
00101-57
00100-61
00011-65
00010-69
00001-73
00000
MUTE
MODE
B7 B6 B5 B4 B3 B2 B1
B0
Power-On
Reset
1111111
1
B4 B3 B2 B1 B0
(LSB)
GAIN
(dB)
111116
111105.5
111015
111004.5
110114
110103.5
110013
110002
101111
101100
10101-1
10100-3
10011-5
10010-7
10001-9
10000-11
01111-13
01110-15
01101-17
01100-19
01011-21
01010-23
01001-25
01000-27
00111-29
00110-31
00101-33
00100-35
00011-37
00010-39
00001-41
00000
MUTE
MAX9723A AND MAX9723B
TRANSFER FUNCTION (B5 = 1)
CODE
GAIN (dB)
-20
-30
-40
10
0
-10
-50
0 6 12 18 24 30
MAX9723A AND MAX9723B
TRANSFER FUNCTION (B5 = 0)
CODE
GAIN (dB)
-40
-50
-60
-70
-80
0
-10
-30
-20
-90
0 6 12 18 24 30
MAX9723C AND MAX9723D
TRANSFER FUNCTION (B5 = 0)
CODE
0 6 12 18 24 30
GAIN (dB)
-30
-40
-50
-60
-70
10
0
-20
-10
-80
MAX9723C AND MAX9723D
TRANSFER FUNCTION (B5 = 1)
CODE
GAIN (dB)
-30
-40
10
0
-20
-10
-50
0 6 12 18 24 30
AA RA RB
RA RB
V TOTAL V VOL__
log=+×
+
−
⎛
⎝
⎜⎞
⎠
⎟
20
fRR
CRR
fRR
CRR
POLE
ZERO
=−
×××
=+
×××
12
2312
12
2312
π
π
AAA
V TOTAL V VOL V BOOST___
=+
ARR
RR
V BOOST_log=× +
−
20 12
12
GAIN PROFILE WITH AND
WITHOUT BassMax
FREQUENCY (Hz)
AV (dB)
1k10010
-8
-6
-4
-2
0
2
4
6
8
10
-10
1 10k
MAX9723A
CMD REGISTER
CODE = 0xFF
R1 = 47kΩ
R2 = 22kΩ
C3 = 0.1μF
fPOLE
fZERO
WITH
BassMax
WITHOUT
BassMax
CA fRARB
POLE
()
=×−
1
2π
CA
RB
RA
R
R
OUT_
BB_
AUDIO
INPUT
MAX9723
BassMax
ENABLE
R2 (kΩ)A
V GAIN (dB)
39 20.6
33 15.1
27 11.3
22 8.8
15 5.7
10 3.7
C3 (nF) fPOLE (Hz) fZERO (Hz)
100 38 106
82 47 130
68 56 156
56 68 190
47 81 230
22 174 490
10 384 1060
FREQUENCY RESPONSE OF FIGURE 12
FREQUENCY (Hz)
AV (dB)
1k100101
1
2
3
4
5
6
7
8
9
10
0
0.1 10k
MAX9723A
CMD REGISTER
CODE = 0xFF
RA = 47kΩ
RB = 22kΩ
CA = 0.33μF
R5
10kΩ
R6
10kΩ
CIN
0.47μF
C4
0.1μF
R4
22kΩ
R3
47kΩ
R1
47kΩ
C5
1μF
C2
1μF
CIN
0.47μF
C1
1μF
1.8V TO 3.6V ANALOG INPUT
I2C INTERFACE
CHARGE PUMP
VDD
INR
SDA
SCL
VDD
VDD
SVSS
VDD
R
OUTR
BBR
BBL
OUTL
R
SVSS
VDD
SVSS
VDD
SVSS
SHDN
C1P
C1N
SGND PGND PVSS SVSS
C3
0.1μF
R2
22kΩ
ANALOG INPUT
BASS BOOST CIRCUIT TUNED
FOR +8.8dB AT 106Hz.
MAX9723
R
INL
R
12
11
10
9
SVSS
INR
INL
SGND
5678
SCL
PVSS
SDA
SHDN
16 15 14 13
BBL
OUTL
OUTR
BBR
1
2
3
4
VDD
C1P
PGND
C1N
MAX9723_
TOP VIEW
TOP VIEW
(BUMP SIDE DOWN)
THIN QFN
UCSP
SHDN
C1N PVSS SDA SGND
INLSCLPGND
C1P
VDD
BBL BBR INR
OUTL OUTR SVSS
MAX9723_
1234
A
B
C
D
+
R3
47kΩ
R4
22kΩ
R1
47kΩ
C3
0.1μF
C4
0.1μF
R2
22kΩ
OUTL
VDD
PVSS
C2
1μF
C5
1μF
R6
10kΩ
R5
10kΩ
I2C
MASTER
CODEC
SVSS PGND SGND
BBL
OUTR
BBR
1.8V TO
3.6V
SDA
SCL
INL
INR
C1P
C1N
CIN
0.47μF
CIN
0.47μF
C1
1μF
MAX9723
24L QFN THIN.EPS
16L,UCSP.EPS
H1
1
21-0101
PACKAGE OUTLINE, 4x4 UCSP
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
2 8/08 Updated TQFN pin configuration, and corrected Typical Operating Circuit and
System Diagram pin names 20, 21