LM160, LM360 www.ti.com SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 LM160/LM360 High Speed Differential Comparator Check for Samples: LM160, LM360 FEATURES DESCRIPTION * * * * * * * * The LM160/LM360 is a very high speed differential input, complementary TTL output voltage comparator with improved characteristics over the A760/A760C, for which it is a pin-for-pin replacement. The device has been optimized for greater speed, input impedance and fan-out, and lower input offset voltage. Typically delay varies only 3 ns for overdrive variations of 5 mV to 400 mV. 1 2 Ensured high speed: 20 ns max Tight delay matching on both outputs Complementary TTL outputs High input impedance Low speed variation with overdrive variation Fan-out of 4 Low input offset voltage Series 74 TTL compatible Complementary outputs having minimum skew are provided. Applications involve high speed analog to digital convertors and zero-crossing detectors in disk file systems. CONNECTION DIAGRAMS TO-99 Package Figure 1. Package Number LMC0008C (1) SOIC or PDIP Package (1) Figure 2. Package Number D0008A or P0008E Also available in SMD# 5962-8767401 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated LM160, LM360 SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) Positive Supply Voltage +8V -8V Negative Supply Voltage Peak Output Current 20 mA Differential Input Voltage 5V V VIN V- + Input Voltage ESD Tolerance (3) Operating Temperature Range 1600V -55C to +125C LM160 LM360 0C to +70C -65C to +150C Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 260C PDIP Package Soldering (10 seconds) 260C SOIC Package Vapor Phase (60 seconds) 215C Infrared (15 seconds) 220C Soldering Information See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" for other methods of soldering surface mount devices. (1) (2) (3) 2 The device may be damaged if used beyond the maximum ratings. Refer to RETS 160X for LM160H, LM160J-14 and LM160J military specifications. Human body model, 1.5 k in series with 100 pF. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 LM160, LM360 www.ti.com SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 Electrical Characteristics (TMIN TA TMAX) Parameter Conditions Min Typ Max Units V Operating Conditions Supply Voltage VCC+ 4.5 5 6.5 Supply Voltage VCC- -4.5 -5 -6.5 V 2 5 mV 0.5 3 A 5 20 A Input Offset Voltage RS 200 Input Offset Current Input Bias Current Output Resistance (Either Output) Response Time VOUT = VOH 100 TA = 25C, VS = 5V (1) (2) 13 25 ns TA = 25C, VS = 5V (3) (2) 12 20 ns TA = 25C, VS = 5V (4) (2) 14 ns Response Time Difference between Outputs (tpd of +VIN1) - (tpd of -VIN2) TA = 25C (1) (2) 2 ns (tpd of +VIN2) - (tpd of -VIN1) TA = 25C (1) (2) 2 ns (tpd of +VIN1) - (tpd of +VIN2) TA = 25C (1) (2) 2 ns TA = 25C (1) (2) (tpd of -VIN1) - (tpd of -VIN2) 2 ns Input Resistance f = 1 MHz 17 k Input Capacitance f = 1 MHz 3 pF Average Temperature Coefficient of Input Offset Voltage RS = 50 8 V/C 7 nA/C 4.5 V Average Temperature Coefficient of Input Offset Current Common Mode Input Voltage Range VS = 6.5V Differential Input Voltage Range 4 5 V Output High Voltage (Either Output) IOUT = -320 A, VS = 4.5V Output Low Voltage (Either Output) ISINK = 6.4 mA 0.25 0.4 V Positive Supply Current VS = 6.5V 18 32 mA Negative Supply Current VS = 6.5V -9 -16 mA (1) (2) (3) (4) 2.4 3 V Response time measured from the 50% point of a 30 mVp-p 10 MHz sinusoidal input to the 50% point of the output. Measurements are made in AC Test Circuit, Fanout = 1 Response time measured from the 50% point of a 2 Vp-p 10 MHz sinusoidal input to the 50% point of the output. Response time measured from the start of a 100 mV input step with 5 mV overdrive to the time when the output crosses the logic threshold. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 3 LM160, LM360 SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 4 Offset Voltage Input Current vs Ambient Temperature Input Characteristics Supply Current vs Ambient Temperature Propagation Delay vs Ambient Temperature Delay of Output 1 With Respect to Output 2 vs Ambient Temperature Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 LM160, LM360 www.ti.com SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Common-Mode Pulse Response Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 5 LM160, LM360 SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 www.ti.com AC TEST CIRCUIT VIN=50 mV FANOUT=1 FANOUT=4 V =+5V R=2.4k R=630 V-=-5V C=15 pF C=30 pF + 6 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 LM160, LM360 www.ti.com SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 SCHEMATIC DIAGRAM Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 7 LM160, LM360 SNOSBJ4C - MAY 1999 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C * 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM160 LM360 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM360M ACTIVE SOIC D 8 95 Non-RoHS & Non-Green Call TI Call TI 0 to 70 LM 360M LM360M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LM 360M LM360MX ACTIVE SOIC D 8 2500 Non-RoHS & Non-Green Call TI Call TI 0 to 70 LM 360M LM360MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LM 360M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM360MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM360MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM360MX SOIC D 8 2500 367.0 367.0 35.0 LM360MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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