NDT454PJ23Z - Fairchild Semiconductor Corporation

June 1996

NDT454P

P-Channel Enhancement Mode Field Effect Transistor

General Description Features

____________________________________________________________________________________________

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter NDT454P Units

VDSS Drain-Source Voltage -30 V

VGSS Gate-Source Voltage ±20 V

IDDrain Current - Continuous (Note 1a) ±5.9 A

- Pulsed ±15

PDMaximum Power Dissipation (Note 1a) 3W

(Note 1b) 1.3

(Note 1c) 1.1

TJ,TSTG Operating and Storage Temperature Range -65 to 150 °C

THERMAL CHARACTERISTICS

RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W

RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W

* Order option J23Z for cropped center drain lead.

NDT454P Rev. D2

Power SOT P-Channel enhancement mode power field effect

transistors are produced using Fairchild's proprietary, high cell

density, DMOS technology. This very high density process is

especially tailored to minimize on-state resistance and provide

superior switching performance. These devices are particularly

suited for low voltage applications such as notebook computer

power management and other battery powered circuits where

fast switching, low in-line power loss, and resistance to

transients are needed.

-5.9A, -30V. RDS(ON) = 0.05Ω @ VGS = -10V

RDS(ON) = 0.07Ω @ VGS = -6V

RDS(ON) = 0.09Ω @ VGS = -4.5V.

High density cell design for extremely low RDS(ON).

High power and current handling capability in a widely used

surface mount package.

Electrical Characteristics (TA = 25°C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V

IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1 µA

VDS = -15 V, VGS = 0 V TJ = 70°C -5 µA

IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA

IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA

ON CHARACTERISTICS (Note 2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -2.7 V

RDS(ON) Static Drain-Source On-Resistance VGS = -10 V, ID = -5.9 A 0.038 0.05 Ω

VGS = -6 V, ID = -5.2 A 0.046 0.07

VGS = -4.5 V, ID = -4.6 A 0.064 0.09

ID(on) On-State Drain Current VGS = -10 V, VDS = -5 V -15 A

VGS = -4.5, VDS = -5V -5

gFS Forward Transconductance VDS = 15 V, ID = 5.9 A 10 S

DYNAMIC CHARACTERISTICS

Ciss Input Capacitance VDS = 15 V, VGS = 0 V,

f = 1.0 MHz 950 pF

Coss Output Capacitance 610 pF

Crss Reverse Transfer Capacitance 220 pF

SWITCHING CHARACTERISTICS (Note 2)

tD(on)Turn - On Delay Time VDD = -15 V, ID = -1 A,

VGEN = -10 V, RGEN = 6 Ω10 30 ns

trTurn - On Rise Time 18 60 ns

tD(off) Turn - Off Delay Time 80 120 ns

tfTurn - Off Fall Time 45 100 ns

QgTotal Gate Charge VDS = -15 V,

ID = -5.9 A, VGS = -10 V 29 40 nC

Qgs Gate-Source Charge 3

Qgd Gate-Drain Charge 11

NDT454P Rev. D2

Electrical Characteristics (TA = 25°C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

ISMaximum Continuous Drain-Source Diode Forward Current -1.9 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -5.9 A (Note 2)-0.85 -1.3 V

trr Reverse Recovery Time VGS = 0V, IF = -5.9 A, dIF/dt = 100 A/µs 100 ns

Notes:

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by

design while RθCA is determined by the user's board design.

PD(t)=TJ−TA

RθJA(t)=TJ−TA

RθJC+RθCA(t)=ID

2(t)×RDS(ON)TJ

Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.

b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.

c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDT454P Rev. D2

1a 1b 1c

NDT454P Rev. D2

-5-4-3-2-10

-30

-25

-20

-15

-10

-5

V , DRAIN-SOURCE VOLTAGE (V)

I , DRAIN-SOURCE CURRENT (A)

-6.0

-4.0

V =-10V

-3.0

-4.5

-3.5

-5.0

-20-16-12-8-40

0.5

1.5

2.5

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

V = -3.5V

R , NORMALIZED

DS(on)

-6.0V

-10V

-6.0V

-5.0V

-4.0V -4.5V

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

Typical Electrical Characteristics

-50 -25 025 50 75 100 125 150

0.6

0.8

1.2

1.4

1.6

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE ON-RESISTANCE

V = -10V

I = -5.9A

R , NORMALIZED

DS(ON)

-20-15-10-50

0.5

1.5

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

R , NORMALIZED

DS(on)

25°C

-55°C

V = -10V

T = 125°C

Figure 3. On-Resistance Variation

with Temperature. Figure 4. On-Resistance Variation

with Drain Current and Temperature.

-5-4-3-2-1

-20

-16

-12

-8

-4

-V , GATE TO SOURCE VOLTAGE (V)

-I , DRAIN CURRENT (A)

25 125

V = -10V

T = -55°C

-50 -25 0 25 50 75 100 125 150

0.6

0.7

0.8

0.9

1.1

1.2

T , JUNCTION TEMPERATURE (°C)

GATE-SOURCE THRESHOLD VOLTAGE

I = -250µA

V = V

DS GS

V , NORMALIZED

Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation

with Temperature.

NDT454P Rev. D2

-50 -25 0 25 50 75 100 125 150

0.94

0.96

0.98

1.02

1.04

1.06

1.08

1.1

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE BREAKDOWN VOLTAGE

I = -250µA

BV , NORMALIZED

DSS

00.3 0.6 0.9 1.2 1.5

0.001

0.01

0.1

-V , BODY DIODE FORWARD VOLTAGE (V)

-I , REVERSE DRAIN CURRENT (A)

T = 125°C

J25°C -55°C

V = 0V

Figure 7. Breakdown Voltage

Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation

with Source Current and

Temperature.

Typical Electrical Characteristics (continued)

0 10 20 30 40

Q , GATE CHARGE (nC)

-V , GATE-SOURCE VOLTAGE (V)

I = -5.9A

DV = -10V

DS -15V -20V

0.1 0.3 1 3 10 30

100

200

300

500

1000

2000

3000

-V , DRAIN TO SOURCE VOLTAGE (V)

CAPACITANCE (pF)

iss

f = 1 MHz

V = 0V

oss

rss

-VDD

VOUT

VGS DUT

VIN

RGEN G

Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.

Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms.

10%

50%

90%

10%

90%

50%

VIN

VOUT

on off

d(off) f

d(on)

t t

ttt

INVERTED

10%

PULSE WIDTH

NDT454P Rev. D2

-20-15-10-50

I , DRAIN CURRENT (A)

g , TRANSCONDUCTANCE (SIEMENS)

T = -55°C

25°C

V = -15V

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature.

Figure 16. Maximum Safe Operating Area.

Typical Electrical and ThermalCharacteristics (continued)

00.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

I , STEADY-STATE DRAIN CURRENT (A)

4.5"x5" FR-4 Board

T = 25 C

Still Air

V = -10V

00.2 0.4 0.6 0.8 1

0.5

1.5

2.5

3.5

2oz COPPER MOUNTING PAD AREA (in )

STEADY-STATE POWER DISSIPATION (W)

4.5"x5" FR-4 Board

T = 25 C

Still Air

0.1 0.2 0.5 1 2 5 10 30 50

0.01

0.03

0.1

0.3

- V , DRAIN-SOURCE VOLTAGE (V)

-I , DRAIN CURRENT (A)

100ms

10s

10ms

RDS(ON) LIMIT

1ms

V = -10V

SINGLE PULSE

R = See Note 1c

T = 25°C

θJA

100us

Figure 15. Maximum Steady-State Drain

Current versus Copper Mounting Pad

Area.

Figure 14. SOT-223 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad

Area.

Figure 15. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

0.0001 0.001 0.01 0.1 1 10 100 300

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

t , TIME (sec)

TRANSIENT THERMAL RESISTANCE

r(t), NORMALIZED EFFECTIVE

Single Pulse

D = 0.5

0.1

0.05

0.02

0.01

0.2

Duty Cycle, D = t / t

R (t) = r(t) * R

R = See Note 1 c

θJA

T - T = P * R (t)

θJA

P(pk)

1 t

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

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