TC3567CFSG TC3567CFSG (R) Bluetooth low energy IC Rev 1.1 (R) The Bluetooth word mark and logos are registered trademarks owned by the Bluetooth SIG, Inc. and any use of such marks by Toshiba is under license. Other trademarks and trade names are those of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. (c)2017 TOSHIBA Corporation 1 2017-06-26 TC3567CFSG Contents 1. General Description...............................................................................................................................................................................4 1.1. Product Concept ...............................................................................................................................................................................4 1.2. Features.............................................................................................................................................................................................4 2. Pin Function ...........................................................................................................................................................................................5 2.1. TC3567CFSG Pin Assignment (Top View)......................................................................................................................................5 2.2. Pin Function Descriptions .................................................................................................................................................................6 2.3. GPIO function list...............................................................................................................................................................................9 2.4. 3. Power Supply Pins ......................................................................................................................................................................... 10 System Configuration..........................................................................................................................................................................11 3.1. 3.2. 4. Block Diagram .................................................................................................................................................................................11 Boot Sequence............................................................................................................................................................................... 12 Hardware Interfaces ........................................................................................................................................................................... 13 4.1. Reset Interface (Power up sequence) .......................................................................................................................................... 13 4.1.1. Features ............................................................................................................................................................................. 13 4.1.2. Connection Example ......................................................................................................................................................... 13 4.2. UART Interface............................................................................................................................................................................... 14 4.2.1. Features ............................................................................................................................................................................. 14 4.2.2. Connection Example ......................................................................................................................................................... 14 4.2.3. Frame Format .................................................................................................................................................................... 15 4.2.4. Flow Control Function........................................................................................................................................................ 15 4.2.5. TX message spacing function........................................................................................................................................... 16 4.2.6. Error Detecting Functions.................................................................................................................................................. 17 4.2.7. Host Wake up Function ..................................................................................................................................................... 18 4.2.8. HCI mode ........................................................................................................................................................................... 18 4.2.8.1. 4.3. 4.3.1. Features ............................................................................................................................................................................. 19 4.3.2. Connection Example ......................................................................................................................................................... 19 4.3.3. 4.4. Frame Format .................................................................................................................................................................... 20 2 I C Interface .................................................................................................................................................................................... 21 4.4.1. Features ............................................................................................................................................................................. 21 4.4.2. Connection Example ......................................................................................................................................................... 21 4.4.3. Selection of External Pull-up Resistor Value .................................................................................................................... 22 4.4.4. Frame Format .................................................................................................................................................................... 23 4.5. PWM Interface................................................................................................................................................................................ 24 4.5.1. Pulse Generation Function................................................................................................................................................ 24 4.5.2. Rhythm Function (Output Masking).................................................................................................................................. 25 4.6. ADC ................................................................................................................................................................................................ 26 4.6.1. Features ............................................................................................................................................................................. 26 4.6.2. Descriptions ....................................................................................................................................................................... 26 4.7. IC Reference Clock Interface ........................................................................................................................................................ 27 4.7.1. Features ............................................................................................................................................................................. 27 4.7.2. Connection Example ......................................................................................................................................................... 27 4.8. 5. HCI Reset ...................................................................................................................................................................... 18 SPI Interface ................................................................................................................................................................................... 19 Sleep Clock Interface ..................................................................................................................................................................... 28 4.8.1. Sleep Clock Connection Example .................................................................................................................................... 28 4.8.2. External Oscillator Connection Example .......................................................................................................................... 28 Electric Characteristics ....................................................................................................................................................................... 29 2 2017-06-26 TC3567CFSG 5.1. Absolute Maximum Ratings........................................................................................................................................................... 29 5.2. Operating Conditions ..................................................................................................................................................................... 30 5.3. DC electric characteristics.............................................................................................................................................................. 31 5.3.1. Current Consumption (Design value) ............................................................................................................................... 31 5.4. Built-in Regulator Characteristics .................................................................................................................................................. 33 5.5. ADC Characteristics....................................................................................................................................................................... 33 5.6. RF Characteristics (Design value)................................................................................................................................................. 34 5.7. AC Interface Characteristics (Design value) ................................................................................................................................. 36 5.7.1. UART Interface .................................................................................................................................................................. 36 5.7.2. I2C Interface........................................................................................................................................................................ 37 5.7.2.1. Normal Mode ................................................................................................................................................................. 37 5.7.2.2. Fast mode ...................................................................................................................................................................... 38 5.7.3. 5.8. 6. SPI Interface....................................................................................................................................................................... 39 Characteristics of Flash-ROM block.............................................................................................................................................. 40 System Configuration Example ......................................................................................................................................................... 41 6.1. 6.2. 7. In HCI mode ................................................................................................................................................................................... 41 In User-App mode .......................................................................................................................................................................... 42 Package outline .................................................................................................................................................................................. 43 7.1. Outline dimensional drawing TC3567CFSG (P-VQFN40-0505-0.40-005/F01)......................................................................... 43 RESTRICTIONS ON PRODUCT USE......................................................................................................................................................... 44 3 2017-06-26 TC3567CFSG 1. General Description 1.1. Product Concept (R) TC3567CFSG (Later omitted TC3567C.) are compliant with Bluetooth core specification 4.2. RF analog parts and baseband (R) (R) digital parts are built in them, and TC3567C provides Bluetooth HCI (Host Control Interface) functions and Bluetooth low energy (R) GATT profile functions defined by Bluetooth core specifications. Additionally, this IC works as an application using low power Bluetooth(R) communication by storing the application program into built-in flash ROM. 1.2. Features (R) Compliant with Bluetooth Ver4.2 low energy (R) Built-in Bluetooth Baseband Built-in Bluetooth RF analog (R) (R) Built-in ARM Cortex(R)-M0 (13 MHz or 26 MHz function mode is able to select to run) On-chip mask ROM for Bluetooth program (216 KB) On-chip work RAM for Bluetooth Baseband process (128 KB) On-chip NOR Flash Memory (128 KB, More than 100,000 erase and program cycles) Supports patch program loader function 2 boot modes (HCI mode, User-App mode) (R) (R) General Purpose IO ( 17 ports) General Purpose Serial Interfaces SPI interface (1 ch assigned to a General Purpose IO) I C interface (1 ch assigned to a General Purpose IO) 2 Host CPU Interface UART interface (9600 bps to 921.6 kbps, 1ch - shared with GPIOs) SPI interface Emulator debug control interface Wake-up Interface (2 ch assigned to a General Purpose IO) PWM Interface (4 ch assigned to General Purpose IOs) Reference Clock Input (26 MHz) Sleep Clock Input (32.768 kHz) SWD(Serial Wire Debug)2-wire (1 ch) Wake-up input function from sleep and deep sleep Built-in oscillator for crystal oscillator connection External oscillator input supported Built-in oscillator for crystal oscillator connection Works as Standalone (In User-App mode, operating by standalone is possible) Sleep and Deep Sleep Functions Built-in DCDC converter and LDO Wide range of input power supply voltages supported (Booting power supply voltage : 2.0 to 3.6 V, low battery voltage detection) Built-in general purpose ADC External analog inputs assigned to GPIOs (5 ch) Internal VDD monitoring (1 ch - connected inside) Package: TC3567CFSG: QFN Package [40 pin, 5 x5 mm, 0.4 mm pitch, 0.9 mm thickness] 4 2017-06-26 TC3567CFSG GPIO3 GPIO4 GPIO9 VDDIOFQ GPIO10 GPIO13 GPIO14 VDDIO2 SLPXOOUT SLPXOIN 2. Pin Function 2.1. TC3567CFSG Pin Assignment (Top View) 30 29 28 27 26 25 24 23 22 21 GPIO0 31 20 VSSDC SWDCLK 32 19 LX GPIO15 33 18 VBAT GPIO12 34 17 SWDIO GPIO11 35 16 GPIO2 GPIO5 36 15 VDDCORE2 GPIO6 37 14 VDDCORE1 GPIO7 38 13 VSSX GPIO8 39 12 XOOUT GPIO1 40 11 XOIN 2 3 4 5 6 7 8 9 10 RESETX TMODE VPGM VSSRFIO RFIO VSSA TRTEST1 TRTEST2 VDDIO1 1 GPIO25 FIN (VSSD) Figure 2-1 Pin Assignment (Top View) 5 2017-06-26 TC3567CFSG 2.2. Pin Function Descriptions Table 2-1 shows attributes, input/output states for operating modes and descriptions for pin functions. Table 2-3 shows descriptions about power supply pins. Table 2-1 Pin Functions Pin name Pin No. Attribute Condition VDD category Default Direction (during reset) Functional description Type Reset interface RESETX 3 VDDIO -- Hardware reset input pin. IN Setting this pin to Low level put the system at reset Schmitt trigger state. Clock interface XOIN 11 VDDCORE IN Reference clock input pin. Please use oscillator with IN 26 MHz and < 50 ppm accuracy. OSC A feedback resistor is built in between XOIN pin and XOOUT pin and a capacity array which can set parameters in the crystal oscillation circuit is built-in, so that external feedback resistances and capacities are unnecessary. XOOUT 12 VDDCORE OUT Oscillator output for Baseband and RF reference OUT clock (26 MHz) pin. OSC A feedback resistor is built in between XOIN pin and XOOUT pin and a capacity array which can set parameters in the crystal oscillation circuit is built-in, so that external feedback resistances and capacities are unnecessary. SLPXOIN 21 VDDIO IN Sleep clock input pin from oscillator. Please use an IN oscillator with 32.768 kHz and < 500 ppm accuracy. OSC A feedback resistor is built in between SLPXOIN pin and SLPXOOUT pin and a capacity array which can set parameters in the crystal oscillation circuit is built-in, so that external feedback resistances and capacities are unnecessary. An external clock can be input from this pin. When the crystal oscillator is not used and do not supply a clock from the outside, this pin should be connected to the GND. SLPXOOUT 22 VDDIO IN Oscillator output (feedback) pin for the oscillation of IN/OUT 32.768 kHz. OSC A feedback resistor is built in between SLPXOIN pin and SLPXOOUT pin and a capacity array which can set parameters in the crystal oscillation circuit is built-in, so that external feedback resistances and capacities are unnecessary. When the crystal oscillator is not used, this pin should be connected to the GND. 6 2017-06-26 TC3567CFSG Pin name Pin No. Attribute Condition VDD category Default Direction (during reset) Functional description Type RF interface RFIO 7 VDDCORE -- RF I/O pins. IN/OUT This product incorporates the 50 matching circuit, Analog so that external matching circuit is unnecessary. The RF output pattern should wire with the 50 transmission line. For details, refer to the hardware application note of this product. General purpose I/O port Refer to Table 2-2 GPIO0 31 VDDIO GPIO15 33 IN/OUT During reset, the input will be disable state with Pull-up disconnecting the Pull-up/Pull-down resistor. Pull-down After the pin configuration by software processing, it Schmitt trigger General purpose I/O pin. works as a GPIO pin of the input and output or function pin. Please refer to Table 2-2. Refer to Table 2-2 GPIO1 40 VDDIO GPIO2 16 IN/OUT During reset, the input will be disable state with GPIO5 36 Pull-up connecting the Pull-up resistor. GPIO6 37 Pull-down After the pin configuration by software processing, it GPIO7 38 Schmitt trigger works as a GPIO pin of the input and output or GPIO8 39 function pin. GPIO11 35 Please refer to Table 2-2. GPIO12 34 In addition, GPIO1 and GPIO2 pin is used in the GPIO25 2 case of switching operation modes. GPIO3 30 VDDIO GPIO4 29 IN/OUT GPIO9 28 Pull-up disconnecting the Pull-up/Pull-down resistor. GPIO10 26 Pull-down After the pin configuration by software processing, it GPIO14 24 Schmitt trigger Refer to Table 2-2 General purpose I/O pin. ADC input and general purpose I/O pin. During reset, the input will be disable state with works as a GPIO pin of the input and output or function pin or general purpose ADC channel pin. Please refer to Table 2-2. GPIO13 25 VDDIO Refer to Table 2-2 General purpose IO pin. IN/OUT During reset, the input will be disable state with Pull-up connecting the Pull-up resistor. Pull-down After the pin configuration by software processing, it Schmitt trigger works as a GPIO pin of the input and output or function pin. Please refer to Table 2-2. 7 2017-06-26 TC3567CFSG Pin name Pin No. Attribute Condition VDD category Default Direction (during reset) Functional description Type SWDCLK 32 VDDIO Pull-down Serial Wire debugger clock pin. IN During the reset, it remains in the input disable state Pull-up with connecting the Pull-down resistor. After the Pull-down reset is released, it will be the input of the Serial Schmitt trigger Wire Debugger clock. When not used, this pin should be open. SWDIO 17 VDDIO Pull-up Serial Wire Debugger data pin and operation IN/OUT switching pin. Pull-up During the reset, it remains in the input disable state Pull-down with connecting the Pull-up resistor. After the reset Schmitt trigger is released, it will be the input and output of the Serial Wire Debugger data. In addition, SWDIO pin is used in the case of switching operation modes. When not used, this pin should be open. IC test interface TMODE 4 VDDIO -- Test mode setting pins. IN This pin is used for IC manufacturing test and need Schmitt trigger to be connected to GND when assembled on a board. TRTEST1 9 VDD12A -- Analog test pins. TRTEST2 10 IN/OUT These pins are used for IC manufacturing test and Analog need to be connected to GND when assembled on a board. 8 2017-06-26 TC3567CFSG 2.3. GPIO function list GPIO pins can be assigned to UART I/Fs, serial memory I/Fs and etc. by TC3567C firmware or command from external Hosts. Table 2-2 shows available functions, during reset status and software controlling after reset release for each GPIO pin. About what function name shown in Table 2-2 is assigned to a plurality of pins in the same, please note that it cannot be assigned to select a plurality of pins at the same time. Table 2-2 Available functions for GPIO Pin During reset status After reset release Disable/ GPIO0 Disable/ Hi-Z Disconnection: Pull-up, Pull-down GPIO1 Disable/ Pull-up GPIO2 Disable/ Pull-up GPIO3 Disable/ Hi-Z PWM0 Output Input/ Pull-up PWM1 (Note2) Output SPI-DIN Output Input Input/ Pull-up UART1-TX SPI-DOUT (Note3) Output Output Input/ Pull-up UART1-RX SPI-DIN (Note3) Input Input GPIO5 Disable/ Pull-up GPIO6 Disable/ Pull-up GPIO7 Disable/ Pull-up Input/ Pull-up GPIO8 Disable/ Pull-up Input/ Pull-up GPIO9 Disable/ Hi-Z Disconnection: -- -- -- -- -- -- -- -- -- -- -- -- -- Open -- -- -- Open SPI-SCS UART1-RTSX Output Output -- Open SPI-SCLK UART1-CTSX Output Input -- Open -- PWM3 Pull-up, Pull-down Open -- Output Disconnection: -- -- SPI-DOUT Disable/ Disable/ Hi-Z -- -- Output Pull-up, Pull-down unused Function 4 PWM2 Disconnection: Pin state at input Function 3 Input (Note2) Analog Function 2 WakeUp0 Input/ Pull-up Disable/ GPIO4 Function 1 I2C-SCL -- Output I2C-SDA -- I/O Disable/ Disconnection: Disable/ Pull-up Input/ Pull-up GPIO12 Disable/ Pull-up Input/ Pull-up GPIO13 Disable/ Pull-up Input/ Pull-up GPIO14 Disable/ Hi-Z Disconnection: Disable/ Pull-up, Pull-down Disable/ GPIO15 Disable/ Hi-Z Disconnection: Pull-up, Pull-down GPIO25 Disable/ Pull-up Input/ Pull-up Input ADC3 Open -- -- -- -- -- -- I2C-SCL SPI-DOUT Output Output -- -- -- Open I2C-SDA SPI-DIN I/O Input -- -- -- Open UART1-RTSX 32 kHz Output Output -- -- -- Open UART1-CTSX 32 kHz Input Output -- -- -- -- -- -- Open -- -- -- -- Open Pull-up, Pull-down GPIO11 ADC2 Open -- Disable/ Disable/ Hi-Z Input Open (Note1) -- Pull-up, Pull-down GPIO10 ADC1 Open (Note1) WakeUp1 Input -- Input ADC4 Input ADC5 Input Open Open Open Note1: Handle with care because of using operation mode switching. Note2: Except in User-App mode, it becomes Pull-down. Note3: In the HCI mode, the pull-up / pull-down resistor is disconnected. 9 2017-06-26 TC3567CFSG 2.4. Power Supply Pins Table 2-3 shows the attributes and descriptions of power supply pins for normal operations. Table 2-3 Power supply pins Pin name Pin number Attribute Description Type VDD/GND VDD/GND VPGM 5 VBAT 18 LX 19 VDDCORE1 14 VDDCORE2 15 TEST Test pin -- Please connect VPGM to GND. VBAT Power supply pin for DCDC and sleep circuit. VDD Connect the external power source for DCDC and LDO built into the IC. VBAT DCDC output pin. VDD Please connect to external inductor for DCDC. -- DCDC for feedback input, analog circuit power supply pin. VDD Please connect to external inductor for DCDC. -- DCDC for feedback input, digital circuit power supply pin. VDD Please connect to external inductor for DCDC. VDDIO1 1 VDDIO IO power supply VDDIO2 23 VDD Power supply pin for GPIO. VDDIOFQ 27 VDDIOFQ Flash ROM external capacitor connection pin. VDD It has been connected to the power supply of the internal flash ROM of the IC. As the LDO load capacitor, a capacitor of 0.1 F or more should be connected at the operation temperature. VSSA 8 Analog GND pin for analog, this pin needs to be connected to GND. GND VSSRFIO 6 Analog GND pin for RFIO, this pin needs to be connected to GND. GND VSSX 13 Analog GND pin for OSC, this pin needs to be connected to GND. GND VSSDC 20 Digital GND pin for DCDC, this pin needs to be connected to GND. GND VSSD FIN Digital Die pad ground Fin. Connect the exposed Die Pad to GND because this pad GND is digital ground as well. 10 2017-06-26 TC3567CFSG 3. System Configuration 3.1. Block Diagram Figure 3-1 shows block diagram of TC3567C. TC3567C is powered by single voltage between 1.8 V and 3.6 V, especially 2.0 V of power supply is required in accessing to the internal flash ROM and the booting process. The chip has built-in DCDC and LDO requiring external capacitors. It uses 26 MHz 2 reference clock and 32.768 kHz sleep clock. External memory interface is SPI or I C, and host CPU interface is UART. HOST I/F VDDCORE2 Selector 32kHz X'tal 26MHz X'tal ClockGen/ Clock Management UART 2ch SPI/ I2C PWM 4ch GPIO ADC 6ch Baseband Block Power Management Controller Ref VBAT Level Detector VBAT 1.8 to 3.6V LDO DCDC RF PLL Modem (R) ARM Cortex(R)-M0 Mask ROM RAM (BackUp) Flash ROM RF Block Figure 3-1 Example of TC3567C system configuration 11 2017-06-26 TC3567CFSG 3.2. Boot Sequence The boot sequence of TC3567C is as shown below. Depending on the pin state of GPIO1 at the time of reset release, it can be used to switch between User-App mode and HCI mode. Reset release Begin of firmware boot-up L: Test mode L GPIO1 check SWDIO check H: User-App mode H: HCI mode See Flash-ROM(NVM) control section in Toshiba Test mode Programming Guide for detail GPIO2 check Read "Check Word" in NVM Check word check H L NG OK Load User-App from NVM to TC3567C RAM Checksum check NG OK HCI mode (UART) Start User-App Reserved mode Error (Hardware reset is required to recovery.) Figure 3-2 Boot Sequence of TC3567C 12 2017-06-26 TC3567CFSG 4. Hardware Interfaces 4.1. Reset Interface (Power up sequence) 4.1.1. Features Reset interface has the following features. 2.0 to 3.6 V operation Level sensitive asynchronous reset (Low level: reset) The reset signal should be at reset status (RESETX = Low) when the power is turned on. When the power supply has become over 2.0 V, to be disable the reset signal (RESETX = High). Then starts the X'tal oscillation after DCDC output has become stable If DCDC is used, or after each LDO output has reached its target voltage from VBAT supplying voltage. Then, an internal timer releases the internal reset after the X'tal oscillation has become stable. 4.1.2. Connection Example Reset signal can be input by an RC time constant circuit or an asynchronous level sensitive reset IC. Figure 4-1 shows a connection example where TC3567C is power-supplied by an RC time constant circuit. Reset signal can be given by RC time constant circuit. Figure 4-2 shows the timings to reset and reset-release for the power supply. Reset TC3567C Power Supply Connection example is the RC circuit that was omitted or simplified. Figure 4-1 Reset signal connection example VDDIO Power supply VBAT Power supply Reset signal DCDC / LDO Output Unstable Reference clock Power off Power ON Stable OSC boot timer Operation Voltage detection RC delay Figure 4-2 Power-on reset release sequence 13 2017-06-26 TC3567CFSG 4.2. UART Interface 4.2.1. Features TC3567C UART interface has the following features. 1.8 to 3.6 V operation Full-duplex start-stop synchronization data transfer (RX, TX, CTSX, RTSX) Two-wire start-stop synchronization data transfer (RX, TX) or four-wire start-stop synchronization data transfer (RX, TX, CTSX, RTSX) are available depending on the settings. Start bit field (1 bit), data bit field ( 8 bit, LSB first), stop bit field (1 bit), no parity bit In HCI mode, UART TX/RX pins can be switched by commands. Programmable baud rate: 9600 bps to 921.6 kbps. More than 3 characters are inserted between TX messages. Interval can be changed on the command. Error detection (receiver timeout error, receiver over run error, receiver frame error) Host wake up function TC3567C communicates commands, status, and data with a host CPU through UART interfaces. The UART interfaces are shared with GPIO pins, and during boot process after a reset, TC3567C firmware assigns UART functions to the GPIOs. The UART interfaces can operate at 1.8 to 3.6 V depending on the VDDIO power supply voltage. Sharing the power supply pin with other hardware interfaces, they cannot operate at a different voltage from the one other hardware interfaces operate at. 4.2.2. Connection Example TC3567C UART can be connected with an UART interface on a host CPU. Figure 4-3 shows an example of two-wire start-stop synchronization data transfer connection with an external host CPU. Figure 4-4 shows the timing when UART is assigned to GPIO and activated. TC3567C HOST CPU UART Received Data (RX) UART Transmitted Data (TX) Figure 4-3 UART connection example Reset UART TX data Output direction UART RX data Input direction Reset GPIO Configuration (Pulled up to high) UART Communication Figure 4-4 Timing for UART function assignment 14 2017-06-26 TC3567CFSG 4.2.3. Frame Format TC3567C supports the following format: Number of data bits: 8 bits (LSB first) Parity bit: no parity Stop bit: 1 stop bit Flow control: RTSX/CTSX Figure 4-5 shows UART data frame. 1 2 3 4 5 6 7 8 9 10 CTSX TX LSB 1 2 3 4 5 6 MSB Start bit Stop bit RTSX RX LSB 1 Start bit 2 3 4 5 6 Over Sampling (x 12 to 17) /bit MSB Stop bit Figure 4-5 UART data frame 4.2.4. Flow Control Function Hardware flow control is available when TC3567C UART interface is assigned to GPIO5 to GPIO8 (GPIO5, 6, 13, 14) as four-wire start-stop synchronization data transfer. Transmit flow control (CTSX) and receive flow control (RTSX). Figure 4-6 shows signals input and output direction. TC3567C UART Request To Send (RTSX) HOST CPU UART Clear To Send (CTSX) UART Received Data (RX) UART Transmitted Data (TX) Figure 4-6 UART connection example CTSX (Clear to Send) input signal is used for UART transmitting. Low input indicates the peer device (for example, the host in the Figure 4-6) is ready to receive data, and TC3567C sends data if it has data to transmit. On the other hand, TC3567C stops transmitting on the basis of UART unit frame when CTSX input is high. RTSX (Request to Send) output signal is used for UART receiving. Low output indicates TC3567C is ready to receive data and requests data to the peer device. TC3567C outputs RTSX low when ready to receive data. When the UART becomes busy and cannot receive data, TC3567C outputs RTSX high, and stops UART communication on the basis of UART unit frame. Response time of UART transmitting and receiving to flow control signals is between 1 frame to 4 frames depending on the baud rate and internal process status of frame. 15 2017-06-26 TC3567CFSG 4.2.5. TX message spacing function TC3567C spaces more than 12 time frames between different TX messages making less than 12 time frames between TX frames in a TX message when several TX frames belong to one TX message. Host CPU is able to know the boundaries between TX messages by measuring time frames between TX frames. UART TX massage UART TX message 1 time frame UART TX data > 12 time frames < 12 time frames < 12 time frames < 12 time frames Figure 4-7 TX frames and TX messages 16 2017-06-26 TC3567CFSG 4.2.6. Error Detecting Functions TC3567C UART interface has 3 kinds of error detecting functions. Receiver timeout error Receiver over run error Receiver frame error Receiver timeout error detection judges an error if an UART RX message made from several RX frames has an RX frame interval longer than a certain value. The interval is counted by internal timer. Keep the interval between RX frames less than 12 time frames that belong to an RX message. For UART1, keep intervals between different RX messages more than 12 time frames. For example, 115200 bps has 0.087 ms for 1 frame, the interval between RX messages should be longer than 0.087 ms x 12 = 1.04 ms. RX messages that has intervals less than 12 time frames gives an error because TC3567C sees them as one UART RX message. Interval of the received frame is the default in the 12 time frame, but it can be changed by the command. UART RX message UART RX message 1 time frame UART RX data > 12 time frames < 12 time frames < 12 time frames < 12 time frames Figure 4-8 RX frames and RX messages Receiver over run error judges if UART receive frame buffer internal TC3567C is overflowed. Normally, this overflow does not happen when the flow control mentioned in 4.2.4 is activated for data communication. Receiver frame error judges if failing recognize the unit frame. A frame formation is judged as failure when its start bit is detected and the corresponding stop bit is detected as "0". 17 2017-06-26 TC3567CFSG 4.2.7. Host Wake up Function TC3567C can wakes up its host before sending UART data to the host. This function is disabled by default, but can be assigned to GPIO by command. Host wake up time can be changed by command (10 ms by default). UART TX message UART TX data Host wake up time (10 ms by default) Host wake up Figure 4-9 Host wake up 4.2.8. HCI mode (R) When TC3567C is used in the HCI mode, UART is the host interface to receive HCI commands. The Bluetooth wireless performance can be tested in HCI mode by the measurement equipment which connects the UART directly. 4.2.8.1. HCI Reset Sends a HCI reset command from the host, at least 150 s from the command complete event can be processed the following command successfully. 18 2017-06-26 TC3567CFSG 4.3. SPI Interface 4.3.1. Features TC3567C has the following main features for a serial memory interface Operation voltage: SPI interface 1.8 to 3.6 V Chip select: 1 ch Selectable: High-active and Low-active Chip select polarity: Serial clock master operation: Polarity and phase are adjustable (4 combinations are selectable) Serial clock frequency: 25 kHz to 6.5 MHz Serial data transfer mode: MSB-first, LSB-first SPI interface can operate at 1.8 to 3.6 V depending on VDDIO, however, cannot operate at different voltage from ones other interfaces are operate at. 4.3.2. Connection Example TC3567C SPI interface can be connected to serial EEPROMs and serial Flash-ROMs and has 1 chip select port. Figure 4-10 shows a connection example, where a serial Flash-ROM is connected to TC3567C SPI interface. Chip select (SPI-SCS) TC3567C Serial clock (SPI-SCLK) Serial Flash-ROM Write data (SPI-DOUT) Read data (SPI-DIN) Figure 4-10 Connection example for serial Flash-ROM using SPI interface 19 2017-06-26 TC3567CFSG 4.3.3. Frame Format When the SPI interface is connected to external ICs, the first 8 bit (X7 to X0) specifies the address and read or write mode. The command recognition code type and the address bit width should be determined by the external IC in use. For more information in detail, please refer to the technical documents for the external IC. Figure 4-11 shows an example where 8-bit address is written and then 8-bit data is read. Figure 4-12 shows an example where 8-bit address is written and then 8-bit data is written. Chip select Bit clock X7 Serial data (write) X1 X0 MSB LSB D7 Serial data (read) D2 D1 D0 MSB LSB Figure 4-11 SPI format (single byte read) Chip select Bit clock Serial data (write) X7 MSB X1 X0 D7 D1 D0 LSB MSB X7 MSB X1 X0 D7-2 LSB MSB D1 D0 LSB Serial data (read) Figure 4-12 SPI format (single byte write) 20 2017-06-26 TC3567CFSG 4.4. I2C Interface 4.4.1. Features 2 I C has the following main features for a serial interface. Operation voltage: 1.8 to 3.6 V 2 I C Interface 2 Operation mode: I C bus master Serial clock frequency: Standard mode (Max 100 kHz), Output mode: Open-drain output, CMOS output Device address format: 7-bit address (10-bit address is not supported) Fast mode (Min 100 kHz to Max 400 kHz) 2 I C interface can operate at 1.8 to 3.6 V depending on VDDIO, however, cannot operate at different voltage from ones other interfaces are operate at. 4.4.2. Connection Example 2 Figure 4-13 shows a connection example of a serial EEPROM using I C bus interface of the open-drain mode. External pull-up resistors (Rext) are necessary for both serial clock line and serial data line. 2 Figure 4-14 shows another connection example where I C bus is in the CMOS output mode. Only the serial data line needs Rext because this line can be driven by neither TC3567C nor a serial EEPROM. VDDIO Rext TC3567C VDDIO Rext Serial clock output Serial EEPROM Serial data input / output Serial EEPROM 2 Figure 4-13 Connection example for serial EEPROM with I C-bus interface (Open-drain output) VDDIO Rext TC3567C Serial clock output Serial EEPROM Serial data input / output Serial EEPROM 2 Figure 4-14 Connection example for serial EEPROM with I C-bus interface (CMOS output) 21 2017-06-26 TC3567CFSG 4.4.3. Selection of External Pull-up Resistor Value 2 An external pull-up resistor value needs to be selected by the following equations in case of I C bus interface. Its maximum value is 2 defined by equation (1), in which tr is rise time of serial clock and data and Cb is I C bus capacity. Its minimum value is defined by equation (2), in which VDDIO is a supply voltage for TC3567C, Vol_max is the maximum value of low level output voltage, and Iol is the low level output current. Please set the pull-up resistor value between these lower and upper limits. Rext_max = tr 0.8473 x Cb (1) Rext_min = VDDIO - Vol _ max Iol (2) 2 2 TC3567C supports I C bus standard mode (Max 100 kHz) and I C bus fast mode (Min 100 kHz to Max 400 kHz). The rise time tr is 1000 ns for the standard mode and it is 300 ns for the fast mode. Cb can vary depending on the IC board and how it is 2 implemented. Table 4-1 and Table 4-2 show examples when I C bus capacity is 20 pF. 2 Table 4-1 External pull-up resistor value for I C standard mode (Cb = 20 pF) 2 I C bus frequency Max 100 kHz tr [ns] 1000 Cb [pF] 20 VDDIO [V] 1.8 Vol_max [V] 3.0 0.3 3.6 0.4 0.4 Iol [mA] 1 2 4 1 2 4 1 2 4 Rext_min [k] 1.50 0.75 0.38 2.60 1.30 0.65 3.20 1.60 0.80 Rext_max [k] 59.01 2 Table 4-2 External pull-up resistor value for I C fast mode (Cb = 20 pF) 2 I C bus frequency Min 100 to Max 400 kHz tr [ns] 300 Cb [pF] 20 VDDIO [V] 1.8 Vol_max [V] 3.0 0.3 3.6 0.4 0.4 Iol [mA] 1 2 4 1 2 4 1 2 4 Rext_min [k] 1.50 0.75 0.38 2.60 1.30 0.65 3.20 1.60 0.80 Rext_max [k] 17.70 22 2017-06-26 TC3567CFSG 4.4.4. Frame Format 2 For I C format, TC3567C first generates start condition. Then, it sends device recognition address (7 bit: [A6:A0]) and the first byte 2 address ([B7:B0]) for the access target. Next, it goes for read or write sequence. For I C, every data is sent as MSB first. How to specify the value and byte address of the device identification address, and it has been determined in accordance with the device to be connected. In order to be connected, it must match the device to be connected. For read operation, TC3567C returns to the serial memory either receive acknowledge bit (ACK) or receive not acknowledge bit (NACK) every time it receives one byte. For write operation, TC3567C receives either ACK or NACK from the serial memory every time it sends one byte. It can handle not only one byte but also several bytes in a row. TC3567C generates stop condition when it has finished all the read or write of data. Figure 4-15 shows an example where TC3567C reads two-byte data. Figure 4-16 shows an example where TC3567C writes two-byte data. In these examples, gray texts and lines indicate signals that are given by the serial memory. For read operation, after having read the final byte data, TC3567C returns NACK with which the serial memory gets to know the completion of the read operation. Start condition Start condition Stop condition Serial clock Serial data A6 MSB A0 W ACK LSB B7 MSB B0 ACK LSB A6 MSB A0 R ACK LSB D7 D0ACK D7 D0 NAC MSB LSB MSB LSB 2 Figure 4-15 I C format (Serial memory, read) Start condition Stop condition Serial clock Serial data A6 MSB A0 W ACK LSB B7 MSB B0 ACK LSB D0 ACK D7 D0 ACK D7 MSB LSB MSB LSB 2 Figure 4-16 I C format (Serial memory, write) 23 2017-06-26 TC3567CFSG 4.5. PWM Interface TC3567C has a PWM interface that can be used for LED, buzzer control, etc. The PWM interface has the following features. Arbitrary pulse generation function It can select the source clock from 13 MHz and 32.768 kHz It has 12-bit clock division setting up to 1/4096: 8 Hz to 16.384 kHz (32.768 kHz), 3.17 kHz to 6.5 MHz (13 MHz) The pulse output can be masked by the regular pattern whose period is one second with 50 ms unit width (Rhythm function). It can generate an interrupt which is synchronized to the rhythm pattern period 1 s. It can switch the pulse output to Low / High active It can adjust the duty cycle of the pulse output. 4.5.1. Pulse Generation Function Figure 4-17 shows a brief explanation of the pulse generation. TC3567C can adjust output pulse frequency by changing its cycle. Also it can adjust on/off ratio by changing its duty. The cycle (frequency) can be set from 8 Hz to 16.384 kHz for 32.768 kHz clock, and from 3.17 kHz to 6.5 MHz for 13 MHz clock. The duty can be set from 0% to 100% Cycle Duty Figure 4-17 PWM pulse generation function 24 2017-06-26 TC3567CFSG 4.5.2. Rhythm Function (Output Masking) Figure 4-18 shows the brief explanation of PWM rhythm function. In addition to the one for pulse generation, TC3567C has another timer that has 50 ms x 20 = 1 s (rhythm counter). That timer has 20-bit register (pattern register), each bit corresponds to the rhythm counter that counts down in every 50 ms. When the pattern register is zero, the PWM output is masked to zero or one. Using this function, LED or buzzer can be on with 1 s periodical pattern 1s (50ms*20) 50ms Rhythm Counter Interrupt 19 18 17 16 15 1 0 19 1 0 1 1 0 1 0 1 PWM Generate Pattern Register PWM Output Note If the rhythm pattern set period (50ms) / pulse cycle time = not an integral, at the boundary of 0 to 1, 1 to 0 pattern register, Duty ratio of the pulse will not be as set. Cycle time 50ms PWM Generate Pattern Register 1 0 1 PWM Output Figure 4-18 PWM Rhythm Function 25 2017-06-26 TC3567CFSG 4.6. ADC 4.6.1. Features TC3567C has 6 ch of 10-bit ADCs for battery monitoring, analog inputs from external sensors, for example. The ADC has the following features. 5 ch for analog inputs Note: Analog inputs are shared with GPIO pins. 1 ch for VBAT voltage monitor Note: The reference input is internally connected to VBAT, and the analog input is to built-in VDDCORE2 output. Please refer to 4.6.2 for how to calculate voltage value. Maximum conversion rate: 1 MS/s 4.6.2. Descriptions The ADC has 10 bits conversion accuracy and can work for input voltages from 0 V to 3.6 V (VBAT). It has 6 ch of analog inputs, and the ch0 is connected to VDDCORE2 output, and the ch1 to ch5 are shared with GPIO pins. When a battery is used as power source, the reference voltage can slide over time because the battery is connected as reference voltage. In that case, the VDDCORE2 output voltage connected to ch0 can be used as a reference voltage. The input voltage to ch1 to ch5 is converted by the reference voltage of ch0 and the converted value is used to calculate a correct digital value by the CPU. The following shows the conversion method of the input voltage. Voltage A at time T can be calculated as follows (1) VDDCORE2 output voltage (VDDCORE2) on Ch0 should be converted by the ADC. The converted digital value is X. (2) The analog signal on Ch1 is converted and the converted digital value is Y. (3) When the absolute value of the analog signal on Ch1 is defined as Z (V), VDDCORE2 (V) / Z (V) = X / Y. So, Z (V) = VDDCORE2 (V) x Y / X Calculation example: Suppose ch0 (for ex. VDDCORE2 output is 1.2 V) is converted to 0x0188, and ch1 (measurement target) is converted to 0x0134, the absolute voltage at ch1 Z (V) is given by 1.2 x 0x0188 / 0x0134 = 1.2 x 392 / 308 = 1.527 (V). Figure 4-19 shows conceptual of voltage conversion. [V] 3.3V A[V] VDDCORE2 voltage VREF (2)=Y (1)=X Time[T] [t] Figure 4-19 Voltage conversion concept The ADC converts inputs from ch selected by register settings. When a conversion has finished, the CPU detects it by the interrupt or register polling, and then returns the results. The maximum sampling rate depends on software load on the CPU. Note: The numerical values are expressed as follows. Hexadecimal number: 0xABC 26 2017-06-26 TC3567CFSG 4.7. IC Reference Clock Interface 4.7.1. Features TC3567C has the following features for IC reference clock interface. Clock frequency: 26 MHz (please adjust the accuracy to < 50 ppm at the temperature in use) TC3567C doesn't require external feedback resistors and load capacitor because it has an internal feedback resistor and capacitor array. Please adjust capacitor array, based on the specification of the used oscillator and PCB layout and assembly. 4.7.2. Connection Example TC3567C XOIN Control Input XOOUT Trimming Figure 4-20 Crystal oscillator connection example 27 2017-06-26 TC3567CFSG 4.8. Sleep Clock Interface TC3567C has the following features for sleep clock interface. Crystal oscillator can be connected. Clock frequency: 32.768 kHz (please adjust the frequency accuracy to less than or equal to 500 ppm at the temperature in use.) Crystal oscillator is connected between SLPXOIN pin and SLPXOOUT pin. TC3567C doesn't require external feedback resistors and load capacitor because it has an internal feedback resistor and capacitor array between SLPXOIN pin and SLPXOOUT pin. Please adjust capacitor array based on PCB layout and assembly if necessary within the range of the X'tal's specification. When an external oscillator is connected, connect it to SLPXOIN and SLPXOOUT should be connected to the GND. When oscillator is not used and do not supply a clock from the outside, this pin needs to be connected to the GND. 4.8.1. Sleep Clock Connection Example TC3567C SLPXOIN Control Input SLPXOOUT Trimming Figure 4-21 Crystal oscillator connection example 4.8.2. External Oscillator Connection Example TC3567C SLPXOIN External oscillator Control SLPXOOUT Input Trimming Figure 4-22 External oscillator connection example 28 2017-06-26 TC3567CFSG 5. Electric Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings must not be exceeded even for a moment. Voltages, currents, and temperatures that exceed the absolute maximum ratings can cause break-downs, degradations, and damages not only for ICs but also for other components and boards. Please make sure application designs not to exceed the absolute maximum ratings in any situation. Table 5-1 Absolute maximum ratings (VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Items Ratings Symbols Units Min Max -0.3 +3.9 VIN -0.3 VDDIO + 0.3 (Note2) V VOUT -0.3 VDDIO + 0.3 (Note2) V Input current IIN -10 +10 mA Input power RFIO -- +6 dBm Storage temperature Tstg -40 +125 C Power supply VBAT VDDIO (Note1) Input voltage Output voltage V Note1: Do not connect VBAT to GND while VDDIO is powered. Current from VDDIO to VBAT through IC may cause damages, break-downs, and degradations. Note2: Please use VDDIO + 0.3 V not to exceed 3.9 V. 29 2017-06-26 TC3567CFSG 5.2. Operating Conditions TC3567C can operate normally with proven quality under the operating ranges. Any diversion from the operating ranges may cause false operation. Thus, please make sure application design to comply these operating ranges. Table 5-2 Operating conditions (VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Items VBAT Operating Voltage1 (Note1) VBAT Operating Voltage2 (Note1) VBAT Operating Voltage3 (Note2) Power Ratings Symbols Units Min Typ. Max VBATopr1 1.60 3.00 3.60 V VBATopr2 1.79 3.00 3.60 V VBATopr3 2.00 3.00 3.60 V VDDIOopr 1.80 3.00 3.60 V VDDIOFQ -- 1.7 -- V -- 1.2 -- V Fc 2400 -- 2483.5 MHz Reference clock Fck 25.99870 26.00000 26.00130 MHz Sleep clock fslclk 32.751616 32.768000 32.784384 kHz Ta -40 +25 +85 C VDDIO Operating Voltage supply (Note3) VDDIOFQ Output Voltage (Note3) VDDCORE Voltage (Note3) RF frequency Clock frequencies Ambient temp. VDDCORE1/ VDDCORE2 Note1: The low-voltage detection function is built in the VBAT pin. The IC operation is stop when the operating voltage falls to the minimum value of the VBAT operating voltage 1 (VBATopr1). The low-voltage detection voltage has a hysteresis in order not to start the IC repeatedly by the load variation after stopping. During voltage boosting, the internal CPU powers on when the operating voltage rises to the minimum value of the VBAT operating voltage 2 (VBATopr2). However, please pay attention that the minimum voltage of the VBAT operating voltage 3 (VBATopr3) is required for the reading and writing operation of the flash ROM as indicated in the Note 2. Note2: For reading and writing operation to the flash ROM in the digital block, the power in the range of VBAT operating voltage 3 should be supplied. In the booting process, please release RESET after the voltage rises to the minimum value (2.0 V) because of accessing to the flash ROM to confirm the existence of applications. Moreover, in case of operating in the User-App mode or driving till the under voltage detection turns off the operation, please pay attention to the relation between R/W operation to the flash ROM and the voltage. Note3: Please refer to other documents (application note) for our connection examples. Please do not input external power supply and do connect external capacitors to VDDIOFQ because they are supplied by the internal LDO. 30 2017-06-26 TC3567CFSG 5.3. DC electric characteristics 5.3.1. Current Consumption (Design value) This section shows current consumption. When the operating temperature (Ta) is 25C, and the operation of each power supply pin is in the recommendation connection state of our company, the current consumption is an average value. Table 5-3 Current consumption (VBAT = VDDIO1 = VDDIO2 = 3.0 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Items Digital operation Flash read Flash write RX Symbols Conditions IDDDIG (Active1) IDDRD (Flash Read) IDDWR IDDRX Max -- -- 0.8 -- -- -- 2.4 -- -- 15.6 -- -- 3.3 -- -- 3.3 -- -- 2.5 -- -- 2.4 -- -- 0.05 -- VBAT -- (Active2) Unit Typ. IDDTX Output Power= (Active3) 0 dBm Low power mode IDDS1 26 MHz crystal oscillator disabled With Connection (Sleep) 32 kHz crystal oscillator enabled Low power mode IDDS2 26 MHz crystal oscillator disabled Without Connection (Backup) 32 kHz crystal oscillator enabled Low power mode IDDS 26 MHz crystal oscillator disabled Without Connection (Deep Sleep) 32 kHz crystal oscillator disabled TX (Note) Ratings Min -- (Flash Write) Pins VBAT mA A Note: Power consumption for IO depends on its settings. 31 2017-06-26 TC3567CFSG Table 5-4 shows DC electric characteristics for each pin under 25C ambient temperature. Table 5-4 DC Electric Characteristics (VBAT = VDDIO1 = VDDIO2 = 3.0 V, VSSD = VSSA = VSSRFIO = VSSDC = VSSX = 0 V) Condition Items Symbols I/F Voltage Other Rating Measuring Pin Condition (Note 1) Min Typ. Max VDDIO 0.8xVDDIO -- -- Unit High Level Input VIH 3.0 V LVCMOS Voltage V Low Level Input VIL 3.0 V LVCMOS VDDIO -- -- 0.2xVDDIO -10 -- 10 10 -- 200 -10 -- 10 -200 -- -10 Voltage High Level Input IIH Current VDDIO = Input Voltage Low Level Input Pull-down Off IIL of each pin Pull-down On VDDIO Pull-up Off Pull-up On Current A High Level Output VOH 3.0 V IOH = 1 mA VDDIO VDDIO-0.6 -- -- V VOL 3.0 V IOL = 1 mA VDDIO -- -- 0.4 V 3.0 V -- SLPXOIN 0.8xVDDIO -- -- V 3.0 V -- SLPXOIN -- -- 0.2xVDDIO V Voltage Low Level Output Voltage External VIH 32 kHz SLPCLK Clock Input VIL level (Note2) SLPCLKL Note 1: Please refer to Table 2-3 for power supply line for each pin. Note 2: External oscillator is used for this case instead of crystal oscillator. 32 2017-06-26 TC3567CFSG 5.4. Built-in Regulator Characteristics Table 5-5 Built-in regulator characteristics (VBAT = 1.8 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Items Symbols Output voltages Vout1 Pin names and conditions VDDCORE1/ VDDCORE2 Ratings Min Typ. Max -- 1.2 -- Units V Table 5-6 Built-in regulator characteristics (VBAT = 1.8 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Items Symbols Pin names and conditions Output voltages Vout2 VDDIOFQ Ratings Min Typ. Max -- 1.7 -- Units V 5.5. ADC Characteristics Table 5-7 ADC characteristics (VBAT = 1.8 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Items Symbols Condition Analog reference voltage VREFH Analog input voltage VAIN Ratings Unit Min Typ. Max -- 1.8 3.0 3.6 V -- VSSD -- VREFH V 33 2017-06-26 TC3567CFSG 5.6. RF Characteristics (Design value) The following conditions are applicable unless otherwise specified. Ta = 25C VBAT = 3.0 V fx'tal = 26 MHz (Frequency accuracy is adjusted to 2 ppm at normal temperature) PAOUT= 0 dBm (R) Table 5-8, Table 5-9 shows RF receiving characteristics and RF transmitting characteristics based on Bluetooth Core Spec. V4.2 low energy. About some the characteristics data here are design values. Table 5-8 RF Characteristic Test Item Output Power In-band Emissions Packet 255 octets 255 octets Modulation 255 Characteristics octets Carrier frequency 255 offset (CFO) octets Carrier frequency 255 drift octets Carrier frequency 255 drift Rate octets bit PRBS9 PRBS9 11110000 10101010 -- ch. Condition 0,12, 19,39 Typ. Max peak -- -- average -- 0 -- Unit Pavg+ 3 dB dBm MHz -- -60 -30 -4 MHz -- -55 -30 -3 MHz -- -53 -30 0,12, -2 MHz -- -48 -20 19,39 2 MHz -- -50 -20 3 MHz -- -53 -30 4 MHz -- -56 -30 5 MHz -- -60 -30 f1avg (11110000) 225 249.3 275 kHz f2max (99.9 %) 99.9 100 -- % f2avg /f1avg 0.8 0.90 -- Ratio average -- 4.4 -- worst -150 -- 150 Absolute maximum -- 4.9 50 kHz Absolute maximum -- 4.9 20 kHz/50 s 0,12, 19,39 0,12, 19,39 10101010 Min -5 10101010 10101010 Spec. 34 dBm kHz 2017-06-26 TC3567CFSG Table 5-9 RF Characteristics Test Item Rx Sensitivity C/I and Receiver Selectivity Performance Sub Item -- Packet 37 octets at 1500 -- ch. 0,12, 19,3 D wave: PER=30.8 % packets bit 255 octets with dirty PRBS9 0,2,12, U wave: 19,37, GFSK 39 PRBS15 Condition at 1500 packets Blocking Performance -- 255 octets PRBS9 12 U wave: CW f1=-50 dBm Performance un-modulati 1500 packets 255 octets on f2=-50 dBm Max Unit -- -93.5 -- dBm -38 or -- <=- -7 MHz -- -6 MHz -- -32 -- -5 MHz -- -26 -- -4 MHz -- -30 -- -3 MHz -- -32 -- -2 MHz -- -35 -- -1 MHz -- -2 -- 0 MHz -- 8 -- 1 MHz -- -2 -- 2 MHz -- -30 -- 3 MHz -- -38 -- 4 MHz -- -40 -- 5 MHz -- MHz -- less -44 -- -38 or -- dB less 30-2000 MHz -30 -- -- 2003-2399 MHz -35 -- -- 2484-2997 MHz -35 -- -- 3000 M-12.75 GHz -30 -- -- 30.8 0 -- % -10 dBm 30.8 0 -- % -30 dBm 50 50 65.4 % dBm -4 MHz with Intermodulation Typ. with dirty => 6 D wave: Min PER=30.8 % 0,12, 19,39 +4 MHz with PRBS15 Maximum input signal level PER Report Integrity PER 255 octets PRBS9 PER 255 octets PRBS9 0,12, 19,39 0,12, 19,39 (R) Note: C/I characteristic and blocking characteristic has the relief specs of the logo attestation test of Bluetooth maybe applied. The blocking characteristic measures D wave as 12 ch. 35 2017-06-26 TC3567CFSG 5.7. AC Interface Characteristics (Design value) 5.7.1. UART Interface Table 5-10 UART Interface AC characteristics Symbols Items Min Typ. Max Unit tCLDTDLY Transmit Data ON from CTSX Low level 192 -- -- ns tCHDTDLY Transmit Data OFF from CTSX High level -- -- 2 byte tRLDTDLY Received Data ON from RTSX Low level 0 -- -- ns tRHDTDLY Received Data OFF from RTSX High level -- -- 8 byte tCLDTDLY tCHDTDLY CTSX TXD tTXDIV START BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 STOP tRLDTDLY tRHDTDLY RTSX RXD tRXDIV START BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 STOP Figure 5-1 UART Interface Timing Diagram 36 2017-06-26 TC3567CFSG 5.7.2. I2C Interface 5.7.2.1. Normal Mode 2 Table 5-11 I C Interface Normal mode AC Characteristics Symbols Items Min Typ. Max Unit tDATS Data set-up time 250 -- -- ns tDATH Data hold time 300 -- -- ns tDATVD Data validity period -- -- 3450 ns tACKVD ACK validity period -- -- 3450 ns tSTAS Restart condition set-up time 4700 -- -- ns tSTAH Restart condition hold time 4000 -- -- ns tSTOS Stop condition set-up time 4000 -- -- ns tBUF Bus open period from stop condition to start condition 4700 -- -- ns tr Rise up time -- -- 1000 ns tf Fall down time -- -- 300 ns tHIGH Serial clock period of High 4000 -- -- ns tLOW Serial clock period of Low 4700 -- -- ns Cb Bus load capacitance -- -- 400 pF tf SDA tr S: Sr : P: tDATS START condition Repeated START Condition STOP condition 70% 30% tf tHIGH tr tDATH tDATVD 70% 30 % SCL tSTAH tLOW 1/fSCL 1st clock S 2nd clock 3rd clock 9th clock tBUF SDA 70% 30% tSTAH tSTAS tACKVD tSTOS 70% SCL 30% 9th clock Sr P S 2 Figure 5-2 I C Interface Normal mode Timing diagram 37 2017-06-26 TC3567CFSG 5.7.2.2. Fast mode 2 Table 5-12 I C Interface Fast mode AC Characteristics Symbols Items Min Typ. Max Unit tDATS Data set-up time 100 -- -- ns tDATH Data hold time 300 -- -- ns tDATVD Datavalidity period -- -- 900 ns tACKVD ACKvalidity period -- -- 900 ns tSTAS Restart condition set-up time 600 -- -- ns tSTAH Restart condition hold time 600 -- -- ns tSTOS Stop condition set-up time 600 -- -- ns tBUF Bus open period from stop condition to start condition 1300 -- -- ns tr Rise up time 20 + 0.1Cb -- 300 ns tf Fall down time 20 + 0.1Cb -- 300 ns tSP Spike pulse width that can be removed 0 -- 50 ns tHIGH Serial clock period of High -- 1423 -- ns tLOW Serial clock period of Low -- 1423 -- ns Cb Bus load capacitance -- -- 400 pF tf SDA tr S : START condition Sr : Repeated START Condition P : STOP condition tDATS 70% 30% tf tDATH tHIGH tr tDATVD 70% 30 % SCL tSTAH tLOW 1/fSCL 1s t clock S 2nd clock 3rd clock 9th clock tBUF SDA 70% 30% tSTAS tSTAH tSP SCL tACKVD tSTOS 70% 30% 9th clock Sr P S Figure 5-3 I2C Interface Fast mode Timing diagram 38 2017-06-26 TC3567CFSG 5.7.3. SPI Interface Table 5-13 SPI Interface Symbols Items Min Typ. Max Unit tSPICLKCYC SPI clock cycle 154 -- -- ns tSPICLKHPW SPI clock high pulse width 77 -- -- ns tSPICLKLPW SPI clock low pulse width 77 -- -- ns tSPICSS SPI chip select setup time 38 -- -- ns tSPICSH SPI chip select hold time 77 -- -- ns tSPIIW SPI transfer idle pulse width 54 -- -- ns tSPIAS SPI address setup time 38 -- -- ns tSPIAH SPI address hold time 77 -- -- ns tSPIDS SPI data setup time 38 -- -- ns tSPIDH SPI data hold time 77 -- ns -- (R) (R) Note: SPI Interface operates on the basis of 1/n frequency of half the frequency of ARM Cortex -M0 core clock (6.5 MHz for 13 MHz core clock) Write SPICLKCYC SPICLKHPW SCLK SPICSS SPICSH SPICLKLPW SCS SPIDS SPIAS DOUT A7 A6 A5 WR A4 A0 D15 D14 D1 SPIIW D0 SPIAH A7 A6 SPIDH Read SPICLKCYC SPICLKHPW SCLK SPICSS SPICSH SPICLKLPW SCS SPIDS SPIAS DIN A7 A6 A5 WR A4 A0 D15 D14 D1 SPIAH SPIIW D0 A7 A6 SPIDH Figure 5-4 SPI Interface timing diagram 39 2017-06-26 TC3567CFSG 5.8. Characteristics of Flash-ROM block Table 5-14 Characteristics of Flash-ROM block (VBAT=2.0 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V) Item Number of times of erase and program Symbol Condition -- Ta=25C 40 Ratings Min Typ. Max 105 -- -- Unit times 2017-06-26 TC3567CFSG 6. System Configuration Example An example of system configuration is shown in the following figures. 6.1. In HCI mode Host interface=UART and 26 MHz Reference Clock= XOSC Connection. VDD 12 1F 2 XOOUT 11 1 0.1F 23 LX SLPXOIN 22 2 21 1 X2 X1 32.768KHz 15 27 0.1F VDDIO2 SLPXOOUT 14 1F VDDIO1 10H MLZ1608N100LT 19 26.000MHz XOIN VBAT X2 BAT_1 2 1 18 3 VDD X1 VDD 4 XOSC (32.768 kHz) of the dotted line enclosure is unnecessary when the external input (HOST common use) is chosen. GPIO and SWD of connection is the connection example of when not in use. 1 4 5 13 20 FIN VDDCORE1 VDDCORE2 VDDIOFQ SleepClockIN TMODE RESETX GPIO5 VPGM GPIO6 VSSX GPIO0 GPIO15 VSSDC VSSD SWDIO SWDCLK 3 36 37 31 33 RESETX UART_TX HOST I/F UART_RX WakeUP0 WakeUP1 17 32 ANT Coaxial Connecter 2 1 7 RFIO GPIO1 3 5 4 6 GPIO2 GPIO3 6 8 9 10 GPIO4 GPIO7 VSSRFIO GPIO8 GPIO9 VSSA GPIO10 GPIO11 TRTEST1 GPIO12 GPIO13 TRTEST2 GPIO14 GPIO25 40 16 30 29 38 39 28 26 35 34 25 24 2 Figure 6-1 Example of TC3567CFSG system configuration (HCI mode) 41 2017-06-26 TC3567CFSG 6.2. In User-App mode GPIO and SWD of connection is the connection example of when not in use. VDD 12 1F 2 XOOUT 11 1 0.1F 23 SLPXOIN 22 2 21 1 X2 X1 32.768KHz 15 27 0.1F LX SLPXOOUT 14 1F VDDIO1 VDDIO2 10H MLZ1608N100LT 19 26.000MHz XOIN VBAT X2 BAT_1 2 1 18 3 VDD X1 VDD 4 XOSC (32.768 kHz) of the dotted line enclosure is unnecessary when the external input (HOST common use) is chosen. 1 4 5 13 20 FIN VDDCORE1 VDDCORE2 VDDIOFQ SleepClockIN TMODE RESETX GPIO0 VPGM GPIO15 3 31 33 VSSX VSSDC VSSD SWDIO SWDCLK 17 32 ANT Coaxial Connecter 2 1 7 GPIO1 GPIO2 RFIO GPIO3 GPIO5 3 5 4 6 GPIO4 GPIO6 6 8 9 10 GPIO7 VSSRFIO GPIO8 GPIO9 VSSA GPIO10 GPIO11 TRTEST1 GPIO12 GPIO13 TRTEST2 GPIO14 GPIO25 40 16 30 29 36 37 38 39 28 26 35 34 25 24 2 Figure 6-2 Example of TC3567CFSG system configuration (User-App mode) 42 2017-06-26 TC3567CFSG 7. Package outline 7.1. Outline dimensional drawing TC3567CFSG (P-VQFN40-0505-0.40-005/F01) Unit: mm Weight: 0.068 g (Typ.) Figure 7-1 Package outline (P-VQFN40-0505-0.40-005/F01) 43 2017-06-26 TC3567CFSG RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. * PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative. * Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. * Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. * The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. * ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. * Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 44 2017-06-26