ICs for Communications
3-Channel ISDN PC Adapter Circuit
3PAC
PSB 2113 Version 1.1
Product Overview 07.97 T2113-XV11-O1-7600
Edition 07.97
This edition wa s rea lized using the so ftwar e syst em Fram eM ak er .
Publi shed by Siem ens AG,
HL TS
© Siem ens AG 1997.
All Rights R eserv ed.
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PSB 2113
Revision History: Current Version: 07.97
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PSB 2113
Table of Contents Page
Semiconductor Group 3 07.97
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Logic Sym bol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Pin Configura tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Pin Definitions and Funct ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.6 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.1 Operating Mo des . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9
2.2 Host Inter fac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2. 1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0
2.2.2 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2.3 In terrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2. 4 DMA Inte rfac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
2.2.5 Host Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3 Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 PCM Inte rfac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 8
3 Electric al Characteris tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.1 DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2 Absolute Max imum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 0
4 Package O utli nes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Semiconductor Group 4 07.97
PSB 2113
Overview
1 Overview
The 3-Chann el ISDN PC Adapter Circuit 3PA C int egrates all B-channe l and D-c hannel
functions for a host based ISDN access solution on a single chip. Especially for U-
interf ace applications only a transceiver needs to be connected to the 3PAC.
The 3P AC is pin com patible to the ISDN PC Ad apter Circ uit IP AC PSB 2115 which is a
one chip solution featuring a 3 channel controller + S-interface.
It includes an HDLC cont roller for the D-cha nnel and t wo protocol controllers f or the B-
channels. They can be used for HDLC protocol or transparent access. The system
integration is simplified by several host interface configurations selected via pin
strapping. They include multiplexed and demultiplexed interface options as well as the
optional indirect register access mechanism which reduces the number of necessary
re gister s in the address space to 2 locations.
The 3PAC combines the functions of the ISDN Communication Controller (ICC PEB
207 0) and the High-Level Se rial Communications C ontroller E xtended (H SCX-TE PSB
215 25) providing additional features and enhanced fu nctiona lity.
The F IFO size of the B-c hannel buff ers is 2x64 byte s per direction.
An auxiliary I/O port with interr upt capabilities on two input lines is available. These I/O
lines may be used to connect a DTMF receiver or other peripheral components to the
3PAC which need software control or have to forward status information to the host.
Peripheral data controllers can transfer data on a PCM interface which is mapped into
the B-c hannels on the IOM- 2 interfa ce.
The 3PA C is produced in advanced CMO S technology .
P-MQFP-64
Semiconductor Group 5 07.97
3-Channel ISDN PC Adapter Circuit
3PAC PSB 2113
Version 1.1 CMOS
Type Ordering Code Package
PSB 2113 H Q67223 - H1057 P-MQFP-64 (SMD)
PSB 2113 F Q67223 - H1058 P-T QFP -64 (SM D)
P-TQFP-64
• Reduced regist er address space due to indirect address mo de option
• Programm able timer (1 ... 63 ms) for cont in uous or single interrupt s
• 3 programmable LED outputs
• 8-bit multi plexed or demultiplexe d bus interface
• Siemens/Int e l or Motorola µP interfac e
1.1 Features
• Integrates D-channel and B-channel protocol
controller
• Replaces solutions based on ICC PEB 2070 and
HSCX-TE PSB 21525
• Easy adjustment of software us ing ICC and HSCX-
TE
• Pin compatible and software compatible to IPAC
PSB 2115
• Various types of protocol support depending on
operating mode (Non-auto mode, transparent
mode)
• Efficient transfer of data blocks from/to system
memory by DMA (for one B-channel) or interrupt
request (for both B-channels)
• Enlarged FIFO buffers for B-channels (2x64 byte)
• FIFO buffers for D-cha nnel (2x32 byte)
• Additional I/O interf ace with 2 interrupt inputs
• PCM interface for non IOM-2 compatible peripher al
data controllers
PSB 2113
Overview
Semiconductor Group 6 07.97
1. 2 Log ic S y mb ol
The logic symbol shows all functions of the 3PAC. It must be noted, that not all functions
are avai lable simultaneously, but depend on the selected mode .
Pins which are mark ed with a “ * “ are multi plexed and not available in all modes.
Figure 1
Logic Symbol
PSB 2113
Overview
Semiconductor Group 7 07.97
1.3 Pin Con figu rati on
Figure 2 shows the pin configur ation for P-MQF P- 64 and for P-T QFP -64 pack ages.
Figure 2
P in C onfi guration
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 13 14 1 5 1 6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48 47 46 45 44 4 3 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
CLKO
DU
DD
FSC
DCL
VSS
res_h
res_l
LDO
SDS
AUX4
AUX3
AUX2
AUX1
AUX0
CH1
CH0
DACKB
res_h
DRQRB
DRQTB
VDD
A7
A6
A5
A4
A3
A2
A1
A0
VSS
res_o
res_o
res_l
res_h
res_h
res_h
res_o
res_h
res_o
VSS
TP
TP
TP
AMODE
RES
CH2
VDD
INT
ALE
CS
WR / R /W
RD / DS
VSS
AD0 / D0
AD1 / D1
AD2 / D2
AD3 / D3
VDD
AD4 / D4
AD5 / D5
AD6 / D6
AD7 / D7
PSB 2113
Overview
Semiconductor Group 8 07.97
1.4 Pin Defin itio ns and Fu nct ion s
Pin No . Symbo l I npu t (I )
Output (O) Function
Microprocessor Bus Interface
8
9
10
11
13
14
15
16
AD0-7
D0...7
I/O
I/O
Multiplexed Bus Mode:
Add ress/d ata bus
Transfers addresses from the host system to the 3PAC
and data between the host system and the 3PAC.
Non-Multiplexed Bus Mode:
Data bus.
Transfers data between the host system and the
3PAC.
18
19
20
21
22
23
24
25
A0-A7 I Non-Multiplexed Bus Mode:
Address bus transfers addresses from the host system
to the 3PAC . For indirect address mode only A0 is
valid.
Multiplexed Bus Mode
Not used in multiplexed bus mode. In this case A0-A7
should directly be connect ed to VDD.
6RD
DS
I
I
Read
Ind icates a read access t o the re gister s (Intel bus
mode).
Data Strobe
The rising edge marks the end of a valid read or write
operation (Mot orola bus mode) .
5WR
R/W
I
I
Write
Ind icates a write access to the regist ers (Intel bus
mode).
Read/Write
A high level identifies a va lid host access as a read
operation and a low level identifies a vali d host access
as a write operation (Mot orola bus mode).
4CS
IChip Select
A LOW on this line selects the 3PA C for a read/ write
operation.
PSB 2113
Overview
Semiconductor Group 9 07.97
3 ALE I Address Latch Enable
A HIGH on this line indicates an address on the
external address/data bus (m ultiplexed bus type only).
ALE also select s the micr oproces sor interfac e type
(multiplexed or non multiplex ed).
2 INT OD Interrupt Request
This signal is activat ed when the 3PAC requests an
interrupt . It is an open dr ain output .
34 RES I/O Reset
A HIGH on this input forces the 3PAC into a reset state.
The minimum pulse length is four DCL-clock periods (if
oscil lator clock is settled) or four ms (i f oscillator is not
yet settled).
If the terminal specific functions are enabled, the 3PAC
may a lso supply a reset signal.
27 DRQTB O DMA Request Transmitter (channel B)
The trans mit ter of the 3PAC reques ts DMA data
transf er by activ ating this line.
The DRQ TB remains HI GH as long as the transm it
FIFO requires data transfer.
The amount of data byt es to be trans ferred from
syst em mem ory to the 3PAC (= byte count) must be
written firs t to the XBCH, XBC L reg ister.
Always blocks o f data (n x 64 bytes + REST , n=0, 1, . .)
are transf erred till the byte count is reached.
DRQTB is deactivated immediately following the falling
edge of the last WR cycle.
28 DRQRB O DM A Request Receiver (channel B)
The receiver of the 3PAC requests DMA data transf er
by activat in g this line.
The DRQ RB rem ain s HIG H as long as the receive
FIFO requires data transfer, thus always blocks of data
(64, 32 , 16, 8 or 4 bytes) are transf erred.
DRQRB is deactivated immediately following the falling
edge of the last read c ycle.
Pin No . Symbo l I npu t (I )
Output (O) Function
PSB 2113
Overview
Semiconductor Group 10 07.97
30 DACKB I DMA Acknowledge (chan nel B)
When LO W, this input signal from the DM A controller
indicates to the 3P AC, that the req uested DMA cy cle
controlled via DRQTB and DRQRB is in progress, i.e.
the DMA control ler has achieved bus mastership from
the CPU and will s tart data transfer cycles (either read
or write).
Together with RD, if DMA has been requested from the
receiver, or with WR, i f DMA has been requested from
the transm itter, this inpu t works like CS to enable a
data byte to be read from or writt en to the top of th e
receive or transmit FIFO of the spec ified channel.
If DACKB is active, the input on pins A0-7 is ign ored
and the FIFO ’s are impl icitly selected.
If the DACKB signals are not used, these pins must be
connected to VDD.
Auxi liary Interface
64 AUX0 I/O • PCM interf ace enab led:
FBOUT (output) - FSC/BCL Output
This pin is programmable to output either an FSC clock
which is derived from the DCL input divided by 192 or
a single bit clock fro m the IOM-2 interf ace, especially
to serve non IO M-2 compat ible periphe ral devices on
the PCM interface.
• PCM interface di sab led:
AUX0 (input/output)
If the PCM interf ace is switc hed off, this pin is
programmable as general input/output. The state of the
pin can be read from (input ) / written to (output) a
register.
Pin No . Symbo l I npu t (I )
Output (O) Function
PSB 2113
Overview
Semiconductor Group 11 07.97
63 AUX1 I/O • PCM interf ace enab l ed:
PCMI N (input ) - PCM Data Inp u t
On this line the 3PAC rec eives 8-bit dat a, which is
transm itted from a peripheral device. This data is
mapped to a B-channel timeslot on IOM-2.
• PCM interface di sab led:
AUX1 (input/output)
If the PCM interf ace is switc hed off, this pin is
programmable as general input/output. The state of the
pin can be read from (input ) / written to (output) a
register.
62 AUX2 I/O • PCM interf ace enab led:
PCMOUT (output) - PCM Data Output
On this line the 3PAC t ransm its 8-bit data, which is
received by a peripheral device. This data is taken from
a B-channel times lot on IOM-2 .
• PCM interface di sab led:
AUX2 (input/output)
If the PCM interf ace is switc hed off, this pin is
programmable as general input/output. The state of the
pin can be read from (input ) / written to (output) a
register.
61
62 AUX3
AUX4 I/O INT0/1
These pins are programmable as general input/output.
The state of the pins can be read from (input) / written
to (output) a register.
Add itionally, as inputs they can generat e a mask ab le
interrupt to the host, which is either edge or level
triggered. An internal pu ll up r esist or is connect ed to
these p in s.
As outputs an LED with pre-resistance can directly be
connected to these pins.
Pin No . Symbo l I npu t (I )
Output (O) Function
PSB 2113
Overview
Semiconductor Group 12 07.97
IOM-2 Interface
53 FSC I Frame Syn c
Synchr o nisation signal. The rising edge indicates the
beginning of the IOM f ram e (HIGH during channel 0).
54 DCL I Data Clock
IOM clock signal of twice the IO M data rate. Rising
edge is used to transmit data, 2nd falli ng edge is used
to sample data.
51 DU I/O(OD) Data Upstream
IOM data signal in upstream direction.
52 DD I/O (OD) Data Downstream
IOM data signal in downstream direct ion.
50 CLKO O Clock Output
At pin CLKO a clock equal to DCL/2 is provided.
59 SDS O Serial Data Strobe
Program mable st robe signal, selecting e ither one or
two channels (8 or 16 bit strobe length) on the IOM-2
or PCM interf ac e.
General Control Functions
35 AMODE I Add ress Mode
Selects between direct and indirect regist er access.
A HIGH se lects indirect address mode and a LOW
selects the direct register acce ss.
31 CH0 I IOM-2 Channel Select 0
Together with CH1 and CH2, this pin selects one of
eight channels on the IOM-2 interface.
32 CH1 I IOM-2 Channel Select 1
Together with CH0 and CH2, this pin selects one of
eight channels on the IOM-2 interface.
33 CH2 I IOM-2 Channel Select 2
Together with CH0 and CH1, this pin selects one of
eight channels on the IOM-2 interface.
Pin No . Symbo l I npu t (I )
Output (O) Function
PSB 2113
Overview
Semiconductor Group 13 07.97
Note: OD = Open Drain
58 LDO O LED Outpu t
This p in funct ions as a programmable output .
An LED with pre-resistance may directly be connected
to LDO.
Power Supply
1
12
26
49
VDD I Power Supply Voltage +5V (+/- 5%)
7
17
39
55
VSS I Ground, 0V
Reserved Pins
36
37
38
TP I Test Pins
These pins are not used for normal operat ion.
They mus t be connect ed to GND.
29
41
43
44
45
56
res_h I Reserved High
These pins mus t be connect ed to VDD.
46
57 res_l I Reserved Low
These pins mus t be connect ed to VSS.
40
42
47
48
res_o O Reserved Open
These pins may be left not connected.
Pin No . Symbo l I npu t (I )
Output (O) Function
PSB 2113
Overview
Semiconductor Group 14 07.97
1.5 Functional Block Diagram
Figure 3
Block Diagram
PSB 2113
Overview
Semiconductor Group 15 07.97
1.6 System Integration
The 3PA C is suited for all host based applications.
ISDN PC Adapter Card for U Interface
An ISDN adapter card which supports the U interface (2B1Q line coding), especially
required in the Northamerican market, may be realized using the 3PAC together with the
PSB 21911 IEC-Q TE (figure 4). The 3PAC provides two B-channel HDLC controllers
and another cont roller for the D-c hannel acces s.
Figure 4
ISDN PC Adapter Card for U Interface (2B1Q)
PSB 2113
Overview
Semiconductor Group 16 07.97
ISDN Voice/Data Terminal
Fig ure 5 shows a voice data terminal developed on a PC card, where the 3PAC provides
its functionality as a data controller within a three chip solution. During ISDN calls the
ARCOFI-SP PSB 2163 provides for speakerphone functions and includes a DTMF
generator. Additionally, a DTMF receiver or keypad may be connected to the auxiliary
interf ace of the 3PA C.
Figure 5
ISDN Voice/Data Terminal
PSB 2113
Overview
Semiconductor Group 17 07.97
ISDN Stan d- alone Termin al with POT S interf ac e
The 3PA C c an be integrate d in a microcon troller based stand-alone ter minal (fig u r e 6)
that is connected to the com munica tions int erfac e of a PC. The SI COFI 2-T E PSB 2132
enabl es connection of analog terminals (e.g. telephones or fax) to its dual channel POTS
interface.
Figure 6
ISDN Stan d- alone Termin al with POT S Interf ac e
PSB 2113
Overview
Semiconductor Group 18 07.97
Multiline PC-Adapter
Three U-interfaces can be combined via the IOM-2 interface using the PCM interface of
the 3PAC to transfer data in 6 B-channels. All three 3PACs exchange user data with the
data controller (e.g. a videocodec) via the PCM interface. The IEC-Q PEB 2091 is
configured to NT-PBX mode and an external PLL generates the FSC and DCL clocks for
all devices connected to the IOM-2 interface. The U-transceivers are programmed via
the IOM -2 MONIT OR channel (as show n in figure 7) or via the parallel host interface.
Figure 7
Multiline PC-Adapter
PSB 2113
Func tional Description
Semiconductor Group 19 07.97
2 Functional Description
The 3-Channel ISDN PC Adapter Circuit 3PAC provides reduced functi onality compared
with the well known IPAC PSB 2115. The S-transceiver is omitted, however besides the
layer-1 part the 3PAC provid es the same funct ionality.
This specification provides an overview on the funct iona l bloc ks of the 3 PAC, a detailed
description of these functional blocks can also be found in the data sheet of the IPAC
PSB 2115.
2.1 Operating Mo des
The HDLC controller of each B-channel and of the D-channel can be programmed to
operate in various modes, which are different in the treatment of the HDLC frame in
receive direct ion. Thus, the receive data f low and the address recog nition feat ures ca n
be effec ted in a very flexible way, which satisfies most requirements.
There are 4 different operating modes for the B-channels which can be set via the
MODEB register:
• Non-Auto Mode (MO DEB : MDS1, MDS0 = 01)
• Transparent Mode 1 (MODEB: MDS1, MDS 0, ADM = 101)
• Transparent Mode 0 (MODEB: MDS1, MDS 0, ADM = 100)
• Extended Transpar ent Modes 0; 1 (MO DEB: MDS1, MDS0 = 11)
5 d if ferent m odes which are s imilar as for the B-channels can be set for the D-c hannel
in the MOD ED regist er:
• Auto mode (MODED: MDS2, MDS1 = 00)
• Non-Auto Mode (MO DED: MDS 2, MDS1 = 01)
• Transparent Mode 1 (MODE D: MDS2, MDS1, MDS0 = 101)
• Transparent Mode 0 (MODE D: MDS2, MDS1, MDS0 = 110)
• Transparent Mode 0 (MODE D: MDS2, MDS1, MDS0 = 111)
The D-chann el cont roller s upports S /G-b it (stop/ go) evaluat ion and the TIC bu s ac cess
mechan ism if more than one D-channel sourc e is connected.
Two C/I channel handler are used to convey commands and indications between the
layer-2 function and a layer-1 device (C/I0) and to exchange real time status information
between th e 3PAC and various non layer-1 devices (C/ I1).
The MONITOR channel handler is used for information exchange between the 3PAC
and other devices attac hed to the IOM -2 interface.
PSB 2113
Func tional Description
Semiconductor Group 20 07.97
2.2 Hos t Interface
2.2. 1 Reg ister Set
The communication between the host and the 3PAC is done via a set of directly or
indirectly accessible 8-bit registers. The host sets the operating modes, controls function
sequences and gets status information by writing or reading these registers (Command/
Stat us tr ansf er).
Each of the two B-channels of the 3PAC is controlled via an equal, but totally
independent register file (channel A and channel B). Additional registers are available for
D- channel cont rol, the PCM and the Aux iliary interfa ce.
2.2. 2 Data Tran sfer M ode
Da ta trans fer betwe en the sy stem m emor y and the 3PA C f or bot h transm it an d receiv e
direction is controlled by either interrupts (Interrupt Mode), or independently from host
interact ion using the 3PA C’s 2-channel DMA interf ace (DM A Mode).
After RE SET , the 3PAC opera tes in Interrupt Mode, where data transfer mus t be do ne
by the host . The user se lects the DMA Mode by setting the DMA bit in a reg ister.
Only channel B can be operated either in Interrupt or DMA mode, channel A can only be
operated in Interrupt mode.
PSB 2113
Func tional Description
Semiconductor Group 21 07.97
2.2.3 Interrupt Interface
Special events in the 3PAC are indicated by means of a single interrupt output, which
request s the host to read status infor mation from t he 3PAC or transf er data from/ to the
3PAC.
Since only one INT request output is provided, the cause of an interrupt must be
determ ined by the host reading the 3PAC’s interrupt status regist ers.
The st ructure of the inte rrupt stat us regist ers is shown in fig ure 8.
Figure 8
3PAC In terrup t Status Reg ist e rs
PSB 2113
Func tional Description
Semiconductor Group 22 07.97
Two interrupt indications can be read directly from the ISTA register and another six
interrupt indications from separate interrupt status registers and extended interrupt
regi sters for the B-channels (ISTAA, EXIRA, ISTAB, EXIRB) and the D-channel (I STAD,
EXIRD).
After the 3PAC has requested an interrupt by setting its INT pin to low, the host must first
read the 3PAC interrupt status register (ISTA) in the associated interrupt service routine.
The six lowest order bits (bit 5-0) of I STA (ICD, EXD, ICA, EXA, ICB, EXB) point to those
registers in which the actual interrupt source is indicated. It is possible that several
interrupt sources are i ndicated referring to one interrupt request (e.g. if the ICA bit is set,
at least one interru pt is indicated in the IST A register of channel A).
An inte rrupt source f rom the g eneral I /O pins AUX3 and A UX4 of the aux i liary interfac e
is directly indicated in bits 6 and 7 of the ISTA register, therefore these bits must always
be checked.
The INT pin of the 3PAC remains active until all interrupt sources are cleared by reading
the corresponding in terrupt regi ster. Therefore it is possibl e that the INT pin is still active
when the interrupt service routine is finished.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupt s at the end of the interrupt service routine (writing FFH into the MASK reg ister)
and write back the old mask to the MA SK register.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register. Masked interrupt status bits are not
indicated when the status register is read, but they remain internally stored and pending
until the mask bit is reset.
PSB 2113
Func tional Description
Semiconductor Group 23 07.97
2.2. 4 DMA Inte rfa ce
The 3PAC comprises a 2-channel DMA interface (B-channel B with receive and transmit
direction) for fast and effective data transfer.
A separa te DMA Request Output f or transm it (DRQTB ) and receive direct ion (DRQ RB)
as well as a DMA Acknowledgm ent (DACK B) input is provided.
The 3PAC activates the DRQRB line as long as data transfer is needed from/to the
specif ic FIFO (level triggered demand trans fer mode of DMA contro ller).
It’s the respons ibility of the DM A controller to perf orm the correc t amount of bus cycles.
Either read cycles will be performed if the DMA transfer has been requested from the
receiver, or write cycles if DMA has been requested from the transmitter. If the DMA
contr oller provides a DMA acknow le dge signal (input t o the 3PA C’s DACK B pin), eac h
bus cycle implicitly select s the top of the FIFO and neither address (via A0-A 6) nor chi p
select need to be supplied (I/O to memory transfers). If no DACKB signal is supplied,
normal read/write operations (providing addresses) must be performed (memory to
me m ory tran sfe rs).
The 3PAC deactivates the DRQRB line immediately after the last read/write cycle of the
data tran sfer has start ed.
PSB 2113
Func tional Description
Semiconductor Group 24 07.97
2.2.5 Host Interface Operation
The 3P AC is programm ed via an 8-bit parallel m icroproc essor interfac e. Easy and fast
micropr ocess or acces s is provided by 8-bit address decoding on the chip.
At the 3PA C thr ee typ es of µP buses are provided (s ee table 1), which are s electe d via
pin ALE:
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
No te: If the multiplexe d address /dat a bus type (3) is selected, t he unused ad dress pins
A0-A7 mus t be tied to
V
DD
.
Table 1
Bus Operatio n Modes
( 1) A LE tied to VDD Motorola t ype with cont rol signals CS, R/W, DS
( 2) A LE tied to VSS Siemens/I ntel non-multi plexed bus type with control
signals CS, W R , R D
(3 ) E dge on ALE Siemens/Intel multiplexed address/dat a bus type with
control signals CS, WR, RD , ALE
PSB 2113
Func tional Description
Semiconductor Group 25 07.97
Re gister Ad dressi ng M odes
The 3PA C provides two diff erent ways to read and write its registers . The comm on way
is for non-multiplexed mode to set the register address to the address bus and then
acces s the reg ister location. In multiplexed mo de, the address on the address/ data bus
is latched in, before a read or write access to the register is performed. This mode is
select ed, if the addres s select mode pin AMO DE is set to 0.
As a second option, the 3PAC allows for indirect access of the registers (AMODE=1).
Only the LS B (A0) of the address line is us ed to select either the ADDRE SS register or
the DATA register. The host writes the register address to the ADDRESS register, before
it reads/writes data from/to the corresponding register location through the DATA
register. Figure 9 shows both register addressing modes.
Figure 9
In direct register ad dress mode
PSB 2113
Func tional Description
Semiconductor Group 26 07.97
2.3 Auxil iary Interf ace
The AUX interf ace provides for various, programmable fun ctions (see t abl e 2 ).
Two PCM receive and transmit lines are available for connection to other data controllers
(e.g. datapump, video processor). In this way non IOM compatible devices with standard
PCM interface can operate on any timeslot on the IOM-2 interface. A BCL output or FSC
output (for IOM-2 frame sync signal) is available which is derived from the DCL input by
an internal divider.
The PCM interface can be disabled, so AUX0-2 are available as general purpose I/O
pins. Two pins INT0 and INT 1 can be used as programm able I/O with optional interrupt
input capability .
AUX0-2
These pins can be used as programmable I/O lines. This function is multiplexed wi th the
PCM interface, i.e. the host can select either PCM functionality or standard I/O
charact erist ic on AUX0- 2.
As inputs the state at the pin is latched in when the host perfor mes a read operation.
As outpu ts the value of the corresponding regist er is driven on the p in s with a minimum
delay af ter the w rite operat ion to this register is perf ormed. They can be c onfigured as
ope n drain or push/pull outputs .
INT0, INT1
Two pins can be used as programmable I/O lines with optional interrupt input capability.
The INT 0/ 1 pins are general input or output pins like AUX0- 2 (see descript ion above).
In addi tion to that, as inputs they can generate an interrupt to the host which is maskable.
The interr upt input is either edge or level triggered.
As outputs both pins are able to sink IOL= 5 mA which allows for direct connection of
LEDs in standalone applicat ions for example.
Table 2
AUX pin f unc tions
Pin Function
AUX0 AUX0 / FB OUT
AUX1 AUX1 / PCMIN
AUX2 AUX2 / PCMOUT
AUX3 INT0
AUX4 INT1
PSB 2113
Func tional Description
Semiconductor Group 27 07.97
PCMIN, PCMOUT
PCMIN and PCMOUT are receive and transmit lines of the general PCM interface. If
ena b led, the B-c hannels on the IOM -2 interf ace can flexibly be switc hed to any tim eslot
of the PCM interface.
If the PCM Interf ace is not used, these pins serve as general I/O pins.
FBOUT (FSC/BCL Output)
This pin can be programm ed to one of two possib le functions :
• FSC Output:
An FSC clock is output which is derived from the DCL input divided by 192. This is
especially suitable for multiline applications, where one of several IPACs generates
the common F SC.
• BCL Output :
The pin can output a single bit clock (DCL input divided by 2) equal to the IOM-2 data
rate, especially to serve non IOM-2 compatible peripheral devices on the PCM
interface.
If the PCM Interf ace is not used, this pin serves as a general I/O pin.
PSB 2113
Func tional Description
Semiconductor Group 28 07.97
2.4 PCM Interface
The 3PA C provides a PCM interf ace that can be disabled, so that the PCM pins can be
used as general I/O pins (see previous ch ap ter 2.3).
Throu gh its standar d PCM interface t he 3PAC can be connect ed to devices in gen eral
TDM (time division multiplex) sys tem s. In this way dat a controllers , which are not
IOM-2 compatible, can indirectly be connected to the IOM-2 interface, since the
programmed PCM timeslots are reflected in the corresponding IOM-2 B-channel
timeslots.
The data and signal lines to be used with the PCM interface depend on the mode of
ope ration and the ty pe of interface of the external device:
The frame sync signal FSC and the data clock DCL which are used on the IOM-2
interf ace a lso serve as th e referenc e clocks on the PCM interf ace.
PCMIN Receive Data:
The 3PAC receives dat a from a peripheral device on PCMIN. The
rece ived data is t hen mapp ed to a B-channel on the IOM-2 interf ace.
PC MOU T T ransm it Data:
The 3PAC transmits data to a peripheral device on PCMOUT. This
data is originated from a B-channel on the IOM- 2 interfac e.
FSC Frame Sync:
FSC is used on the IOM-2 interface to indicate the beginning of a new
IOM -2 frame. It is also us ed for the PCM interf ace t o mark the
beginning of new frame.
DCL Bit Cloc k (double rate):
DCL is the reference cloc k accord ing to which data is written to
PCMO UT and read from PCMI N. For peripheral devices support ing
double rate bit clock, the clock signal is directly provided by t he system.
DCL is the same clock as used for the IOM- 2 interfac e.
BCL
(FBOUT) Bit Clock (single rate):
For peripheral devices supporting single rate bit clock, the clock si gnal
is provided at FBOUT. It is derived from the system clock by an internal
divider (division by 2).
FSC
(FBOUT) Frame Sync:
The frame sync signal is mul tiplexed with BCL (see above) and output
at FBOUT . It is derived from the system clock by an internal divider
(division by 192).
PSB 2113
Func tional Description
Semiconductor Group 29 07.97
The PCM interface can be used to build a connection between non IOM-2 compatible
voice/ data controllers and the IOM -2 interf ace in order t o t ransfer B- channel data from/
to the external device. Receive data on the DD line can be mapped to any timeslot on
the PCMOUT line. Data recei ved from the external device on any timeslot on PCMIN can
be mapped to the DU line (see fi gure 1 0).
Data which is received on PCMIN is forwarded to the DU line with the next IOM-2 frame.
Similar for the opposite d irect ion , data on DD is forwarded to the PCMO UT line with th e
next FSC frame.
Figure 10
Sw itc hin g Data betw een PCM an d IOM -2
For test purposes data on PCMIN can be mapped to DD and B-channel data on DU can
be mapped to PCM O UT.
PSB 2113
Electri cal Ch aracteristi c s
Semiconductor Group 30 07.97
3 Electrical Ch aracteristics
Note: Maximum ratings are absolute ratings; exceeding only one of these values may
cause irrevers ible damage to the integrated circuit .
3.2 DC-Characteristics
No te: The list ed charact eristics are ensured over the operating ra nge of the integrat ed
circu it . Typica l char acterist ic s specify mean values expect ed over the product ion
spread. If not otherwis e spe cified, typical charac teristics apply at
T
A
= 25
°
C and
the given supply v oltage.
3.1 Absolute Maximum Ratings
Paramete r Symb ol Limit Values Unit
Ambient temperature under bias: TA0 to 70 °C
Storage temperature Tstg − 65 to 150 °C
Voltage on any pin with respect to ground VS− 0.3 to VDD + 0. 3 V
Maxim um volt age on any pin Vmax 7V
Paramete r Symb ol Limit Values Unit Cond itio n
min. max.
L-inp ut voltage VIL -0.3 0.8 V (a ll pins except XTAL1/ 2)
H- input volt age VIH 2.0 VDD + 0 .3 V
L-output voltage VOL 0.45 V IOL= 7 mA (DU, DD)
IOL= 5 mA (LDO, AUX3, 4,
AD0-7)
IOL= 2 mA (all others)
H-outpu t voltage VOH 2.4 V IOH= - 5 m A (AD0-7)
IOH= - 400 µA (all others)
VDD - 0.5 V IOH= -100 µA
Power supply
current -
power down
ICC 3mAV
DD = 5V,
Inputs at VDD/VDD ,
No output loads,
DCL = 1536 kHz
Power supply
current -
operational
19 mA
PSB 2113
Package O utlin es
Semiconductor Group 31 07.97
4 Package O utlines
P-MQFP-64
(Plas tic M etric Quad Flat Package)
GPM05247
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Pa ckage Information”. Dimensions in mm
SMD = Surface Mounted Device
PSB 2113
Package O utlin es
Semiconductor Group 32 07.97
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Pa ckage Information”. Dimensions in mm
SMD = Surface Mounted Device
P-TQFP-64
(Plas tic Thin Quad F lat Pack age)
GPM05613
