DDR SDRAM 256Mb F-die (x16) DDR SDRAM 256Mb F-die DDR400 SDRAM Specification 60Ball FBGA (x16) Revision 1.0 Rev. 1.0 August. 2003 DDR SDRAM 256Mb F-die (x16) DDR SDRAM 256Mb F-die Revision History Revison 1.0 (August. 2003) 1. First release Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Key Features * 200MHz Clock, 400Mbps data rate. * VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Four banks operation * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock(CK) * Data I/O transactions on both edges of data strobe * Edge aligned data output, center aligned data input * LDM,UDM for write masking only (x16) * Auto & Self refresh * 7.8us refresh interval(8K/64ms refresh) * Maximum burst refresh cycle : 8 * 60Ball FBGA Package Ordering Information Part No. Org. K4H561638F-GCCC K4H561638F-GCC4 16M x 16 Max Freq. CC(DDR400@CL=3) Interface Package SSTL2 60 FBGA C4(DDR400@CL=3) Operating Frequencies - CC(DDR400@CL=3) - C4(DDR400@CL=3) Speed @CL3 200MHz 200MHz CL-tRCD-tRP 3-3-3 3-4-4 *CL : CAS Latency Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Pin Description 16M x 16 1 VSSQ DQ14 DQ12 DQ10 DQ8 VREF 2 DQ15 VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4 3 VSS DQ13 DQ11 DQ9 UDQS UDM CK CKE A9 A7 A5 VSS A B C D E F G H J K L M 7 VDD DQ2 DQ4 DQ6 LDQS LDM WE RAS BA1 A0 A2 VDD 8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3 9 VDDQ DQ1 DQ3 DQ5 DQ7 NC Organization Row Address Column Address 16Mx16 A0~A12 A0-A8 DM is internally loaded to match DQ and DQS identically. Row & Column address configuration Package Physical Dimension ( Unit : mm ) 0.10 Max 8.00 0.10 0.80 x 8 = 6.40 ENCAPSULANT AREA 0.80 x 4 = 3.20 1.60 1.60 8.0 0 0.10 9 8 7 6 5 4 3 2 1 0.80 1.00 A B 0.50 5.50 G 0.45 0.05 H J 14.00 0.10 F 1.00 x 11 = 11.00 0.50 E 14.0 0.10 14.00 0.10 D 5.50 C K L M 0.35 0.05 60 - 0.45 TOP VIEW (0.90) (0.90) 0.05 (1.80) 1.10 0.10 BOTTOM VIEW 60Ball FBGA Package Dimension Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Block Diagram (8Mb x 8 / 4Mb x 16 I/O x 4 Banks) CK, CK (L)WE I/O Control 16 Data Input Register L(U)DM Serial to parallel Bank Select 32 2Mx32 16 Output Buffer 2Mx32 32 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADD Address Register CK, CK 2Mx32 x16 DQi 2Mx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe Gen. DLL Programming Register Data Strobe LCKE LRAS LCBR LWE L(U)DM LCAS CK, CK CKE CS RAS LWCBR CK, CK Timing Register DM Input Register CAS L(U)DM WE Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Input/Output Function Description SYMBOL TYPE DESCRIPTION CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. LDM,(UDM) Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or floating during READs. BA0, BA1 Input Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. A [0 : 12] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). A12 & A13 are used on device densities of 256Mb and greater, and A13 is used only on 1Gb decices. DQ I/O Data Input/Output : Data bus LDQS,(U)DQS I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15 NC - VDDQ Supply DQ Power Supply : +2.6V 0.1V. VSSQ Supply DQ Ground. VDD Supply Power Supply : +2.6V 0.1V (device specific). VSS Supply Ground. VREF Input No Connect : No internal electrical connection is present. SSTL_2 reference voltage. Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Command Truth Table (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) COMMAND Register Register CKEn-1 CKEn Extended MRS H Mode Register Set H Auto Refresh Refresh Entry Self Refresh Exit Bank Active & Row Addr. Read & Column Address Auto Precharge Disable Write & Column Address Auto Precharge Disable WE X L L L L OP CODE 1, 2 X L L L L OP CODE 1, 2 L L L H X L L H H X L H H H H X X X L L H H V L H L H V H X L H L L V H X L H H L H X L L H L Entry H L H X X X L V V V Exit L H X X X X Entry H L Exit L H Bank Selection All Banks Precharge Power Down Mode DM(UDM/LDM for x16 only) H No operation (NOP) : Not defined H H X X X L H H H H X X X L V V V X X X X X L H H H 3 3 3 Row Address L Column Address H L Column Address H X V L X H 4 4 4 4, 6 7 X 5 X X X H Note 3 X X Auto Precharge Enable Active Power Down CAS H Auto Precharge Enable Burst Stop Precharge H RAS H BA0,1 A10/AP A0 ~ A9, A11, A12 CS X 8 9 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) 4M x 16Bit x 4 Banks Double Data Rate SDRAM General Description The K4H560838F / K4H561638F is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 8 / 16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 1.5 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Supply voltage(for device with a nominal VDD of 2.5V) Symbol Min Max VDD 2.5 2.7 Unit Note 5 I/O Supply voltage VDDQ 2.5 2.7 V 5 I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 VIH(DC) VREF+0.15 VDDQ+0.3 V Input logic high voltage Input logic low voltage VIL(DC) -0.3 VREF-0.15 V Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Input leakage current IOH -16.8 Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V mA IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Note : 1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 5. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV. Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) DDR SDRAM Spec Items & Test Conditions Conditions Symbol Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; CS = high between valid commands. IDD0 Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition; CS = high between valid commands. IDD1 Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=5ns for DDR400; Vin = Vref for DQ,DQS and DM. IDD2P Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM IDD2Q Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=5ns DDR400; Vin = Vref for DQ,DQS and DM IDD3P Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3N Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=3 at 5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A IDD4R Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=3 at tCK=5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every transfer IDD4W Auto refresh current; tRC = tRFC(min) - 14*tCK for DDR400 at tCK=5ns; IDD5 Self refresh current; CKE =< 0.2V; External clock on; tCK = 5ns for DDR400. IDD6 Input/Output Capacitance Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) (VDD=2.6, VDDQ=2.6V, TA= 25C, f=1MHz) Symbol Min Max Delta Unit Note CIN1 1.5 2.5 0.5 pF 4 0.25 pF 4 pF 1,2,3,4 pF 1,2,3,4 Input capacitance( CK, CK ) CIN2 1.5 2.5 Data & DQS input/output capacitance COUT 3.5 4.5 Input capacitance(DM for 8, UDM/LDM for x16) CIN3 3.5 4.5 0.5 Note : 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system. 3. Unused pins are tied to ground. 4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25C, Vout(dc) = VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) DDR SDRAM IDD spec table Symbol (VDD=2.7V, T = 10C) 16Mx16 - CC(DDR400@CL=3) - C4(DDR400@CL=3) Unit IDD0 110 105 mA IDD1 150 145 mA mA IDD2P 4 4 IDD2F 30 30 mA IDD2Q 25 25 mA IDD3P 55 55 mA IDD3N 75 75 mA IDD4R 220 220 mA IDD4W 250 250 mA IDD5 200 200 mA mA IDD6 Normal 3 3 Low power 1.5 1.5 mA 380 380 mA IDD7A Notes Optional < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle. Iout = 0mA 2. Timing patterns - CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK Setup : A0 N N R0 N N N N P0 N N Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer IDD7A : Operating current: Four bank operation 1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing. Iout = 1mA 2. Timing patterns - CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) AC Operating Conditions Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals Parameter/Condition VIH(AC) VREF + 0.31 Max-10 Unit Note Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 V VREF - 0.31 V Notes : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. AC Overshoot/Undershoot specification for Address and Control Pins Parameter Specification DDR400 Maximum peak amplitude allowed for overshoot 1.5V Maximum peak amplitude allowed for undershoot 1.5V The area between the overshoot signal and VDD must be less than or equal to 4.5V-ns The area between the undershoot signal and GND must be less than or equal to 4.5V-ns VDD Overshoot 5 Maximum Amplitude = 1.5V 4 3 Volts (V) 2 Area = 4.5V-ns 1 0 -1 -2 -3 Maximum Amplitude = 1.5V GND -4 -5 0 0.6875 1.5 2.5 3.5 4.5 5.5 6.3125 7.0 0.5 1.0 2.0 3.0 4.0 5.0 6.0 6.5 Tims(ns) undershoot AC overshoot/Undershoot Definition Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Specification Parameter DDR400 Maximum peak amplitude allowed for overshoot 1.2V Maximum peak amplitude allowed for undershoot 1.2V The area between the overshoot signal and VDD must be less than or equal to 2.5V-ns The area between the undershoot signal and GND must be less than or equal to 2.5V-ns VDDQ Overshoot 5 Maximum Amplitude = 1.2V 4 3 Volts (V) 2 1 Area = 2.5V-ns 0 -1 -2 -3 Maximum Amplitude = 1.2V GND -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 Tims(ns) undershoot DQ/DM/DQS AC overshoot/Undershoot Definition Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) AC Timing Parameters and Specifications Parameter Symbol Row cycle time - CC(DDR400@CL=3) Min Max - C4(DDR400@CL=3) Min tRC 55 Refresh row cycle time tRFC 70 Row active time tRAS 40 RAS to CAS delay tRCD 15 18 Row precharge time Row active to Row active delay Write recovery time Internal write to read command delay Clock cycle time CL=3.0 CL=2.5 Clock high level width Clock low level width Max 60 ns 40 70K ns ns tRP 15 18 ns tRRD 10 10 ns tWR 15 15 ns tWTR 2 2 tCK tCK tCH 5 10 5 10 ns 6 12 6 12 ns 0.45 0.55 0.45 0.55 tCK tCL 0.45 0.55 0.45 0.55 tCK tDQSCK -0.55 +0.55 -0.55 +0.55 ns Output data access time from CK/CK tAC -0.65 +0.65 -0.65 +0.65 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.4 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK 1.28 0.72 1.28 tCK DQS-out access time from CK/CK CK to valid DQS-in tDQSS 0.72 tWPRES 0 Write preamble tWPRE 0.25 Write postamble tWPST 0.4 tDSS 0.2 Write preamble setup time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time 0 ps 0.25 0.6 Note ns 70 70K Unit 16 13 5 tCK 0.4 0.6 0.2 tCK 4 tCK tDSH 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 tCK tIS 0.6 0.6 ns h,7~10 Address and Control Input hold time tIH 0.6 ns h,7~10 Data-out high impedence time from CK/CK tHZ - tAC max - tAC max ns 3 tAC max tAC min tAC max ns 3 Address and Control Input setup time 0.6 tLZ tAC min tMRD 2 2 tCK DQ & DM setup time to DQS, slew rate 0.5V/ns tDS 0.4 0.4 ns i, j DQ & DM hold time to DQS, slew rate 0.5V/ns tDH 0.4 0.4 ns i, j tDIPW 1.75 1.75 ns 9 Control & Address input pulse width for each input tIPW 2.2 Refresh interval time tREFI Data-out low impedence time from CK/CK Mode register set cycle time DQ & DM input pulse width 2.2 7.8 ns 9 7.8 us 6 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - ns 12 Clock half period tHP min tCH/tCL - min tCH/tCL - ns 11, 12 Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) Parameter Symbol Data hold skew factor tQHS Auto Precharge write recovery + precharge time tDAL - CC(DDR400@CL=3) Min Max - C4(DDR400@CL=3) Min 0.5 - Exit self refresh to non-READ command tXSNR 75 Exit self refresh to READ command tXSRD 200 - - - 200 Unit Note 0.5 ns 12 - ns 14 ns 15 - tCK Max 75 Component Notes 1.VID is the magnitude of the difference between the input level on CK and the input level on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 7. For command/address input slew rate 0.5 V/ns 8. For CK & CK slew rate 0.5 V/ns 9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 10. Slew Rate is measured between VOH(ac) and VOL(ac). 11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 12. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 13. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 14. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400(CC) at CL=3 and tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}CLK tDAL = 6 clocks 15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK 16. The only time that the clock frequency is allowed to change is during self-refresh mode. Rev. 1.0 August. 2003 DDR SDRAM DDR SDRAM 256Mb F-die (x16) System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS DDR400 PARAMETER SYMBOL MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW 0.5 4.0 V/ns a, k Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate tIS tIH Units Notes 0.5 V/ns 0 0 ps h 0.4 V/ns +50 0 ps h 0.3 V/ns +100 0 ps h Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate tDS tDH Units 0.5 V/ns 0 0 ps Notes j 0.4 V/ns +75 +75 ps j 0.3 V/ns +150 +150 ps j Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate tDS tDH Units Notes i +/- 0.0 V/ns 0 0 ps +/- 0.25 V/ns +50 +50 ps i +/- 0.5 V/ns +100 +100 ps i Table 5 : Output Slew Rate Characteristice (X8 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR400 MIN MAX Notes - - e,k Rev. 1.0 August. 2003 DDR SDRAM 256Mb F-die (x16) DDR SDRAM System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Test point Output 50 VSSQ Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. VDDQ 50 Output Test point Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. For Maximum slew rate, only one DQ is switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.6V, typical process Minimum : 70 C (T Ambient), VDDQ = 2.5V, slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. Rev. 1.0 August. 2003 DDR SDRAM 256Mb F-die (x16) DDR SDRAM j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotony. Rev. 1.0 August. 2003