Datasheet RL78/L13 R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 RENESAS MCU Integrated LCD controller/driver, True Low Power Platform (as low as 112.5 A/MHz, and 0.61 A for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 128 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications 1. OUTLINE <R> 1.1 Features Ultra-low power consumption technology * VDD = single power supply voltage of 1.6 to 5.5 V which can operate a 1.8 V device at a low voltage * HALT mode * STOP mode * SNOOZE mode Serial interface * CSI: 2 channels * UART/UART (LIN-bus supported): 3, 4 channels/1 channel * I2C/Simplified I2C communication: 1 channel/2 channels RL78 CPU core * CISC architecture with 3-stage pipeline * Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed onchip oscillator) to ultra-low speed (30.5 s: @ 32.768 kHz operation with subsystem clock) * Address space: 1 MB * General-purpose registers: (8-bit register x 8) x 4 banks * On-chip RAM: 1 to 8 KB Code flash memory * Code flash memory: 16 to 128 KB * Block size: 1 KB * Prohibition of block erase and rewriting (security function) * On-chip debug function * Self-programming (with boot swap function/flash shield window function) Data flash memory * Data flash memory: 4 KB * Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. * Number of rewrites: 1,000,000 times (TYP.) * Voltage of rewrites: VDD = 1.8 to 5.5 V High-speed on-chip oscillator * Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz * High accuracy: +/-1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85C) Operating ambient temperature * TA = -40 to +85C (A: Consumer applications) * TA = -40 to +105C (G: Industrial applications) Power management and reset function * On-chip power-on-reset (POR) circuit * On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels) DMA (Direct Memory Access) controller * 4 channels * Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks Multiplier and divider/multiply-accumulator * 16 bits x 16 bits = 32 bits (Unsigned or signed) * 32 bits / 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) Timer * 16-bit timer: 8 channels (with remote control output function) * 16-bit timer KB20 (IH): 1 channel (IH-only PWM output function) * 12-bit interval timer: 1 channel * Real-time clock 2: 1 channel (calendar for 99 years, alarm function, and clock correction function) * Watchdog timer: 1 channel (operable with the dedicated lowspeed on- chip oscillator) A/D converter * 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V) * Analog input: 9 to 12 channels * Internal reference voltage (1.45 V) and temperature sensorNote 1 Comparator * 2 channels * Operation mode: Comparator high-speed mode, comparator low-speed mode, or window mode * External reference voltage and internal reference voltage are selectable LCD controller/driver * Segment signal output: 36 (32)Note 2 to 51 (47)Note 2 * Common signal output: 4 (8)Note 2 * Internal voltage boosting method, capacitor split method, and external resistance division method are switchable I/O port * I/O port: 49 to 65 (N-ch open drain I/O [withstand voltage of 6 V]: 2, N-ch open drain I/O [VDD withstand voltage]: 12 to 18) * Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor * Different potential interface: Can connect to a 1.8/2.5/3 V device * On-chip key interrupt function * On-chip clock output/buzzer output controller Others * On-chip BCD (binary-coded decimal) correction circuit Notes 1. Can be selected only in HS (high-speed main) mode 2. The values in parentheses are the number of signal outputs when 8 com is used. Remark The functions mounted depend on the product. See 1.6 Outline of Functions. * There are differences in specifications between every product. Please refer to specification for details. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 1 of 123 RL78/L13 1. OUTLINE ROM, RAM capacities Flash ROM Data Flash RAM 128 KB 4 KB 96 KB 4 KB 6 KB 64 KB 4 KB 4 KB R5F10WLE R5F10WME 48 KB 4 KB 2 KB R5F10WLD R5F10WMD 32 KB 4 KB 1.5 KB R5F10WLC R5F10WMC 16 KB 4 KB 1 KB R5F10WLA R5F10WMA 8 KB Note RL78/L13 64 pins 80 pins R5F10WLG R5F10WMG R5F10WLF R5F10WMF Note This is about 7 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/L13 User's Manual.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 2 of 123 RL78/L13 1. OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/L13 Part No. R 5 F 1 0 W L E A x x x F B #30 Packaging specification #30 : Tray (LFQFP, LQFP) #50 : Embossed Tape (LFQFP, LQFP) Package type: FA : LQFP, 0.65 mm pitch FB : LFQFP, 0.50 mm pitch ROM number (Omitted with blank products) Fields of application: A : Consumer applications, TA = -40C to +85C G : Industrial applications, TA = -40C to +105C ROM capacity: A : 16 KB C : 32 KB D : 48 KB E : 64 KB F : 96 KB G : 128 KB Pin count: L : 64-pin M : 80-pin RL78/L13 group Memory type: F : Flash memory Renesas MCU Renesas semiconductor product R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 3 of 123 RL78/L13 Pin Count 1. OUTLINE Package Data Flash Fields of Ordering Part Number ApplicationNote 64 pins 64-pin plastic LQFP Mounted A R5F10WLAAFA#30, R5F10WLAAFA#50, R5F10WLCAFA#30, (12 x 12 mm, 0.65 R5F10WLCAFA#50, R5F10WLDAFA#30, R5F10WLDAFA#50, mm pitch) R5F10WLEAFA#30, R5F10WLEAFA#50, R5F10WLFAFA#30, R5F10WLFAFA#50, R5F10WLGAFA#30, R5F10WLGAFA#50 64-pin plastic LFQFP Mounted A R5F10WLAAFB#30, R5F10WLAAFB#50, R5F10WLCAFB#30, (10 x 10 mm, 0.5 R5F10WLCAFB#50, R5F10WLDAFB#30, R5F10WLDAFB#50, mm pitch) R5F10WLEAFB#30, R5F10WLEAFB#50, R5F10WLFAFB#30, R5F10WLFAFB#50, R5F10WLGAFB#30, R5F10WLGAFB#50, G R5F10WLAGFB#30, R5F10WLAGFB#50, R5F10WLCGFB#30, R5F10WLCGFB#50, R5F10WLDGFB#30, R5F10WLDGFB#50, R5F10WLEGFB#30, R5F10WLEGFB#50, R5F10WLFGFB#30, R5F10WLFGFB#50, R5F10WLGGFB#30, R5F10WLGGFB#50 80 pins 80-pin plastic LQFP Mounted A R5F10WMAAFA#30, R5F10WMAAFA#50, R5F10WMCAFA#30, (14 x 14 mm, 0.65 R5F10WMCAFA#50, R5F10WMDAFA#30, R5F10WMDAFA#50, mm pitch) R5F10WMEAFA#30, R5F10WMEAFA#50, R5F10WMFAFA#30, R5F10WMFAFA#50, R5F10WMGAFA#30, R5F10WMGAFA#50 80-pin plastic LFQFP Mounted A R5F10WMAAFB#30, R5F10WMAAFB#50, R5F10WMCAFB#30, (12 x 12 mm, 0.5 R5F10WMCAFB#50, R5F10WMDAFB#30, R5F10WMDAFB#50, mm pitch) R5F10WMEAFB#30, R5F10WMEAFB#50, R5F10WMFAFB#30, R5F10WMFAFB#50, R5F10WMGAFB#30, R5F10WMGAFB#50, G R5F10WMAGFB#30, R5F10WMAGFB#50, R5F10WMCGFB#30, R5F10WMCGFB#50, R5F10WMDGFB#30, R5F10WMDGFB#50, R5F10WMEGFB#30, R5F10WMEGFB#50, R5F10WMFGFB#30, R5F10WMFGFB#50, R5F10WMGGFB#30, R5F10WMGGFB#50 Note For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/L13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 4 of 123 RL78/L13 1. OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 64-pin products * 64-pin plastic LQFP (12 x 12 mm, 0.65 mm pitch) P03/RxD2/SEG46/VCOUT0 P04/TxD2/SEG47/VCOUT1 P05/SCK10/SCL10/SEG48 P06/SI10/RxD1/SDA10/SEG49 P07/SO10/TxD1/(PCLBUZ0)/SEG50 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P52/TI00/TO00/INTP1/SEG6 P53/INTP2/SEG7 P54/TI02/TO02/SEG8 * 64-pin plastic LFQFP (10 x 10 mm, 0.5 mm pitch) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P02/INTP7/PCLBUZ0/SEG45 P01/(TI05)/(TO05)/INTP5/PCLBUZ1/SEG44 P00/SEG43/SO00/TxD0/TOOLTxD P17/SEG42/SI00/RxD0/TOOLRxD/SDA00 P16/SEG41/SCK00/SCL00 P15/TI07/TO07/SEG40 P14/TI04/TO04/SEG39 P13/ANI25/SEG38 P12/ANI24/SEG37 P11/ANI23/SEG36 P10/ANI22/SEG35 P27/ANI21/SEG34 P26/ANI20/SEG33 P22/ANI16/SEG29 P21/ANI0/AVREFP P20/ANI1/AVREFM 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RL78/L13 (Top View) 1 2 3 4 5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P57/INTP6/SEG11 P70/KR0/SEG12 P74/KR4/SEG16/TKBO00 P75/KR5/SEG17/TKBO01-2 P76/KR6/SEG18/TKBO01-1 P77/KR7/SEG19/TKBO01-0 P30/TI03/TO03/SEG20/REMOOUT P31/INTP3/RTC1HZ/SEG21 P32/TI01/TO01/SEG22 P33/INTP4/SEG23 P125/VL3/TI06/TO06 VL4 VL2 VL1 P126/CAPL/(TI04)/(TO04) P127/CAPH/(TI03)/(TO03)/(REMOOUT) 6 7 8 9 10 11 12 13 14 15 16 P45/VREF0 P44/(SCK10)/(SCL10)/IVCMP0 P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP1 P42/TI05/TO05/(SO10)/(TxD1)/IVREF1 P40/TOOL0/(TI00)/(TO00) RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0/(TI01)/(TO01) P61/SDAA0/(TI02)/(TO02) <R> Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/L13 User's Manual. . R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 5 of 123 RL78/L13 1.3.2 80-pin products * 80-pin plastic LQFP (14 x 14 mm, 0.65 mm pitch) P04/TxD2/SEG47/VCOUT1 P05/SCK10/SCL10/SEG48 P06/SI10/RxD1/SDA10/SEG49 P07/SO10/TxD1/(PCLBUZ0)/SEG50 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P50/SEG4 P51/SEG5 P52/TI00/TO00/INTP1/SEG6 P53/INTP2/SEG7 P54/TI02/TO02/SEG8 P55/INTP5/SEG9 P56/TI06/TO06/SEG10 P57/INTP6/SEG11 * 80-pin plastic LFQFP (12 x 12 mm, 0.5 mm pitch) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P03/RxD2/SEG46/VCOUT0 P02/INTP7/PCLBUZ0/SEG45 P01/(TI05)/(TO05)/(INTP5)/PCLBUZ1/SEG44 P00/SEG43/SO00/TxD0/TOOLTxD P17/SEG42/SI00/RxD0/TOOLRxD/SDA00 P16/SEG41/SCK00/SCL00 P15/TI07/TO07/SEG40 P14/TI04/TO04/SEG39 P13/ANI25/SEG38 P12/ANI24/SEG37 P11/ANI23/SEG36 P10/ANI22/SEG35 P27/ANI21/SEG34 P26/ANI20/SEG33 P25/ANI19/SEG32 P24/ANI18/SEG31 P23/ANI17/SEG30 P22/ANI16/SEG29 P21/ANI0/AVREFP P20/ANI1/AVREFM 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RL78/L13 (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P70/KR0/SEG12 P71/KR1/SEG13 P72/KR2/SEG14 P73/KR3/SEG15 P74/KR4/SEG16/TKBO00 P75/KR5/SEG17/TKBO01-2 P76/KR6/SEG18/TKBO01-1 P77/KR7/SEG19/TKBO01-0 P30/TI03/TO03/SEG20/REMOOUT P31/INTP3/RTC1HZ/SEG21 P32/TI01/TO01/SEG22 P33/INTP4/SEG23 P34/RxD3/SEG24 P35/TxD3/SEG25 P125/VL3/(TI06)/(TO06) VL4 VL2 VL1 P126/CAPL/(TI04)/(TO04) P127/CAPH/(TI03)/(TO03)/(REMOOUT) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P130/(SO00)/(TxD0)/SEG28 P47/(SI00)/(RxD0)/(SDA00)/SEG27 P46/(SCK00)/(SCL00)/SEG26 P45/IVREF0 P44/(SCK10)/(SCL10)/IVCMP0 P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP1 P42/TI05/TO05/(SO10)/(TxD1)/IVREF1 P41/(TI07)/(TO07) P40/TOOL0/(TI00)/(TO00) RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0/(TI01)/(TO01) P61/SDAA0/(TI02)/(TO02) <R> 1. OUTLINE Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/L13 User's Manual. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 6 of 123 RL78/L13 1. OUTLINE 1.4 Pin Identification PCLBUZ0, PCLBUZ1: ANI0, ANI1, Programmable Clock Output/ Buzzer Output ANI16 to ANI25: Analog Input AVREFM: Analog Reference Voltage REGC: Regulator Capacitance Minus REMOOUT: Remote control Output Analog Reference Voltage RESET: Reset Plus RTC1HZ: Real-time Clock 2 Correction Clock AVREFP: (1 Hz) Output CAPH, CAPL: Capacitor for LCD COM0 to COM7: LCD Common Output RxD0 to RxD3: EXCLK: EXCLKS: Receive Data External Clock Input SCK00, SCK10, SCLA0: Serial Clock Input/Output (Main System Clock) SCL00, SCL10: Serial Clock Output External Clock Input SDAA0, SDA00, SDA10: Serial Data Input/Output (Subsystem Clock) SEG0 to SEG50: External Interrupt Input LCD Segment Output SI00, SI10: Serial Data Input IVCMP0, IVCMP1: Comparator Input SO00, SO10: Serial Data Output IVREF0, IVREF1: Comparator Reference Input TI00 to TI07: Timer Input KR0 to KR7: Key Return TO00 to TO07, P00 to P07: Port 0 TKBO00, TKBO01-0, P10 to P17: Port 1 TKBO01-1, TKBO01-2: Timer Output P20 to P27: Port 2 TOOL0: Data Input/Output for Tool P30 to P35: Port 3 TOOLRxD, TOOLTxD: Data Input/Output for External Device P40 to P47: Port 4 TxD0 to TxD3: Transmit Data P50 to P57: Port 5 VCOUT0, VCOUT1: Comparator Output INTP0 to INTP7: P60, P61: Port 6 VDD: Power Supply P70 to P77: Port 7 VL1 to VL4: LCD Power Supply P121 to P127: Port 12 VSS: Ground P130, P137: Port 13 X1, X2: Crystal Oscillator (Main System Clock) XT1, XT2: Crystal Oscillator (Subsystem Clock) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 7 of 123 RL78/L13 1. OUTLINE 1.5 Block Diagram 1.5.1 64-pin products TIMER ARRAY UNIT0 (8ch) TI00/TO00/P52 (TI00/TO00/P40) ch0 TI01/TO01/P32 (TI01/TO01/P60) ch1 TI02/TO02/P54 (TI02/TO02/P61) ch2 TI03/TO03/P30 (TI03/TO03/P127) ch3 TI04/TO04/P14 (TI04/TO04/P126) ch4 TI05/TO05/P42 (TI05/TO05/P01) ch5 TI06/TO06/P125 ch6 TI07/TO07/P15 RxD0/P17 ch7 REMOOUT/P30 (REMOOUT/P127) TKBO00/P74, TKBO01-0/P77, TKBO01-1/P76, TKBO01-2/P75 Remote Carrier 4 2 3 A/D CONVERTER 4 ANI0/P21, ANI1/P20 ANI16/P22, ANI20/P26, ANI21/P27 ANI22/P10 to ANI25/P13 AVREFP/P21 AVREFM/P20 COMPARATOR (2ch) COMPARATOR0 VCOUT0/P03 IVCMP0/P44 IVREF0/P45 COMPARATOR1 VCOUT1/P04 IVCMP1/P43 IVREF1/P42 PORT 0 8 P00 to P07 PORT 1 8 P10 to P17 PORT 2 5 P20 to P22, P26, P27 PORT 3 4 P30 to P33 PORT 4 5 P40, P42 to P45 PORT 5 4 P52 to P54, P57 PORT 6 2 P60, P61 PORT 7 5 P70, P74 to P77 PORT 12 4 P121 to P124 3 P125 to P127 PORT 13 P137 16-bit TIMER KB20 KEY RETURN POWER ON RESET/ VOLTAGE DETECTOR SERIAL ARRAY UNIT0 (4ch) KR0/P70, KR4/P74 to KR7/P77 5 POR/LVD CONTROL UART0 RxD0/P17 TxD0/P00 LINSEL RESET CONTROL RxD1/P06(RxD1/P43) TxD1/P07(TxD0/P42) UART1 SCK00/P16 SI00/P17 SO00/P00 CSI00 SCK10/P05(SCK10/P44) SI10/P06(SI10/P43) SO10/P07(SO10/P42) CSI10 SYSTEM CONTROL SCL00/P16 SDA00/P17 IIC00 OSCILLATOR CODE FLASH MEMORY RL78 CPU CORE DATA FLASH MEMORY TOOL0/P40 ON-CHIP DEBUG RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP XT2/EXCLKS/P124 RAM SCL10/P05(SCL10/P44) SDA10/P06(SDA10/P43) IIC10 SERIAL ARRAY UNIT1 (4ch) RxD2/P03 TxD2/P04 VOLTAGE REGULATOR VDD REGC VSS TOOLRxD/P17, TOOLTxD/P00 UART2 3 SDAA0/P61 SERIAL INTERFACE IICA0 COM0 to COM7 VL1 to VL4 CAPH CAPL 2 36 8 LCD CONTROLLER/ DRIVER RAM SPACE FOR LCD DATA CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT Remark 2 INTP3/P31, INTP4/P33 2 INTP5/P01, INTP7/P02(INTP7/P43) SCLA0/P60 BUZZER OUTPUT SEG0 to SEG3, SEG6 to SEG8, SEG11, SEG12, SEG16 to SEG23, SEG29, SEG33 to SEG50 INTERRUPT CONTROL RxD0/P17 INTP0/P137 INTP1/P52, INTP2/P53, INTP6/P57 PCLBUZ0/P02 (PCLBUZ0/P07), PCLBUZ1/P01 CRC WINDOW WATCHDOG TIMER 12- BIT INTERVAL TIMER REAL-TIME CLOCK 2 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P31 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/L13 User's Manual. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 8 of 123 RL78/L13 1. OUTLINE 1.5.2 80-pin products TIMER ARRAY UNIT0 (8ch) PORT 0 8 P00 to P07 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 6 P30 to P35 PORT 4 8 P40 to P47 ch5 PORT 5 8 P50 to P57 ch6 PORT 6 2 P60, P61 PORT 7 8 P70 to P77 TI00/TO00/P52 (TI00/TO00/P40) ch0 TI01/TO01/P32 (TI01/TO01/P60) ch1 TI02/TO02/P54 (TI02/TO02/P61) ch2 TI03/TO03/P30 (TI03/TO03/P127) ch3 TI04/TO04/P14 (TI04/TO04/P126) ch4 TI05/TO05/P42 (TI05/TO05/P01) TI06/TO06/P56 (TI06/TO06/P125) TI07/TO07/P15 (TI07/TO07/P41) RxD0/P17 (RxD0/P47) ch7 REMOOUT/P30 (REMOOUT/P127) TKBO00/P74, TKBO01-0/P77, TKBO01-1/P76, TKBO01-2/P75 Remote Carrier 4 A/D CONVERTER 2 ANI0/P21, ANI1/P20 6 ANI16/P22 to ANI21/P27 4 ANI22/P10 to ANI25/P13 AVREFM/P20 AVREFP/P21 COMPARATOR (2ch) COMPARATOR0 VCOUT0/P03 IVCMP0/P44 IVREF0/P45 PORT 12 COMPARATOR1 VCOUT1/P04 IVCMP1/P43 IVREF1/P42 PORT 13 16-bit TIMER KB20 KEY RETURN 4 P121 to P124 3 P125 to P127 P130 P137 KR0/P70 to KR7/P77 8 SERIAL ARRAY UNIT0 (4ch) POWER ON RESET/ VOLTAGE DETECTOR UART0 RxD0/P17(RxD0/P47) TxD0/P00(TxD0/P130) LINSEL RxD1/P06(RxD1/P43) TxD1/P07(TxD0/P42) UART1 SCK00/P16(SCK00/P46) SI00/P17(SI00/P47) SO00/P00(SO00/P130) CSI00 SCK10/P05(SCK10/P44) SI10/P06(SI10/P43) SO10/P07(SO10/P42) CSI10 SCL00/P16(SCL00/P46) SDA00/P17(SDA00/P47) IIC00 SCL10/P05(SCL10/P44) SDA10/P06(SDA10/P43) IIC10 POR/LVD CONTROL RESET CONTROL CODE FLASH MEMORY RL78 CPU CORE DATA FLASH MEMORY TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR XT2/EXCLKS/P124 RAM VOLTAGE REGULATOR REGC SERIAL ARRAY UNIT1 (4ch) RxD2/P03 TxD2/P04 UART2 RxD3/P34 TxD3/P35 UART3 VDD VSS TOOLRxD/P17, TOOLTxD/P00 RxD0/P17 (RxD0/P47) INTP0/P137 4 SEG0 to SEG50 51 COM0 to COM7 VL1 to VL4 CAPH CAPL 8 LCD CONTROLLER/ DRIVER RAM SPACE FOR LCD DATA SCLA0/P60 2 BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT Remark SDAA0/P61 SERIAL INTERFACE IICA0 INTERRUPT CONTROL INTP1/P52, INTP2/P53, INTP5/P55(INTP5/P01), INTP6/P57 INTP3/P31, INTP4/P33 INTP7/P02(INTP7/P43) PCLBUZ0/P02 (PCLBUZ0/P07), PCLBUZ1/P01 CRC WINDOW WATCHDOG TIMER 12- BIT INTERVAL TIMER REAL-TIME CLOCK 2 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P31 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/L13 User's Manual. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 9 of 123 RL78/L13 1. OUTLINE 1.6 Outline of Functions (1/2) Item 64-pin 80-pin R5F10WLx (x = A, C-G) R5F10WMx (x = A, C-G) Code flash memory (KB) 16 to 128 16 to 128 Data flash memory (KB) 4 4 RAM (KB) 1 to 8 Address space <R> 1 to 8Note 1 Note 1 1 MB Main system High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V), clock HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) High-speed on-chip oscillator HS (High-speed main) mode: HS (High-speed main) mode: LS (Low-speed main) mode: LV (Low-voltage main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V), 1 to 8 MHz (VDD = 1.8 to 5.5 V), 1 to 4 MHz (VDD = 1.6 to 5.5 V) Clock for 16-bit timer KB20 48 MHz (TYP.): VDD = 2.7 to 5.5 V Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose register (8-bit register x 8) x 4 banks Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator: fIH = 24 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) * * * * Instruction set I/O port Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits x 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 49 65 42 (N-ch O.D. I/O [VDD withstand voltage]: 12) 58 (N-ch O.D. I/O [VDD withstand voltage]: 18) CMOS input 5 5 CMOS output - - N-ch O.D I/O (withstand voltage: 6 V) 2 2 CMOS I/O Timer Notes 1. 16-bit timer TAU 8 channels 16-bit timer KB20 1 channel Watchdog timer 1 channel 12-bit interval timer (IT) 1 channel Real-time clock 2 1 channel RTC2 output 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) Timer output 8 channels (PWM outputs: 7Note 2) (TAU used) 1 channel (timer KB20 used) Remote control output function 1 (TAU used) In the case of the 8 KB, this is about 7 KB when the self-programming function and data flash function are used. 2. The number of outputs varies depending on the setting of the channels in use and the number of master channels (see 6.9.3 Operation as multiple PWM output function in the RL78/L13 User's Manual.). R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 10 of 123 RL78/L13 1. OUTLINE (2/2) Item 64-pin 80-pin R5F10WLx (x = A, C-G) R5F10WMx (x = A, C-G) Clock output/buzzer output controller 2 * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 9 channels Comparator 2 channels Serial interface [64-pin] 12 channels * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * UART: 1 channel [80-pin] * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * UART: 2 channels 2 I C bus LCD controller/driver 1 channel Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. Segment signal output 36 (32)Note 1 Common signal output 51 (47)Note 1 4 (8)Note 1 Multiplier and divider/multiply- * 16 bits x 16 bits = 32 bits (Unsigned or signed) accumulator * 32 bits / 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 4 channels Vectored Internal 32 35 interrupt sources External 11 11 5 8 Key interrupt * Reset by RESET pin Reset * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction executionNote 2 * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 V (TYP.) * Power-down-reset: 1.50 V (TYP.) Voltage detector * Rising edge: 1.67 V to 4.06 V (14 steps) * Falling edge: 1.63 V to 3.98 V (14 steps) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V (TA = -40 to +85C) Operating ambient temperature Consumer applications: TA = -40 to +85C VDD = 2.4 to 5.5 V (TA = -40 to +105C) Industrial applications: TA = -40 to +105C Notes 1. 2. The values in parentheses are the number of signal outputs when 8 com is used. This reset occurs when instruction code FFH is executed. This reset does not occur during emulation using an in-circuit emulator or an on-chip debugging emulator. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 11 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Target products A: Consumer applications; TA = -40 to +85C R5F10WLAAFA, R5F10WLCAFA, R5F10WLDAFA, R5F10WLEAFA, R5F10WLFAFA, R5F10WLGAFA, R5F10WLAAFB, R5F10WLCAFB, R5F10WLDAFB, R5F10WLEAFB, R5F10WLFAFB, R5F10WLGAFB, R5F10WMAAFA, R5F10WMCAFA, R5F10WMDAFA, R5F10WMEAFA, R5F10WMFAFA, R5F10WMGAFA, R5F10WMAAFB, R5F10WMCAFB, R5F10WMDAFB, R5F10WMEAFB, R5F10WMFAFB, R5F10WMGAFB G: Industrial applications; when using TA = -40 to +105C specification products at TA = -40 to +85C R5F10WLAGFB, R5F10WLCGFB, R5F10WLDGFB, R5F10WLEGFB, R5F10WLFGFB, R5F10WLGGFB R5F10WMAGFB, R5F10WMCGFB, R5F10WMDGFB, R5F10WMEGFB, R5F10WMFGFB, R5F10WMGGFB Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 With functions for each product in the RL78/L13 User's Manual. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 12 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (1/3) Parameter Symbol Supply voltage VDD REGC pin input voltage VIREGC Conditions REGC Ratings Unit -0.5 to +6.5 V -0.3 to +2.8 V and -0.3 to VDD +0.3Note 1 Input voltage VI1 P00 to P07, P10 to P17, P20 to P27, P30 to P35, -0.3 to VDD +0.3Note 2 V -0.3 to +6.5 V V V P40 to P47, P50 to P57, P60, P61, P70 to P77, P121 to P127, P130, P137 Output voltage VI2 P60 and P61 (N-ch open-drain) VI3 EXCLK, EXCLKS, RESET -0.3 to VDD +0.3 Note 2 VO1 P00 to P07, P10 to P17, P20 to P27, P30 to P35, -0.3 to VDD +0.3 Note 2 P40 to P47, P50 to P57, P60, P61, P70 to P77, P121 to P127, P130, P137 Analog input voltage VAI1 ANI0, ANI1, ANI16 to ANI26 -0.3 to VDD +0.3 V and -0.3 to AVREF(+) +0.3Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+): + side reference voltage of the A/D converter. 3. VSS: Reference voltage R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 13 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Absolute Maximum Ratings (2/3) Parameter LCD voltage Symbol VL1 Conditions VL1 voltage Note 1 Ratings Unit -0.3 to +2.8 and V -0.3 to VL4 +0.3 VL2 VL2 voltageNote 1 -0.3 to VL4 +0.3Note 2 V VL3 VL3 voltageNote 1 -0.3 to VL4 +0.3Note 2 V VL4 VL4 voltageNote 1 -0.3 to +6.5 V VLCAP CAPL, CAPH voltage -0.3 to VL4 +0.3 V VOUT COM0 to COM7 External resistance division method SEG0 to SEG50 output voltage Note 1 Note 2 -0.3 to VDD +0.3 Note 2 V Capacitor split method -0.3 to VDD +0.3 Note 2 V Internal voltage boosting method -0.3 to VL4 +0.3 Note 2 V Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 F 30%) and connect a capacitor (0.47 F 30%) between the CAPL and CAPH pins. 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark VSS: Reference voltage R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 14 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Absolute Maximum Ratings (3/3) Parameter <R> Output current, high Symbol IOH1 Conditions Per pin P00 to P07, P10 to P17, P22 to P27, Ratings Unit -40 mA -170 mA -0.5 mA P30 to P35, P40 to P47, P50 to P57, P60, P61, P70 to P77, P125 to P127, P130 <R> Total of all pins P00 to P07, P10 to P17, P22 to P27, -170 mA P30 to P35, P40 to P47, P50 to P57, P60, P61, P70 to P77, P125 to P127, P130 <R> IOH2 <R> <R> Per pin P20, P21 Total of all pins Output current, low IOL1 Per pin P00 to P07, P10 to P17, P22 to P27, -1 mA 40 mA P30 to P35, P40 to P47, P50 to P57, P60, P61, P70 to P77, P125 to P127, P130 <R> Total of all pins P40 to P47, P130 70 mA 170 mA P00 to P07, P10 to P17, P22 to P27, 100 mA 1 mA 2 mA -40 to +85 C -65 to +150 C P30 to P35, P50 to P57, P60, P61, P70 to P77, P125 to P127 <R> IOL2 <R> Per pin P20, P21 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 15 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.2 Oscillator Characteristics 2.2.1 X1 and XT1 oscillator characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit MHz X1 clock oscillation Ceramic resonator/ 2.7 V VDD 5.5 V 1.0 20.0 frequency (fX)Note crystal resonator 2.4 V VDD < 2.7 V 1.0 16.0 1.8 V VDD < 2.4 V 1.0 8.0 1.6 V VDD < 1.8 V 1.0 4.0 XT1 clock oscillation Crystal resonator 32 32.768 35 kHz frequency (fXT)Note Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, see 5.4 System Clock Oscillator in the RL78/L13 User's Manual. 2.2.2 On-chip oscillator characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter High-speed on-chip oscillator Symbol Conditions MAX. Unit 1 24 MHz 1.8 V VDD 5.5 V -1.0 +1.0 % 1.6 V VDD < 1.8 V -5.0 +5.0 % 1.8 V VDD 5.5 V -1.5 +1.5 % 1.6 V VDD < 1.8 V -5.5 +5.5 % fIH MIN. TYP. clock frequencyNotes 1, 2 -20 to +85C High-speed on-chip oscillator clock frequency accuracy -40 to -20C Low-speed on-chip oscillator 15 fIL kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. The high-speed on-chip oscillator frequency is selected by bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of the HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for the instruction execution time. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 16 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol IOH1 Output current, highNote 1 <R> IOH2 Notes 1. Conditions MIN. TYP. MAX. -10.0 Unit Per pin for P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130 1.6 V VDD 5.5 V Total of P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130 (When duty = 70%Note 3) 4.0 V VDD 5.5 V -90.0 mA 2.7 V VDD < 4.0 V -15.0 mA 1.8 V VDD < 2.7 V -7.0 mA 1.6 V VDD < 1.8 V -3.0 mA Per pin for P20 and P21 1.6 V VDD 5.5 V Total of all pins (When duty = 70%Note 3) 1.6 V VDD 5.5 V -0.1 Note 2 Note 2 -0.2 mA mA mA Value of the current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin 2. 3. Do not exceed the total current value. Output current value under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -90.0 mA Total output current of pins = (-90.0 x 0.7)/(80 x 0.01) -78.75 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, and P130 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 17 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Output current, lowNote 1 IOL1 MAX. Unit Per pin for P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130 Conditions 20.0Note 2 mA Per pin for P60 and P61 15.0Note 2 mA 70.0 mA 2.7 V VDD < 4.0 V 15.0 mA 1.8 V VDD < 2.7 V 9.0 mA 1.6 V VDD < 1.8 V 4.5 mA 4.0 V VDD 5.5 V 90.0 mA 2.7 V VDD < 4.0 V 35.0 mA 1.8 V VDD < 2.7 V 20.0 mA 1.6 V VDD < 1.8 V 10.0 mA Total of all pins (When duty = 70%Note 3) 160.0 mA Per pin for P20 and P21 0.4Note 2 mA 0.8 mA Total of P00 to P07, P10 to P17, P22 to P27, P30 to P35, P50 to P57, P70 to P77, P125 to P127 (When duty = 70%Note 3) IOL2 Total of all pins (When duty = 70%Note 3) Notes 1. TYP. 4.0 V VDD 5.5 V Total of P40 to P47, P130 (When duty = 70%Note 3) <R> MIN. 1.6 V VDD 5.5 V Value of the current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin 2. 3. Do not exceed the total current value. Output current value under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 70.0 mA Total output current of pins = (70.0 x 0.7)/(80 x 0.01) 61.25 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 18 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Input voltage, Symbol VIH1 Conditions P00 to P07, P10 to P17, P22 to P27, MIN. Normal input buffer TYP. MAX. Unit 0.8VDD VDD V 2.2 VDD V 2.0 VDD V 1.5 VDD V P30 to P35, P40 to P47, P50 to P57, high P70 to P77, P125 to P127, P130, P137 VIH2 P03, P05, P06, P16, P17, P34, P43, TTL input buffer P44, P46, P47, P53, P55 4.0 V VDD 5.5 V TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 1.6 V VDD < 3.3 V VIH3 P20, P21 0.7VDD VDD V VIH4 P60, P61 0.7VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V Normal input buffer 0 0.2VDD V P03, P05, P06, P16, P17, P34, P43, TTL input buffer 0 0.8 V P44, P46, P47, P53, P55 4.0 V VDD 5.5 V 0 0.5 V 0 0.32 V Input voltage, low VIL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130, P137 VIL2 TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 1.6 V VDD < 3.3 V VIL3 P20, P21 0 0.3VDD V VIL4 P60, P61 0 0.3VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, and P130 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 19 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Output voltage, VOH1 high Conditions MIN. P00 to P07, P10 to P17, P22 to P27, 4.0 V VDD 5.5 V, P30 to P35, P40 to P47, P50 to P57, IOH1 = -10.0 mA P70 to P77, P125 to P127, P130 4.0 V VDD 5.5 V, TYP. MAX. Unit VDD - 1.5 V VDD - 0.7 V VDD - 0.6 V VDD - 0.5 V VDD - 0.5 V VDD - 0.5 V IOH1 = -3.0 mA 2.7 V VDD 5.5 V, IOH1 = -2.0 mA 1.8 V VDD 5.5 V, IOH1 = -1.5 mA 1.6 V VDD 5.5 V, IOH1 = -1.0 mA VOH2 P20 and P21 1.6 V VDD 5.5 V, IOH2 = -100 A Output voltage, VOL1 low P00 to P07, P10 to P17, P22 to P27, 4.0 V VDD 5.5 V, P30 to P35, P40 to P47, P50 to P57, IOL1 = 20 mA P70 to P77, P125 to P127, P130 4.0 V VDD 5.5 V, 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V 0.4 V IOL1 = 8.5 mA 2.7 V VDD 5.5 V, IOL1 = 3.0 mA 2.7 V VDD 5.5 V, IOL1 = 1.5 mA 1.8 V VDD 5.5 V, IOL1 = 0.6 mA 1.6 V VDD < 1.8 V, IOL1 = 0.3 mA VOL2 P20 and P21 1.6 V VDD 5.5 V, IOL2 = 400 A VOL3 P60 and P61 4.0 V VDD 5.5 V, IOL3 = 15.0 mA 4.0 V VDD 5.5 V, IOL3 = 5.0 mA 2.7 V VDD 5.5 V, IOL3 = 3.0 mA 1.8 V VDD 5.5 V, IOL3 = 2.0 mA 1.6 V VDD < 1.8 V, IOL3 = 1.0 mA Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, and P130 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 20 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Input leakage ILIH1 Conditions P00 to P07, P10 to P17, MIN. TYP. MAX. Unit VI = VDD 1 A 1 A 1 A 10 A VI = VSS -1 A -1 A -1 A -10 A P22 to P27, P30 to P35, current, high P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130, P137 ILIH2 P20 and P21, RESET VI = VDD ILIH3 P121 to P124 VI = VDD In input port mode (X1, X2, XT1, XT2, EXCLK, and when external EXCLKS) clock is input Resonator connected Input leakage ILIL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, current, low P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130, P137 ILIL2 P20 and P21, RESET VI = VSS ILIL3 P121 to P124 VI = VSS In input port mode (X1, X2, XT1, XT2, EXCLK, and when external EXCLKS) clock is input Resonator connected On-chip pull-up RU1 P00 to P07, P10 to P17, VI = VSS P22 to P27, P30 to P35, resistance P45 to P47, P50 to P57, 2.4 V VDD < 5.5 V 10 20 100 k 1.6 V VDD < 2.4 V 10 30 100 k 10 20 100 k P70 to P77, P125 to P127, P130 RU2 Remark P40 to P44 VI = VSS Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 21 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.3.2 Supply current characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply currentNote IDD1 (1/2) Conditions Operating mode 1 HS (highspeed main) modeNote 5 MIN. fHOCO = 48 MHzNote 3, fIH = 24 MHzNote 3 TYP. MAX. Unit Basic operation VDD = 5.0 V VDD = 3.0 V 2.0 Normal operation VDD = 5.0 V 3.8 6.5 mA VDD = 3.0 V 3.8 6.5 mA Basic operation VDD = 5.0 V 1.7 mA VDD = 3.0 V 1.7 mA Normal operation VDD = 5.0 V 3.6 6.1 mA VDD = 3.0 V 3.6 6.1 mA fHOCO = 16 MHzNote 3, fIH = 16 MHzNote 3 Normal operation VDD = 5.0 V 2.7 4.7 mA VDD = 3.0 V 2.7 4.7 mA fHOCO = 8 MHzNote 3 , fIH = 8 MHzNote 3 Normal operation VDD = 3.0 V 1.2 2.1 mA VDD = 2.0 V 1.2 2.1 mA LV (lowfHOCO = 4 MHzNote 3, voltage main) fIH = 4 MHzNote 3 modeNote 5 Normal operation VDD = 3.0 V 1.2 1.8 mA VDD = 2.0 V 1.2 1.8 mA fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 3.0 5.1 mA Resonator connection 3.2 5.2 mA fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 2.9 5.1 mA Resonator connection 3.2 5.2 mA fMX = 16 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 2.5 4.4 mA Resonator connection 2.7 4.5 mA fMX = 16 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 2.5 4.4 mA Resonator connection 2.7 4.5 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 1.9 3.0 mA Resonator connection 1.9 3.0 mA fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.9 3.0 mA Resonator connection 1.9 3.0 mA fMX = 8 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.1 2.0 mA Resonator connection 1.1 2.0 mA fMX = 8 MHzNote 2, VDD = 2.0 V Normal operation Square wave input 1.1 2.0 mA Resonator connection 1.1 2.0 mA fSUB = 32.768 kHzNote 4 , TA = -40C Normal operation Square wave input 4.0 5.4 A Resonator connection 4.3 5.4 A fSUB = 32.768 kHz Note , TA = +25C Normal operation Square wave input 4.0 5.4 A Resonator connection 4.3 5.4 A fSUB = 32.768 kHzNote , TA = +50C Normal operation Square wave input 4.1 7.1 A Resonator connection 4.4 7.1 A fSUB = 32.768 kHzNote , TA = +70C Normal operation Square wave input 4.3 8.7 A Resonator connection 4.7 8.7 A fSUB = 32.768 kHzNote , TA = +85C Normal operation Square wave input 4.7 12.0 A Resonator connection 5.2 12.0 A fHOCO = 24 MHz fIH = 24 MHzNote 3 , Note 3 LS (lowspeed main) modeNote 5 HS (highspeed main) modeNote 5 LS (lowspeed main) modeNote 5 Subsystem clock operation 4 4 4 4 2.0 mA mA (Notes and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 22 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, onchip pull-up/pull-down resistors, and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When setting ultra-low power consumption oscillation (AMPHS1 = 1). The current flowing into the LCD controller/driver, 16-bit timer KB20, real-time clock 2, 12-bit interval timer, and watchdog timer is not included. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.) 3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 23 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply I Note 2 DD2 Conditions HALT mode currentNote 1 (2/2) HS (high-speed main) modeNote 7 MIN. fHOCO = 48 MHz Note 4 , fIH = 24 MHzNote 4 fHOCO = 24 MHz Note 4 , fIH = 24 MHzNote 4 fHOCO = 16 MHz Note 4 , fIH = 16 MHzNote 4 LS (low-speed main) modeNote 7 fHOCO = 8 MHz Note 4 , fIH = 8 MHz Note 4 LV (low-voltage fHOCO = 4 MHzNote 4, main) modeNote 7 fIH = 4 MHzNote 4 HS (high-speed main) modeNote 7 fMX = 20 MHz , VDD = 5.0 V 0.71 1.95 mA VDD = 3.0 V 0.71 1.95 VDD = 5.0 V 0.49 1.64 VDD = 3.0 V 0.49 1.64 VDD = 5.0 V 0.43 1.11 VDD = 3.0 V 0.43 1.11 VDD = 3.0 V 280 770 VDD = 2.0 V 280 770 VDD = 3.0 V 430 700 VDD = 2.0 V 430 700 0.31 1.42 Resonator connection 0.48 1.42 fMX = 20 MHzNote 3, Square wave input 0.29 1.42 VDD = 3.0 V Resonator connection 0.48 1.42 Square wave input 0.26 0.86 Resonator connection 0.45 1.15 Square wave input 0.25 0.86 Resonator connection 0.44 1.15 fMX = 16 MHz , Note 3 , Note 3 VDD = 3.0 V fMX = 10 MHz , Square wave input 0.20 0.63 VDD = 5.0 V Resonator connection 0.28 0.71 fMX = 10 MHzNote 3, Square wave input 0.19 0.63 VDD = 3.0 V Resonator connection 0.28 0.71 Square wave input 100 560 Resonator connection 160 560 Square wave input 100 560 Resonator connection 160 560 0.34 0.62 Resonator connection 0.51 0.80 fSUB = 32.768 kHzNote 5, Square wave input TA = +25C Resonator connection 0.38 0.62 0.57 0.80 0.46 2.30 0.67 2.49 0.65 4.03 0.91 4.22 1.00 8.04 fMX = 8 MHz Note 3 Note 3 , main) modeNote 7 VDD = 3.0 V fMX = 8 MHz Note 3 , VDD = 2.0 V fSUB = 32.768 kHz Note 5 clock operation TA = -40C fSUB = 32.768 kHz Note 5 TA = +50C fSUB = 32.768 kHz fSUB = 32.768 kHz TA = +85C , Square wave input , Square wave input Resonator connection Note 5 TA = +70C IDD3Note 6 Unit Square wave input Note 3 VDD = 5.0 V Subsystem MAX. VDD = 5.0 V fMX = 16 MHz LS (low-speed TYP. , Square wave input Resonator connection Note 5 , Square wave input 1.31 8.23 STOP TA = -40C Resonator connection 0.18 0.52 modeNote 8 TA = +25C 0.24 0.52 TA = +50C 0.33 2.21 TA = +70C 0.53 3.94 TA = +85C 0.93 7.95 mA mA A A mA mA mA mA mA mA A A A A A A A A (Notes and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 24 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, onchip pull-up/pull-down resistors, and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the realtime clock 2 is included. However, not including the current flowing into the clock output/buzzer output, 12-bit interval timer, and watchdog timer. 6. Not including the current flowing into the real-time clock 2, clock output/buzzer output, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.) 3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25C R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 25 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Low-speed on- Symbol I Conditions MIN. Note 1 FIL TYP. MAX. Unit 0.20 A 0.02 A 0.04 A 0.22 A chip oscillator operating current RTC2 operating IRTCNotes 1, 2, current 3 12-bit interval ITMKANotes 1, 2, timer operating 4 fSUB = 32.768 kHz current Watchdog timer IWDTNotes 1, 2, 5 fIL = 15 kHz IADCNotes 1, 6 When conversion at maximum speed operating current A/D converter operating current Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V 1.3 1.7 mA 0.5 0.7 mA A/D converter IADREFNote 1 reference voltage current 75.0 A Temperature sensor operating current ITMPSNote 1 75.0 A LVD operating ILVDNotes 1, 7 0.08 A Window mode 12.5 A Comparator high-speed mode 6.5 A Comparator low-speed mode 1.7 A Window mode 8.0 A Comparator high-speed mode 4.0 A Comparator low-speed mode 1.3 A current Comparator operating current ICMPNotes 1, 11 VDD = 5.0 V, Regulator output voltage = 2.1 V VDD = 5.0 V, Regulator output voltage = 1.8 V Selfprogramming operating current I Notes 1, 9 FSP 2.00 12.20 mA BGO operating IBGONotes 1, 8 2.00 12.20 mA While the mode is shiftingNote 10 0.50 0.60 mA During A/D conversion, in low voltage 1.20 1.44 mA 0.70 0.84 mA 0.04 0.20 A 0.85 2.20 A 1.55 3.70 A 0.20 0.50 A current SNOOZE ISNOZNote 1 ADC operation operating current mode, AVREFP = VDD = 3.0 V CSI/UART operation LCD operating I External resistance fLCD = fSUB 1/3 bias, VDD = 5.0 V, current 13 division method LCD clock = 128 Hz four time slices VL4 = 5.0 V ILCD2Note 1, 12 Internal voltage fLCD = fSUB 1/3 bias, VDD = 3.0 V, boosting method LCD clock = 128 Hz four time slices VL4 = 3.0 V Notes 1, 12, LCD1 (VLCD = 04H) VDD = 5.0 V, VL4 = 5.1 V (VLCD = 12H) I Note 1, 12 LCD3 Capacitor split fLCD = fSUB 1/3 bias, VDD = 3.0 V, method LCD clock = 128 Hz four time slices VL4 = 3.0 V (Notes and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 26 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock 2 operates in operation mode or HALT mode. When the lowspeed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of real-time clock 2. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 6. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode, see 21.3.3 SNOOZE mode in the RL78/L13 User's Manual. . 11. Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates. 12. Current flowing only to the LCD controller/driver. The value of the current for the RL78 microcontrollers is the sum of the supply current (IDD1 or IDD2) and LCD operating current (ILCD1, ILCD2, or ILCD3), when the LCD controller/driver operates in operation mode or HALT mode. However, not including the current flowing into the LCD panel. Conditions of the TYP. value and MAX. value are as follows. * Setting 20 pins as the segment function and blinking all * Selecting fSUB for system clock when LCD clock = 128 Hz (LCDC0 = 07H) * Setting four time slices and 1/3 bias 13. Not including the current flowing into the external division resistor when using the external resistance division method. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. The temperature condition for the TYP. value is TA = 25C. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 27 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.4 AC Characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) operation MIN. MAX. Unit 1 s 0.0625 1 s 0.125 1 s LV (low-voltage 1.6 V VDD 5.5 V main) mode 0.25 1 s 1.8 V VDD 5.5 V 28.5 31.3 s HS (high-speed 2.7 V VDD 5.5 V main) mode 2.4 V VDD < 2.7 V 1.8 V VDD 5.5 V LS (low-speed main) mode Subsystem clock (fSUB) operationNote 0.0417 1 s 1 s 0.125 1 s 0.25 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD < 2.7 V 1.0 16.0 MHz 1.8 V VDD < 2.4 V 1.0 8.0 MHz 1.6 V VDD < 1.8 V 1.0 4.0 MHz 32 35 kHz LV (low-voltage 1.8 V VDD 5.5 V main) mode fEX fEXS External system clock input high-level width, low-level width tEXH, tEXL 2.7 V VDD 5.5 V 24 ns 2.4 V VDD < 2.7 V 30 ns 1.8 V VDD < 2.4 V 60 ns 1.6 V VDD < 1.8 V 120 ns 13.7 s 1/fMCK+10 ns tEXHS, tEXLS TI00 to TI07 input high-level width, low-level width tTIH, tTIL TO00 to TO07, TKBO00, TKBO01-0 to TKBO01-2 output frequency fTO PCLBUZ0, PCLBUZ1 output frequency fPCL 30.5 0.0625 In the self HS (high-speed 2.7 V VDD 5.5 V programming main) mode 2.4 V VDD < 2.7 V mode LS (low-speed 1.8 V VDD 5.5 V main) mode External system clock frequency TYP. 0.0417 4.0 V VDD 5.5 V 12 MHz 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz LV (low-voltage main) mode 1.6 V VDD 5.5 V 2 MHz LS (low-speed main) mode 1.8 V VDD 5.5 V 4 MHz HS (high-speed main) mode 4.0 V VDD 5.5 V 16 MHz 2.7 V VDD < 4.0 V 8 MHz HS (high-speed main) mode 2.4 V VDD < 2.7 V 4 MHz LV (low-voltage main) mode 1.8 V VDD 5.5 V 4 MHz 1.6 V VDD < 1.8 V 2 MHz LS (low-speed main) mode 1.8 V VDD 5.5 V 4 MHz Interrupt input high-level width, tINTH, low-level width tINTL INTP0 to INTP7 1.6 V VDD 5.5 V 1 s Key interrupt input high-level width, low-level width tKRH, tKRL KR0 to KR7 1.8 V VDD 5.5 V 250 ns 1 s IH-PWM output restart input high-level width tIHR INTP0 to INTP7 2 fCLK TMKB2 forced output stop input high-level width tIHR INTP0 to INTP2 2 fCLK RESET low-level width tRSL 10 s 1.6 V VDD < 1.8 V (Note and Remark are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 28 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Note Operation is not possible if 1.6 V VDD < 1.8 V in LV (low-voltage main) mode while the system is operating on the subsystem clock. Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn) m: Unit number (m = 0), n: Channel number (n = 0 to 7)) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.0417 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 29 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 TCY vs VDD (LS (low-speed main) mode) 10 When the high-speed on-chip oscillator clock is selected Cycle time TCY [s] 1.0 During self programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 1.8 3.0 5.0 5.5 6.0 4.0 Supply voltage VDD [V] TCY vs VDD (LV (low-voltage main) mode) 10 Cycle time TCY [s] 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.25 0.1 0.01 0 1.0 2.0 1.6 1.8 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 30 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS EXCLK/EXCLKS TI/TO Timing tTIH tTIL TI00 to TI07 1/fTO TO00 to TO07, TKBO00, TKBO01-0, TKBO01-1, TKBO01-2 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 31 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 32 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Transfer rate Note 2.4 V VDD 5.5 V 1 Theoretical value of the MAX. MIN. MAX. MIN. Unit MAX. fMCK/6 fMCK/6 fMCK/6 bps 4.0 1.3 0.6 Mbps - fMCK/6 fMCK/6 bps - 1.3 0.6 Mbps - - fMCK/6 bps - - 0.6 Mbps maximum transfer rate fMCK = fCLKNote 2 1.8 V VDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 1.6 V VDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller RxDq R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 User device Tx Page 33 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 34 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. MIN. MIN. MAX. MAX. Unit MAX. 2.7 V VDD 5.5 V 167 Note 1 500 Note 1 1000 Note 1 2.4 V VDD 5.5 V 250 Note 1 500 Note 1 1000 Note 1 ns 1.8 V VDD 5.5 V - 500 Note 1 1000 Note 1 ns 1.6 V VDD 5.5 V - - 1000 Note 1 ns ns SCKp high-/low-level tKH1, 4.0 V VDD 5.5 V tKCY1/2-12 tKCY1/2-50 tKCY1/2-50 ns width tKL1 2.7 V VDD 5.5 V tKCY1/2-18 tKCY1/2-50 tKCY1/2-50 ns 2.4 V VDD 5.5 V tKCY1/2-38 tKCY1/2-50 tKCY1/2-50 ns 1.8 V VDD 5.5 V - tKCY1/2-50 tKCY1/2-50 ns 1.6 V VDD 5.5 V - - tKCY1/2-100 ns 2.7 V VDD 5.5 V 44 110 110 ns 2.4 V VDD 5.5 V 75 110 110 ns 1.8 V VDD 5.5 V - 110 110 ns SIp setup time tSIK1 (to SCKp)Note 2 SIp hold time tKSI1 (from SCKp)Note 3 Delay time from tKSO1 SCKp to SOp outputNote 4 1.8 V VDD 5.5 V - - 220 ns 2.4 V VDD 5.5 V 19 19 19 ns 1.8 V VDD 5.5 V - 19 19 ns 1.6 V VDD 5.5 V - - 19 ns C = 30 pF Note 5 2.4 V VDD 5.5 V 25 25 25 ns 1.8 V VDD 5.5 V - 25 25 ns 1.6 V VDD 5.5 V - - 25 ns Notes 1. The value must also be equal to or more than 2/fCLK for CSI00 and equal to or more than 4/fCLK for CSI10. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2), g: PIM and POM numbers (g = 0, 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 35 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCKp cycle tKCY2 4.0 V VDD 5.5 V timeNote 5 2.7 V VDD 5.5 V MAX. MIN. MAX. MIN. Unit MAX. fMCK > 20 MHz 8/fMCK - - ns fMCK 20 MHz 6/fMCK 6/fMCK 6/fMCK ns fMCK > 16 MHz 8/fMCK - - ns fMCK 16 MHz 6/fMCK 6/fMCK 6/fMCK ns 6/fMCK 6/fMCK 6/fMCK ns 2.4 V VDD 5.5 V and 500 1.8 V VDD 5.5 V - 6/fMCK 6/fMCK ns 1.6 V VDD 5.5 V - - 6/fMCK ns SCKp high-/low- tKH2, 4.0 V VDD 5.5 V tKCY2/2-7 tKCY2/2-7 tKCY2/2-7 ns level width 2.7 V VDD 5.5 V tKCY2/2-8 tKCY2/2-8 tKCY2/2-8 ns 2.4 V VDD 5.5 V tKCY2/2-18 tKCY2/2-18 tKCY2/2-18 ns 1.8 V VDD 5.5 V - tKCY2/2-18 tKCY2/2-18 ns 1.6 V VDD 5.5 V - - tKCY2/2-66 ns tKL2 SIp setup time tSIK2 (to SCKp)Note 1 SIp hold time tKSI2 (from SCKp)Note 2 Delay time from tKSO2 2.7 V VDD 5.5 V 1/fMCK+20 1/fMCK+30 1/fMCK+30 ns 2.4 V VDD 5.5 V 1/fMCK+30 1/fMCK+30 1/fMCK+30 ns 1.8 V VDD 5.5 V - 1/fMCK+30 1/fMCK+30 ns 1.6 V VDD 5.5 V - - 1/fMCK+40 ns 2.4 V VDD 5.5 V 1/fMCK+31 1/fMCK+31 1/fMCK+31 ns 1.8 V VDD 5.5 V - 1/fMCK+31 1/fMCK+31 ns 1.6 V VDD 5.5 V - - 1/fMCK+250 ns C = 30 pF Note 4 SCKp to SOp outputNote 3 2.7 V VDD 5.5 V 2/fMCK+44 2/fMCK+110 2/fMCK+110 ns 2.4 V VDD 5.5 V 2/fMCK+75 2/fMCK+110 2/fMCK+110 ns 1.8 V VDD 5.5 V - 2/fMCK+110 2/fMCK+110 ns 1.6 V VDD 5.5 V - - 2/fMCK+220 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2), g: PIM number (g = 0, 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 36 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO SOp SI User device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 10) m: Unit number, n: Channel number (mn = 00, 02) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 37 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (4) During communication at same potential (simplified I2C mode) (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCLr clock fSCL 2.7 V VDD 5.5 V, 1000 Cb = 50 pF, Rb = 2.7 k frequency MAX. MIN. MAX. MIN. Unit MAX. Note 1 400Note 1 kHz 400Note 1 400Note 1 400Note 1 kHz 300Note 1 300Note 1 300Note 1 kHz - - 250Note 1 kHz 400 Note 1 1.8 V (2.4 VNote 3) VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V (2.4 VNote 3) VDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V VDD < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when tLOW SCLr = "L" 2.7 V VDD 5.5 V, 475 1150 1150 ns 1150 1150 1150 ns 1550 1550 1550 ns - - 1850 ns 475 1150 1150 ns 1150 1150 1150 ns 1550 1550 1550 ns - - 1850 ns ns Cb = 50 pF, Rb = 2.7 k 1.8 V (2.4 VNote 3) VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V (2.4 VNote 3) VDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V VDD < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when tHIGH SCLr = "H" 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V (2.4 VNote 3) VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V (2.4 VNote 3) VDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V VDD < 1.8 V, Cb = 100 pF, Rb = 5 k Data setup time tSU:DAT (reception) 2.7 V VDD 5.5 V, 1/fMCK+ 1/fMCK+ 1/fMCK+ Cb = 50 pF, Rb = 2.7 k 85Note 2 145Note 2 145Note 2 1.8 V (2.4 VNote 3) VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V (2.4 VNote 3) VDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1/fMCK+ 1/fMCK+ 1/fMCK+ 145Note 2 145Note 2 145Note 2 1/fMCK+ 1/fMCK+ 1/fMCK+ 230Note 2 230Note 2 230Note 2 - - 1.6 V VDD < 1.8 V, (transmission) tHD:DAT 2.7 V VDD 5.5 V, ns 1/fMCK+ Cb = 100 pF, Rb = 5 k Data hold time ns ns 290Note 2 0 305 0 305 0 305 ns 0 355 0 355 0 355 ns 0 405 0 405 0 405 ns - - - - 0 405 ns Cb = 50 pF, Rb = 2.7 k 1.8 V (2.4 VNote 3) VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V (2.4 VNote 3) VDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V VDD < 1.8 V, Cb = 100 pF, Rb = 5 k (Notes, Caution, and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 38 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. Caution The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". 3. Condition in the HS (high-speed main) mode Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78 microcontroller User device SCL SCLr Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT tSU : DAT Remarks 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 10), g: PIM and POM number (g = 0, 1) <R> 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0-3), mn = 00-03, 10-13) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 39 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Transfer rate Reception 4.0 V VDD 5.5 V, MAX. fMCK/6 2.7 V Vb 4.0 V Note MIN. MAX. fMCK/6 Note MIN. Unit MAX. fMCK/6Note bps 1 1 1 4.0 1.3 0.6 Mbps fMCK/6Note fMCK/6Note fMCK/6Note bps 1 1 1 4.0 1.3 0.6 Mbps bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 3 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLKNote 3 1.8 V (2.4 VNote 4) VDD < 3.3 V, fMCK/6 fMCK/6 fMCK/6 Note s1, 2 Notes 1, 2 Notes 1, 2 4.0 1.3 0.6 1.6 V Vb 2.0 V Theoretical value of the Mbps maximum transfer rate fMCK = fCLKNote 3 Notes 1. Transfer rate in SNOOZE mode is 4800 bps only. 2. Use it with VDD Vb. 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V) 4. Condition in the HS (high-speed main) mode Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 40 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Transfer rate Trans 4.0 V VDD 5.5 V, MAX. MIN. MAX. MIN. Unit MAX. bps Note 1 Note 1 Note 1 2.8Note 2 2.8Note 2 2.8Note 2 Mbps Note 3 Note 3 Note 3 1.2Note 4 1.2Note 4 1.2Note 4 Mbps Notes Notes Notes 5, 6 5, 6 5, 6 0.43Note 7 0.43Note 7 mission 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate (Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V) 2.7 V VDD < 4.0 V, bps 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate (Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V) 1.8 V (2.4 VNote 8) VDD < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum bps 0.43Note 7 Mbps transfer rate (Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V) Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.2 Vb )} x 3 [bps] 2.2 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.0 Vb )} x 3 [bps] 2.0 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. Use it with VDD Vb. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 41 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V (2.4 VNote 8) VDD < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 1.5 Vb )} x 3 [bps] 1.5 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. 8. Condition in the HS (high-speed main) mode Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller RxDq R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 User device Tx Page 42 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 43 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (6) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCKp cycle time tKCY1 tKCY1 2/fCLK 4.0 V VDD 5.5 V, MAX. MIN. MAX. MIN. Unit MAX. 200 1150 1150 ns 300 1150 1150 ns tKCY1/2 - tKCY1/2 - tKCY1/2 - ns 50 50 50 tKCY1/2 - tKCY1/2 - tKCY1/2 - 120 120 120 tKCY1/2 - tKCY1/2 - tKCY1/2 - 7 50 50 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp high-level tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k width 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp low-level tKL1 width 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, SIp setup time tSIK1 (to SCKp)Note 1 ns ns tKCY1/2 - tKCY1/2 - tKCY1/2 - Cb = 20 pF, Rb = 2.7 k 10 50 50 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 58 479 479 ns 121 479 479 ns 10 10 10 ns 10 10 10 ns ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (from SCKp)Note 1 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from tKSO1 SCKp to 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 60 60 60 ns 130 130 130 ns Cb = 20 pF, Rb = 1.4 k SOp outputNote 1 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp setup time tSIK1 (to SCKp)Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 23 110 110 ns 33 110 110 ns 10 10 10 ns 10 10 10 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (from SCKp)Note 2 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp to SOp outputNote 2 tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 10 10 10 ns 10 10 10 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k (Notes, Caution and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 44 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. This specification is valid only when CSI00's peripheral I/O redirect function is not used. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 45 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V VDD 5.5 V, MAX. MIN. MAX. MIN. Unit MAX. 300 1150 1150 ns 500 1150 1150 ns 1150 1150 1150 ns tKCY1/2 - tKCY1/2 - tKCY1/2 - ns 75 75 75 tKCY1/2 - tKCY1/2 - tKCY1/2 - 170 170 170 tKCY1/2 - tKCY1/2 - tKCY1/2 - 458 458 458 tKCY1/2 - tKCY1/2 - tKCY1/2 - 12 50 50 tKCY1/2 - tKCY1/2 - tKCY1/2 - 18 50 50 tKCY1/2 - tKCY1/2 - tKCY1/2 - 50 50 50 81 479 479 ns 177 479 479 ns 479 479 479 ns 19 19 19 ns 19 19 19 ns 19 19 19 ns 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 1.8 VNote 2, Cb = 30 pF, Rb = 5.5 k SCKp high-level tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k width 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, ns ns Cb = 30 pF, Rb = 5.5 k SCKp low-level tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k width 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, ns ns ns Cb = 30 pF, Rb = 5.5 k SIp setup time tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k (to SCKp)Note 3 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k SIp hold time tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k (from SCKp)Note 3 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to SOp outputNote 3 tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 100 100 100 ns 195 195 195 ns 483 483 483 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 46 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SIp setup time tSIK1 (to SCKp)Note 4 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MAX. MIN. MAX. MIN. Unit MAX. 44 110 110 ns 44 110 110 ns 110 110 110 ns 19 19 19 ns 19 19 19 ns 19 19 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k SIp hold time tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k (from SCKp)Note 4 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 25 25 25 ns 25 25 25 ns 25 25 25 ns Cb = 30 pF, Rb = 1.4 k SOp outputNote 4 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V (2.4 VNote 1) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k Notes 1. Condition in HS (high-speed main) mode 2. Use it with VDD Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 4. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Master> Vb Rb SCKp RL78 microcontroller R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Vb Rb SCK SIp SO SOp SI User device Page 47 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 Output data SOp CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Remarks 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10), m: Unit number , n: Channel number (mn = 00, 02), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 48 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCKp cycle tKCY2 timeNote 1 - - ns 8 MHz < fMCK 20 MHz 10/fMCK - - ns 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK - ns fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 16/fMCK - - ns 2.3 V Vb 16 MHz < fMCK 20 MHz 14/fMCK - - ns 8 MHz < fMCK 16 MHz 12/fMCK - - ns 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK - ns fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 20 MHz < fMCK 36/fMCK - - ns 16 MHz < fMCK 20 MHz 32/fMCK - - ns 8 MHz < fMCK 16 MHz 26/fMCK - - ns 4 MHz < fMCK 8 MHz 16/fMCK 16/fMCK - ns fMCK 4 MHz 10/fMCK 10/fMCK 10/fMCK ns tKCY2/2 tKCY2/2 tKCY2/2 ns - 12 - 50 - 50 tKCY2/2 tKCY2/2 tKCY2/2 - 18 - 50 - 50 1.6 V Vb 2.0 VNote 3 ) Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V 1.8 V (2.4 VNote 2) VDD < 3.3 V, SIp setup time tSIK2 tKCY2/2 tKCY2/2 tKCY2/2 1.6 V Vb 2.0 VNote 3 - 50 - 50 - 50 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK 1/fMCK 1/fMCK + 20 + 30 + 30 1/fMCK 1/fMCK 1/fMCK + 20 + 30 + 30 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1/fMCK 1/fMCK 1/fMCK 1.6 V Vb 2.0 VNote 3 + 30 + 30 + 30 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK 1/fMCK 1/fMCK + 31 + 31 + 31 1/fMCK 1/fMCK 1/fMCK + 31 + 31 + 31 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1/fMCK 1/fMCK 1/fMCK 1.6 V Vb 2.0 VNote 3 + 31 + 31 + 31 (to SCKp)Note 4 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V SIp hold time tKSI2 (from SCKp)Note 5 Delay time from SCKp to SOp outputNote 6 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V tKSO2 MAX. 12/fMCK VDD < 3.3 V, tKH2, MIN. 20 MHz < fMCK 1.8 V (2.4 V tKL2 MAX. 2.7 V Vb 2.7 V /low-level width MIN. 4.0 V VDD 5.5 V, 4.0 V SCKp high- MAX. Unit ns ns ns ns ns ns ns ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK 2/fMCK 2/fMCK Cb = 30 pF, Rb = 1.4 k + 120 + 573 + 573 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, 2/fMCK 2/fMCK 2/fMCK Cb = 30 pF, Rb = 2.7 k + 214 + 573 + 573 1.8 V (2.4 VNote 2) VDD < 3.3 V, 2/fMCK 2/fMCK 2/fMCK 1.6 V Vb 2.0 VNote 3, + 573 + 573 + 573 ns ns ns Cb = 30 pF, Rb = 5.5 k (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 49 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. Transfer rate in SNOOZE mode: MAX. 1 Mbps 2. Condition in HS (high-speed main) mode 3. Use it with VDD Vb. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 SCK SIp SO SOp SI User device Page 50 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remarks 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn) m: Unit number, n: Channel number (mn = 00, 02)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 51 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCLr clock fSCL 4.0 V VDD 5.5 V, 1000 2.7 V Vb 4.0 V, frequency MAX. MIN. MAX. MIN. Unit MAX. Note 1 300Note 1 kHz 300Note 1 300Note 1 kHz 400Note 1 300Note 1 300Note 1 kHz 400Note 1 300Note 1 300Note 1 kHz 300Note 1 300Note 1 300Note 1 kHz 300 Note 1 Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 1000Note 2.3 V Vb 2.7 V, 1 Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 3, Cb = 100 pF, Rb = 5.5 k Hold time when tLOW 4.0 V VDD 5.5 V, 475 1550 1550 ns 475 1550 1550 ns 1150 1550 1550 ns 1150 1550 1550 ns 1550 1550 1550 ns 245 610 610 ns 200 610 610 ns 675 610 610 ns 600 610 610 ns 610 610 610 ns 2.7 V Vb 4.0 V, SCLr = "L" Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 3, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 3, Cb = 100 pF, Rb = 5.5 k (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 52 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Data setup time tSU:DAT (reception) MAX. MIN. MAX. MIN. 4.0 V VDD 5.5 V, 1/fMCK+ 1/fMCK+ 1/fMCK+ 2.7 V Vb 4.0 V, 135Note 4 190Note 4 190Note 4 Unit MAX. ns Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 1/fMCK+ 1/fMCK+ 1/fMCK+ 2.3 V Vb 2.7 V, 135Note 4 190Note 4 190Note 4 ns Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 1/fMCK+ 1/fMCK+ 1/fMCK+ 2.7 V Vb 4.0 V, 190Note 4 190Note 4 190Note 4 ns Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 1/fMCK+ 1/fMCK+ 1/fMCK+ 2.3 V Vb 2.7 V, 190Note 4 190Note 4 190Note 4 ns Cb = 100 pF, Rb = 2.7 k 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 3, 1/fMCK+ 1/fMCK+ 1/fMCK+ 190Note 4 190Note 4 190Note 4 ns Cb = 100 pF, Rb = 5.5 k Data hold time (transmission) tHD:DAT 4.0 V VDD 5.5 V, 0 305 0 305 0 305 ns 0 305 0 305 0 305 ns 0 355 0 355 0 355 ns 0 355 0 355 0 355 ns 0 405 0 405 0 405 ns 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V (2.4 VNote 2) VDD < 3.3 V, 1.6 V Vb 2.0 VNote 3, Cb = 100 pF, Rb = 5.5 k Notes 1. The value must also be equal to or less than fMCK/4. 2. Condition in HS (high-speed main) mode 3. Use it with VDD Vb. 4. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 53 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr RL78 microcontroller User device SCL SCLr Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT tSU : DAT Remarks 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 10), g: PIM, POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 54 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.5.2 Serial interface IICA (1) I2C standard mode (1/2) (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter SCLA0 clock Symbol fSCL frequency Conditions tSU:STA restart condition Hold time Note 1 Hold time when tLOW SCLA0 = "L" Hold time when SCLA0 = "H" main) Mode MIN. MAX. MIN. MAX. MIN. MAX. Unit 2.7 V VDD 5.5 V 0 100 0 100 0 100 kHz 1.8 V (2.4 V ) 0 100 0 100 0 100 kHz 1.6 V VDD 5.5 V - - - - 0 100 kHz Note 3 VDD 5.5 V 2.7 V VDD 5.5 V ) VDD 5.5 V Note 3 4.7 4.7 4.7 s 4.7 4.7 4.7 s 4.7 s 1.6 V VDD 5.5 V - 2.7 V VDD 5.5 V 4.0 4.0 4.0 s 1.8 V (2.4 VNote 3) VDD 5.5 V 4.0 4.0 4.0 s 4.0 s - - - 1.6 V VDD 5.5 V - 2.7 V VDD 5.5 V 4.7 4.7 4.7 s 4.7 4.7 4.7 s 4.7 s 1.8 V (2.4 V tHIGH LV (low-voltage main) Mode mode: fCLK 1.8 V (2.4 V tHD:STA LS (low-speed main) Mode Normal 1 MHz Setup time of HS (high-speed ) VDD 5.5 V Note 3 - - - 1.6 V VDD 5.5 V - 2.7 V VDD 5.5 V 4.0 4.0 4.0 s 4.0 4.0 4.0 s 4.0 s 1.8 V (2.4 V ) VDD 5.5 V Note 3 1.6 V VDD 5.5 V - - - - - - - (Notes, Caution and Remark are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 55 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (1) I2C standard mode (2/2) (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Data setup time tSU:DAT (reception) 2.7 V VDD 5.5 V 1.8 V (2.4 V Data hold time tHD:DAT (transmission)Note 2 Setup time of stop tSU:STO tBUF Caution MAX. 250 250 250 ns 250 250 250 ns ns - - 250 2.7 V VDD 5.5 V 0 3.45 0 3.45 0 3.45 s 0 3.45 0 3.45 0 3.45 s 1.6 V VDD 5.5 V - - - - 0 3.45 s 2.7 V VDD 5.5 V 4.0 4.0 4.0 s 4.0 4.0 4.0 s 4.0 s ) VDD 5.5 V Note 3 ) VDD 5.5 V Note 3 1.6 V VDD 5.5 V - 2.7 V VDD 5.5 V 4.7 4.7 4.7 s 4.7 4.7 4.7 s 4.7 s ) VDD 5.5 V Note 3 1.6 V VDD 5.5 V 3. MIN. - 1.8 V (2.4 V Notes 1. 2. MAX. - 1.8 V (2.4 V Bus-free time MIN. 1.6 V VDD 5.5 V 1.8 V (2.4 V condition ) VDD 5.5 V Note 3 MAX. Unit - - - - - - - The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Condition in HS (high-speed main) mode The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 56 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (2) I2C fast mode (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter SCLA0 clock Symbol fSCL frequency Conditions Fast 2.7 V VDD mode: fCLK 5.5 V 3.5 MHz 1.8 V (2.4 VNote 3) HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. 0 400 0 400 0 400 kHz 0 400 0 400 0 400 kHz VDD 5.5 V Setup time of tSU:STA restart condition Hold time Note 1 Hold time when 2.7 V VDD 5.5 V 1.8 V (2.4 V tHD:STA tLOW SCLA0 ="L" tHIGH SCLA0 ="H" tSU:DAT (reception) tHD:DAT Setup time of stop tSU:STO condition tBUF 3. Caution 0.6 0.6 0.6 s 0.6 0.6 s 0.6 0.6 s 2.7 V VDD 5.5 V 1.3 1.3 1.3 s 1.3 1.3 1.3 s 0.6 0.6 0.6 s 0.6 0.6 0.6 s 100 100 100 ns 100 100 100 ns ) VDD 5.5 V Note 3 2.7 V VDD 5.5 V ) VDD 5.5 V Note 3 2.7 V VDD 5.5 V ) VDD 5.5 V Note 3 2.7 V VDD 5.5 V 0 0.9 0 0.9 0 0.9 s 1.8 V (2.4 VNote 3) VDD 5.5 V 0 0.9 0 0.9 0 0.9 s 2.7 V VDD 5.5 V ) VDD 5.5 V Note 3 2.7 V VDD 5.5 V 1.8 V (2.4 V Notes 1. 2. s 0.6 1.8 V (2.4 V Bus-free time 0.6 0.6 1.8 V (2.4 V Data hold time (transmission)Note 2 0.6 2.7 V VDD 5.5 V 1.8 V (2.4 V Data setup time 0.6 1.8 V (2.4 VNote 3) VDD 5.5 V 1.8 V (2.4 V Hold time when ) VDD 5.5 V Note 3 ) VDD 5.5 V Note 3 0.6 0.6 0.6 s 0.6 0.6 0.6 s 1.3 1.3 1.3 s 1.3 1.3 1.3 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Condition in HS (high-speed main) mode The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 k R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 57 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (3) I2C fast mode plus (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCLA0 clock Conditions fSCL frequency Fast mode 2.7 V VDD plus: fCLK 5.5 V HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. MAX. 0 1000 MIN. MAX. MIN. Unit MAX. - - kHz 10 MHz tSU:STA 2.7 V VDD 5.5 V 0.26 - - s Hold timeNote 1 tHD:STA 2.7 V VDD 5.5 V 0.26 - - s Hold time when tLOW 2.7 V VDD 5.5 V 0.5 - - s tHIGH 2.7 V VDD 5.5 V 0.26 - - s tSU:DAT 2.7 V VDD 5.5 V 50 - - ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V VDD 5.5 V 0 - - s Setup time of stop tSU:STO 2.7 V VDD 5.5 V 0.26 - - s tBUF 2.7 V VDD 5.5 V 0.5 - - s Setup time of restart condition SCLA0 ="L" Hold time when SCLA0 ="H" Data setup time (reception) 0.45 condition Bus-free time Notes 1. 2. Caution The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing tLOW tR SCLA0 tHD:DAT tHD:STA tHIGH tF tSU:STA tHD:STA tSU:STO tSU:DAT SDAA0 tBUF Stop condition Start condition R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Restart condition Stop condition Page 58 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Input channel Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Reference voltage (-) = AVREFM Reference voltage (-) = VSS Reference voltage (-) = AVREFM - See 2.6.1 (2). See 2.6.1 (3). ANI0, ANI1 ANI16 to ANI25 See 2.6.1 (1). Internal reference voltage See 2.6.1 (1). - Temperature sensor output voltage (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI16 to ANI25, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Conditions MIN. RES Overall error AINL Note 1 Conversion time tCONV TYP. MAX. Unit 10 bit 1.2 5.0 LSB 1.2 8.5 LSB 8 10-bit resolution 1.8 V AVREFP 5.5 V AVREFP = VDDNote 3 1.6 V AVREFP 5.5 V 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s Target pin: 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target pin: Internal 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 0.35 %FSR 0.60 %FSR 0.35 %FSR 0.60 %FSR 3.5 LSB ANI16 to ANI25 reference voltage, and temperature Note 4 sensor output voltage (HS (high-speed main) mode) Zero-scale error Notes 1, 2 Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity errorNote 1 Analog input voltage EZS EFS ILE DLE VAIN 10-bit resolution 1.8 V AVREFP 5.5 V AVREFP = VDDNote 3 1.6 V AVREFP 5.5 V 10-bit resolution 1.8 V AVREFP 5.5 V AVREFP = VDDNote 3 1.6 V AVREFP 5.5 V 10-bit resolution 1.8 V AVREFP 5.5 V AVREFP = VDDNote 3 1.6 V AVREFP 5.5 V 6.0 LSB 10-bit resolution 1.8 V AVREFP 5.5 V 2.0 LSB AVREFP = VDDNote 3 1.6 V AVREFP 5.5 VNote 4 2.5 LSB AVREFP V Note 4 Note 4 Note 4 ANI16 to ANI25 Internal reference voltage 0 VBGR Note 5 V (2.4 V VDD 5.5 V, HS (high-speed main) mode)) Temperature sensor output voltage VTMPS25Note 5 V (2.4 V VDD 5.5 V, HS (high-speed main) mode)) (Notes are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 59 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 4 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.2%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2 LSB to the MAX. value when AVREFP = VDD. 4. Values when the conversion time is set to 57 s (min.) and 95 s (max.). 5. See 2.6.2 Temperature sensor/internal reference voltage characteristics. (2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pins: ANI0, ANI1, ANI16 to ANI25, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution Conditions MIN. RES Overall error AINL Notes 1, 2 tCONV MAX. Unit 10 bit 1.2 7.0 LSB 1.2 10.5 LSB 8 10-bit resolution 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Conversion time TYP. Note 3 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s Target pin: 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target pin: Internal 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 0.60 %FSR 0.85 %FSR 0.60 %FSR 0.85 %FSR 4.0 LSB ANI0, ANI1, ANI16 to ANI25Note 3 reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) Zero-scale error Notes 1, 2 EZS 10-bit resolution 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Full-scale error Notes 1, 2 EFS 10-bit resolution 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Integral linearity error Note 1 ILE 10-bit resolution 10-bit resolution 1 Analog input voltage VAIN Note 3 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Differential linearity error Note DLE Note 3 6.5 LSB 1.8 V VDD 5.5 V 2.0 LSB 1.6 V VDD 5.5 VNote 3 2.5 LSB VDD V Note 3 ANI0, ANI1, ANI16 to ANI25 0 Internal reference voltage VBGR Note 4 V (2.4 V VDD 5.5 V, HS (high-speed main) mode)) Temperature sensor output voltage VTMPS25Note 4 V (2.4 V VDD 5.5 V, HS (high-speed main) mode)) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Values when the conversion time is set to 57 s (min.) and 95 s (max.). 4. See 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 60 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (3) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI0, ANI16 to ANI25 (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGRNote 3, Reference voltage (-) = AVREFMNote 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES Conversion time tCONV 8-bit resolution 2.4 V VDD 5.5 V 39 s Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB Differential linearity error DLE 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB Note 1 Analog input voltage 8 VAIN bit 17 0 VBGR Note 3 V Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. See 2.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the AVREFM MAX. value. Integral linearity error: Add 0.5 LSB to the AVREFM MAX. value. Differential linearity error: Add 0.2 LSB to the AVREFM MAX. value. 2.6.2 Temperature sensor /internal reference voltage characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 ADS register = 80H, TA = +25C Internal reference output voltage VBGR ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the MIN. TYP. MAX. 1.05 1.38 1.45 Unit V 1.5 -3.6 V mV/C temperature Operation stabilization wait time R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 tAMP 5 s Page 61 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.6.3 Comparator characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V ) Parameter Symbol Input voltage range Conditions MIN. Ivref TYP. 0 MAX. Unit VDD - V 1.4 -0.3 Ivcmp VDD + V 0.3 Output delay td VDD = 3.0 V Comparator high-speed mode, Input slew rate > 50 mV/s standard mode 1.2 s 2.0 s 3.0 5.0 s 0.66VDD 0.76VDD 0.86VDD V 0.14VDD 0.24VDD 0.34VDD V Comparator high-speed mode, window mode Comparator low-speed mode, standard mode High-electric-potential VTW+ Comparator high-speed mode, window mode reference voltage Low-electric-potential VTW- reference voltage Operation stabilization Comparator high-speed mode, window mode tCMP s 100 wait time Internal reference VBGR 2.4 V VDD 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V output voltageNote Note Cannot be used in LS (low-speed main) mode, LV (low-voltage main) mode, subsystem clock operation, and STOP mode. 2.6.4 POR circuit characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Note Symbol Conditions MIN. TYP. MAX. Unit VPOR When power supply rises 1.47 1.51 1.55 V VPDR When power supply falls 1.46 1.50 1.54 V TPW s 300 Note This is the time required for the POR circuit to execute a reset operation when VDD falls below VPDR. When the microcontroller enters STOP mode and when the main system clock (fMAIN) has been stopped by setting bit 0 (HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required for the POR circuit to execute a reset operation between when VDD falls below 0.7 V and when VDD rises to VPOR or higher. TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 62 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.6.5 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection Supply voltage level Symbol VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 VLVD13 Minimum pulse width Detection delay time R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 tLW Conditions MIN. TYP. MAX. Unit When power supply rises 3.98 4.06 4.14 V When power supply falls 3.90 3.98 4.06 V When power supply rises 3.68 3.75 3.82 V When power supply falls 3.60 3.67 3.74 V When power supply rises 3.07 3.13 3.19 V When power supply falls 3.00 3.06 3.12 V When power supply rises 2.96 3.02 3.08 V When power supply falls 2.90 2.96 3.02 V When power supply rises 2.86 2.92 2.97 V When power supply falls 2.80 2.86 2.91 V When power supply rises 2.76 2.81 2.87 V When power supply falls 2.70 2.75 2.81 V When power supply rises 2.66 2.71 2.76 V When power supply falls 2.60 2.65 2.70 V When power supply rises 2.56 2.61 2.66 V When power supply falls 2.50 2.55 2.60 V When power supply rises 2.45 2.50 2.55 V When power supply falls 2.40 2.45 2.50 V When power supply rises 2.05 2.09 2.13 V When power supply falls 2.00 2.04 2.08 V When power supply rises 1.94 1.98 2.02 V When power supply falls 1.90 1.94 1.98 V When power supply rises 1.84 1.88 1.91 V When power supply falls 1.80 1.84 1.87 V When power supply rises 1.74 1.77 1.81 V When power supply falls 1.70 1.73 1.77 V When power supply rises 1.64 1.67 1.70 V When power supply falls 1.60 1.63 1.66 V s 300 300 s Page 63 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVD13 mode VLVD12 VLVD11 VLVD4 VLVD11 VLVD10 VLVD9 VLVD2 VLVD8 VLVD7 VLVD6 VLVD1 VLVD5 VLVD4 VLVD3 VLVD0 Conditions VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage LVIS1, LVIS0 = 1, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 Rising release reset voltage LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 Unit 1.60 1.63 1.66 V 1.74 1.77 1.81 V 1.70 1.73 1.77 Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V 1.80 1.84 1.87 V Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V 2.40 2.45 2.50 V Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V 2.70 2.75 2.81 V Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage LVIS1, LVIS0 = 1, 0 MAX. Falling interrupt voltage VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage LVIS1, LVIS0 = 1, 0 TYP. V VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage LVIS1, LVIS0 = 1, 0 MIN. Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V MIN. TYP. MAX. Unit 54 V/ms 2.6.6 Supply voltage rising slope characteristics (TA = -40 to +85C, VSS = 0 V) Parameter VDD rising slope Symbol Conditions SVDD Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.4 AC Characteristics. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 64 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.7 LCD Characteristics 2.7.1 External resistance division method (1) Static display mode (TA = -40 to +85C, VL4 (MIN.) VDD 5.5 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.0 MAX. Unit VDD V MAX. Unit VDD V MAX. Unit VDD V (2) 1/2 bias method, 1/4 bias method (TA = -40 to +85C, VL4 (MIN.) VDD 5.5 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.7 (3) 1/3 bias method (TA = -40 to +85C, VL4 (MIN.) VDD 5.5 V, VSS = 0 V) Parameter LCD drive voltage R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Symbol VL4 Conditions MIN. 2.5 TYP. Page 65 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.7.2 Internal voltage boosting method (1) 1/3 bias method (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions MIN. TYP. MAX. Unit C1 to C4Note 1 VLCD = 04H 0.90 1.00 1.08 V = 0.47 FNote 2 VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage VL2 C1 to C4Note 1 = 0.47 F 2 VL1 - 0.10 2 VL1 2 VL1 V Tripler output voltage VL4 C1 to C4Note 1 = 0.47 F 3 VL1 - 0.15 3 VL1 3 VL1 V Reference voltage setup time Voltage boost wait time Note 2 Note 3 tVWAIT1 tVWAIT2 C1 to C4 Note 1 = 0.47 F 5 ms 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F 30 % 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 66 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 (2) 1/4 bias method (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions MIN. TYP. MAX. Unit C1 to C5 VLCD = 04H 0.90 1.00 1.08 V = 0.47 FNote 2 VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V Note 1 Doubler output voltage VL2 C1 to C5Note 1 = 0.47 F 2 VL1-0.08 2 VL1 2 VL1 V Tripler output voltage VL3 C1 to C5 = 0.47 F 3 VL1-0.12 3 VL1 3 VL1 V Quadruply output voltage VL4 C1 to C5 = 0.47 F 4 VL1-0.16 4 VL1 4 VL1 V Reference voltage setup time Voltage boost wait time Note 2 Note 3 Note 1 Note 1 tVWAIT1 tVWAIT2 C1 to C5 Note 1 = 0.47 F 5 ms 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 F 30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). 2.7.3 Capacitor split method (1) 1/3 bias method (TA = -40 to +85C, 2.2 V VD 5.5 V, VSS = 0 V) Parameter Symbol Conditions VL4 voltage VL4 C1 to C4 = 0.47 F VL2 voltage VL2 C1 to C4 = 0.47 F MIN. Note 2 TYP. 2/3 VL4 - 2/3 VL4 0.1 VL1 voltage VL1 C1 to C4 = 0.47 FNote 2 1/3 VL4 - 0.1 Capacitor split wait timeNote 1 Notes 1. 2. tVWAIT MAX. VDD Note 2 100 Unit V 2/3 VL4 + V 0.1 1/3 VL4 1/3 VL4 + V 0.1 ms This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F 30% R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 67 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 <R> 2.8 RAM Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention supply voltage Conditions VDDDR MIN. TYP. 1.46Note MAX. Unit 5.5 V <R> Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. <R> Caution Data in RAM are not retained if the CPU operates outside the specified operating voltage range. Therefore, place the CPU in STOP mode before the operating voltage drops below the specified range. Operation mode STOP mode RAM data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.9 Flash Memory Programming Characteristics (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol System clock frequency Number of code flash rewrites Notes 1, 2, 3 Conditions fCLK 1.8 V VDD 5.5 V Cerwr Retained for 20 years MIN. TYP. 1 MAX. Unit 24 MHz 1,000 Times TA = 85C Retained for 1 year Number of data flash rewritesNotes 1, 2, 3 1,000,000 TA = 25C Retained for 5 years 100,000 TA = 85C Retained for 20 years 10,000 TA = 85C Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test. Remark When updating data multiple times, use the flash memory as one for updating data. 2.10 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 68 of 123 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RL78/L13 2.11 Timing Specifications for Switching Flash Memory Programming Modes (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Time to complete the tSUINIT Conditions MIN. TYP. POR and LVD reset must be released before MAX. Unit 100 ms the external reset is released. communication for the initial setting after the external reset is released Time to release the external reset tSU POR and LVD reset must be released before 10 s 1 ms the external reset is released. after the TOOL0 pin is set to the low level Time to hold the TOOL0 pin at the tHD POR and LVD reset must be released before the external reset is released. low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET 723 s + tHD 00H reception processing (TOOLRxD, TOOLTxD mode) time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and completion the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 69 of 123 RL78/L13 3. 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) This chapter describes the following electrical specifications. Target products G: Industrial applications TA = -40 to +105C R5F10WLAGFB, R5F10WLCGFB, R5F10WLDGFB, R5F10WLEGFB, R5F10WLFGFB, R5F10WLGGFB R5F10WMAGFB, R5F10WMCGFB, R5F10WMDGFB, R5F10WMEGFB, R5F10WMFGFB, R5F10WMGGFB Cautions 1. The RL78/L13 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 With functions for each product in the RL78/L13 User's Manual. 3. Consult Renesas salesperson and distributor for derating when the product is used at TA = +85C to +105C. Note that derating means "systematically lowering the load from the rated value to improve reliability". <R> Remark When RL78/L13 is used in the range of TA = -40 to +85C, see CHAPTER 2 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C). R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 70 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 "G: Industrial applications (TA = -40 to +105C) differ from "A: Consumer applications" in function as follows: Fields of Application A: Consumer applications G: Industrial applications TA = -40 to +85C TA = -40 to +105C Operation mode HS (high-speed main) mode: HS (high-speed main) mode only: operating voltage 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.7 V VDD 5.5 V@1 MHz to 24 MHz range 2.4 V VDD 5.5 V@1 MHz to 16 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Operating ambient temperature LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz High-speed on-chip 1.8 V VDD 5.5 V: oscillator clock 1.0 % @ TA = -20 to +85C 2.4 V VDD 5.5 V: 2.0 % @ TA = +85 to +105C accuracy 1.5 % @ TA = -40 to -20C 1.0 % @ TA = -20 to +85C 1.6 V VDD < 1.8 V: 1.5 % @ TA = -40 to -20C 5.0 % @ TA = -20 to +85C 5.5 % @ TA = -40 to -20C Serial array unit IICA UART UART CSI: fCLK/2 (16 Mbps supported), fCLK/4 CSI: fCLK/4 Simplified I2C Simplified I2C Standard mode Standard mode Fast mode Fase mode Fast mode plus Voltage detector Remark * Rising: 1.67 V to 4.06 V (14 levels) * Rising: 2.61 V to 4.06 V (8 levels) * Falling: 1.63 V to 3.98 V (14 levels) * Falling: 2.55 V to 3.98 V (8 levels) Electrical specifications of G: Industrial applications (TA = -40 to +105C) differ from "A: Consumer applications". For details, see 3.1 to 3.11 below. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 71 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (1/3) Parameter Symbol Supply voltage VDD REGC pin input voltage VIREGC Conditions REGC Ratings Unit -0.5 to +6.5 V -0.3 to +2.8 V and -0.3 to VDD +0.3Note 1 Input voltage VI1 P00 to P07, P10 to P17, P20 to P27, P30 to P35, -0.3 to VDD +0.3Note 2 V -0.3 to +6.5 V V P40 to P47, P50 to P57, P60, P61, P70 to P77, P121 to P127, P130, P137 Output voltage VI2 P60 and P61 (N-ch open-drain) VI3 EXCLK, EXCLKS, RESET -0.3 to VDD +0.3 VO1 P00 to P07, P10 to P17, P20 to P27, P30 to P35, -0.3 to VDD +0.3 Note 2 Note 2 V P40 to P47, P50 to P57, P60, P61, P70 to P77, P121 to P127, P130, P137 Analog input voltage VAI1 ANI0, ANI1, ANI16 to ANI26 -0.3 to VDD +0.3 V and -0.3 to AVREF(+) +0.3Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+): + side reference voltage of the A/D converter. 3. VSS: Reference voltage R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 72 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 Absolute Maximum Ratings (2/3) Parameter LCD voltage Symbol VL1 Conditions VL1 voltage Note 1 Ratings Unit -0.3 to +2.8 and V -0.3 to VL4 +0.3 VL2 VL2 voltageNote 1 -0.3 to VL4 +0.3Note 2 V VL3 VL3 voltageNote 1 -0.3 to VL4 +0.3Note 2 V VL4 VL4 voltageNote 1 -0.3 to +6.5 V VLCAP CAPL, CAPH voltage -0.3 to VL4 +0.3 V VOUT COM0 to COM7 External resistance division method SEG0 to SEG50 output voltage Note 1 Note 2 -0.3 to VDD +0.3 Note 2 V Capacitor split method -0.3 to VDD +0.3 Note 2 V Internal voltage boosting method -0.3 to VL4 +0.3 Note 2 V Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 F 30%) and connect a capacitor (0.47 F 30%) between the CAPL and CAPH pins. 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark VSS: Reference voltage R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 73 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) Absolute Maximum Ratings (TA = 25C) (3/3) Parameter <R> Output current, high Symbol IOH1 Conditions Per pin P00 to P07, P10 to P17, P22 to P27, Ratings Unit -40 mA -170 mA -0.5 mA P30 to P35, P40 to P47, P50 to P57, P60, P61, P70 to P77, P125 to P127, P130 <R> Total of all pins P00 to P07, P10 to P17, P22 to P27, -170 mA P30 to P35, P40 to P47, P50 to P57, P60, P61, P70 to P77, P125 to P127, P130 <R> IOH2 Per pin P20, P21 Total of all pins <R> Output current, low IOL1 Per pin P00 to P07, P10 to P17, P22 to P27, -1 mA 40 mA P30 to P35, P40 to P47, P50 to P57, P60, P61, P70 to P77, P125 to P127, P130 <R> Total of all pins P40 to P47, P130 70 mA 170 mA P00 to P07, P10 to P17, P22 to P27, 100 mA 1 mA 2 mA -40 to +105 C P30 to P35, P50 to P57, P60, P61, P70 to P77, P125 to P127 <R> IOL2 <R> Per pin P20, P21 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode C In flash memory programming mode Tstg -65 to +150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 74 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.2 Oscillator Characteristics 3.2.1 X1 and XT1 oscillator characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit MHz X1 clock oscillation Ceramic resonator/ 2.7 V VDD 5.5 V 1.0 20.0 frequency (fX)Note crystal resonator 2.4 V VDD < 2.7 V 1.0 16.0 XT1 clock oscillation Crystal resonator 32 32.768 35 kHz frequency (fXT)Note Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, see 5.4 System Clock Oscillator in the RL78/L13 User's Manual. 3.2.2 On-chip oscillator characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter High-speed on-chip oscillator Symbol Conditions fIH MIN. TYP. MAX. Unit 1 24 MHz clock frequencyNotes 1, 2 High-speed on-chip oscillator +85 to +105C 2.4 V VDD 5.5 V -2 +2 % clock frequency accuracy -20 to +85C 2.4 V VDD 5.5 V -1 +1 % -40 to -20C 2.4 V VDD 5.5 V -1.5 Low-speed on-chip oscillator fIL +1.5 15 % kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. The high-speed on-chip oscillator frequency is selected by bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of the HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for the instruction execution time. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 75 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.3 DC Characteristics 3.3.1 Pin characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol IOH1 Output current, highNote 1 <R> IOH2 Notes 1. Conditions MIN. TYP. MAX. -3.0 Unit Per pin for P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130 2.4 V VDD 5.5 V Total of P00 to P07, P10 to P17, 4.0 V VDD 5.5 V -45.0 mA P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130 (When duty = 70%Note 3) 2.7 V VDD < 4.0 V -15.0 mA 2.4 V VDD < 2.7 V -7.0 mA Per pin for P20 and P21 2.4 V VDD 5.5 V -0.1Note 2 mA Total of all pins (When duty = 70%Note 3) 2.4 V VDD 5.5 V -0.2 mA Note 2 mA Value of the current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin 2. 3. Do not exceed the total current value. Output current value under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -45.0 mA Total output current of pins = (-45.0 x 0.7)/(80 x 0.01) = -39.375 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, and P130 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 76 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Output current, lowNote 1 IOL1 MAX. Unit Per pin for P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130 Conditions 8.5Note 2 mA Per pin for P60 and P61 15.0Note 2 mA 40.0 mA 2.7 V VDD < 4.0 V 15.0 mA 2.4 V VDD < 2.7 V 9.0 mA 4.0 V VDD 5.5 V 60.0 mA 2.7 V VDD < 4.0 V 35.0 mA 2.4 V VDD < 2.7 V 20.0 mA Total of all pins (When duty = 70%Note 3) 100.0 mA Per pin for P20 and P21 0.4Note 2 mA 0.8 mA Total of P00 to P07, P10 to P17, P22 to P27, P30 to P35, P50 to P57, P70 to P77, P125 to P127 (When duty = 70%Note 3) Total of all pins (When duty = 70%Note 3) Notes 1. TYP. 4.0 V VDD 5.5 V Total of P40 to P47, P130 (When duty = 70%Note 3) IOL2 MIN. 2.4 V VDD 5.5 V Value of the current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin 2. Do not exceed the total current value. 3. Output current value under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 40.0 mA Total output current of pins = (40.0 x 0.7)/(80 x 0.01) = 35.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 77 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Input voltage, Symbol VIH1 Conditions P00 to P07, P10 to P17, P22 to P27, MIN. Normal input buffer TYP. MAX. Unit 0.8VDD VDD V 2.2 VDD V 2.0 VDD V 1.5 VDD V P30 to P35, P40 to P47, P50 to P57, high P70 to P77, P125 to P127, P130, P137 VIH2 P03, P05, P06, P16, P17, P34, P43, TTL input buffer P44, P46, P47, P53, P55 4.0 V VDD 5.5 V TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 2.4 V VDD < 3.3 V VIH3 P20, P21 0.7VDD VDD V VIH4 P60, P61 0.7VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V Normal input buffer 0 0.2VDD V P03, P05, P06, P16, P17, P34, P43, TTL input buffer 0 0.8 V P44, P46, P47, P53, P55 4.0 V VDD 5.5 V 0 0.5 V 0 0.32 V Input voltage, low VIL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130, P137 VIL2 TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 2.4 V VDD < 3.3 V VIL3 P20, P21 0 0.3VDD V VIL4 P60, P61 0 0.3VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, and P130 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 78 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Output voltage, VOH1 high Conditions MIN. P00 to P07, P10 to P17, P22 to P27, 4.0 V VDD 5.5 V, P30 to P35, P40 to P47, P50 to P57, IOH1 = -3.0 mA P70 to P77, P125 to P127, P130 2.7 V VDD 5.5 V, TYP. MAX. Unit VDD - 0.7 V VDD - 0.6 V VDD - 0.5 V VDD - 0.5 V IOH1 = -2.0 mA 2.4 V VDD 5.5 V, IOH1 = -1.5 mA VOH2 P20 and P21 2.4 V VDD 5.5 V, IOH2 = -100 A Output voltage, VOL1 low P00 to P07, P10 to P17, P22 to P27, 4.0 V VDD 5.5 V, P30 to P35, P40 to P47, P50 to P57, IOL1 = 8.5 mA P70 to P77, P125 to P127, P130 2.7 V VDD 5.5 V, 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V IOL1 = 3.0 mA 2.7 V VDD 5.5 V, IOL1 = 1.5 mA 2.4 V VDD 5.5 V, IOL1 = 0.6 mA VOL2 P20 and P21 2.4 V VDD 5.5 V, IOL2 = 400 A VOL3 P60 and P61 4.0 V VDD 5.5 V, IOL3 = 15.0 mA 4.0 V VDD 5.5 V, IOL3 = 5.0 mA 2.7 V VDD 5.5 V, IOL3 = 3.0 mA 2.4 V VDD 5.5 V, IOL3 = 2.0 mA Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, and P130 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 79 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Input leakage ILIH1 Conditions P00 to P07, P10 to P17, MIN. TYP. MAX. Unit VI = VDD 1 A 1 A 1 A 10 A VI = VSS -1 A -1 A -1 A -10 A P22 to P27, P30 to P35, current, high P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130, P137 ILIH2 P20 and P21, RESET VI = VDD ILIH3 P121 to P124 VI = VDD In input port (X1, X2, XT1, XT2, EXCLK, mode and EXCLKS) when external clock is input Resonator connected Input leakage ILIL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, current, low P40 to P47, P50 to P57, P70 to P77, P125 to P127, P130, P137 ILIL2 P20 and P21, RESET VI = VSS ILIL3 P121 to P124 VI = VSS In input port (X1, X2, XT1, XT2, EXCLK, mode and EXCLKS) when external clock is input Resonator connected On-chip pull-up RU1 P00 to P07, P10 to P17, VI = VSS 10 20 100 k VI = VSS 10 20 100 k P22 to P27, P30 to P35, resistance P45 to P47, P50 to P57, P70 to P77, P125 to P127, P130 RU2 Remark P40 to P44 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 80 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.3.2 Supply current characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply I current Note 1 DD1 (1/2) Conditions Operating HS (high- fHOCO = 48 MHz mode speed main) 3 modeNote 5 fIH = 24 MHzNote 3 MIN. Note , Basic operation Normal operation fHOCO = 24 MHz Note Basic operation , 3 fIH = 24 MHzNote 3 Normal operation fHOCO = 16 MHz Note Normal operation , 3 fIH = 16 MHzNote 3 TYP. MAX. Unit VDD = 5.0 V 2.0 mA VDD = 3.0 V 2.0 mA VDD = 5.0 V 3.8 7.0 mA VDD = 3.0 V 3.8 7.0 mA VDD = 5.0 V 1.7 mA VDD = 3.0 V 1.7 mA VDD = 5.0 V 3.6 6.5 mA VDD = 3.0 V 3.6 6.5 mA VDD = 5.0 V 2.7 5.0 mA VDD = 3.0 V 2.7 5.0 mA HS (high- fMX = 20 MHzNote 2, Normal Square wave input 3.0 5.4 mA speed main) VDD = 5.0 V operation Resonator connection 3.2 5.6 mA Normal 5.4 mA modeNote 5 fMX = 20 MHz , Square wave input 2.9 VDD = 3.0 V operation Resonator connection 3.2 5.6 mA fMX = 10 MHzNote 2, Normal Square wave input 1.9 3.2 mA VDD = 5.0 V operation Resonator connection 1.9 3.2 mA fMX = 10 MHz Note 2 Normal Square wave input 1.9 3.2 mA VDD = 3.0 V , operation Resonator connection 1.9 3.2 mA Subsystem fSUB = Normal Square wave input 4.0 5.4 A clock 32.768 kHzNote 4, operation operation TA = -40C Resonator connection 4.3 5.4 A fSUB = Normal Square wave input 4.0 5.4 A 32.768 kHz Note 4, operation Resonator connection 4.3 5.4 A fSUB = Normal Square wave input 4.1 7.1 A 32.768 kHzNote 4, operation Resonator connection 4.4 7.1 A fSUB = Normal Square wave input 4.3 8.7 A 32.768 kHzNote 4, operation Resonator connection 4.7 8.7 A fSUB = Normal Square wave input 4.7 12.0 A 32.768 kHzNote 4, operation Resonator connection 5.2 12.0 A fSUB = Normal Square wave input 6.4 35.0 A 32.768 kHzNote 4, operation Resonator connection 6.6 35.0 A Note 2 TA = +25C TA = +50C TA = +70C TA = +85C TA = +105C (Notes and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 81 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, onchip pull-up/pull-down resistors, and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When setting ultra-low power consumption oscillation (AMPHS1 = 1). The current flowing into the LCD controller/driver, 16-bit timer KB20, real-time clock 2, 12-bit interval timer, and watchdog timer is not included. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.) 3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 82 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply I Note 2 DD2 Conditions HALT mode current Note 1 (2/2) HS (highspeed main) modeNote 7 fHOCO = 48 MHz MIN. Note 4 , fIH = 24 MHzNote 4 fHOCO = 24 MHz Note 4 , fIH = 24 MHzNote 4 fHOCO = 16 MHz Note 4 , fIH = 16 MHzNote 4 HS (highspeed main) modeNote 7 fMX = 20 MHz , Note 3 VDD = 5.0 V fMX = 20 MHz , Note 3 VDD = 3.0 V fMX = 10 MHz VDD = 5.0 V 0.71 2.55 mA VDD = 3.0 V 0.71 2.55 mA VDD = 5.0 V 0.49 1.95 mA VDD = 3.0 V 0.49 1.95 mA VDD = 5.0 V 0.43 1.50 mA VDD = 3.0 V 0.43 1.50 mA Square wave input 0.31 1.76 mA Resonator connection 0.48 1.92 mA Square wave input 0.29 1.76 mA Resonator connection 0.48 1.92 mA 0.20 0.96 mA Square wave input Resonator connection 0.28 1.07 mA fMX = 10 MHzNote 3, Square wave input 0.19 0.96 mA VDD = 3.0 V Resonator connection 0.28 1.07 mA Square wave input 0.34 0.62 A Resonator connection 0.51 0.80 A Square wave input 0.38 0.62 A Resonator connection 0.57 0.80 A fSUB = 32.768 kHz clock TA = -40C fSUB = 32.768 kHz Note 5 Note 5 , , Square wave input 0.46 2.30 A TA = +50C Resonator connection 0.67 2.49 A fSUB = 32.768 kHzNote 5, Square wave input 0.65 4.03 A TA = +70C Resonator connection 0.91 4.22 A Square wave input 1.00 8.04 A Resonator connection 1.31 8.23 A Square wave input 3.05 27.00 A Resonator connection 3.24 27.00 A fSUB = 32.768 kHz fSUB = 32.768 kHz Note 5 Note 5 , , TA = +85C fSUB = 32.768 kHz TA = +105C I Unit , TA = +25C Note 6 DD3 MAX. VDD = 5.0 V Note 3 Subsystem operation TYP. Note 5 , STOP TA = -40C 0.18 0.52 A modeNote 8 TA = +25C 0.24 0.52 A TA = +50C 0.33 2.21 A TA = +70C 0.53 3.94 A TA = +85C 0.93 7.95 A TA = +105C 2.91 25.00 A (Notes and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 83 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, onchip pull-up/pull-down resistors, and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the realtime clock 2 is included. The current flowing into the clock output/buzzer output, 12-bit interval timer, and watchdog timer is not included. 6. The current flowing into the real-time clock 2, clock output/buzzer output, 12-bit interval timer, and watchdog timer is not included. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.) 3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25C R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 84 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Low-speed on- Symbol I Conditions MIN. Note 1 FIL TYP. MAX. Unit 0.20 A 0.02 A 0.04 A 0.22 A chip oscillator operating current RTC2 operating IRTCNotes 1, 2, 3 fSUB = 32.768 kHz current 12-bit interval ITMKANotes 1, 2, 4 timer operating current Watchdog timer IWDTNotes 1, 2, 5 fIL = 15 kHz A/D converter operating current IADCNotes 1, 6 When conversion at maximum speed A/D converter reference voltage current IADREFNote 1 75.0 A Temperature sensor operating current ITMPSNote 1 75.0 A LVD operating ILVDNotes 1, 7 0.08 A Window mode 12.5 A Comparator high-speed mode 6.5 A Comparator low-speed mode 1.7 A Window mode 8.0 A Comparator high-speed mode 4.0 A Comparator low-speed mode 1.3 A operating current Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V 1.3 1.7 mA 0.5 0.7 mA current Comparator operating current ICMPNotes 1, 11 VDD = 5.0 V, Regulator output voltage = 2.1 V VDD = 5.0 V, Regulator output voltage = 1.8 V Selfprogramming operating current I Notes 1, 9 FSP 2.00 12.20 mA BGO operating IBGONotes 1, 8 2.00 12.20 mA While the mode is shiftingNote 10 0.50 0.60 mA During A/D conversion, in low voltage 1.20 1.44 mA 0.70 0.84 mA 0.04 0.20. A 0.85 2.20 A 1.55 3.70 A 0.20 0.50 A current SNOOZE ISNOZNote 1 ADC operation operating current mode, AVREFP = VDD = 3.0 V CSI/UART operation LCD operating I External resistance fLCD = fSUB 1/3 bias, VDD = 5.0 V, current 13 division method LCD clock = 128 Hz four time slices VL4 = 5.0 V ILCD2Note 1, 12 Internal voltage fLCD = fSUB 1/3 bias, VDD = 3.0 V, boosting method LCD clock = 128 Hz four time slices VL4 = 3.0 V Notes 1, 12, LCD1 (VLCD = 04H) VDD = 5.0 V, VL4 = 5.1 V (VLCD = 12H) I Note 1, 12 LCD3 Capacitor split fLCD = fSUB 1/3 bias, VDD = 3.0 V, method LCD clock = 128 Hz four time slices VL4 = 3.0 V (Notes and Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 85 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock 2 operates in operation mode or HALT mode. When the lowspeed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of real-time clock 2. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 6. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. Current flowing only during data flash rewrite. Current flowing only during self programming. For shift time to the SNOOZE mode, see 21.3.3 SNOOZE mode in the RL78/L13 User's Manual. Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates. 12. Current flowing only to the LCD controller/driver. The value of the current for the RL78 microcontrollers is the sum of the supply current (IDD1 or IDD2) and LCD operating current (ILCD1, ILCD2, or ILCD3), when the LCD controller/driver operates in operation mode or HALT mode. However, not including the current flowing into the LCD panel. Conditions of the TYP. value and MAX. value are as follows. * Setting 20 pins as the segment function and blinking all * Selecting fSUB for system clock when LCD clock = 128 Hz (LCDC0 = 07H) * Setting four time slices and 1/3 bias 13. Not including the current flowing into the external division resistor when using the external resistance division method. 8. 9. 10. 11. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. The temperature condition for the TYP. value is TA = 25C. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 86 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.4 AC Characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. TYP. MAX. Unit Main system HS (high-speed 2.7 V VDD 5.5 V 0.0417 1 s clock (fMAIN) main) mode 2.4 V VDD < 2.7 V 0.0625 1 s 2.4 V VDD 5.5 V 28.5 31.3 s operation Subsystem clock (fSUB) 30.5 operation In the self HS (high-speed 2.7 V VDD 5.5 V 0.0417 1 s programming main) mode 2.4 V VDD < 2.7 V 0.0625 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD < 2.7 V 1.0 16.0 MHz 32 35 kHz 2.7 V VDD 5.5 V 24 ns 2.4 V VDD < 2.7 V 30 ns 13.7 s 1/fMCK+ ns mode External system clock fEX frequency fEXS External system clock input tEXH, tEXL high-level width, low-level width TI00 to TI07 input high-level tEXHS, tEXLS tTIH, tTIL width, low-level width TO00 to TO07, TKBO00Note, 10 fTO TKBO01-0 to TKBO01-2Note HS (high-speed main) 4.0 V VDD 5.5 V 12 MHz mode 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz HS (high-speed main) 4.0 V VDD 5.5 V 16 MHz mode 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz output frequency PCLBUZ0, PCLBUZ1 output fPCL frequency Interrupt input high-level tINTH, tINTL INTP0 to INTP7 2.4 V VDD 5.5 V 1 s tKRH, tKRL KR0 to KR7 2.4 V VDD 5.5 V 250 ns tIHR INTP0 to INTP7 2 fCLK tIHR INTP0 to INTP2 2 fCLK 10 s width, low-level width Key interrupt input high-level width, low-level width IH-PWM output restart input high-level width TMKB2 forced output stop input high-level width RESET low-level width tRSL (Note and Remark are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 87 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 Note Specification under conditions where the duty factor is 50%. Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn) m: Unit number (m = 0), n: Channel number (n = 0 to 7)) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.0417 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] AC Timing Test Points VIH/VOH Test points VIL/VOL VIH/VOH VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS EXCLK/EXCLKS R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 88 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 TI/TO Timing tTIH tTIL TI00 to TI07 1/fTO TO00 to TO07, TKBO00, TKBO01-0, TKBO01-1, TKBO01-2 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 89 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Note Theoretical value of the maximum transfer rate Unit MAX. fMCK/12 bps 2.0 Mbps fCLK = 24 MHz, fMCK = fCLK Note Transfer rate in the SNOOZE mode is 4800 bps only. Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) Rx TxDq RL78 microcontroller User device Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 90 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp)Note 2 334 2.4 V VDD 5.5 V 500 Note 1 MAX. ns ns tKH1, 4.0 V VDD 5.5 V tKCY1/2 - 24 ns tKL1 2.7 V VDD 5.5 V tKCY1/2 - 36 ns 2.4 V VDD 5.5 V tKCY1/2 - 76 ns 4.0 V VDD 5.5 V 66 ns 2.7 V VDD 5.5 V 66 ns 2.4 V VDD 5.5 V 113 ns 38 ns tSIK1 SIp hold time (from SCKp) tKSI1 Delay time from SCKp to tKSO1 Note 3 2.7 V VDD 5.5 V Note 1 Unit C = 30 pF Note 5 50 ns SOp outputNote 4 Notes 1. The value must also be equal to or more than 4/fCLK. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2), g: PIM and POM numbers (g = 0, 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 91 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 5 tKCY2 4.0 V VDD 5.5 V SIp setup time tKH2, tKL2 tSIK2 (to SCKp)Note 1 SIp hold time MAX. fMCK > 20 MHz 16/fMCK ns fMCK 20 MHz 12/fMCK ns fMCK > 16 MHz 16/fMCK ns fMCK 16 MHz 12/fMCK ns 2.4 V VDD 5.5 V 12/fMCK and 1000 ns 2.7 V VDD 5.5 V SCKp high-/low-level width Unit 4.0 V VDD 5.5 V tKCY2/2-14 ns 2.7 V VDD 5.5 V tKCY2/2-16 ns 2.4 V VDD 5.5 V tKCY2/2-36 ns 2.7 V VDD 5.5 V 1/fMCK+40 ns 2.4 V VDD 5.5 V 1/fMCK+60 ns 1/fMCK+62 ns tKSI2 (from SCKp)Note 2 Delay time from SCKp to SOp output tKSO2 C = 30 pFNote 4 Note 3 2.7 V VDD 5.5 V 2/fMCK+66 ns 2.4 V VDD 5.5 V 2/fMCK+113 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2), g: PIM number (g = 0, 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 92 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO SOp SI User device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 10) m: Unit number, n: Channel number (mn = 00, 02) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 93 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (4) During communication at same potential (simplified I2C mode) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency fSCL 2.7 V VDD 5.5 V, Unit MAX. 400Note 1 kHz 100Note 1 kHz Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Hold time when SCLr = "L" tLOW 2.7 V VDD 5.5 V, 1200 ns 4600 ns 1200 ns 4600 ns 1/fMCK + 220Note 2 ns 1/fMCK + 580Note 2 ns Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Hold time when SCLr = "H" tHIGH 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Data setup time (reception) tSU:DAT 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Data hold time (transmission) tHD:DAT 2.7 V VDD 5.5 V, 0 770 ns 0 1420 ns Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). (Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 94 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78 microcontroller User device SCL SCLr Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT tSU : DAT Remarks 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 10), g: PIM and POM number (g = 0, 1) <R> 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0-3), mn = 00-03, 10-13) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 95 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Reception 4.0 V VDD 5.5 V, Unit MAX. fMCK/12Note bps 2.0 Mbps fMCK/12Note bps 2.0 Mbps fMCK/12Note bps 2.0 Mbps 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate fCLK = 24 MHz, fMCK = fCLK 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fCLK = 24 MHz, fMCK = fCLK 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate fCLK = 24 MHz, fMCK = fCLK Note Transfer rate in SNOOZE mode is 4800 bps only. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 96 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Transmission 4.0 V VDD 5.5 V, Unit MAX. Note 1 bps 2.0Note 2 Mbps Note 3 bps 1.2Note 4 Mbps Note 5 bps 0.43Note 6 Mbps 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.2 Vb )} x 3 [bps] 2.2 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.0 Vb )} x 3 [bps] 2.0 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 97 of 123 RL78/L13 Notes 5. 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V VDD < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 1.5 Vb )} x 3 [bps] 1.5 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller RxDq R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 User device Tx Page 98 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 99 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V VDD 5.5 V, Unit MAX. 600 ns 1000 ns 2300 ns tKCY1/2 - 150 ns tKCY1/2 - 340 ns tKCY1/2 - 916 ns tKCY1/2 - 24 ns tKCY1/2 - 36 ns tKCY1/2 - 100 ns 162 ns 354 ns 958 ns 38 ns 38 ns 38 ns 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 1.8 V, Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp setup time tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k (to SCKp)Note 1 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time tKSI1 (from SCKp)Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to tKSO1 SOp outputNote 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 200 ns 390 ns 966 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k (Note, Caution and Remark are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 100 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Unit MAX. 88 ns 88 ns 220 ns 38 ns 38 ns 38 ns Cb = 20 pF, Rb = 1.4 k (to SCKp)Note 2 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time tKSI1 (from SCKp)Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to tKSO1 SOp outputNote 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 50 ns 50 ns 50 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k CSI mode connection diagram (during communication at different potential) <Master> Vb Rb SCKp RL78 microcontroller Vb Rb SCK SIp SO SOp SI User device Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 101 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 Output data SOp CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Remark p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02), g: PIM and POM number (g = 0, 1) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 102 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 1 tKCY2 SIp setup time tKH2, tKL2 tSIK2 (to SCKp)Note 2 SIp hold time tKSI2 (from SCKp)Note 3 Delay time from SCKp to tKSO2 SOp outputNote 4 MAX. 4.0 V VDD 5.5 V, 20 MHz < fMCK 24/fMCK ns 2.7 V Vb 4.0 V 8 MHz < fMCK 20 MHz 20/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 32/fMCK ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 28/fMCK ns 8 MHz < fMCK 16 MHz 24/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 2.4 V VDD < 3.3 V, 20 MHz < fMCK 72/fMCK ns 1.6 V Vb 2.0 V 16 MHz < fMCK 20 MHz 64/fMCK ns 8 MHz < fMCK 16 MHz 52/fMCK ns 4 MHz < fMCK 8 MHz 32/fMCK ns fMCK 4 MHz SCKp high-/low-level width Unit 20/fMCK ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 - 24 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 36 ns 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V tKCY2/2 - 100 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + 40 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 40 ns 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V 1/fMCK + 60 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + 62 ns 2.7 V VDD 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 62 ns 2.4 V VDD 3.3 V, 1.6 V Vb 2.0 V 1/fMCK + 62 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK + 240 ns 2/fMCK + 428 ns 2/fMCK + 1146 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 103 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User device Notes 1. Transfer rate in SNOOZE mode: MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 104 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remarks 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn) m: Unit number, n: Channel number (mn = 00, 02)) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 105 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency fSCL 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Unit MAX. 400Note 1 kHz 400Note 1 kHz 100Note 1 kHz 100Note 1 kHz 100Note 1 kHz Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 1200 ns 1200 ns 4600 ns 4600 ns 4650 ns 620 ns 500 ns 2700 ns 2400 ns 1830 ns Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 106 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Data setup time (reception) Data hold time (transmission) tSU:DAT tHD:DAT Unit MAX. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340Note 2 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340Note 2 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1/fMCK + 760Note 2 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 760Note 2 ns 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 570Note 2 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 1420 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 1420 ns 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V , Cb = 100 pF, Rb = 5.5 k 0 1215 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 107 of 123 RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) Simplified I2C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDA SDAr RL78 microcontroller User device SCL SCLr Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT tSU : DAT Remarks 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 10), g: PIM, POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 108 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.5.2 Serial interface IICA (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Standard Mode Unit Fast Mode MIN. MAX. MIN. MAX. - - 0 400 kHz 0 100 - - kHz Fast mode: fCLK 3.5 MHz SCLA0 clock frequency fSCL Setup time of restart condition tSU:STA 4.7 0.6 s Hold timeNote 1 tHD:STA 4.0 0.6 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s tSU:DAT 250 100 ns Normal mode: fCLK 1 MHz Data setup time (reception) Data hold time (transmission) tHD:DAT Note 2 0 Note 3 3.45 0 Note 3 0.9 s Setup time of stop condition tSU:STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Notes 1. 2. Remark The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k IICA serial transfer timing tLOW tR SCLA0 tHD:DAT tHD:STA tHIGH tF tSU:STA tHD:STA tSU:STO tSU:DAT SDAA0 tBUF Stop condition Start condition R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Restart condition Stop condition Page 109 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.6 Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Input channel Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Reference voltage (-) = AVREFM Reference voltage (-) = VSS Reference voltage (-) = AVREFM - See 3.6.1 (2). See 3.6.1 (3). ANI0, ANI1 ANI16 to ANI25 See 3.6.1 (1). Internal reference voltage See 3.6.1 (1). - Temperature sensor output voltage (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI16 to ANI25, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Resolution Symbol Conditions MIN. RES Overall error Note 1 AINL TYP. 8 10-bit resolution 2.4 V VDD 5.5 V 1.2 MAX. Unit 10 bit 5.0 LSB AVREFP = VDDNote 3 Conversion time tCONV 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target pin: Internal reference 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 2.4 V VDD 5.5 V 0.35 %FSR 2.4 V VDD 5.5 V 0.35 %FSR 2.4 V VDD 5.5 V 3.5 LSB 2.4 V VDD 5.5 V 2.0 LSB AVREFP V 10-bit resolution Target pin: ANI16 to ANI25 voltage, and temperature sensor output voltage (HS (high-speed main) mode) Zero-scale error Notes 1, 2 EZS 10-bit resolution AVREFP = VDDNote 3 Full-scale errorNotes 1, 2 EFS 10-bit resolution AVREFP = VDDNote 3 Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDDNote 3 Differential linearity errorNote 1 DLE 10-bit resolution AVREFP = VDDNote 3 Analog input voltage VAIN ANI16 to ANI25 Internal reference voltage 0 VBGRNote 4 V VTMPS25Note 4 V (2.4 V VDD 5.5 V, HS (high-speed main) mode)) Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode)) (Notes are listed on the next page.) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 110 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 4 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.2%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2 LSB to the MAX. value when AVREFP = VDD. 4. See 3.6.2 Temperature sensor/internal reference voltage characteristics. (2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pins: ANI0, ANI1, ANI16 to ANI25, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution Conditions MIN. RES TYP. 8 MAX. Unit 10 bit Overall error AINL 10-bit resolution 2.4 V VDD 5.5 V 7.0 LSB Conversion time tCONV 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s Target pin: 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 2.375 39 s 3.5625 39 s 17 39 s Note 1 ANI0, ANI1, ANI16 to ANI25 3.6 V VDD 5.5 V Target pin: Internal reference 2.7 V VDD 5.5 V voltage, and temperature 2.4 V VDD 5.5 V sensor output voltage 10-bit resolution 1.2 (HS (high-speed main) mode) Zero-scale error Notes 1, 2 Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Analog input voltage Note 1 EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB VAIN ANI0, ANI1, ANI16 to ANI25 VDD V Internal reference voltage 0 VBGRNote 3 V VTMPS25Note 3 V (2.4 V VDD 5.5 V, HS (high-speed main) mode)) Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode)) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. See 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 111 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (3) When reference voltage (+) = internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI0, ANI16 to ANI25 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGRNote 3, Reference voltage (-) = AVREFMNote 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Resolution RES Conversion time tCONV 8-bit resolution 2.4 V VDD 5.5 V 39 s Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB Differential linearity error DLE 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB Note 1 Analog input voltage 8 Unit 17 VAIN 0 bit VBGR Note 3 V Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. See 3.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the AVREFM MAX. value. Integral linearity error: Add 0.5 LSB to the AVREFM MAX. value. Differential linearity error: Add 0.2 LSB to the AVREFM MAX. value. 3.6.2 Temperature sensor/internal reference voltage characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 ADS register = 80H, TA = +25C Internal reference output voltage VBGR ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the MIN. TYP. MAX. 1.05 1.38 1.45 Unit V 1.5 -3.6 V mV/C temperature Operation stabilization wait time R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 tAMP 5 s Page 112 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.6.3 Comparator (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Input voltage range Conditions MIN. Ivref TYP. 0 MAX. Unit VDD - V 1.4 -0.3 Ivcmp VDD + V 0.3 Output delay td VDD = 3.0 V Input slew rate > 50 mV/s Comparator high-speed mode, standard mode 1.2 s Comparator high-speed mode, window mode 2.0 s 5.0 s Comparator low-speed mode, standard mode High-electric-potential VTW+ Comparator high-speed mode, window mode 0.66VDD 0.76VDD 0.86VDD V VTW- Comparator high-speed mode, window mode 0.14VDD 0.24VDD 0.34VDD V reference voltage Low-electric-potential reference voltage Operation stabilization 3.0 tCMP s 100 wait time Internal reference VBGR 2.4 V VDD 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V output voltageNote Note Cannot be used in subsystem clock operation and STOP mode. 3.6.4 POR circuit characteristics (TA = -40 to +105C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Note Symbol Conditions MIN. TYP. MAX. Unit VPOR When power supply rises 1.45 1.51 1.57 V VPDR When power supply falls 1.44 1.50 1.56 V TPW s 300 Note This is the time required for the POR circuit to execute a reset operation when VDD falls below VPDR. When the microcontroller enters STOP mode and when the main system clock (fMAIN) has been stopped by setting bit 0 (HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required for the POR circuit to execute a reset operation between when VDD falls below 0.7 V and when VDD rises to VPOR or higher. TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 113 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.6.5 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +105C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection Symbol Supply voltage level VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Conditions MIN. TYP. MAX. Unit When power supply rises 3.90 4.06 4.22 V When power supply falls 3.83 3.98 4.13 V When power supply rises 3.60 3.75 3.90 V When power supply falls 3.53 3.67 3.81 V When power supply rises 3.01 3.13 3.25 V When power supply falls 2.94 3.06 3.18 V When power supply rises 2.90 3.02 3.14 V When power supply falls 2.85 2.96 3.07 V When power supply rises 2.81 2.92 3.03 V When power supply falls 2.75 2.86 2.97 V When power supply rises 2.71 2.81 2.92 V When power supply falls 2.64 2.75 2.86 V When power supply rises 2.61 2.71 2.81 V When power supply falls 2.55 2.65 2.75 V When power supply rises 2.51 2.61 2.71 V When power supply falls 2.45 2.55 2.65 V tLW s 300 Detection delay time 300 s LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +105C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVD5 mode VLVD4 Conditions MIN. TYP. MAX. Unit 2.64 2.75 2.86 V Rising release reset voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V Rising release reset voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V Rising release reset voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V MIN. TYP. MAX. Unit 54 V/ms VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage VLVD3 VLVD0 LVIS1, LVIS0 = 1, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 3.6.6 Supply voltage rise time (TA = -40 to +105C, VSS = 0 V) Parameter VDD rise slope Symbol Conditions SVDD Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 3.4 AC Characteristics. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 114 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.7 LCD Characteristics 3.7.1 External resistance division method (1) Static display mode (TA = -40 to +105C, VL4 (MIN.) VDD 5.5 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.0 MAX. Unit VDD V MAX. Unit VDD V MAX. Unit VDD V (2) 1/2 bias method, 1/4 bias method (TA = -40 to +105C, VL4 (MIN.) VDD 5.5 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.7 (3) 1/3 bias method (TA = -40 to +105C, VL4 (MIN.) VDD 5.5 V, VSS = 0 V) Parameter LCD drive voltage R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Symbol VL4 Conditions MIN. 2.5 TYP. Page 115 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.7.2 Internal voltage boosting method (1) 1/3 bias method (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions Tripler output voltage Reference voltage setup time Voltage boost wait time Note 2 Note 3 TYP. MAX. Unit C1 to C4Note 1 VLCD = 04H 0.90 1.00 1.08 V = 0.47 FNote 2 VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H Doubler output voltage MIN. 1.65 1.75 1.83 V VL2 C1 to C4Note 1 = 0.47 F 2 VL1 - 0.10 2 VL1 2 VL1 V VL4 C1 to C4Note 1 = 0.47 F 3 VL1 - 0.15 3 VL1 3 VL1 V tVWAIT1 tVWAIT2 C1 to C4 Note 1 = 0.47 F 5 ms 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F 30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 116 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 (2) 1/4 bias method (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions MIN. TYP. MAX. Unit C1 to C5 VLCD = 04H 0.90 1.00 1.08 V = 0.47 FNote 2 VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V Note 1 Doubler output voltage VL2 C1 to C5Note 1 = 0.47 F 2 VL1 - 0.08 2 VL1 2 VL1 V Tripler output voltage VL3 C1 to C5 = 0.47 F 3 VL1 - 0.12 3 VL1 3 VL1 V Quadruply output voltage VL4 C1 to C5 = 0.47 F 4 VL1 - 0.16 4 VL1 4 VL1 V Reference voltage setup time Voltage boost wait time Note 2 Note 3 Note 1 Note 1 tVWAIT1 tVWAIT2 C1 to C5 Note 1 = 0.47 F 5 ms 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 F 30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). 3.7.3 Capacitor split method (1) 1/3 bias method (TA = -40 to +105C, 2.4 V VD 5.5 V, VSS = 0 V) Parameter Symbol Conditions VL4 voltage VL4 C1 to C4 = 0.47 FNote 2 VL2 voltage VL2 C1 to C4 = 0.47 FNote 2 MIN. TYP. VDD 2/3 VL4 - 2/3 VL4 0.1 VL1 voltage VL1 C1 to C4 = 0.47 FNote 2 1/3 VL4 - 0.1 Capacitor split wait timeNote 1 Notes 1. 2. tVWAIT MAX. 100 Unit V 2/3 VL4 + V 0.1 1/3 VL4 1/3 VL4 + V 0.1 ms This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 pF30 % R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 117 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.8 RAM Data Retention Characteristics <R> (TA = -40 to +105C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.44 TYP. Note MAX. Unit 5.5 V <R> Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. Operation mode STOP mode <R> RAM data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 3.9 Flash Memory Programming Characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions System clock frequency fCLK 2.4 V VDD 5.5 V Number of code flash rewritesNote 1, 2, 3 Cerwr Retained for 20 years MIN. TYP. 1 MAX. Unit 24 MHz 1,000 Times TA = 85C Note 4 Retained for 1 year Number of data flash rewritesNote 1, 2, 3 1,000,000 TA = 25C Retained for 5 years 100,000 TA = 85C Note 4 Retained for 20 years 10,000 TA = 85C Note 4 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test. 4. This temperature is the average value at which data are retained. Remark When updating data multiple times, use the flash memory as one for updating data. 3.10 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 118 of 123 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) RL78/L13 3.11 Timing Specifications for Switching Flash Memory Programming Modes (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Time to complete the tSUINIT Conditions MIN. POR and LVD reset must be released before TYP. MAX. Unit 100 ms the external reset is released. communication for the initial setting after the external reset is released Time to release the external reset tSU POR and LVD reset must be released before 10 s 1 ms the external reset is released. after the TOOL0 pin is set to the low level Time to hold the TOOL0 pin at the low level after the external reset is tHD POR and LVD reset must be released before the external reset is released. released (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET 723 s + tHD 00H reception processing (TOOLRxD, TOOLTxD mode) time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and completion the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 119 of 123 RL78/L13 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS 4.1 64-pin Products R5F10WLAAFA, R5F10WLCAFA, R5F10WLDAFA, R5F10WLEAFA, R5F10WLFAFA, R5F10WLGAFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51 HD D detail of lead end 48 33 49 32 A3 c E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A2 S S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 A y ITEM D A1 0.25 b 0.32 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD 1.125 ZE 1.125 2012 Renesas Electronics Corporation. All rights reserved. R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 120 of 123 S 64 49 ZD 1 48 D HD e 1 y S Index mark *1 6 33 *3 bp 17 32 x ZE F Previous Code 64P6Q-A / FP-64K / FP-64KV E *2 RENESAS Code PLQP0064KB-A b1 bp c1 Detail F Terminal cross section MASS[Typ.] 0.3g A HE JEITA Package Code P-LFQFP64-10x10-0.50 A2 R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 A1 c L1 L e x y ZD ZE L L1 D E A2 HD HE A A1 bp b1 c c1 Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 Reference Dimension in Millimeters Symbol NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. RL78/L13 4. PACKAGE DRAWINGS R5F10WLAAFB, R5F10WLCAFB, R5F10WLDAFB, R5F10WLEAFB, R5F10WLFAFB, R5F10WLGAFB, R5F10WLAGFB, R5F10WLCGFB, R5F10WLDGFB, R5F10WLEGFB, R5F10WLFGFB, R5F10WLGGFB Page 121 of 123 c RL78/L13 4. PACKAGE DRAWINGS 4.2 80-pin Products R5F10WMAAFA, R5F10WMCAFA, R5F10WMDAFA, R5F10WMEAFA, R5F10WMFAFA, R5F10WMGAFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP80-14x14-0.65 PLQP0080JB-E P80GC-65-UBT-2 0.69 HD detail of lead end D L1 A A3 c 60 61 41 40 L Lp B E HE Referance Symbol 80 1 21 20 Dimension in Millimeters Min Nom Max D 13.80 14.00 14.20 14.20 E 13.80 14.00 HD 17.00 17.20 17.40 HE 17.00 17.20 17.40 A1 0.05 0.125 0.20 A2 1.35 1.40 1.45 bp 0.26 0.32 0.38 c 0.10 0.145 0.20 Lp 0.736 0.886 1.036 L1 1.40 1.60 1.80 0 3 8 A ZE e ZD 1.70 A3 bp x M S AB L A A2 S e y R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 0.25 0.80 0.65 x S A1 0.13 y 0.10 ZD 0.825 ZE 0.825 Page 122 of 123 RL78/L13 4. PACKAGE DRAWINGS R5F10WMAAFB, R5F10WMCAFB, R5F10WMDAFB, R5F10WMEAFB, R5F10WMFAFB, R5F10WMGAFB, R5F10WMAGFB, R5F10WMCGFB, R5F10WMDGFB, R5F10WMEGFB, R5F10WMFGFB, R5F10WMGGFB R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 123 of 123 Revision History RL78/L13 Data Sheet Description Rev. Date Page 0.01 Apr 13, 2012 - First Edition issued Summary 0.02 Oct 31, 2012 - Change of the number of segment pins * 64-pin products: 36 pins * 80-pin products: 51 pins 2.10 Aug 12, 2016 1 Modification of features of 16-bit timer and 16-bit timer KB20 (IH) in 1.1 Features 5 Addition of product name (RL78/L13) and description (Top View) in 1.3.1 64-pin products 6 Addition of product name (RL78/L13) and description (Top View) in 1.3.2 80-pin products 10 Modification of functional overview of main system clock in 1.6 Outline of Functions 15 Modification of description in Absolute Maximum Ratings (3/3) 17, 18 Modification of description in 2.3.1 Pin characteristics 38 Modification of remark 3 in 2.5.1 (4) During communication at same potential (simplified I2C mode) 68 Modification of the title and note, and addition of caution in 2.8 RAM Data Retention Characteristics 70 Addition of Remark 74 Modification of description in Absolute Maximum Ratings (TA = 25 C) (3/3) 76 Modification of description in 3.3.1 Pin characteristics 95 Modification of remark 3 in 3.5.1 (4) During communication at same potential (simplified I2C mode) 118 Modification of the title and note, and addition of caution in 3.8 RAM Data Retention Characteristics All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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