Datasheet
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016 Page 1 of 123
R01DS0168EJ0210
Rev.2.10
Aug 12, 2016
RL78/L13
RENESAS MCU
Integrated LCD controller/driver, True Low Power Platform (as low as 112.5 μA/MHz, and 0.61 μA for RTC + LVD),
1.6 V to 5.5 V operation, 16 to 128 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 5.5 V which can
operate a 1.8 V device at a low voltage
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high
speed (0.04167 µs: @ 24 MHz operation with high-speed on-
chip oscillator) to ultra-low speed (30.5 µs: @ 32.768 kHz
operation with subsystem clock)
• Address space: 1 MB
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 1 to 8 KB
Code flash memory
• Code flash memory: 16 to 128 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield window
function)
Data flash memory
• Data flash memory: 4 KB
• Back ground operation (BGO): Instructions can be executed
from the program memory while rewriting the data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
• Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz,
4 MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: +/-1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85°C)
Operating ambient temperature
• TA = -40 to +85°C (A: Consumer applications)
• TA = -40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and reset from
14 levels)
DMA (Direct Memory Access) controller
• 4 channels
• Number of clocks during transfer between 8/16-bit SFR and
internal RAM: 2 clocks
Multiplier and divider/multiply-accumulator
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
Serial interface
• CSI: 2 channels
• UART/UART (LIN-bus supported): 3, 4 channels/1 channel
• I2C/Simplified I2C communication: 1 channel/2 channels
Timer
• 16-bit timer: 8 channels (with remote control output function)
• 16-bit timer KB20 (IH): 1 channel
(IH-only PWM output function)
• 12-bit interval timer: 1 channel
• Real-time clock 2: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel (operable with the dedicated low-
speed on- chip oscillator)
A/D converter
• 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
• Analog input: 9 to 12 channels
• Internal reference voltage (1.45 V) and temperature sensorNote 1
Comparator
• 2 channels
• Operation mode: Comparator high-speed mode, comparator
low-speed mode, or window mode
• External reference voltage and internal reference voltage are
selectable
LCD controller/driver
• Segment signal output: 36 (32)Note 2 to 51 (47)Note 2
• Common signal output: 4 (8)Note 2
• Internal voltage boosting method, capacitor split method, and
external resistance division method are switchable
I/O port
• I/O port: 49 to 65 (N-ch open drain I/O [withstand voltage of 6
V]: 2, N-ch open drain I/O [VDD withstand voltage]: 12 to 18)
• Can be set to N-ch open drain, TTL input buffer, and on-chip
pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5/3 V
device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
Notes 1. Can be selected only in HS (high-speed main) mode
2. The values in parentheses are the number of signal
outputs when 8 com is used.
Remark The functions mounted depend on the product. See
1.6 Outline of Functions.
* There are differences in specifications between every product.
Please refer to specification for details.
<R>
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 2 of 123
ROM, RAM capacities
Flash ROM
Data Flash
RAM RL78/L13
64 pins 80 pins
128 KB 4 KB 8 KBNote R5F10WLG R5F10WMG
96 KB 4 KB 6 KB R5F10WLF R5F10WMF
64 KB 4 KB 4 KB R5F10WLE R5F10WME
48 KB 4 KB 2 KB R5F10WLD R5F10WMD
32 KB 4 KB 1.5 KB R5F10WLC R5F10WMC
16 KB 4 KB 1 KB R5F10WLA R5F10WMA
Note This is about 7 KB when the self-programming function and data flash function are used. (For details, see
CHAPTER 3 in the RL78/L13 User’s Manual.)
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 3 of 123
1.2 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/L13
Part No. R 5 F 1 0 W L E A x x x F B #30
Package type:
ROM number (Omitted with blank products)
ROM capacity:
RL78/L13 group
Renesas MCU
Renesas semiconductor product
A
: 16 KB
C
: 32 KB
D
: 48 KB
E
: 64 KB
F
: 96 KB
G : 128 KB
Pin count:
L : 64-pin
M : 80-pin
Fields of application:
Memory type:
F : Flash memory
Packaging specification
#30 : Tray (LFQFP, LQFP)
#50 : Embossed Tape (LFQFP, LQFP)
FA : LQFP, 0.65 mm pitch
FB : LFQFP, 0.50 mm pitch
A : Consumer applications, T
A
= −40˚C to +85˚C
G : Industrial applications, T
A
= −40˚C to +105˚C
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 4 of 123
Pin Count Package Data Flash Fields of
ApplicationNote
Ordering Part Number
64 pins 64-pin plastic LQFP
(12 × 12 mm, 0.65
mm pitch)
Mounted A R5F10WLAAFA#30, R5F10WLAAFA#50, R5F10WLCAFA#30,
R5F10WLCAFA#50, R5F10WLDAFA#30, R5F10WLDAFA#50,
R5F10WLEAFA#30, R5F10WLEAFA#50, R5F10WLFAFA#30,
R5F10WLFAFA#50, R5F10WLGAFA#30, R5F10WLGAFA#50
64-pin plastic LFQFP
(10 × 10 mm, 0.5
mm pitch)
Mounted A
G
R5F10WLAAFB#30, R5F10WLAAFB#50, R5F10WLCAFB#30,
R5F10WLCAFB#50, R5F10WLDAFB#30, R5F10WLDAFB#50,
R5F10WLEAFB#30, R5F10WLEAFB#50, R5F10WLFAFB#30,
R5F10WLFAFB#50, R5F10WLGAFB#30, R5F10WLGAFB#50,
R5F10WLAGFB#30, R5F10WLAGFB#50, R5F10WLCGFB#30,
R5F10WLCGFB#50, R5F10WLDGFB#30, R5F10WLDGFB#50,
R5F10WLEGFB#30, R5F10WLEGFB#50, R5F10WLFGFB#30,
R5F10WLFGFB#50, R5F10WLGGFB#30, R5F10WLGGFB#50
80 pins 80-pin plastic LQFP
(14 × 14 mm, 0.65
mm pitch)
Mounted A R5F10WMAAFA#30, R5F10WMAAFA#50, R5F10WMCAFA#30,
R5F10WMCAFA#50, R5F10WMDAFA#30, R5F10WMDAFA#50,
R5F10WMEAFA#30, R5F10WMEAFA#50, R5F10WMFAFA#30,
R5F10WMFAFA#50, R5F10WMGAFA#30, R5F10WMGAFA#50
80-pin plastic LFQFP
(12 × 12 mm, 0.5
mm pitch)
Mounted A
G
R5F10WMAAFB#30, R5F10WMAAFB#50, R5F10WMCAFB#30,
R5F10WMCAFB#50, R5F10WMDAFB#30, R5F10WMDAFB#50,
R5F10WMEAFB#30, R5F10WMEAFB#50, R5F10WMFAFB#30,
R5F10WMFAFB#50, R5F10WMGAFB#30, R5F10WMGAFB#50,
R5F10WMAGFB#30, R5F10WMAGFB#50, R5F10WMCGFB#30,
R5F10WMCGFB#50, R5F10WMDGFB#30, R5F10WMDGFB#50,
R5F10WMEGFB#30, R5F10WMEGFB#50, R5F10WMFGFB#30,
R5F10WMFGFB#50, R5F10WMGGFB#30, R5F10WMGGFB#50
Note For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package o f RL 78/L13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 5 of 123
1.3 Pin Configuration (Top View)
1.3.1 64-pin products
• 64-pin plastic LQFP (12 × 12 mm, 0.65 mm pitch)
• 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)
P03/RxD2/SEG46/VCOUT0
P04/TxD2/SEG47/VCOUT1
P05/SCK10/SCL10/SEG48
P06/SI10/RxD1/SDA10/SEG49
P07/SO10/TxD1/(PCLBUZ0)/SEG50
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P52/TI00/TO00/INTP1/SEG6
P53/INTP2/SEG7
P54/TI02/TO02/SEG8
P02/INTP7/PCLBUZ0/SEG45
P01/(TI05)/(TO05)/INTP5/PCLBUZ1/SEG44
P00/SEG43/SO00/TxD0/TOOLTxD
P17/SEG42/SI00/RxD0/TOOLRxD/SDA00
P16/SEG41/SCK00/SCL00
P15/TI07/TO07/SEG40
P14/TI04/TO04/SEG39
P13/ANI25/SEG38
P12/ANI24/SEG37
P11/ANI23/SEG36
P10/ANI22/SEG35
P27/ANI21/SEG34
P26/ANI20/SEG33
P22/ANI16/SEG29
P21/ANI0/AV
REFP
P20/ANI1/AV
REFM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P57/INTP6/SEG11
P70/KR0/SEG12
P74/KR4/SEG16/TKBO00
P75/KR5/SEG17/TKBO01-2
P76/KR6/SEG18/TKBO01-1
P77/KR7/SEG19/TKBO01-0
P30/TI03/TO03/SEG20/REMOOUT
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SEG23
P125/V
L3
/TI06/TO06
V
L4
V
L2
V
L1
P126/CAPL/(TI04)/(TO04)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P45/VREF0
P44/(SCK10)/(SCL10)/IVCMP0
P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP1
P42/TI05/TO05/(SO10)/(TxD1)/IVREF1
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RL78/L13
(Top View)
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/L13 User’s Manual.
.
<R>
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 6 of 123
1.3.2 80-pin products
• 80-pin plastic LQFP (14 × 14 mm, 0.65 mm pitch)
• 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch)
P04/TxD2/SEG47/VCOUT1
P05/SCK10/SCL10/SEG48
P06/SI10/RxD1/SDA10/SEG49
P07/SO10/TxD1/(PCLBUZ0)/SEG50
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4
P51/SEG5
P52/TI00/TO00/INTP1/SEG6
P53/INTP2/SEG7
P54/TI02/TO02/SEG8
P55/INTP5/SEG9
P56/TI06/TO06/SEG10
P57/INTP6/SEG11
P130/(SO00)/(TxD0)/SEG28
P47/(SI00)/(RxD0)/(SDA00)/SEG27
P46/(SCK00)/(SCL00)/SEG26
P45/IVREF0
P44/(SCK10)/(SCL10)/IVCMP0
P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP1
P42/TI05/TO05/(SO10)/(TxD1)/IVREF1
P41/(TI07)/(TO07)
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P03/RxD2/SEG46/VCOUT0
P02/INTP7/PCLBUZ0/SEG45
P01/(TI05)/(TO05)/(INTP5)/PCLBUZ1/SEG44
P00/SEG43/SO00/TxD0/TOOLTxD
P17/SEG42/SI00/RxD0/TOOLRxD/SDA00
P16/SEG41/SCK00/SCL00
P15/TI07/TO07/SEG40
P14/TI04/TO04/SEG39
P13/ANI25/SEG38
P12/ANI24/SEG37
P11/ANI23/SEG36
P10/ANI22/SEG35
P27/ANI21/SEG34
P26/ANI20/SEG33
P25/ANI19/SEG32
P24/ANI18/SEG31
P23/ANI17/SEG30
P22/ANI16/SEG29
P21/ANI0/AV
REFP
P20/ANI1/AV
REFM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P70/KR0/SEG12
P71/KR1/SEG13
P72/KR2/SEG14
P73/KR3/SEG15
P74/KR4/SEG16/TKBO00
P75/KR5/SEG17/TKBO01-2
P76/KR6/SEG18/TKBO01-1
P77/KR7/SEG19/TKBO01-0
P30/TI03/TO03/SEG20/REMOOUT
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SEG23
P34/RxD3/SEG24
P35/TxD3/SEG25
P125/V
L3
/(TI06)/(TO06)
V
L4
V
L2
V
L1
P126/CAPL/(TI04)/(TO04)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RL78/L13
(Top View)
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/L13 User’s Manual.
<R>
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 7 of 123
1.4 Pin Identification
A
NI0, ANI1,
A
NI16 to ANI25: Analog Input
A
VREFM: Analog Reference Voltage
Minus
A
VREFP: Analog Reference Voltage
Plus
CAPH, CAPL: Capacitor for LCD
COM0 to COM7: LCD Common Output
EXCLK: External Clock Input
(Main System Clock)
EXCLKS: External Clock Input
(Subsystem Clock)
INTP0 to INTP7: External Interrupt Input
IVCMP0, IVCMP1: Comparator Input
IVREF0, IVREF1: Comparator Reference Input
KR0 to KR7: Key Return
P00 to P07: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30 to P35: Port 3
P40 to P47: Port 4
P50 to P57: Port 5
P60, P61: Port 6
P70 to P77: Port 7
P121 to P127: Port 12
P130, P137: Port 13
PCLBUZ0, PCLBUZ1: Programmable Clock Output/
Buzzer Output
REGC: Regulator Capacitance
REMOOUT: Remote control Output
RESET: Reset
RTC1HZ: Real-time Clock 2 Correction Clock
(1 Hz) Output
RxD0 to RxD3: Receive Data
SCK00, SCK10, SCLA0: Serial Clock Input/Output
SCL00, SCL10: Serial Clock Output
SDAA0, SDA00, SDA10: Serial Data Input/Output
SEG0 to SEG50: LCD Segment Output
SI00, SI10: Serial Data Input
SO00, SO10: Serial Data Output
TI00 to TI07: Timer Input
TO00 to TO07,
TKBO00, TKBO01-0,
TKBO01-1, TKBO01-2: Timer Output
TOOL0: Data Input/Output for Tool
TOOLRxD, TOOLTxD: Data Input/Output for External Device
TxD0 to TxD3: Transmit Data
VCOUT0, VCOUT1: Comparator Output
VDD: Power Supply
VL1 to VL4: LCD Power Supply
VSS: Ground
X1, X2: Crystal Oscillator (Main System Clock)
XT1, XT2: Crystal Oscillator (Subsystem Clock)
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 8 of 123
1.5 Block Diagram
1.5.1 64-pin products
PORT 1
PORT 2 P20 to P22,
P26, P27
5
PORT 3 P30 to P33
4
PORT 4
PORT 5
P10 to P178
P40, P42 to P455
P52 to P54, P574
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
SYSTEM
CONTROL RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
ON-CHIP DEBUG
TOOL0/P40
SERIAL ARRAY
UNIT0 (4ch)
UART0
UART1
IIC00
RxD0/P17
TxD0/P00
RxD1/P06(RxD1/P43)
TxD1/P07(TxD0/P42)
SCL00/P16
SDA00/P17
TIMER ARRAY
UNIT0 (8ch)
ch2
TI02/TO02/P54
(TI02/TO02/P61)
ch3
TI03/TO03/P30
(TI03/TO03/P127)
ch0
ch1
ch4
TI04/TO04/P14
(TI04/TO04/P126)
ch5
TI05/TO05/P42
(TI05/TO05/P01)
ch6
TI06/TO06/P125
ch7
3
2
INTP0/P137
INTP3/P31,
INTP4/P33
INTP1/P52,
INTP2/P53,
INTP6/P57
RxD0/P17
CSI10
SCK10/P05(SCK10/P44)
SO10/P07(SO10/P42)
SI10/P06(SI10/P43)
A/D CONVERTER
2ANI0/P21, ANI1/P20
AVREFP/P21
AVREFM/P20
IIC10
SCL10/P05(SCL10/P44)
SDA10/P06(SDA10/P43)
TI07/TO07/P15
BCD
ADJUSTMENT
SO00/P00
SI00/P17
CSI00
VSS TOOLRxD/P17,
TOOLTxD/P00
VDD
SERIAL
INTERFACE IICA0 SCLA0/P60
SDAA0/P61 2
INTP5/P01,
INTP7/P02(INTP7/P43)
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
XT1/P123
XT2/EXCLKS/P124
PORT 0 P00 to P07
8
BUZZER OUTPUT PCLBUZ0/P02
(PCLBUZ0/P07),
PCLBUZ1/P01
CLOCK OUTPUT
CONTROL
KEY RETURN
5KR0/P70,
KR4/P74 to KR7/P77
4ANI22/P10 to ANI25/P13
DIRECT MEMORY
ACCESS
CONTROL
PORT 6
PORT 7 P70, P74 to P77
5
P60, P61
2
2
TI01/TO01/P32
(TI01/TO01/P60)
TI00/TO00/P52
(TI00/TO00/P40)
RxD0/P17
3ANI16/P22,
ANI20/P26, ANI21/P27
PORT 12 P121 to P124
4P125 to P127
3
SERIAL ARRAY
UNIT1 (4ch)
RxD2/P03
TxD2/P04
UART2
LINSEL
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
SCK00/P16
CRC WINDOW
WATCHDOG
TIMER
RTC1HZ/P31
REAL-TIME
CLOCK 2
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
4
TKBO00/P74, TKBO01-0/P77,
TKBO01-1/P76, TKBO01-2/P75 16-bit TIMER KB20
COMPARATOR
(2ch)
COMPARATOR0
VCOUT0/P03
IVCMP0/P44
IVREF0/P45
COMPARATOR1
VCOUT1/P04
IVCMP1/P43
IVREF1/P42
LCD
CONTROLLER/
DRIVER
COM0 to COM7
36
SEG0 to SEG3, SEG6 to SEG8,
SEG11, SEG12, SEG16 to SEG23,
SEG29, SEG33 to SEG50
8
VL1 to VL4
CAPH
CAPL
RAM SPACE
FOR LCD DATA
PORT 13 P137
Remote Carrier
REMOOUT/P30
(REMOOUT/P127)
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/L13
User’s Manual.
RL78/L13 1. OUTLINE
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 9 of 123
1.5.2 80-pin products
PORT 1
PORT 2 P20 to P278
PORT 3 P30 to P35
6
PORT 4
PORT 5
P10 to P178
P40 to P478
P50 to P578
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
SYSTEM
CONTROL RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
ON-CHIP DEBUG
TOOL0/P40
SERIAL ARRAY
UNIT0 (4ch)
UART0
UART1
IIC00
RxD0/P17(RxD0/P47)
TxD0/P00(TxD0/P130)
RxD1/P06(RxD1/P43)
TxD1/P07(TxD0/P42)
SCL00/P16(SCL00/P46)
SDA00/P17(SDA00/P47)
TIMER ARRAY
UNIT0 (8ch)
ch2
TI02/TO02/P54
(TI02/TO02/P61)
ch3
TI03/TO03/P30
(TI03/TO03/P127)
ch0
ch1
ch4
TI04/TO04/P14
(TI04/TO04/P126)
Remote Carrier
REMOOUT/P30
(REMOOUT/P127)
ch5
TI05/TO05/P42
(TI05/TO05/P01)
ch6
TI06/TO06/P56
(TI06/TO06/P125)
ch7
4
INTP0/P137
INTP3/P31,
INTP4/P33
INTP1/P52,
INTP2/P53,
RxD0/P17 (RxD0/P47)
CSI10
SCK10/P05(SCK10/P44)
SO10/P07(SO10/P42)
SI10/P06(SI10/P43)
A/D CONVERTER
2ANI0/P21, ANI1/P20
AV
REFM
/P20
AV
REFP
/P21
IIC10
SCL10/P05(SCL10/P44)
SDA10/P06(SDA10/P43)
TI07/TO07/P15
(TI07/TO07/P41)
BCD
ADJUSTMENT
SO00/P00(SO00/P130)
SI00/P17(SI00/P47)
CSI00
V
SS
TOOLRxD/P17,
TOOLTxD/P00
V
DD
SERIAL
INTERFACE IICA0 SCLA0/P60
SDAA0/P61 INTP5/P55(INTP5/P01),
INTP6/P57
2
INTP7/P02(INTP7/P43)
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
XT1/P123
XT2/EXCLKS/P124
PORT 0 P00 to P07
8
BUZZER OUTPUT PCLBUZ0/P02
(PCLBUZ0/P07),
PCLBUZ1/P01
CLOCK OUTPUT
CONTROL
KEY RETURN
8KR0/P70 to
KR7/P77
4ANI22/P10 to ANI25/P13
DIRECT MEMORY
ACCESS
CONTROL
PORT 6
PORT 7 P70 to P77
8
P60, P61
2
2
TI01/TO01/P32
(TI01/TO01/P60)
TI00/TO00/P52
(TI00/TO00/P40)
RxD0/P17
(RxD0/P47)
6ANI16/P22 to ANI21/P27
PORT 12 P121 to P124
4P125 to P127
3
SERIAL ARRAY
UNIT1 (4ch)
UART3
RxD2/P03
TxD2/P04
RxD3/P34
TxD3/P35
UART2
LINSEL
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
SCK00/P16(SCK00/P46)
CRC WINDOW
WATCHDOG
TIMER
RTC1HZ/P31
REAL-TIME
CLOCK 2
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
4
TKBO00/P74, TKBO01-0/P77,
TKBO01-1/P76, TKBO01-2/P75 16-bit TIMER KB20
COMPARATOR
(2ch)
COMPARATOR0
VCOUT0/P03
IVCMP0/P44
IVREF0/P45
COMPARATOR1
VCOUT1/P04
IVCMP1/P43
IVREF1/P42
LCD
CONTROLLER/
DRIVER
COM0 to COM7
51
SEG0 to SEG50
8
V
L1
to V
L4
CAPH
CAPL
RAM SPACE
FOR LCD DATA
PORT 13 P130
P137
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/L13
User’s Manual.
RL78/L13 1. OUTLINE
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1.6 Outline of Functions
(1/2)
Item 64-pin 80-pin
R5F10WLx (x = A, C-G) R5F10WMx (x = A, C-G)
Code flash memory (KB) 16 to 128 16 to 128
Data flash memory (KB) 4 4
RAM (KB) 1 to 8Note 1 1 to 8Note 1
Address space 1 MB
Main system
clock
High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
High-speed on-chip
oscillator
HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Clock for 16-bit timer KB20 48 MHz (TYP.): VDD = 2.7 to 5.5 V
Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator 15 kHz (TYP.)
General-purpose register (8-bit register × 8) × 4 banks
Minimum instruction execution time 0.04167
μ
s (High-speed on-chip oscillator: fIH = 24 MHz operation)
0.05
μ
s (High-speed system clock: fMX = 20 MHz operation)
30.5
μ
s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 49 65
CMOS I/O 42
(N-ch O.D. I/O [VDD withstand voltage]: 12)
58
(N-ch O.D. I/O [VDD withstand voltage]: 18)
CMOS input 5 5
CMOS output − −
N-ch O.D I/O
(withstand voltage: 6 V)
2 2
Timer 16-bit timer TAU 8 channels
16-bit timer KB20 1 channel
Watchdog timer 1 channel
12-bit interval timer (IT) 1 channel
Real-time clock 2 1 channel
RTC2 output 1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Timer output 8 channels (PWM outputs: 7Note 2) (TAU used)
1 channel (timer KB20 used)
Remote control output
function
1 (TAU used)
Notes 1. In the case of the 8 KB, this is about 7 KB when the self-programming function and data flash function are
used.
2. The number of outputs varies depending on the setting of the channels in use and the number of master
channels (see 6.9.3 Operation as mu ltip le PWM output function in the RL78/L13 User’s Manual.).
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RL78/L13 1. OUTLINE
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(2/2)
Item 64-pin 80-pin
R5F10WLx (x = A, C-G) R5F10WMx (x = A, C-G)
Clock output/buzzer output controller 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 9 channels 12 channels
Comparator 2 channels
Serial interface [64-pin]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• UART: 1 channel
[80-pin]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• UART: 2 channels
I
2C bus 1 channel
LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance division
method are switchable.
Segment signal output 36 (32)Note 1 51 (47)Note 1
Common signal output 4 (8)Note 1
Multiplier and divider/multiply-
accumulator
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller 4 channels
Vectored
interrupt sources
Internal 32 35
External 11 11
Key interrupt 5 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction executionNote 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.)
• Power-down-reset: 1.50 V (TYP.)
Voltage detector • Rising edge: 1.67 V to 4.06 V (14 steps)
• Falling edge: 1.63 V to 3.98 V (14 steps)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V (TA = -40 to +85°C)
VDD = 2.4 to 5.5 V (TA = -40 to +105°C)
Operating ambient temperature Consumer applications: TA = −40 to +85°C
Industrial applications: TA = −40 to +105°C
Notes 1. The values in parentheses are the number of signal outputs when 8 com is used.
2. This reset occurs when instruction code FFH is executed.
This reset does not occur during emulation using an in-circuit emulator or an on-chip debugging emulator.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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Page 12 of 123
2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Target products A: Consumer applications; TA = −40 to +85°C
R5F10WLAAFA, R5F10WLCAFA, R5F10WLDAFA,
R5F10WLEAFA, R5F10WLFAFA, R5F10WLGAFA,
R5F10WLAAFB, R5F10WLCAFB, R5F10WLDAFB,
R5F10WLEAFB, R5F10WLFAFB, R5F10WLGAFB,
R5F10WMAAFA, R5F10WMCAFA, R5F10WMDAFA,
R5F10WMEAFA, R5F10WMFAFA, R5F10WMGAFA,
R5F10WMAAFB, R5F10WMCAFB, R5F10WMDAFB,
R5F10WMEAFB, R5F10WMFAFB, R5F10WMGAFB
G: Industrial applications; when using TA = −40 to +105°C specification products at TA = −40 to +85°C
R5F10WLAGFB, R5F10WLCGFB, R5F10WLDGFB,
R5F10WLEGFB, R5F10WLFGFB, R5F10WLGGFB
R5F10WMAGFB, R5F10WMCGFB, R5F10WMDGFB,
R5F10WMEGFB, R5F10WMFGFB, R5F10WMGGFB
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 With functions for
each product in the RL78/L13 User’s Manual.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (1/3)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD −0.5 to +6.5 V
REGC pin input voltage VIREGC REGC −0.3 to +2.8
and −0.3 to VDD +0.3Note 1
V
Input voltage VI1 P00 to P07, P10 to P17, P20 to P27, P30 to P35,
P40 to P47, P50 to P57, P60, P61, P70 to P77,
P121 to P127, P130, P137
−0.3 to VDD +0.3Note 2 V
VI2 P60 and P61 (N-ch open-drain) −0.3 to +6.5 V
VI3 EXCLK, EXCLKS, RESET −0.3 to VDD +0.3Note 2 V
Output voltage VO1 P00 to P07, P10 to P17, P20 to P27, P30 to P35,
P40 to P47, P50 to P57, P60, P61, P70 to P77,
P121 to P127, P130, P137
−0.3 to VDD +0.3Note 2 V
Analog input voltage VAI1 ANI0, ANI1, ANI16 to ANI26 −0.3 to VDD +0.3
and −0.3 to AVREF(+) +0.3Notes 2, 3
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damag e, and th erefore the p roduct mu st be u sed under cond itions that en sure th at
the absolute maximum ratings are n ot exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. V
SS: Reference voltage
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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Absolute Maximum Ratings (2/3)
Parameter Symbol Conditions Ratings Unit
LCD voltage VL1 VL1 voltageNote 1 −0.3 to +2.8 and
−0.3 to VL4 +0.3
V
VL2 VL2 voltageNote 1 −0.3 to VL4 +0.3Note 2 V
VL3 VL3 voltageNote 1 −0.3 to VL4 +0.3Note 2 V
VL4 VL4 voltageNote 1 −0.3 to +6.5 V
VLCAP CAPL, CAPH voltageNote 1 −0.3 to VL4 +0.3Note 2 V
VOUT COM0 to COM7
SEG0 to SEG50
output voltage
External resistance division method −0.3 to VDD +0.3Note 2 V
Capacitor split method −0.3 to VDD +0.3Note 2 V
Internal voltage boosting method −0.3 to VL4 +0.3Note 2 V
Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins;
it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting
method or capacitance split method, connect these pins to VSS via a capacitor (0.47
μ
F ± 30%) and connect a
capacitor (0.47
μ
F ± 30%) between the CAPL and CAPH pins.
2. Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damag e, and th erefore the p roduct mu st be u sed under cond itions that en sure th at
the absolute maximum ratings are n ot exceeded.
Remark V
SS: Reference voltage
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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Page 15 of 123
Absolute Maximum Ratings (3/3)
Parameter Symbol Conditions Ratings Unit
Output current, high IOH1 Per pin P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47,
P50 to P57, P60, P61,
P70 to P77, P125 to P127, P130
−40 mA
Total of all pins
−170 mA
P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47,
P50 to P57, P60, P61,
P70 to P77, P125 to P127, P130
−170 mA
IOH2 Per pin P20, P21 −0.5 mA
Total of all pins −1 mA
Output current, low IOL1 Per pin P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47,
P50 to P57, P60, P61,
P70 to P77, P125 to P127, P130
40 mA
Total of all pins
170 mA
P40 to P47, P130 70 mA
P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P50 to P57,
P60, P61, P70 to P77,
P125 to P127
100 mA
IOL2 Per pin P20, P21 1 mA
Total of all pins 2 mA
Operating ambient
temperature
TA In normal operation mode −40 to +85 °C
In flash memory programming mode
Storage temperature Tstg −65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damag e, and th erefore the p roduct mu st be u sed under cond itions that en sure th at
the absolute maximum ratings are n ot exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
<R>
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RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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Page 16 of 123
2.2 Oscillator Characteristics
2.2.1 X1 and XT1 oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation
frequency (fX)Note
Ceramic resonator/
crystal resonator
2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0
1.8 V ≤ VDD < 2.4 V 1.0 8.0
1.6 V ≤ VDD < 1.8 V 1.0 4.0
XT1 clock oscillation
frequency (fXT)Note
Crystal resonator 32 32.768 35 kHz
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, see 5.4 System Clock Oscillator in the RL78/L13 User’s
Manual.
2.2.2 On-chip oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator
clock frequencyNotes 1, 2
fIH 1 24 MHz
High-speed on-chip oscillator
clock frequency accuracy
−20 to +85°C 1.8 V ≤ VDD ≤ 5.5 V −1.0 +1.0 %
1.6 V ≤ VDD < 1.8 V −5.0 +5.0 %
−40 to −20°C 1.8 V ≤ VDD ≤ 5.5 V −1.5 +1.5 %
1.6 V ≤ VDD < 1.8 V −5.5 +5.5 %
Low-speed on-chip oscillator
clock frequency
fIL 15 kHz
Low-speed on-chip oscillator
clock frequency accuracy
−15 +15 %
Notes 1. The high-speed on-chip oscillator frequency is selected by bits 0 to 4 of the option byte (000C2H/010C2H)
and bits 0 to 2 of the HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for the instruction execution
time.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V , VSS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output current,
highNote 1
IOH1 Per pin for P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P40 to P47,
P50 to P57, P70 to P77, P125 to P127,
P130
1.6 V ≤ VDD ≤ 5.5 V −10.0Note 2 mA
Total of P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P40 to P47,
P50 to P57, P70 to P77, P125 to P127,
P130
(When duty = 70%Note 3)
4.0 V ≤ VDD ≤ 5.5 V
−90.0 mA
2.7 V ≤ VDD < 4.0 V −15.0 mA
1.8 V ≤ VDD < 2.7 V −7.0 mA
1.6 V ≤ VDD < 1.8 V −3.0 mA
IOH2 Per pin for P20 and P21 1.6 V ≤ VDD ≤ 5.5 V −0.1Note 2 mA
Total of all pins
(When duty = 70%Note 3)
1.6 V ≤ VDD ≤ 5.5 V −0.2 mA
Notes 1. Value of the current at which the device operation is guaranteed even if the current flows from the VDD pin
to an output pin
2. Do not exceed the total current value.
3. Output current value under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −90.0 mA
Total output current of pins = (−90.0 × 0.7)/(80 × 0.01) ≅ −78.75 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, an d P130 d o n ot out put high level in
N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output current,
lowNote 1
IOL1 Per pin for P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P40 to P47,
P50 to P57, P70 to P77,
P125 to P127, P130
20.0Note 2 mA
Per pin for P60 and P61 15.0Note 2 mA
Total of P40 to P47, P130
(When duty = 70%Note 3)
4.0 V ≤ VDD ≤ 5.5 V 70.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
1.8 V ≤ VDD < 2.7 V 9.0 mA
1.6 V ≤ VDD < 1.8 V 4.5 mA
Total of P00 to P07, P10 to P17,
P22 to P27,
P30 to P35, P50 to P57, P70 to P77,
P125 to P127
(When duty = 70%Note 3)
4.0 V ≤ VDD ≤ 5.5 V 90.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
1.8 V ≤ VDD < 2.7 V 20.0 mA
1.6 V ≤ VDD < 1.8 V 10.0 mA
Total of all pins
(When duty = 70%Note 3)
160.0 mA
IOL2 Per pin for P20 and P21 0.4Note 2 mA
Total of all pins
(When duty = 70%Note 3)
1.6 V ≤ VDD ≤ 5.5 V 0.8 mA
Notes 1. Value of the current at which the device operation is guaranteed even if the current flows from an output pin
to the VSS pin
2. Do not exceed the total current value.
3. Output current value under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 70.0 mA
Total output current of pins = (70.0 × 0.7)/(80 × 0.01) ≅ 61.25 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
<R>
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
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Page 19 of 123
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage,
high
VIH1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130,
P137
Normal input buffer 0.8VDD VDD V
VIH2 P03, P05, P06, P16, P17, P34, P43,
P44, P46, P47, P53, P55
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
2.2 VDD V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
2.0 VDD V
TTL input buffer
1.6 V ≤ VDD < 3.3 V
1.5 VDD V
VIH3 P20, P21 0.7VDD VDD V
VIH4 P60, P61 0.7VDD 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V
Input voltage, low VIL1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130,
P137
Normal input buffer 0 0.2VDD V
VIL2 P03, P05, P06, P16, P17, P34, P43,
P44, P46, P47, P53, P55
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
0 0.8 V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
0 0.5 V
TTL input buffer
1.6 V ≤ VDD < 3.3 V
0 0.32 V
VIL3 P20, P21 0 0.3VDD V
VIL4 P60, P61 0 0.3VDD V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V
Caution The maximum value of VIH of pins P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56,
and P130 is VDD, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 20 of 123
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output voltage,
high
VOH1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −10.0 mA
VDD − 1.5 V
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA
VDD − 0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOH1 = −2.0 mA
VDD − 0.6 V
1.8 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.5 mA
VDD − 0.5 V
1.6 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.0 mA
VDD − 0.5 V
VOH2 P20 and P21 1.6 V ≤ VDD ≤ 5.5 V,
IOH2 = −100
μ
A
VDD − 0.5 V
Output voltage,
low
VOL1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 20 mA
1.3 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
0.6 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
0.4 V
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
0.4 V
1.6 V ≤ VDD < 1.8 V,
IOL1 = 0.3 mA
0.4 V
VOL2 P20 and P21 1.6 V ≤ VDD ≤ 5.5 V,
IOL2 = 400
μ
A
0.4 V
VOL3 P60 and P61
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 15.0 mA
2.0 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 5.0 mA
0.4 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL3 = 3.0 mA
0.4 V
1.8 V ≤ VDD ≤ 5.5 V,
IOL3 = 2.0 mA
0.4 V
1.6 V ≤ VDD < 1.8 V,
IOL3 = 1.0 mA
0.4 V
Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, an d P130 d o n ot out put high level in
N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 21 of 123
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
ILIH1 P00 to P07, P10 to P17,
P22 to P27, P30 to P35,
P40 to P47, P50 to P57,
P70 to P77, P125 to P127,
P130, P137
VI = VDD 1
μ
A
ILIH2 P20 and P21, RESET VI = VDD 1
μ
A
ILIH3 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VDD In input port mode
and when external
clock is input
1
μ
A
Resonator
connected
10
μ
A
Input leakage
current, low
ILIL1 P00 to P07, P10 to P17,
P22 to P27, P30 to P35,
P40 to P47, P50 to P57,
P70 to P77, P125 to P127,
P130, P137
VI = VSS −1
μ
A
ILIL2 P20 and P21, RESET VI = VSS −1
μ
A
ILIL3 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VSS In input port mode
and when external
clock is input
−1
μ
A
Resonator
connected
−10
μ
A
On-chip pull-up
resistance
RU1 P00 to P07, P10 to P17,
P22 to P27, P30 to P35,
P45 to P47, P50 to P57,
P70 to P77, P125 to P127,
P130
VI = VSS 2.4 V ≤ VDD < 5.5 V 10 20 100 kΩ
1.6 V ≤ VDD < 2.4 V 10 30 100 kΩ
RU2 P40 to P44 VI = VSS 10 20 100 kΩ
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 22 of 123
2.3.2 Supply current characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V ) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
currentNote
1
IDD1 Operating
mode
HS (high-
speed main)
mode
Note 5
fHOCO = 48 MHzNote 3,
fIH = 24 MHzNote 3
Basic
operation
VDD = 5.0 V 2.0 mA
VDD = 3.0 V 2.0 mA
Normal
operation
VDD = 5.0 V
3.8 6.5 mA
VDD = 3.0 V 3.8 6.5 mA
fHOCO = 24 MHzNote 3,
fIH = 24 MHzNote 3
Basic
operation
VDD = 5.0 V 1.7 mA
VDD = 3.0 V 1.7 mA
Normal
operation
VDD = 5.0 V
3.6 6.1 mA
VDD = 3.0 V 3.6 6.1 mA
fHOCO = 16 MHzNote 3,
fIH = 16 MHzNote 3
Normal
operation
VDD = 5.0 V
2.7 4.7 mA
VDD = 3.0 V 2.7 4.7 mA
LS (low-
speed main)
mode
Note 5
fHOCO = 8 MHzNote 3 ,
fIH = 8 MHzNote 3
Normal
operation
VDD = 3.0 V 1.2 2.1 mA
VDD = 2.0 V
1.2 2.1 mA
LV (
low-
voltage
main)
mode
Note 5
fHOCO = 4 MHzNote 3,
fIH = 4 MHzNote 3
Normal
operation
VDD = 3.0 V 1.2 1.8 mA
VDD = 2.0 V
1.2 1.8 mA
HS (high-
speed main)
mode
Note 5
fMX = 20 MHzNote 2,
VDD = 5.0 V
Normal
operation
Square wave input
3.0 5.1 mA
Resonator connection
3.2 5.2 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V
Normal
operation
Square wave input
2.9 5.1 mA
Resonator connection
3.2 5.2 mA
fMX = 16 MHzNote 2,
VDD = 5.0 V
Normal
operation
Square wave input
2.5 4.4 mA
Resonator connection
2.7 4.5 mA
fMX = 16 MHzNote 2,
VDD = 3.0 V
Normal
operation
Square wave input
2.5 4.4 mA
Resonator connection
2.7 4.5 mA
fMX = 10 MHzNote 2,
VDD = 5.0 V
Normal
operation
Square wave input
1.9 3.0 mA
Resonator connection
1.9 3.0 mA
fMX = 10 MHzNote 2,
VDD = 3.0 V
Normal
operation
Square wave input
1.9 3.0 mA
Resonator connection
1.9 3.0 mA
LS (low-
speed main)
mode
Note 5
fMX = 8 MHzNote 2,
VDD = 3.0 V
Normal
operation
Square wave input
1.1 2.0 mA
Resonator connection
1.1 2.0 mA
fMX = 8 MHzNote 2,
VDD = 2.0 V
Normal
operation
Square wave input
1.1 2.0 mA
Resonator connection
1.1 2.0 mA
Subsystem
clock
operation
fSUB = 32.768 kHzNote
4,
TA = −40°C
Normal
operation
Square wave input
4.0 5.4 μA
Resonator connection
4.3 5.4 μA
fSUB = 32.768 kHz Note
4,
TA = +25°C
Normal
operation
Square wave input
4.0 5.4 μA
Resonator connection
4.3 5.4 μA
fSUB = 32.768 kHzNote
4,
TA = +50°C
Normal
operation
Square wave input
4.1 7.1 μA
Resonator connection
4.4 7.1 μA
fSUB = 32.768 kHzNote
4,
TA = +70°C
Normal
operation
Square wave input
4.3 8.7 μA
Resonator connection
4.7 8.7 μA
fSUB = 32.768 kHzNote
4,
TA = +85°C
Normal
operation
Square wave input
4.7 12.0 μA
Resonator connection
5.2 12.0 μA
(Notes and Remarks are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 23 of 123
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not
including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, on-
chip pull-up/pull-down resistors, and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When setting ultra-low power
consumption oscillation (AMPHS1 = 1). The current flowing into the LCD controller/driver, 16-bit timer KB20,
real-time clock 2, 12-bit interval timer, and watchdog timer is not included.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
HOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
3. f
IH: High-speed on-chip oscillator clock frequency (24 MHz max.)
4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 24 of 123
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V ) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
currentNote 1
IDD2Note 2 HALT
mode
HS (high-speed
main) mode
Note
7
fHOCO = 48 MHzNote 4,
fIH = 24 MHzNote 4
VDD = 5.0 V
0.71 1.95 mA
VDD = 3.0 V 0.71 1.95
fHOCO = 24 MHzNote 4,
fIH = 24 MHzNote 4
VDD = 5.0 V
0.49 1.64 mA
VDD = 3.0 V 0.49 1.64
fHOCO = 16 MHzNote 4,
fIH = 16 MHzNote 4
VDD = 5.0 V
0.43 1.11 mA
VDD = 3.0 V 0.43 1.11
LS (low-speed
main) mode
Note
7
fHOCO = 8 MHz Note 4,
fIH = 8 MHz Note 4
VDD = 3.0 V 280 770
μ
A
VDD = 2.0 V
280 770
LV (
low-voltage
main) mode
Note 7
fHOCO = 4 MHzNote 4,
fIH = 4 MHzNote 4
VDD = 3.0 V 430 700
μ
A
VDD = 2.0 V
430 700
HS (high-speed
main) mode
Note
7
fMX = 20 MHzNote 3,
VDD = 5.0 V
Square wave input 0.31 1.42 mA
Resonator connection 0.48 1.42
fMX = 20 MHzNote 3,
VDD = 3.0 V
Square wave input 0.29 1.42 mA
Resonator connection 0.48 1.42
fMX = 16 MHzNote 3,
VDD = 5.0 V
Square wave input 0.26 0.86 mA
Resonator connection 0.45 1.15
fMX = 16 MHzNote 3,
VDD = 3.0 V
Square wave input 0.25 0.86 mA
Resonator connection 0.44 1.15
fMX = 10 MHzNote 3,
VDD = 5.0 V
Square wave input 0.20 0.63 mA
Resonator connection 0.28 0.71
fMX = 10 MHzNote 3,
VDD = 3.0 V
Square wave input 0.19 0.63 mA
Resonator connection 0.28 0.71
LS (low-speed
main) mode
Note 7
fMX = 8 MHzNote 3,
VDD = 3.0 V
Square wave input 100 560
μ
A
Resonator connection 160 560
fMX = 8 MHzNote 3,
VDD = 2.0 V
Square wave input 100 560
μ
A
Resonator connection 160 560
Subsystem
clock operation
fSUB = 32.768 kHzNote 5,
TA = −40°C
Square wave input 0.34 0.62
μ
A
Resonator connection 0.51 0.80
fSUB = 32.768 kHzNote 5,
TA = +25°C
Square wave input 0.38 0.62
μ
A
Resonator connection 0.57 0.80
fSUB = 32.768 kHzNote 5,
TA = +50°C
Square wave input 0.46 2.30
μ
A
Resonator connection 0.67 2.49
fSUB = 32.768 kHzNote 5,
TA = +70°C
Square wave input 0.65 4.03
μ
A
Resonator connection 0.91 4.22
fSUB = 32.768 kHzNote 5,
TA = +85°C
Square wave input 1.00 8.04
μ
A
Resonator connection 1.31 8.23
IDD3Note 6 STOP
modeNote 8
TA = −40°C 0.18 0.52
μ
A
TA = +25°C 0.24 0.52
TA = +50°C 0.33 2.21
TA = +70°C 0.53 3.94
TA = +85°C 0.93 7.95
(Notes and Remarks are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 25 of 123
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not
including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, on-
chip pull-up/pull-down resistors, and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped.
When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the real-
time clock 2 is included. However, not including the current flowing into the clock output/buzzer output, 12-bit
interval timer, and watchdog timer.
6. Not including the current flowing into the real-time clock 2, clock output/buzzer output, 12-bit interval timer, and
watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
HOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
3. f
IH: High-speed on-chip oscillator clock frequency (24 MHz max.)
4. f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 26 of 123
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-
chip oscillator
operating current
IFILNote 1 0.20
μ
A
RTC2 operating
current
IRTCNotes 1, 2,
3
fSUB = 32.768 kHz 0.02
μ
A
12-bit interval
timer operating
current
ITMKANotes 1, 2,
4
0.04
μ
A
Watchdog timer
operating current
IWDTNo tes 1, 2, 5 fIL = 15 kHz 0.22
μ
A
A/D converter
operating current
IADCNotes 1, 6 When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA
A/D converter
reference voltage
current
IADREFNote 1 75.0
μ
A
Temperature
sensor operating
current
ITMPSNote 1 75.0
μ
A
LVD operating
current
ILVDNotes 1, 7 0.08
μ
A
Comparator
operating current
ICMPNotes 1, 11 VDD = 5.0 V,
Regulator output
voltage = 2.1 V
Window mode 12.5
μ
A
Comparator high-speed mode 6.5
μ
A
Comparator low-speed mode 1.7
μ
A
VDD = 5.0 V,
Regulator output
voltage = 1.8 V
Window mode 8.0
μ
A
Comparator high-speed mode 4.0
μ
A
Comparator low-speed mode 1.3
μ
A
Self-
programming
operating current
IFSPNotes 1, 9 2.00 12.20 mA
BGO operating
current
IBGONotes 1, 8 2.00 12.20 mA
SNOOZE
operating current
ISNOZNote 1 ADC operation While the mode is shiftingNote 10 0.50 0.60 mA
During A/D conversion, in low voltage
mode, AVREFP = VDD = 3.0 V
1.20 1.44 mA
CSI/UART operation 0.70 0.84 mA
LCD operating
current
ILCD1Notes 1, 12,
13
External resistance
division method
fLCD = fSUB
LCD clock =
128 Hz
1/3 bias,
four time
slices
VDD = 5.0 V,
VL4 = 5.0 V
0.04 0.20
μ
A
ILCD2Note 1, 12 Internal voltage
boosting method
fLCD = fSUB
LCD clock =
128 Hz
1/3 bias,
four time
slices
VDD = 3.0 V,
VL4 = 3.0 V
(VLCD = 04H)
0.85 2.20
μ
A
VDD = 5.0 V,
VL4 = 5.1 V
(VLCD = 12H)
1.55 3.70
μ
A
ILCD3Note 1, 12 Capacitor split
method
fLCD = fSUB
LCD clock =
128 Hz
1/3 bias,
four time
slices
VDD = 3.0 V,
VL4 = 3.0 V
0.20 0.50
μ
A
(Notes and Remarks are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 27 of 123
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator
and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the values of either
IDD1 or IDD2, and IRTC, when the real-time clock 2 operates in operation mode or HALT mode. When the low-
speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the
operational current of real-time clock 2.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer
operates.
6. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ILVD when the LVD circuit operates.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode, see 21.3.3 SNOOZE mode in the RL78/L13 User’s Manual.
.
11. Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of
IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates.
12. Current flowing only to the LCD controller/driver. The value of the current for the RL78 microcontrollers is the
sum of the supply current (IDD1 or IDD2) and LCD operating current (ILCD1, ILCD2, or ILCD3), when the LCD
controller/driver operates in operation mode or HALT mode. However, not including the current flowing into
the LCD panel. Conditions of the TYP. value and MAX. value are as follows.
• Setting 20 pins as the segment function and blinking all
• Selecting fSUB for system clock when LCD clock = 128 Hz (LCDC0 = 07H)
• Setting four time slices and 1/3 bias
13. Not including the current flowing into the external division resistor when using the external resistance division
method.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. f
CLK: CPU/peripheral hardware clock frequency
4. The temperature condition for the TYP. value is TA = 25°C.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 28 of 123
2.4 AC Characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle (minimum
instruction execution time)
TCY Main system
clock (fMAIN)
operation
HS (high-speed
main) mode
2.7 V ≤ VDD ≤ 5.5 V 0.0417 1
μ
s
2.4 V ≤ VDD < 2.7 V 0.0625 1
μ
s
LS (low-speed
main) mode
1.8 V ≤ VDD ≤ 5.5 V 0.125 1
μ
s
LV (low-voltage
main) mode
1.6 V ≤ VDD ≤ 5.5 V 0.25 1
μ
s
Subsystem clock (fSUB)
operationNote
1.8 V ≤ VDD ≤ 5.5 V 28.5 30.5 31.3
μ
s
In the self
programming
mode
HS (high-speed
main) mode
2.7 V ≤ VDD ≤ 5.5 V 0.0417 1
μ
s
2.4 V ≤ VDD < 2.7 V 0.0625 1
μ
s
LS (low-speed
main) mode
1.8 V ≤ VDD ≤ 5.5 V 0.125 1
μ
s
LV (low-voltage
main) mode
1.8 V ≤ VDD ≤ 5.5 V 0.25 1
μ
s
External system clock
frequency
fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz
1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz
fEXS 32 35 kHz
External system clock input
high-level width, low-level
width
tEXH,
tEXL
2.7 V ≤ VDD ≤ 5.5 V 24 ns
2.4 V ≤ VDD < 2.7 V 30 ns
1.8 V ≤ VDD < 2.4 V 60 ns
1.6 V ≤ VDD < 1.8 V 120 ns
tEXHS,
tEXLS
13.7
μ
s
TI00 to TI07 input high-level
width, low-level width
tTIH,
tTIL
1/fMCK+10 ns
TO00 to TO07, TKBO00,
TKBO01-0 to TKBO01-2
output frequency
fTO HS (high-speed main) mode 4.0 V ≤ VDD ≤ 5.5 V 12 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
LV (low-voltage main) mode 1.6 V ≤ VDD ≤ 5.5 V 2 MHz
LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL HS (high-speed main) mode 4.0 V ≤ VDD ≤ 5.5 V 16 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
LV (low-voltage main) mode 1.8 V ≤ VDD ≤ 5.5 V 4 MHz
1.6 V ≤ VDD < 1.8 V 2 MHz
LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 4 MHz
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0 to INTP7 1.6 V ≤ VDD ≤ 5.5 V 1
μ
s
Key interrupt input high-level
width, low-level width
tKRH, tKRL KR0 to KR7 1.8 V ≤ VDD ≤ 5.5 V 250 ns
1.6 V ≤ VDD < 1.8 V 1
μ
s
IH-PWM output restart input
high-level width
tIHR INTP0 to INTP7 2 fCLK
TMKB2 forced output stop
input high-level width
tIHR INTP0 to INTP2 2 fCLK
RESET low-level width tRSL 10
μ
s
(Note and Remark are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 29 of 123
Note Operation is not possible if 1.6 V ≤ VDD < 1.8 V in LV (low-voltage main) mode while the system is operating on the
subsystem clock.
Remark f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn)
m: Unit number (m = 0), n: Channel number (n = 0 to 7))
Minimum Instruction Execution Time during Main Syste m Clo ck Operation
TCY vs VDD (HS (high-speed main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.0417
0.0625
0.05
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
Cycle time T
CY
[s]
Supply voltage V
DD
[V]
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 30 of 123
TCY vs VDD (LS (low-speed main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
0.01
1.8
0.125
Cycle time T
CY
[s]
Supply voltage V
DD
[V]
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
TCY vs VDD (LV (low-voltage main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
0.01
1.8
0.25
1.6
Cycle time T
CY
[s]
Supply voltage V
DD
[V]
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 31 of 123
AC Timing Test Points
V
IH
/V
OH
V
IL
/V
OL
Test points V
IH
/V
OH
V
IL
/V
OL
External System Clock Timing
EXCLK/EXCLKS
1/f
EX
/
1/f
EXS
t
EXL
/
t
EXLS
t
EXH
/
t
EXHS
TI/TO Timing
TI00 to TI07
t
TIL
t
TIH
TO00 to TO07, TKBO00,
TKBO01-0, TKBO01-1,
TKBO01-2
1/f
TO
Interrupt Request Input Timing
INTP0 to INTP7
t
INTL
t
INTH
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 32 of 123
Key Interrupt Input Timing
KR0 to KR7
t
KR
RESET Input Timing
RESET
t
RSL
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
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Aug 12, 2016
Page 33 of 123
2.5 Peripheral Functions Characteristics
AC Timing Test Points
V
IH
/V
OH
V
IL
/V
OL
Test points V
IH
/V
OH
V
IL
/V
OL
2.5.1 Serial array unit
(1) During commu nication at same potential (UART mode)
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rateNote
1
2.4 V≤ VDD ≤ 5.5 V fMCK/6 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 2
4.0 1.3 0.6 Mbps
1.8 V ≤ VDD ≤ 5.5 V −
fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 2
− 1.3 0.6 Mbps
1.6 V ≤ VDD ≤ 5.5 V − − fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 2
− − 0.6 Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
RL78
microcontroller
TxDq
RxDq
Rx
Tx
User device
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 34 of 123
UART mode bit w idth (during communicatio n at same potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
TxDq
RxDq
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 35 of 123
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 2.7 V ≤ VDD ≤ 5.5 V 167Note 1 500Note 1 1000Note 1 ns
2.4 V ≤ VDD ≤ 5.5 V 250Note 1 500Note 1 1000Note 1 ns
1.8 V ≤ VDD ≤ 5.5 V − 500Note 1 1000Note 1 ns
1.6 V ≤ VDD ≤ 5.5 V − −
1000Note 1 ns
SCKp high-/low-level
width
tKH1,
tKL1
4.0 V ≤ VDD ≤ 5.5 V
t
KCY1
/2
−
12
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
2.7 V ≤ VDD ≤ 5.5 V
t
KCY1
/2
−
18
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
2.4 V ≤ VDD ≤ 5.5 V
t
KCY1
/2
−
38
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
1.8 V ≤ VDD ≤ 5.5 V −
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
1.6 V ≤ VDD ≤ 5.5 V −
−
t
KCY1
/2
−
100
ns
SIp setup time
(to SCKp↑)Note 2
tSIK1 2.7 V ≤ VDD ≤ 5.5 V 44 110 110 ns
2.4 V ≤ VDD ≤ 5.5 V 75 110 110 ns
1.8 V ≤ VDD ≤ 5.5 V − 110 110 ns
1.8 V ≤ VDD ≤ 5.5 V − −
220 ns
SIp hold time
(from SCKp↑)Note 3
tKSI1 2.4 V ≤ VDD ≤ 5.5 V 19 19 19 ns
1.8 V ≤ VDD ≤ 5.5 V − 19 19 ns
1.6 V ≤ VDD ≤ 5.5 V − −
19 ns
Delay time from
SCKp↓ to
SOp outputNote 4
tKSO1 C = 30 pFNote 5 2.4 V ≤ VDD ≤ 5.5 V 25 25 25 ns
1.8 V ≤ VDD ≤ 5.5 V − 25 25 ns
1.6 V ≤ VDD ≤ 5.5 V − − 25 ns
Notes 1. The value must also be equal to or more than 2/fCLK for CSI00 and equal to or more than 4/fCLK for CSI10.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2),
g: PIM and POM numbers (g = 0, 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02))
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 36 of 123
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
timeNote 5
tKCY2 4.0 V ≤ VDD ≤ 5.5 V fMCK > 20 MHz 8/fMCK − − ns
fMCK ≤ 20 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.7 V ≤ VDD ≤ 5.5 V fMCK > 16 MHz 8/fMCK − − ns
fMCK ≤ 16 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.4 V ≤ VDD ≤ 5.5 V 6/fMCK
and 500
6/fMCK 6/fMCK ns
1.8 V ≤ VDD ≤ 5.5 V − 6/fMCK 6/fMCK ns
1.6 V ≤ VDD ≤ 5.5 V − − 6/fMCK ns
SCKp high-/low-
level width
tKH2,
tKL2
4.0 V ≤ VDD ≤ 5.5 V tKCY2/2−7 tKCY2/2−7 tKCY2/2−7 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY2/2−8 tKCY2/2−8 tKCY2/2−8 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY2/2−18 tKCY2/2−18 tKCY2/2−18 ns
1.8 V ≤ VDD ≤ 5.5 V − tKCY2/2−18 tKCY2/2−18 ns
1.6 V ≤ VDD ≤ 5.5 V − − tKCY2/2−66 ns
SIp setup time
(to SCKp↑)Note 1
tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+20 1/fMCK+30 1/fMCK+30 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+30 1/fMCK+30 1/fMCK+30 ns
1.8 V ≤ VDD ≤ 5.5 V − 1/fMCK+30 1/fMCK+30 ns
1.6 V ≤ VDD ≤ 5.5 V − − 1/fMCK+40 ns
SIp hold time
(from
SCKp↑)Note 2
tKSI2 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+31 1/fMCK+31 1/fMCK+31 ns
1.8 V ≤ VDD ≤ 5.5 V − 1/fMCK+31 1/fMCK+31 ns
1.6 V ≤ VDD ≤ 5.5 V − −
1/f
MCK
+250
ns
Delay time from
SCKp↓ to SOp
outputNote 3
tKSO2 C = 30 pFNote 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+44
2/f
MCK
+110
2/f
MCK
+110
ns
2.4 V ≤ VDD ≤ 5.5 V 2/fMCK+75
2/f
MCK
+110
2/f
MCK
+110
ns
1.8 V ≤ VDD ≤ 5.5 V −
2/f
MCK
+110
2/f
MCK
+110
ns
1.6 V ≤ VDD ≤ 5.5 V − −
2/f
MCK
+220
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2),
g: PIM number (g = 0, 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02))
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 37 of 123
CSI mode connection diagram (during communication at same potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User device
SIp SO
CSI mode serial transfer timing (during commun i cation at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
Input data
t
KSO1, 2
Output data
SCKp
CSI mode serial transfer timing (during commun i cation at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
Input data
t
KSO1, 2
Output data
SCKp
Remarks 1. p: CSI number (p = 00, 10)
2. m: Unit number, n: Channel number (mn = 00, 02)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 38 of 123
(4) During communi cation at same potential (simplified I2C mode)
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLr clock
frequency
fSCL 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000Note
1
400Note 1 400Note 1 kHz
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
400Note 1 400Note 1 400Note 1 kHz
1.8 V (2.4 VNote 3) ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
300Note 1 300Note 1 300Note 1 kHz
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
−
– 250Note 1 kHz
Hold time when
SCLr = “L”
tLOW 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 1150 1150 ns
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150 1150 1150 ns
1.8 V (2.4 VNote 3) ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550 1550 1550 ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
– – 1850 ns
Hold time when
SCLr = “H”
tHIGH 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 1150 1150 ns
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150 1150 1150 ns
1.8 V (2.4 VNote 3) ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550 1550 1550 ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
– – 1850 ns
Data setup time
(reception)
tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK+
85Note 2
1/fMCK+
145Note 2
1/fMCK+
145Note 2
ns
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK+
145Note 2
1/fMCK+
145Note 2
1/fMCK+
145Note 2
ns
1.8 V (2.4 VNote 3) ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1/fMCK+
230Note 2
1/fMCK+
230Note 2
1/fMCK+
230Note 2
ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
– –
1/fMCK+
290Note 2
ns
Data hold time
(transmission)
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 305 0 305 0 305 ns
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 355 0 355 0 355 ns
1.8 V (2.4 VNote 3) ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
0 405 0 405 0 405 ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
– – – – 0 405 ns
(Notes, Caution, and Remarks are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 39 of 123
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
3. Condition in the HS (high-speed main) mode
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
Simplified I2C mode connection diagram (during communication at same p otential)
RL78
microcontroller
SDAr
SCLr
SDA
SCL
User device
V
DD
R
b
Simplified I2C mode serial transfer timing (during communication at same p o tential)
SDAr
t
LOW
t
HIGH
t
HD : DAT
SCLr
t
SU : DAT
1/f
SCL
Remarks 1. R
b[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 10), g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0-3), mn = 00-03, 10-13)
<R>
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 40 of 123
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate Reception 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fMCK/6Note
1
fMCK/6Note
1
fMCK/6Note
1
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 3
4.0 1.3 0.6 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK/6Note
1
fMCK/6Note
1
fMCK/6Note
1
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 3
4.0 1.3 0.6 Mbps
1.8 V (2.4 VNote 4) ≤ VDD < 3.3
V,
1.6 V ≤ Vb ≤ 2.0 V
fMCK/6
Note s1, 2
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 3
4.0 1.3 0.6 Mbps
Notes 1. Transfer rate in SNOOZE mode is 4800 bps only.
2. Use it with VDD ≥ Vb.
3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V)
4. Condition in the HS (high-speed main) mode
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. V
b[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 41 of 123
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate Trans
mission
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Note 1 Note 1 Note 1 bps
Theoretical value of the maximum
transfer rate
(Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V)
2.8Note 2 2.8Note 2 2.8
Note 2 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 3 Note 3 Note 3 bps
Theoretical value of the maximum
transfer rate
(Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V)
1.2Note 4 1.2Note 4 1.2
Note 4 Mbps
1.8 V (2.4 VNote 8) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Notes
5, 6 Notes
5, 6 Notes
5, 6
bps
Theoretical value of the maximum
transfer rate
(Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V)
0.43Note 7 0.43Note 7 0.43Note 7 Mbps
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.0
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5. Use it with VDD ≥ Vb.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 42 of 123
Notes 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 1.8 V (2.4 VNote 8) ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 1.5
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
8. Condition in the HS (high-speed main) mode
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the
TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
RL78
microcontroller
TxDq
RxDq
Rx
Tx
User device
V
b
R
b
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 43 of 123
UART mode bit width (during communication at different potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq
Remarks 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 44 of 123
(6) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
200 1150 1150 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
300 1150 1150 ns
SCKp high-level
width
tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
t
KCY1
/2
−
50
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
t
KCY1
/2
−
120
t
KCY1
/2
−
120
t
KCY1
/2
−
120
ns
SCKp low-level
width
tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
t
KCY1
/2
−
7
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
t
KCY1
/2
−
10
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
SIp setup time
(to SCKp↑)Note 1
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
58 479 479 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
121 479 479 ns
SIp hold time
(from SCKp↑)Note
1
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 10 10 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 10 10 ns
Delay time from
SCKp↓ to
SOp outputNote 1
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
60 60 60 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
130 130 130 ns
SIp setup time
(to SCKp↓)Note 2
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
23 110 110 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
33 110 110 ns
SIp hold time
(from SCKp↓)Note
2
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 10 10 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 10 10 ns
Delay time from
SCKp↑ to
SOp outputNote 2
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 10 10 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 10 10 ns
(Notes, Caution and Remarks are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 45 of 123
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the
SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. R
b[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
4. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 46 of 123
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
300 1150 1150 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
500 1150 1150 ns
1.8 V (2.4 V
Note 1
)
≤
V
DD
<
3.3
V,
1.6 V ≤ Vb ≤ 1.8 V
Note 2
,
Cb = 30 pF, Rb = 5.5 kΩ
1150 1150 1150 ns
SCKp high-level
width
tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
t
KCY1
/2
−
75
t
KCY1
/2
−
75
t
KCY1
/2
−
75
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
t
KCY1
/2
−
170
t
KCY1
/2
−
170
t
KCY1
/2
−
170
ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
t
KCY1
/2
−
458
t
KCY1
/2
−
458
t
KCY1
/2
−
458
ns
SCKp low-level
width
tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
t
KCY1
/2
−
12
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
t
KCY1
/2
−
18
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
t
KCY1
/2
−
50
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
SIp setup time
(to SCKp↑)Note 3
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
81 479 479 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177 479 479 ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
479 479 479 ns
SIp hold time
(from SCKp↑)Note
3
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19 19 19 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19 19 19 ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
19 19 19 ns
Delay time from
SCKp↓ to
SOp outputNote 3
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
100 100 100 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
195 195 195 ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
483 483 483 ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 47 of 123
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↓)Note 4
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
44 110 110 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44 110 110 ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
110 110 110 ns
SIp hold time
(from SCKp↓)Note
4
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19 19 19 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19 19 19 ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
19 19 19 ns
Delay time from
SCKp↑ to
SOp outputNote 4
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
25 25 25 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25 25 25 ns
1.8 V (2.4 VNote 1) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 kΩ
25 25 25 ns
Notes 1. Condition in HS (high-speed main) mode
2. Use it with VDD ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
4. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the
SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
V
b
R
b
SCKp
SOp
SCK
SI
User device
SIp SO
V
b
R
b
<Master>
RL78
microcontroller
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 48 of 123
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
Input data
t
KSO1
Output data
SCKp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
Input data
t
KSO1
Output data
SCKp
Remarks 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10), m: Unit number , n: Channel number (mn = 00, 02),
g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 49 of 123
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
timeNote 1
tKCY2 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤
4.0 V
20 MHz < fMCK 12/fMCK –
– ns
8 MHz < fMCK ≤ 20 MHz 10/fMCK – – ns
4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK – ns
fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤
2.7 V
20 MHz < fMCK 16/fMCK – – ns
16 MHz < fMCK ≤ 20 MHz 14/fMCK – – ns
8 MHz < fMCK ≤ 16 MHz 12/fMCK – – ns
4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK – ns
fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns
1.8 V (2.4 VNote 2) ≤
VDD < 3.3 V,
1.6 V ≤ Vb ≤
2.0 VNote 3
20 MHz < fMCK 36/fMCK – – ns
16 MHz < fMCK ≤ 20 MHz 32/fMCK – – ns
8 MHz < fMCK ≤ 16 MHz 26/fMCK – – ns
4 MHz < fMCK ≤ 8 MHz 16/fMCK 16/fMCK – ns
fMCK ≤ 4 MHz 10/fMCK 10/fMCK 10/fMCK ns
SCKp high-
/low-level width
tKH2,
tKL2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2
− 12
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2
− 18
tKCY2/2
− 50
tKCY2/2
− 50
ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3
tKCY2/2
− 50
tKCY2/2
− 50
tKCY2/2
− 50
ns
SIp setup time
(to SCKp↑)Note 4
tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
SIp hold time
(from
SCKp↑)Note 5
tKSI2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
Delay time
from SCKp↓ to
SOp outputNote 6
tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 50 of 123
Notes 1. Transfer rate in SNOOZE mode: MAX. 1 Mbps
2. Condition in HS (high-speed main) mode
3. Use it with VDD ≥ Vb.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User device
SIp SO
V
b
R
b
<Slave>
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 51 of 123
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
Input data
t
KSO2
Output data
SCKp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
Input data
t
KSO2
Output data
SCKp
Remarks 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02),
g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn)
m: Unit number, n: Channel number (mn = 00, 02))
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 52 of 123
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLr clock
frequency
fSCL 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000Note
1
300Note 1 300Note 1 kHz
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000Note
1
300Note 1 300Note 1 kHz
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
400Note 1 300Note 1 300Note 1 kHz
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
400Note 1 300Note 1 300Note 1 kHz
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 100 pF, Rb = 5.5 kΩ
300Note 1
300Note 1 300Note 1 kHz
Hold time when
SCLr = “L”
tLOW 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 1550 1550 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 1550 1550 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1150 1550 1550 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1150 1550 1550 ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 100 pF, Rb = 5.5 kΩ
1550 1550 1550 ns
Hold time when
SCLr = “H”
tHIGH 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
245 610 610 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
200 610 610 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
675 610 610 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
600 610 610 ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 100 pF, Rb = 5.5 kΩ
610 610 610 ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 53 of 123
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time
(reception)
tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK+
135Note 4
1/fMCK+
190Note 4
1/fMCK+
190Note 4
ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK+
135Note 4
1/fMCK+
190Note 4
1/fMCK+
190Note 4
ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1/fMCK+
190Note 4
1/fMCK+
190Note 4
1/fMCK+
190Note 4
ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK+
190Note 4
1/fMCK+
190Note 4
1/fMCK+
190Note 4
ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK+
190Note 4
1/fMCK+
190Note 4
1/fMCK+
190Note 4
ns
Data hold time
(transmission)
tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 305 0 305 0 305 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 305 0 305 0 305 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0 355 0 355 0 355 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0 355 0 355 0 355 ns
1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 VNote 3,
Cb = 100 pF, Rb = 5.5 kΩ
0 405 0 405 0 405 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Condition in HS (high-speed main) mode
3. Use it with VDD ≥ Vb.
4. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and
the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 54 of 123
Simplified I2C mode connection diagram (during communication at different potential)
SDAr
SCLr
SDA
SCL
User device
V
b
R
b
V
b
R
b
RL78
microcontroller
Simplified I2C mode serial transfe r timing (during communication at different potential)
SDAr
tLOW tHIGH
tHD : DAT
SCLr
tSU : DAT
1/fSCL
Remarks 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 10), g: PIM, POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 02)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 55 of 123
2.5.2 Serial interface IICA
(1) I2C standard mode (1/2)
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock
frequency
fSCL Normal
mode: fCLK
≥ 1 MHz
2.7 V ≤ VDD ≤ 5.5 V 0 100 0 100 0 100 kHz
1.8 V (2.4 VNote 3) ≤
VDD ≤ 5.5 V
0 100 0 100 0 100 kHz
1.6 V ≤ VDD ≤ 5.5 V – – – – 0 100 kHz
Setup time of
restart condition
tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 4.7 4.7 4.7
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 4.7 4.7 4.7
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 4.7
μ
s
Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 4.0 4.0 4.0
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 4.0 4.0 4.0
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 4.0
μ
s
Hold time when
SCLA0 = “L”
tLOW 2.7 V ≤ VDD ≤ 5.5 V 4.7 4.7 4.7
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 4.7 4.7 4.7
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 4.7
μ
s
Hold time when
SCLA0 = “H”
tHIGH 2.7 V ≤ VDD ≤ 5.5 V 4.0 4.0 4.0
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 4.0 4.0 4.0
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 4.0
μ
s
(Notes, Caution and Remark are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 56 of 123
(1) I2C standard mode (2/2)
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time
(reception)
tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 250 250 250 ns
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 250 250 250 ns
1.6 V ≤ VDD ≤ 5.5 V – – – – 250 ns
Data hold time
(transmission)Note 2
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 0 3.45
μ
s
Setup time of stop
condition
tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 4.0 4.0 4.0
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 4.0 4.0 4.0
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 4.0
μ
s
Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 4.7 4.7 4.7
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 4.7 4.7 4.7
μ
s
1.6 V ≤ VDD ≤ 5.5 V – – – – 4.7
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
3. Condition in HS (high-speed main) mode
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 57 of 123
(2) I2C fast mode
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock
frequency
fSCL Fast
mode: fCLK
≥ 3.5 MHz
2.7 V ≤ VDD ≤
5.5 V
0 400 0 400 0 400 kHz
1.8 V (2.4 VNote 3)
≤ VDD ≤ 5.5 V
0 400 0 400 0 400 kHz
Setup time of
restart condition
tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
Hold time when
SCLA0 =“L”
tLOW 2.7 V ≤ VDD ≤ 5.5 V 1.3 1.3 1.3
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 1.3 1.3 1.3
μ
s
Hold time when
SCLA0 =“H”
tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
Data setup time
(reception)
tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 100 100 100 ns
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 100 100 100 ns
Data hold time
(transmission)Note 2
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.9 0 0.9 0 0.9
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0 0.9 0 0.9 0 0.9
μ
s
Setup time of stop
condition
tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0.6 0.6 0.6
μ
s
Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 1.3 1.3 1.3
μ
s
1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 1.3 1.3 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
3. Condition in HS (high-speed main) mode
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode: Cb = 320 pF, Rb = 1.1 kΩ
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 58 of 123
(3) I2C fast mode plus
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock
frequency
fSCL Fast mode
plus: fCLK ≥
10 MHz
2.7 V ≤ VDD ≤
5.5 V
0 1000 – – kHz
Setup time of restart
condition
tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 – –
μ
s
Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 – –
μ
s
Hold time when
SCLA0 =“L”
tLOW 2.7 V ≤ VDD ≤ 5.5 V 0.5 – –
μ
s
Hold time when
SCLA0 =“H”
tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26 – –
μ
s
Data setup time
(reception)
tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 50 – – ns
Data hold time
(transmission)Note 2
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45 – –
μ
s
Setup time of stop
condition
tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.26 – –
μ
s
Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 0.5 – –
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW tR
tHIGH tF
tHD:STA
tBUF
Stop
condition Start
condition Restart
condition Stop
condition
tSU:DAT
tSU:STA tSU:STOtHD:STA
tHD:DAT
SCLA0
SDAA0
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 59 of 123
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Input channel
Reference voltage (+) = AVREFP
Reference voltage (−) = AVREFM
Reference voltage (+) = VDD
Reference voltage (−) = VSS
Reference voltage (+) = VBGR
Reference voltage (−) = AVREFM
ANI0, ANI1 – See 2.6.1 (2). See 2.6.1 (3).
ANI16 to ANI25 See 2.6.1 (1).
Internal reference voltage
Temperature sensor output
voltage
See 2.6.1 (1). –
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1
(ADREFM = 1), target pins: ANI16 to ANI25, internal reference voltage, and temp erature sensor outp ut voltage
(T
A
=
−
40 to +85
°
C, 1.6 V
≤
V
DD
≤
5.5 V, V
SS
= 0 V, Refe rence voltage (+) = AV
REFP
, Reference voltage (
−
) = AV
REFM
= 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL
10-bit resolution
AVREFP = VDDNote 3
1.8 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB
1.6 V ≤ AVREFP ≤ 5.5 VNote 4 1.2 ±8.5 LSB
Conversion time tCONV 10-bit resolution
Target pin:
ANI16 to ANI25
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
1.8 V ≤ VDD ≤ 5.5 V 17 39
μ
s
1.6 V ≤ VDD ≤ 5.5 V 57 95
μ
s
10-bit resolution
Target pin: Internal
reference voltage,
and temperature
sensor output
voltage
(HS (high-speed
main) mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 10-bit resolution
AVREFP = VDDNote 3
1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR
1.6 V ≤ AVREFP ≤ 5.5 VNote 4 ±0.60 %FSR
Full-scale errorNotes 1, 2 EFS 10-bit resolution
AVREFP = VDDNote 3
1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR
1.6 V ≤ AVREFP ≤ 5.5 VNote 4 ±0.60 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution
AVREFP = VDDNote 3
1.8 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB
1.6 V ≤ AVREFP ≤ 5.5 VNote 4 ±6.0 LSB
Differential linearity errorNote 1 DLE 10-bit resolution
AVREFP = VDDNote 3
1.8 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB
1.6 V ≤ AVREFP ≤ 5.5 VNote 4 ±2.5 LSB
Analog input voltage VAIN ANI16 to ANI25 0 AVREFP V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VBGRNote 5 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VTMPS25Note 5 V
(Notes are listed on the next page.)
RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 60 of 123
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±4 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.2%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2 LSB to the MAX. value when AVREFP = VDD.
4. Values when the conversion time is set to 57
μ
s (min.) and 95
μ
s (max.).
5. See 2.6.2 Temperature se nsor/internal reference voltage characteristics.
(2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0),
target pins: ANI0, ANI1, ANI16 to ANI25, internal reference voltage, and temperature sensor output voltage
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNotes 1, 2 AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB
1.6 V ≤ VDD ≤ 5.5 VNote 3 1.2 ±10.5 LSB
Conversion time tCONV 10-bit resolution
Target pin:
ANI0, ANI1,
ANI16 to ANI25Note 3
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
1.8 V ≤ VDD ≤ 5.5 V 17 39
μ
s
1.6 V ≤ VDD ≤ 5.5 V 57 95
μ
s
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor
output voltage
(HS (high-speed main)
mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
1.6 V ≤ VDD ≤ 5.5 VNote 3 ±0.85 %FSR
Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
1.6 V ≤ VDD ≤ 5.5 VNote 3 ±0.85 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±4.0 LSB
1.6 V ≤ VDD ≤ 5.5 VNote 3 ±6.5 LSB
Differential linearity error Note
1
DLE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±2.0 LSB
1.6 V ≤ VDD ≤ 5.5 VNote 3 ±2.5 LSB
Analog input voltage VAIN ANI0, ANI1, ANI16 to ANI25 0 VDD V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VBGRNote 4 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VTMPS25Note 4 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Values when the conversion time is set to 57
μ
s (min.) and 95
μ
s (max.).
4. See 2.6.2 Temperature se nsor/internal reference voltage characteristics.
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(3) When reference voltage (+) = Internal reference voltage ( ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target pins: ANI0, ANI16 to ANI25
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGRNote 3,
Reference voltage (−) = AVREFMNote 4 = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB
Analog input voltage VAIN 0 VBGRNote 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (−) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the AVREFM MAX. value.
Integral linearity error: Add ±0.5 LSB to the AVREFM MAX. value.
Differential linearity error: Add ±0.2 LSB to the AVREFM MAX. value.
2.6.2 Temperature sensor /internal reference voltage characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mo de)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 ADS register = 80H, TA = +25°C 1.05 V
Internal reference output voltage VBGR ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature
−3.6 mV/°C
Operation stabilization wait time tAMP 5
μ
s
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2.6.3 Comparator characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range Ivref 0 VDD −
1.4
V
Ivcmp −0.3
VDD +
0.3
V
Output delay td VDD = 3.0 V
Input slew rate > 50 mV/
μ
s
Comparator high-speed mode,
standard mode
1.2
μ
s
Comparator high-speed mode,
window mode
2.0
μ
s
Comparator low-speed mode,
standard mode
3.0 5.0
μ
s
High-electric-potential
reference voltage
VTW+ Comparator high-speed mode,
window mode
0.66VDD 0.76VDD 0.86VDD V
Low-electric-potential
reference voltage
VTW− Comparator high-speed mode,
window mode
0.14VDD 0.24VDD 0.34VDD V
Operation stabilization
wait time
tCMP 100
μ
s
Internal reference
output voltageNote
VBGR 2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V
Note Cannot be used in LS (low-speed main) mode, LV (low-voltage main) mode, subsystem clock operation, and
STOP mode.
2.6.4 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR When power supply rises 1.47 1.51 1.55 V
VPDR When power supply falls 1.46 1.50 1.54 V
Minimum pulse widthNote TPW 300
μ
s
Note This is the time required for the POR circuit to execute a reset operation when VDD falls below VPDR. When the
microcontroller enters STOP mode and when the main system clock (fMAIN) has been stopped by setting bit 0
(HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required for
the POR circuit to execute a reset operation between when VDD falls below 0.7 V and when VDD rises to VPOR or
higher.
Supply voltage (V
DD
)
TPW
VPOR
V
PDR
or 0.7 V
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2.6.5 LVD circuit characteristics
LVD Detection Voltage o f Reset Mode and Interrupt Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection
voltage
Supply voltage level VLVD0 When power supply rises 3.98 4.06 4.14 V
When power supply falls 3.90 3.98 4.06 V
VLVD1 When power supply rises 3.68 3.75 3.82 V
When power supply falls 3.60 3.67 3.74 V
VLVD2 When power supply rises 3.07 3.13 3.19 V
When power supply falls 3.00 3.06 3.12 V
VLVD3 When power supply rises 2.96 3.02 3.08 V
When power supply falls 2.90 2.96 3.02 V
VLVD4 When power supply rises 2.86 2.92 2.97 V
When power supply falls 2.80 2.86 2.91 V
VLVD5 When power supply rises 2.76 2.81 2.87 V
When power supply falls 2.70 2.75 2.81 V
VLVD6 When power supply rises 2.66 2.71 2.76 V
When power supply falls 2.60 2.65 2.70 V
VLVD7 When power supply rises 2.56 2.61 2.66 V
When power supply falls 2.50 2.55 2.60 V
VLVD8 When power supply rises 2.45 2.50 2.55 V
When power supply falls 2.40 2.45 2.50 V
VLVD9 When power supply rises 2.05 2.09 2.13 V
When power supply falls 2.00 2.04 2.08 V
VLVD10 When power supply rises 1.94 1.98 2.02 V
When power supply falls 1.90 1.94 1.98 V
VLVD11 When power supply rises 1.84 1.88 1.91 V
When power supply falls 1.80 1.84 1.87 V
VLVD12 When power supply rises 1.74 1.77 1.81 V
When power supply falls 1.70 1.73 1.77 V
VLVD13 When power supply rises 1.64 1.67 1.70 V
When power supply falls 1.60 1.63 1.66 V
Minimum pulse width tLW 300
μ
s
Detection delay time 300
μ
s
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LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and reset
mode
VLVD13 VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 V
VLVD12 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.74 1.77 1.81 V
Falling interrupt voltage 1.70 1.73 1.77 V
VLVD11 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V
Falling interrupt voltage 1.80 1.84 1.87 V
VLVD4 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVD11 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V
VLVD10 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V
Falling interrupt voltage 1.90 1.94 1.98 V
VLVD9 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V
Falling interrupt voltage 2.00 2.04 2.08 V
VLVD2 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V
Falling interrupt voltage 3.00 3.06 3.12 V
VLVD8 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V
VLVD7 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V
Falling interrupt voltage 2.50 2.55 2.60 V
VLVD6 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V
Falling interrupt voltage 2.60 2.65 2.70 V
VLVD1 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V
Falling interrupt voltage 3.60 3.67 3.74 V
VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V
VLVD4 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVD3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V
Falling interrupt voltage 2.90 2.96 3.02 V
VLVD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V
Falling interrupt voltage 3.90 3.98 4.06 V
2.6.6 Supply voltage rising slope characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD rising slope SVDD 54 V/ms
Caution Make sure to keep th e internal reset state by the LVD circu it or an external reset until VDD reaches the
operating voltage range sh o wn in 2.4 AC Characteristics.
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2.7 LCD Characteristics
2.7.1 External resistance division method
(1) Static display mode
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VL4 2.0 VDD V
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VL4 2.7 VDD V
(3) 1/3 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VL4 2.5 VDD V
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2.7.2 Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD output voltage variation range VL1 C1 to C4Note 1
= 0.47
μ
FNote 2
VLCD = 04H 0.90 1.00 1.08 V
VLCD = 05H 0.95 1.05 1.13 V
VLCD = 06H 1.00 1.10 1.18 V
VLCD = 07H 1.05 1.15 1.23 V
VLCD = 08H 1.10 1.20 1.28 V
VLCD = 09H 1.15 1.25 1.33 V
VLCD = 0AH 1.20 1.30 1.38 V
VLCD = 0BH 1.25 1.35 1.43 V
VLCD = 0CH 1.30 1.40 1.48 V
VLCD = 0DH 1.35 1.45 1.53 V
VLCD = 0EH 1.40 1.50 1.58 V
VLCD = 0FH 1.45 1.55 1.63 V
VLCD = 10H 1.50 1.60 1.68 V
VLCD = 11H 1.55 1.65 1.73 V
VLCD = 12H 1.60 1.70 1.78 V
VLCD = 13H 1.65 1.75 1.83 V
Doubler output voltage VL2 C1 to C4Note 1 = 0.47
μ
F 2 VL1 − 0.10 2 VL1 2 VL1 V
Tripler output voltage VL4 C1 to C4Note 1 = 0.47
μ
F 3 VL1 − 0.15 3 VL1 3 VL1 V
Reference voltage setup timeNote 2 tVWAIT1 5 ms
Voltage boost wait timeNote 3 tVWAIT2 C1 to C4Note 1 = 0.47
μ
F 500
ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47
μ
F ± 30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON =
1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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(2) 1/4 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD output voltage variation range VL1 C1 to C5Note 1
= 0.47
μ
FNote 2
VLCD = 04H 0.90 1.00 1.08 V
VLCD = 05H 0.95 1.05 1.13 V
VLCD = 06H 1.00 1.10 1.18 V
VLCD = 07H 1.05 1.15 1.23 V
VLCD = 08H 1.10 1.20 1.28 V
VLCD = 09H 1.15 1.25 1.33 V
VLCD = 0AH 1.20 1.30 1.38 V
Doubler output voltage VL2 C1 to C5Note 1 = 0.47
μ
F 2 VL1−0.08 2 VL1 2 VL1 V
Tripler output voltage VL3 C1 to C5Note 1 = 0.47
μ
F 3 VL1−0.12 3 VL1 3 VL1 V
Quadruply output voltage VL4 C1 to C5Note 1 = 0.47
μ
F 4 VL1−0.16 4 VL1 4 VL1 V
Reference voltage setup timeNote 2 tVWAIT1 5 ms
Voltage boost wait timeNote 3 tVWAIT2 C1 to C5Note 1 = 0.47
μ
F 500 ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47
μ
F ± 30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON =
1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
2.7.3 Capacitor split method
(1) 1/3 bias method
(TA = −40 to +85°C, 2.2 V ≤ VD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VL4 voltage VL4 C1 to C4 = 0.47
μ
FNote 2 VDD V
VL2 voltage VL2 C1 to C4 = 0.47
μ
FNote 2 2/3 VL4 −
0.1
2/3 VL4 2/3 VL4 +
0.1
V
VL1 voltage VL1 C1 to C4 = 0.47
μ
FNote 2 1/3 VL4 −
0.1
1/3 VL4 1/3 VL4 +
0.1
V
Capacitor split wait timeNote 1 tVWAIT 100 ms
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47
μ
F ± 30%
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2.8 RAM Data Retention Characteristics
(TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.46Note 5.5 V
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Caution Data in RAM are not retained if the CPU operates outside the specified operating voltage range.
Therefore, place the CPU in ST OP mode before the operating voltage drop s b elow the specified range.
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
RAM data retention mode
V
DDDR
Operation mode
2.9 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V 1 24 MHz
Number of code flash rewritesNotes 1, 2, 3 Cerwr Retained for 20 years
TA = 85°C
1,000 Times
Number of data flash rewritesNotes 1, 2, 3 Retained for 1 year
TA = 25°C
1,000,000
Retained for 5 years
TA = 85°C
100,000
Retained for 20 years
TA = 85°C
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test.
Remark When updating data multiple times, use the flash memory as one for updating data.
2.10 Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
<R>
<R>
<R>
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2.11 Timing Specifications for Switching Flash Memory Programming Modes
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Time to complete the
communication for the initial setting
after the external reset is released
tSUINIT POR and LVD reset must be released before
the external reset is released.
100 ms
Time to release the external reset
after the TOOL0 pin is set to the
low level
tSU POR and LVD reset must be released before
the external reset is released.
10
μ
s
Time to hold the TOOL0 pin at the
low level after the external reset is
released
(excluding the processing time of
the firmware to control the flash
memory)
tHD POR and LVD reset must be released before
the external reset is released.
1 ms
RESET
TOOL0
<1> <2> <3>
t
SUINIT
723 s + t
HD
processing
time
t
SU
<4>
00H reception
(TOOLRxD, TOOLTxD mode)
<1> The low level is input to the TOOL0 pin.
<2> The external reset is released (POR and LVD reset must be released before the external
reset is released.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and completion the
baud rate setting.
Remark t
SUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU: Time to release the external reset after the TOOL0 pin is set to the low level
tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to
+105°C)
This chapter describes the following electrical specifications.
Target products G: Industrial applications TA = −40 to +105°C
R5F10WLAGFB, R5F10WLCGFB, R5F10WLDGFB,
R5F10WLEGFB, R5F10WLFGFB, R5F10WLGGFB
R5F10WMAGFB, R5F10WMCGFB, R5F10WMDGFB,
R5F10WMEGFB, R5F10WMFGFB, R5F10WMGGFB
Cautions 1. The RL78/L13 microcontrollers have an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products designated for
mass production, because the guaranteed number of rewritable times of the flash memory may
be exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 With functions for
each product in the RL78/L13 User’s Manual.
3. Consult Renesas salesperson and distributor for derating when the product is used at TA = +85°C
to +105°C. Note that derating means “systematically lowering the load from the rated value to
improve reliability”.
Remark When RL78/L13 is used in the range of TA = -40 to +85°C, see CHAPTER 2 ELECTRICAL
SPECIFICATIONS (TA = -40 to +85°C).
<R>
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“G: Industrial applications (TA = −40 to +105°C) differ from “A: Consumer applications” in function as follows:
Fields of Application A: Consumer applications G: Industrial applications
Operating ambient
temperature
TA = −40 to +85°C TA = −40 to +105°C
Operation mode
operating voltage
range
HS (high-speed main) mode:
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
HS (high-speed main) mode only:
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
High-speed on-chip
oscillator clock
accuracy
1.8 V ≤ VDD ≤ 5.5 V:
±1.0 % @ TA = −20 to +85°C
±1.5 % @ TA = −40 to −20°C
1.6 V ≤ VDD < 1.8 V:
±5.0 % @ TA = −20 to +85°C
±5.5 % @ TA = −40 to −20°C
2.4 V ≤ VDD ≤ 5.5 V:
±2.0 % @ TA = +85 to +105°C
±1.0 % @ TA = −20 to +85°C
±1.5 % @ TA = −40 to −20°C
Serial array unit UART
CSI: fCLK/2 (16 Mbps supported), fCLK/4
Simplified I2C
UART
CSI: fCLK/4
Simplified I2C
IICA Standard mode
Fast mode
Fast mode plus
Standard mode
Fase mode
Voltage detector • Rising: 1.67 V to 4.06 V (14 levels)
• Falling: 1.63 V to 3.98 V (14 levels)
• Rising: 2.61 V to 4.06 V (8 levels)
• Falling: 2.55 V to 3.98 V (8 levels)
Remark Electrical specifications of G: Industrial applications (TA = −40 to +105°C) differ from “A: Consumer
applications”. For details, see 3.1 to 3.11 below.
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (1/3)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD −0.5 to +6.5 V
REGC pin input voltage VIREGC REGC −0.3 to +2.8
and −0.3 to VDD +0.3Note 1
V
Input voltage VI1 P00 to P07, P10 to P17, P20 to P27, P30 to P35,
P40 to P47, P50 to P57, P60, P61, P70 to P77,
P121 to P127, P130, P137
−0.3 to VDD +0.3Note 2 V
VI2 P60 and P61 (N-ch open-drain) −0.3 to +6.5 V
VI3 EXCLK, EXCLKS, RESET −0.3 to VDD +0.3Note 2 V
Output voltage VO1 P00 to P07, P10 to P17, P20 to P27, P30 to P35,
P40 to P47, P50 to P57, P60, P61, P70 to P77,
P121 to P127, P130, P137
−0.3 to VDD +0.3Note 2 V
Analog input voltage VAI1 ANI0, ANI1, ANI16 to ANI26 −0.3 to VDD +0.3
and −0.3 to AVREF(+) +0.3Notes 2, 3
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damag e, and th erefore the p roduct mu st be u sed under cond itions that en sure th at
the absolute maximum ratings are n ot exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. V
SS: Reference voltage
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Page 73 of 123
Absolute Maximum Ratings (2/3)
Parameter Symbol Conditions Ratings Unit
LCD voltage VL1 VL1 voltageNote 1 −0.3 to +2.8 and
−0.3 to VL4 +0.3
V
VL2 VL2 voltageNote 1 −0.3 to VL4 +0.3Note 2 V
VL3 VL3 voltageNote 1 −0.3 to VL4 +0.3Note 2 V
VL4 VL4 voltageNote 1 −0.3 to +6.5 V
VLCAP CAPL, CAPH voltageNote 1 −0.3 to VL4 +0.3Note 2 V
VOUT COM0 to COM7
SEG0 to SEG50
output voltage
External resistance division method −0.3 to VDD +0.3Note 2 V
Capacitor split method −0.3 to VDD +0.3Note 2 V
Internal voltage boosting method −0.3 to VL4 +0.3Note 2 V
Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins;
it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting
method or capacitance split method, connect these pins to VSS via a capacitor (0.47
μ
F ± 30%) and connect a
capacitor (0.47
μ
F ± 30%) between the CAPL and CAPH pins.
2. Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damag e, and th erefore the p roduct mu st be u sed under cond itions that en sure th at
the absolute maximum ratings are n ot exceeded.
Remark V
SS: Reference voltage
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Page 74 of 123
Absolute Maximum Ratings (TA = 25°C) (3/3)
Parameter Symbol Conditions Ratings Unit
Output current, high IOH1 Per pin P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47,
P50 to P57, P60, P61,
P70 to P77, P125 to P127, P130
−40 mA
Total of all pins
−170 mA
P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47,
P50 to P57, P60, P61,
P70 to P77, P125 to P127, P130
−170 mA
IOH2 Per pin P20, P21 −0.5 mA
Total of all pins −1 mA
Output current, low IOL1 Per pin P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47,
P50 to P57, P60, P61,
P70 to P77, P125 to P127, P130
40 mA
Total of all pins
170 mA
P40 to P47, P130 70 mA
P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P50 to P57, P60, P61,
P70 to P77, P125 to P127
100 mA
IOL2 Per pin P20, P21 1 mA
Total of all pins 2 mA
Operating ambient
temperature
TA In normal operation mode −40 to +105 °C
In flash memory programming mode °C
Storage temperature Tstg −65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damag e, and th erefore the p roduct mu st be u sed under cond itions that en sure th at
the absolute maximum ratings are n ot exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
<R>
<R>
<R>
<R>
<R>
<R>
<R>
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Page 75 of 123
3.2 Oscillator Characteristics
3.2.1 X1 and XT1 oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation
frequency (fX)Note
Ceramic resonator/
crystal resonator
2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0
XT1 clock oscillation
frequency (fXT)Note
Crystal resonator 32 32.768 35 kHz
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, see 5.4 System Clock Oscillator in the RL78/L13 User’s
Manual.
3.2.2 On-chip oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator
clock frequencyNotes 1, 2
fIH 1 24 MHz
High-speed on-chip oscillator
clock frequency accuracy
+85 to +105°C 2.4 V ≤ VDD ≤ 5.5 V −2 +2 %
−20 to +85°C 2.4 V ≤ VDD ≤ 5.5 V −1 +1 %
−40 to −20°C 2.4 V ≤ VDD ≤ 5.5 V −1.5 +1.5 %
Low-speed on-chip oscillator
clock frequency
fIL 15 kHz
Low-speed on-chip oscillator
clock frequency accuracy
−15 +15 %
Notes 1. The high-speed on-chip oscillator frequency is selected by bits 0 to 4 of the option byte (000C2H/010C2H)
and bits 0 to 2 of the HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for the instruction execution
time.
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Page 76 of 123
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output current,
highNote 1
IOH1 Per pin for P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P40 to P47, P50
to P57, P70 to P77, P125 to P127, P130
2.4 V ≤ VDD ≤ 5.5 V −3.0Note 2 mA
Total of P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P40 to P47, P50
to P57, P70 to P77, P125 to P127, P130
(When duty = 70%Note 3)
4.0 V ≤ VDD ≤ 5.5 V −45.0 mA
2.7 V ≤ VDD < 4.0 V −15.0 mA
2.4 V ≤ VDD < 2.7 V −7.0 mA
IOH2 Per pin for P20 and P21 2.4 V ≤ VDD ≤ 5.5 V −0.1Note 2 mA
Total of all pins
(When duty = 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V −0.2 mA
Notes 1. Value of the current at which the device operation is guaranteed even if the current flows from the VDD pin
to an output pin
2. Do not exceed the total current value.
3. Output current value under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −45.0 mA
Total output current of pins = (−45.0 × 0.7)/(80 × 0.01) = −39.375 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, an d P130 d o n ot out put high level in
N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
<R>
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 77 of 123
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output current,
lowNote 1
IOL1 Per pin for P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P40 to P47,
P50 to P57, P70 to P77,
P125 to P127, P130
8.5Note 2 mA
Per pin for P60 and P61 15.0Note 2 mA
Total of P40 to P47, P130
(When duty = 70%Note 3)
4.0 V ≤ VDD ≤ 5.5 V 40.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
2.4 V ≤ VDD < 2.7 V 9.0 mA
Total of P00 to P07, P10 to P17,
P22 to P27, P30 to P35, P50 to P57,
P70 to P77, P125 to P127
(When duty = 70%Note 3)
4.0 V ≤ VDD ≤ 5.5 V 60.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
2.4 V ≤ VDD < 2.7 V 20.0 mA
Total of all pins
(When duty = 70%Note 3)
100.0 mA
IOL2 Per pin for P20 and P21 0.4Note 2 mA
Total of all pins
(When duty = 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V 0.8 mA
Notes 1. Value of the current at which the device operation is guaranteed even if the current flows from an output pin
to the VSS pin
2. Do not exceed the total current value.
3. Output current value under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 40.0 mA
Total output current of pins = (40.0 × 0.7)/(80 × 0.01) = 35.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 78 of 123
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage,
high
VIH1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130,
P137
Normal input buffer 0.8VDD VDD V
VIH2 P03, P05, P06, P16, P17, P34, P43,
P44, P46, P47, P53, P55
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
2.2 VDD V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
2.0 VDD V
TTL input buffer
2.4 V ≤ VDD < 3.3 V
1.5 VDD V
VIH3 P20, P21 0.7VDD VDD V
VIH4 P60, P61 0.7VDD 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V
Input voltage, low VIL1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130,
P137
Normal input buffer 0 0.2VDD V
VIL2 P03, P05, P06, P16, P17, P34, P43,
P44, P46, P47, P53, P55
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
0 0.8 V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
0 0.5 V
TTL input buffer
2.4 V ≤ VDD < 3.3 V
0 0.32 V
VIL3 P20, P21 0 0.3VDD V
VIL4 P60, P61 0 0.3VDD V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V
Caution The maximum value of VIH of pins P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56,
and P130 is VDD, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 79 of 123
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output voltage,
high
VOH1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA
VDD − 0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOH1 = −2.0 mA
VDD − 0.6 V
2.4 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.5 mA
VDD − 0.5 V
VOH2 P20 and P21 2.4 V ≤ VDD ≤ 5.5 V,
IOH2 = −100
μ
A
VDD − 0.5 V
Output voltage,
low
VOL1 P00 to P07, P10 to P17, P22 to P27,
P30 to P35, P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
0.6 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
0.4 V
2.4 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
0.4 V
VOL2 P20 and P21 2.4 V ≤ VDD ≤ 5.5 V,
IOL2 = 400
μ
A
0.4 V
VOL3 P60 and P61
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 15.0 mA
2.0 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 5.0 mA
0.4 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL3 = 3.0 mA
0.4 V
2.4 V ≤ VDD ≤ 5.5 V,
IOL3 = 2.0 mA
0.4 V
Caution P00, P04 to P07, P16, P17, P35, P42 to P44, P46, P47, P53 to P56, an d P130 d o n ot out put high level in
N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 80 of 123
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
ILIH1 P00 to P07, P10 to P17,
P22 to P27, P30 to P35,
P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130,
P137
VI = VDD 1
μ
A
ILIH2 P20 and P21, RESET VI = VDD 1
μ
A
ILIH3 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VDD In input port
mode and
when external
clock is input
1
μ
A
Resonator
connected
10
μ
A
Input leakage
current, low
ILIL1 P00 to P07, P10 to P17,
P22 to P27, P30 to P35,
P40 to P47, P50 to P57,
P70 to P77, P125 to P127, P130,
P137
VI = VSS −1
μ
A
ILIL2 P20 and P21, RESET VI = VSS −1
μ
A
ILIL3 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VSS In input port
mode and
when external
clock is input
−1
μ
A
Resonator
connected
−10
μ
A
On-chip pull-up
resistance
RU1 P00 to P07, P10 to P17,
P22 to P27, P30 to P35,
P45 to P47, P50 to P57,
P70 to P77, P125 to P127,
P130
VI = VSS 10 20 100 kΩ
RU2 P40 to P44 VI = VSS 10 20 100 kΩ
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Page 81 of 123
3.3.2 Supply current characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
IDD1Note 1 Operating
mode
HS (high-
speed main)
mode
Note 5
fHOCO = 48 MHzNo te
3,
fIH = 24 MHzNote 3
Basic
operation
VDD = 5.0 V 2.0 mA
VDD = 3.0 V 2.0 mA
Normal
operation
VDD = 5.0 V
3.8 7.0 mA
VDD = 3.0 V 3.8 7.0 mA
fHOCO = 24 MHzNo te
3,
fIH = 24 MHzNote 3
Basic
operation
VDD = 5.0 V 1.7 mA
VDD = 3.0 V 1.7 mA
Normal
operation
VDD = 5.0 V
3.6 6.5 mA
VDD = 3.0 V 3.6 6.5 mA
fHOCO = 16 MHzNo te
3,
fIH = 16 MHzNote 3
Normal
operation
VDD = 5.0 V
2.7 5.0 mA
VDD = 3.0 V 2.7 5.0 mA
HS (high-
speed main)
mode
Note 5
fMX = 20 MHzNote 2,
VDD = 5.0 V
Normal
operation
Square wave input
3.0 5.4 mA
Resonator connection
3.2 5.6 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V
Normal
operation
Square wave input
2.9 5.4 mA
Resonator connection
3.2 5.6 mA
fMX = 10 MHzNote 2,
VDD = 5.0 V
Normal
operation
Square wave input
1.9 3.2 mA
Resonator connection
1.9 3.2 mA
fMX = 10 MHzNote 2,
VDD = 3.0 V
Normal
operation
Square wave input
1.9 3.2 mA
Resonator connection
1.9 3.2 mA
Subsystem
clock
operation
fSUB =
32.768 kHzNote 4,
TA = −40°C
Normal
operation
Square wave input
4.0 5.4
μ
A
Resonator connection
4.3 5.4
μ
A
fSUB =
32.768 kHz Note 4,
TA = +25°C
Normal
operation
Square wave input
4.0 5.4
μ
A
Resonator connection
4.3 5.4
μ
A
fSUB =
32.768 kHzNote 4,
TA = +50°C
Normal
operation
Square wave input
4.1 7.1
μ
A
Resonator connection
4.4 7.1
μ
A
fSUB =
32.768 kHzNote 4,
TA = +70°C
Normal
operation
Square wave input
4.3 8.7
μ
A
Resonator connection
4.7 8.7
μ
A
fSUB =
32.768 kHzNote 4,
TA = +85°C
Normal
operation
Square wave input
4.7 12.0
μ
A
Resonator connection
5.2 12.0
μ
A
fSUB =
32.768 kHzNote 4,
TA = +105°C
Normal
operation
Square wave input
6.4 35.0
μ
A
Resonator connection
6.6 35.0
μ
A
(Notes and Remarks are listed on the next page.)
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
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Page 82 of 123
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not
including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, on-
chip pull-up/pull-down resistors, and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When setting ultra-low power
consumption oscillation (AMPHS1 = 1). The current flowing into the LCD controller/driver, 16-bit timer KB20,
real-time clock 2, 12-bit interval timer, and watchdog timer is not included.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
HOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
4. f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current Note 1
IDD2Note 2 HALT
mode
HS (high-
speed main)
modeNote 7
fHOCO = 48 MHzNote 4,
fIH = 24 MHzNote 4
VDD = 5.0 V
0.71 2.55 mA
VDD = 3.0 V 0.71 2.55 mA
fHOCO = 24 MHzNote 4,
fIH = 24 MHzNote 4
VDD = 5.0 V
0.49 1.95 mA
VDD = 3.0 V 0.49 1.95 mA
fHOCO = 16 MHzNote 4,
fIH = 16 MHzNote 4
VDD = 5.0 V
0.43 1.50 mA
VDD = 3.0 V 0.43 1.50 mA
HS (high-
speed main)
modeNote 7
fMX = 20 MHzNote 3,
VDD = 5.0 V
Square wave input 0.31 1.76 mA
Resonator connection 0.48 1.92 mA
fMX = 20 MHzNote 3,
VDD = 3.0 V
Square wave input 0.29 1.76 mA
Resonator connection 0.48 1.92 mA
fMX = 10 MHzNote 3,
VDD = 5.0 V
Square wave input 0.20 0.96 mA
Resonator connection 0.28 1.07 mA
fMX = 10 MHzNote 3,
VDD = 3.0 V
Square wave input 0.19 0.96 mA
Resonator connection 0.28 1.07 mA
Subsystem
clock
operation
fSUB = 32.768 kHzNote 5,
TA = −40°C
Square wave input 0.34 0.62
μ
A
Resonator connection 0.51 0.80
μ
A
fSUB = 32.768 kHzNote 5,
TA = +25°C
Square wave input 0.38 0.62
μ
A
Resonator connection 0.57 0.80
μ
A
fSUB = 32.768 kHzNote 5,
TA = +50°C
Square wave input 0.46 2.30
μ
A
Resonator connection 0.67 2.49
μ
A
fSUB = 32.768 kHzNote 5,
TA = +70°C
Square wave input 0.65 4.03
μ
A
Resonator connection 0.91 4.22
μ
A
fSUB = 32.768 kHzNote 5,
TA = +85°C
Square wave input 1.00 8.04
μ
A
Resonator connection 1.31 8.23
μ
A
fSUB = 32.768 kHzNote 5,
TA = +105°C
Square wave input 3.05 27.00
μ
A
Resonator connection 3.24 27.00
μ
A
IDD3Note 6 STOP
modeNote 8
TA = −40°C 0.18 0.52
μ
A
TA = +25°C 0.24 0.52
μ
A
TA = +50°C 0.33 2.21
μ
A
TA = +70°C 0.53 3.94
μ
A
TA = +85°C 0.93 7.95
μ
A
TA = +105°C 2.91 25.00
μ
A
(Notes and Remarks are listed on the next page.)
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Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not
including the current flowing into the LCD controller/driver, A/D converter, LVD circuit, comparator, I/O port, on-
chip pull-up/pull-down resistors, and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped.
When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the real-
time clock 2 is included. The current flowing into the clock output/buzzer output, 12-bit interval timer, and
watchdog timer is not included.
6. The current flowing into the real-time clock 2, clock output/buzzer output, 12-bit interval timer, and watchdog
timer is not included.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
HOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
3. f
IH: High-speed on-chip oscillator clock frequency (24 MHz max.)
4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
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(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-
chip oscillator
operating current
IFILNote 1 0.20
μ
A
RTC2 operating
current
IRTCNotes 1, 2, 3 fSUB = 32.768 kHz 0.02
μ
A
12-bit interval
timer operating
current
ITMKANotes 1, 2, 4 0.04
μ
A
Watchdog timer
operating current
IWDTNotes 1, 2, 5 fIL = 15 kHz 0.22
μ
A
A/D converter
operating current
IADCNotes 1, 6 When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA
A/D converter
reference
voltage current
IADREFNote 1 75.0
μ
A
Temperature
sensor operating
current
ITMPSNote 1 75.0
μ
A
LVD operating
current
ILVDNotes 1, 7 0.08
μ
A
Comparator
operating current
ICMPNotes 1, 11 VDD = 5.0 V,
Regulator output
voltage = 2.1 V
Window mode 12.5
μ
A
Comparator high-speed mode 6.5
μ
A
Comparator low-speed mode 1.7
μ
A
VDD = 5.0 V,
Regulator output
voltage = 1.8 V
Window mode 8.0
μ
A
Comparator high-speed mode 4.0
μ
A
Comparator low-speed mode 1.3
μ
A
Self-
programming
operating current
IFSPNotes 1, 9 2.00 12.20 mA
BGO operating
current
IBGONotes 1, 8 2.00 12.20 mA
SNOOZE
operating current
ISNOZNote 1 ADC operation While the mode is shiftingNote 10 0.50 0.60 mA
During A/D conversion, in low voltage
mode, AVREFP = VDD = 3.0 V
1.20 1.44 mA
CSI/UART operation 0.70 0.84 mA
LCD operating
current
ILCD1Notes 1, 12,
13
External resistance
division method
fLCD = fSUB
LCD clock
= 128 Hz
1/3 bias,
four time
slices
VDD = 5.0 V,
VL4 = 5.0 V
0.04 0.20.
μ
A
ILCD2Note 1, 12 Internal voltage
boosting method
fLCD = fSUB
LCD clock
= 128 Hz
1/3 bias,
four time
slices
VDD = 3.0 V,
VL4 = 3.0 V
(VLCD = 04H)
0.85 2.20
μ
A
VDD = 5.0 V,
VL4 = 5.1 V
(VLCD = 12H)
1.55 3.70
μ
A
ILCD3Note 1, 12 Capacitor split
method
fLCD = fSUB
LCD clock
= 128 Hz
1/3 bias,
four time
slices
VDD = 3.0 V,
VL4 = 3.0 V
0.20 0.50
μ
A
(Notes and Remarks are listed on the next page.)
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Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator
and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the values of either
IDD1 or IDD2, and IRTC, when the real-time clock 2 operates in operation mode or HALT mode. When the low-
speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the
operational current of real-time clock 2.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The value of the current for the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer
operates.
6. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ILVD when the LVD circuit operates.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode, see 21.3.3 SNOOZE mode in the RL78/L13 User’s Manual.
11. Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of
IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates.
12. Current flowing only to the LCD controller/driver. The value of the current for the RL78 microcontrollers is the
sum of the supply current (IDD1 or IDD2) and LCD operating current (ILCD1, ILCD2, or ILCD3), when the LCD
controller/driver operates in operation mode or HALT mode. However, not including the current flowing into
the LCD panel. Conditions of the TYP. value and MAX. value are as follows.
• Setting 20 pins as the segment function and blinking all
• Selecting fSUB for system clock when LCD clock = 128 Hz (LCDC0 = 07H)
• Setting four time slices and 1/3 bias
13. Not including the current flowing into the external division resistor when using the external resistance division
method.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. The temperature condition for the TYP. value is TA = 25°C.
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3.4 AC Characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle (minimum
instruction execution time)
TCY Main system
clock (fMAIN)
operation
HS (high-speed
main) mode
2.7 V
≤
V
DD
≤
5.5 V
0.0417 1
μ
s
2.4 V
≤
V
DD
< 2.7 V
0.0625 1
μ
s
Subsystem clock (fSUB)
operation
2.4 V
≤
V
DD
≤
5.5 V
28.5 30.5 31.3
μ
s
In the self
programming
mode
HS (high-speed
main) mode
2.7 V
≤
V
DD
≤
5.5 V
0.0417 1
μ
s
2.4 V
≤
V
DD
< 2.7 V
0.0625 1
μ
s
External system clock
frequency
fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
fEXS 32 35 kHz
External system clock input
high-level width, low-level
width
tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns
2.4 V ≤ VDD < 2.7 V 30 ns
tEXHS, tEXLS 13.7
μ
s
TI00 to TI07 input high-level
width, low-level width
tTIH, tTIL 1/fMCK+
10
ns
TO00 to TO07, TKBO00Note,
TKBO01-0 to TKBO01-2Note
output frequency
fTO HS (high-speed main)
mode
4.0 V ≤ VDD ≤ 5.5 V 12 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL HS (high-speed main)
mode
4.0 V ≤ VDD ≤ 5.5 V 16 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
Interrupt input high-level
width, low-level width
tINTH, tINTL INTP0 to INTP7 2.4 V ≤ VDD ≤ 5.5 V 1
μ
s
Key interrupt input high-level
width, low-level width
tKRH, tKRL KR0 to KR7 2.4 V ≤ VDD ≤ 5.5 V 250 ns
IH-PWM output restart input
high-level width
tIHR INTP0 to INTP7 2 fCLK
TMKB2 forced output stop
input high-level width
tIHR INTP0 to INTP2 2 fCLK
RESET low-level width tRSL 10
μ
s
(Note and Remark are listed on the next page.)
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Note Specification under conditions where the duty factor is 50%.
Remark f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn)
m: Unit number (m = 0), n: Channel number (n = 0 to 7))
Minimum Instruction Execution Time during Main Syste m Clo ck Operation
TCY vs VDD (HS (high-speed main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.0417
0.0625
0.05
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
Cycle time T
CY
[s]
Supply voltage V
DD
[V]
AC Timing Test Points
V
IH
/V
OH
V
IL
/V
OL
Test points V
IH
/V
OH
V
IL
/V
OL
External System Clock Timing
EXCLK/EXCLKS
1/f
EX
/
1/f
EXS
t
EXL
/
t
EXLS
t
EXH
/
t
EXHS
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TI/TO Timing
TI00 to TI07
t
TIL
t
TIH
TO00 to TO07, TKBO00,
TKBO01-0, TKBO01-1,
TKBO01-2
1/f
TO
Interrupt Request Input Timing
INTP0 to INTP7
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR7
t
KR
RESET Input Timing
RESET
t
RSL
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3.5 Peripheral Functions Characteristics
AC Timing Test Points
V
IH
/V
OH
V
IL
/V
OL
Test points V
IH
/V
OH
V
IL
/V
OL
3.5.1 Serial array unit
(1) During commu nication at same potential (UART mode)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rateNote fMCK/12 bps
Theoretical value of the maximum transfer rate
fCLK = 24 MHz, fMCK = fCLK
2.0 Mbps
Note Transfer rate in the SNOOZE mode is 4800 bps only.
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
RL78
microcontroller
TxDq
RxDq
Rx
Tx
User device
UART mode bit w idth (during communicatio n at same potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
TxDq
RxDq
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Notes 1. The value must also be equal to or more than 4/fCLK.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2),
g: PIM and POM numbers (g = 0, 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02))
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time tKCY1 2.7 V ≤ VDD ≤ 5.5 V 334Note 1 ns
2.4 V ≤ VDD ≤ 5.5 V 500Note 1 ns
SCKp high-/low-level width tKH1,
tKL1
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 24 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 36 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 − 76 ns
SIp setup time (to SCKp↑)Note 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 66 ns
2.7 V ≤ VDD ≤ 5.5 V 66 ns
2.4 V ≤ VDD ≤ 5.5 V 113 ns
SIp hold time (from SCKp↑)Note 3 tKSI1 38 ns
Delay time from SCKp↓ to
SOp outputNote 4
tKSO1 C = 30 pFNote 5 50 ns
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(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle timeNote 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V fMCK > 20 MHz 16/fMCK ns
fMCK ≤ 20 MHz 12/fMCK ns
2.7 V ≤ VDD ≤ 5.5 V fMCK > 16 MHz 16/fMCK ns
fMCK ≤ 16 MHz 12/fMCK ns
2.4 V ≤ VDD ≤ 5.5 V 12/fMCK and 1000 ns
SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V tKCY2/2−14 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY2/2−16 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY2/2−36 ns
SIp setup time
(to SCKp↑)Note 1
tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+40 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+60 ns
SIp hold time
(from SCKp↑)Note 2
tKSI2 1/fMCK+62 ns
Delay time from SCKp↓ to
SOp outputNote 3
tKSO2 C = 30 pFNote 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+66 ns
2.4 V ≤ VDD ≤ 5.5 V 2/fMCK+113 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2),
g: PIM number (g = 0, 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02))
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CSI mode connection diagram (during communication at same potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User device
SIp SO
CSI mode serial transfer timing (during commun i cation at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
Input data
t
KSO1, 2
Output data
SCKp
CSI mode serial transfer timing (during commun i cation at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
Input data
t
KSO1, 2
Output data
SCKp
Remarks 1. p: CSI number (p = 00, 10)
2. m: Unit number, n: Channel number (mn = 00, 02)
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(4) During communi cation at same potential (simplified I2C mode)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
400Note 1 kHz
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
100Note 1 kHz
Hold time when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
4600 ns
Hold time when SCLr = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
4600 ns
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 220Note 2 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 580Note 2 ns
Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 770 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 1420 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
(Remarks are listed on the next page.)
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 95 of 123
Simplified I2C mode connection diagram (during communication at same p otential)
RL78
microcontroller
SDAr
SCLr
SDA
SCL
User device
V
DD
R
b
Simplified I2C mode serial transfer timing (during communication at same p o tential)
SDAr
t
LOW
t
HIGH
t
HD : DAT
SCLr
t
SU : DAT
1/f
SCL
Remarks 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 10), g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0-3), mn = 00-03, 10-13)
<R>
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 96 of 123
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rate Reception 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
f
MCK/12Note bps
Theoretical value of the maximum transfer rate
fCLK = 24 MHz, fMCK = fCLK
2.0 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
f
MCK/12Note bps
Theoretical value of the maximum transfer rate
fCLK = 24 MHz, fMCK = fCLK
2.0 Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
f
MCK/12Note bps
Theoretical value of the maximum transfer rate
fCLK = 24 MHz, fMCK = fCLK
2.0 Mbps
Note Transfer rate in SNOOZE mode is 4800 bps only.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 97 of 123
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rate Transmission 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Note 1 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.0Note 2 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 3 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.2Note 4 Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 5 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
0.43Note 6 Mbps
Notes 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.0
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Page 98 of 123
Notes 5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 1.5
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the
TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
RL78
microcontroller
TxDq
RxDq
Rx
Tx
User device
V
b
R
b
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 99 of 123
UART mode bit width (during communication at different potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq
Remarks 1. R
b[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Page 100 of 123
(6)
Communication at different potential (1.8 V, 2.5 V, 3 V) (C SI m ode) (master mode, SC Kp... internal clock output) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
600 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1000 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 1.8 V,
Cb = 30 pF, Rb = 5.5 kΩ
2300 ns
SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 150 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 340 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 − 916 ns
SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 24 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 36 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 − 100 ns
SIp setup time
(to SCKp↑)Note 1
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
162 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
354 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
958 ns
SIp hold time
(from SCKp↑)Note 1
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
38 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
38 ns
Delay time from SCKp↓ to
SOp outputNote 1
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
200 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
390 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
966 ns
(Note, Caution and Remark are listed on the next page.)
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 101 of 123
(6)
Communication at different potential (1.8 V, 2.5 V, 3 V) (C SI m ode) (master mode, SC Kp... internal clock output) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SIp setup time
(to SCKp↓)Note 2
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
88 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
88 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
220 ns
SIp hold time
(from SCKp↓)Note 2
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
38 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
38 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
38 ns
Delay time from SCKp↑ to
SOp outputNote 2
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
50 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
50 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
50 ns
CSI mode connection diagram (during communication at different potential)
V
b
R
b
SCKp
SOp
SCK
SI
User device
SIp SO
V
b
R
b
<Master>
RL78
microcontroller
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the
SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. R
b[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02),
g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
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Aug 12, 2016
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CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
Input data
t
KSO1
Output data
SCKp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
Input data
t
KSO1
Output data
SCKp
Remark p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02),
g: PIM and POM number (g = 0, 1)
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 103 of 123
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time Note 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
20 MHz < fMCK 24/fMCK ns
8 MHz < fMCK ≤ 20 MHz 20/fMCK ns
4 MHz < fMCK ≤ 8 MHz 16/fMCK ns
fMCK ≤ 4 MHz 12/fMCK ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
20 MHz < fMCK 32/fMCK ns
16 MHz < fMCK ≤ 20 MHz 28/fMCK ns
8 MHz < fMCK ≤ 16 MHz 24/fMCK ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK ns
fMCK ≤ 4 MHz
12/fMCK ns
2.4 V
≤
V
DD
< 3.3 V,
1.6 V
≤
V
b
≤
2.0 V
20 MHz < fMCK 72/fMCK ns
16 MHz < fMCK ≤ 20 MHz 64/fMCK ns
8 MHz < fMCK ≤ 16 MHz 52/fMCK ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK ns
fMCK ≤ 4 MHz
20/fMCK ns
SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
t
KCY2/2 − 24 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
t
KCY2/2 − 36 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
t
KCY2/2 − 100 ns
SIp setup time
(to SCKp↑)Note 2
tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 40 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 40 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V 1/fMCK + 60
ns
SIp hold time
(from SCKp↑)Note 3
tKSI2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 62 ns
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 62 ns
2.4 V ≤ VDD ≤ 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V 1/fMCK + 62 ns
Delay time from SCKp↓ to
SOp outputNote 4
tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK + 240 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK + 428 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK + 1146 ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 104 of 123
CSI mode connection diagram (during communication at different potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User device
SIp SO
V
b
R
b
<Slave>
Notes 1. Transfer rate in SNOOZE mode: MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
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Aug 12, 2016
Page 105 of 123
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
Input data
t
KSO2
Output data
SCKp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
Input data
t
KSO2
Output data
SCKp
Remarks 1. R
b[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10), m: Unit number, n: Channel number (mn = 00, 02),
g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn)
m: Unit number, n: Channel number (mn = 00, 02))
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
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Aug 12, 2016
Page 106 of 123
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCLr clock frequency fSCL 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
400Note 1 kHz
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
400Note 1 kHz
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
100Note 1 kHz
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
100Note 1 kHz
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
100Note 1 kHz
Hold time when SCLr = “L” tLOW 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
4600 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
4600 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
4650 ns
Hold time when SCLr = “H” tHIGH 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
620 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
500 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2700 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2400 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
1830 ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 340Note 2 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 340Note 2 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1/fMCK + 760Note 2 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 760Note 2 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK + 570Note 2 ns
Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 770 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 770 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0 1420 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0 1420 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V ,
Cb = 100 pF, Rb = 5.5 kΩ
0 1215 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and
the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
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Simplified I2C mode connection diagram (during communication at different potential)
SDAr
SCLr
SDA
SCL
User device
V
b
R
b
V
b
R
b
RL78
microcontroller
Simplified I2C mode serial transfe r timing (during communication at different potential)
SDAr
tLOW tHIGH
tHD : DAT
SCLr
tSU : DAT
1/fSCL
Remarks 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 10), g: PIM, POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (mn = 00, 02)
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3.5.2 Serial interface IICA
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
Standard Mode Fast Mode
MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz − − 0 400 kHz
Normal mode: fCLK ≥ 1 MHz 0 100 − − kHz
Setup time of restart condition tSU:STA 4.7 0.6
μ
s
Hold timeNote 1 tHD:STA 4.0 0.6
μ
s
Hold time when SCLA0 = “L” tLOW 4.7 1.3
μ
s
Hold time when SCLA0 = “H” tHIGH 4.0 0.6
μ
s
Data setup time (reception) tSU:DAT 250 100 ns
Data hold time (transmission)Note 2 tHD:DAT 0
Note 3 3.45 0Note 3 0.9
μ
s
Setup time of stop condition tSU:STO 4.0 0.6
μ
s
Bus-free time tBUF 4.7 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode: Cb = 320 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW tR
tHIGH tF
tHD:STA
tBUF
Stop
condition Start
condition Restart
condition Stop
condition
tSU:DAT
tSU:STA tSU:STOtHD:STA
tHD:DAT
SCLA0
SDAA0
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3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Input channel
Reference voltage (+) = AVREFP
Reference voltage (−) = AVREFM
Reference voltage (+) = VDD
Reference voltage (−) = VSS
Reference voltage (+) = VBGR
Reference voltage (−) = AVREFM
ANI0, ANI1 – See 3.6.1 (2). See 3.6.1 (3).
ANI16 to ANI25 See 3.6.1 (1).
Internal reference voltage
Temperature sensor output
voltage
See 3.6.1 (1). –
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1
(ADREFM = 1), target pins: ANI16 to ANI25, internal reference voltage, and temp erature sensor outp ut voltage
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM =
0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL
10-bit resolution
AVREFP = VDDNote 3
2.4 V ≤ VDD ≤ 5.5 V 1.2 ±5.0 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI16 to ANI25
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
10-bit resolution
Target pin: Internal reference
voltage, and temperature
sensor output voltage
(HS (high-speed main) mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 10-bit resolution
AVREFP = VDDNote 3
2.4 V ≤ VDD ≤ 5.5 V ±0.35 %FSR
Full-scale errorNotes 1, 2 EFS 10-bit resolution
AVREFP = VDDNote 3
2.4 V ≤ VDD ≤ 5.5 V ±0.35 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution
AVREFP = VDDNote 3
2.4 V ≤ VDD ≤ 5.5 V ±3.5 LSB
Differential linearity errorNote 1 DLE 10-bit resolution
AVREFP = VDDNote 3
2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Analog input voltage VAIN ANI16 to ANI25 0 AVREFP V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VBGRNote 4 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VTMPS25Note 4 V
(Notes are listed on the next page.)
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Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±4 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.2%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2 LSB to the MAX. value when AVREFP = VDD.
4. See 3.6.2 Temperature se nsor/internal reference voltage characteristics.
(2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0),
target pins: ANI0, ANI1, ANI16 to ANI25, internal reference voltage, and temperature sensor output voltage
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB
Conversion time tCONV 10-bit resolution
Target pin:
ANI0, ANI1, ANI16 to ANI25
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
10-bit resolution
Target pin: Internal reference
voltage, and temperature
sensor output voltage
(HS (high-speed main)
mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Full-scale errorNotes 1, 2 EFS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB
Differential linearity errorNote 1 DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Analog input voltage VAIN ANI0, ANI1, ANI16 to ANI25 0 VDD V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VBGRNote 3 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode))
VTMPS25Note 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 3.6.2 Temperature se nsor/internal reference voltage characteristics.
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(3) When reference voltage (+) = internal reference voltage ( ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target pins: ANI0, ANI16 to ANI25
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGRNote 3,
Reference voltage (−) = AVREFMNote 4 = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Differential linearity errorNote 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB
Analog input voltage VAIN 0 VBGRNote 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (−) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the AVREFM MAX. value.
Integral linearity error: Add ±0.5 LSB to the AVREFM MAX. value.
Differential linearity error: Add ±0.2 LSB to the AVREFM MAX. value.
3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main ) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 ADS register = 80H, TA = +25°C 1.05 V
Internal reference output voltage VBGR ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature
−3.6 mV/°C
Operation stabilization wait time tAMP 5
μ
s
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3.6.3 Comparator
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range Ivref 0 VDD −
1.4
V
Ivcmp −0.3
VDD +
0.3
V
Output delay td VDD = 3.0 V
Input slew rate > 50 mV/
μ
s
Comparator high-speed mode,
standard mode
1.2
μ
s
Comparator high-speed mode,
window mode
2.0
μ
s
Comparator low-speed mode,
standard mode
3.0 5.0
μ
s
High-electric-potential
reference voltage
VTW+ Comparator high-speed mode,
window mode
0.66VDD 0.76VDD 0.86VDD V
Low-electric-potential
reference voltage
VTW− Comparator high-speed mode,
window mode
0.14VDD 0.24VDD 0.34VDD V
Operation stabilization
wait time
tCMP 100
μ
s
Internal reference
output voltageNote
VBGR 2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V
Note Cannot be used in subsystem clock operation and STOP mode.
3.6.4 POR circuit characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR When power supply rises 1.45 1.51 1.57 V
VPDR When power supply falls 1.44 1.50 1.56 V
Minimum pulse widthNote TPW 300
μ
s
Note This is the time required for the POR circuit to execute a reset operation when VDD falls below VPDR. When the
microcontroller enters STOP mode and when the main system clock (fMAIN) has been stopped by setting bit 0
(HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required for
the POR circuit to execute a reset operation between when VDD falls below 0.7 V and when VDD rises to VPOR or
higher.
Supply voltage (V
DD
)
T
PW
V
POR
VPDR or 0.7 V
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3.6.5 LVD circuit characteristics
LVD Detection Voltage o f Reset Mode and Interrupt Mode
(TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection
voltage
Supply voltage level VLVD0 When power supply rises 3.90 4.06 4.22 V
When power supply falls 3.83 3.98 4.13 V
VLVD1 When power supply rises 3.60 3.75 3.90 V
When power supply falls 3.53 3.67 3.81 V
VLVD2 When power supply rises 3.01 3.13 3.25 V
When power supply falls 2.94 3.06 3.18 V
VLVD3 When power supply rises 2.90 3.02 3.14 V
When power supply falls 2.85 2.96 3.07 V
VLVD4 When power supply rises 2.81 2.92 3.03 V
When power supply falls 2.75 2.86 2.97 V
VLVD5 When power supply rises 2.71 2.81 2.92 V
When power supply falls 2.64 2.75 2.86 V
VLVD6 When power supply rises 2.61 2.71 2.81 V
When power supply falls 2.55 2.65 2.75 V
VLVD7 When power supply rises 2.51 2.61 2.71 V
When power supply falls 2.45 2.55 2.65 V
Minimum pulse width tLW 300
μ
s
Detection delay time 300
μ
s
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and reset
mode
VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V
VLVD4 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.81 2.92 3.03 V
Falling interrupt voltage 2.75 2.86 2.97 V
VLVD3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.90 3.02 3.14 V
Falling interrupt voltage 2.85 2.96 3.07 V
VLVD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.90 4.06 4.22 V
Falling interrupt voltage 3.83 3.98 4.13 V
3.6.6 Supply voltage rise time
(TA = −40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD rise slope SVDD 54 V/ms
Caution Make sure to keep th e internal reset state by the LVD circu it or an external reset until VDD reaches the
operating voltage range sh o wn in 3.4 AC Characteristics.
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3.7 LCD Characteristics
3.7.1 External resistance division method
(1) Static display mode
(TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VL4 2.0 VDD V
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VL4 2.7 VDD V
(3) 1/3 bias method
(TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VL4 2.5 VDD V
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3.7.2 Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD output voltage variation range VL1 C1 to C4Note 1
= 0.47
μ
FNote 2
VLCD = 04H 0.90 1.00 1.08 V
VLCD = 05H 0.95 1.05 1.13 V
VLCD = 06H 1.00 1.10 1.18 V
VLCD = 07H 1.05 1.15 1.23 V
VLCD = 08H 1.10 1.20 1.28 V
VLCD = 09H 1.15 1.25 1.33 V
VLCD = 0AH 1.20 1.30 1.38 V
VLCD = 0BH 1.25 1.35 1.43 V
VLCD = 0CH 1.30 1.40 1.48 V
VLCD = 0DH 1.35 1.45 1.53 V
VLCD = 0EH 1.40 1.50 1.58 V
VLCD = 0FH 1.45 1.55 1.63 V
VLCD = 10H 1.50 1.60 1.68 V
VLCD = 11H 1.55 1.65 1.73 V
VLCD = 12H 1.60 1.70 1.78 V
VLCD = 13H 1.65 1.75 1.83 V
Doubler output voltage VL2 C1 to C4Note 1 = 0.47
μ
F 2 VL1 − 0.10 2 VL1 2 VL1 V
Tripler output voltage VL4 C1 to C4Note 1 = 0.47
μ
F 3 VL1 − 0.15 3 VL1 3 VL1 V
Reference voltage setup timeNote 2 tVWAIT1 5 ms
Voltage boost wait timeNote 3 tVWAIT2 C1 to C4Note 1 = 0.47
μ
F 500 ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47
μ
F ± 30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON =
1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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(2) 1/4 bias method
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD output voltage variation range VL1 C1 to C5Note 1
= 0.47
μ
FNote 2
VLCD = 04H 0.90 1.00 1.08 V
VLCD = 05H 0.95 1.05 1.13 V
VLCD = 06H 1.00 1.10 1.18 V
VLCD = 07H 1.05 1.15 1.23 V
VLCD = 08H 1.10 1.20 1.28 V
VLCD = 09H 1.15 1.25 1.33 V
VLCD = 0AH 1.20 1.30 1.38 V
Doubler output voltage VL2 C1 to C5Note 1 = 0.47
μ
F 2 VL1 − 0.08 2 VL1 2 VL1 V
Tripler output voltage VL3 C1 to C5Note 1 = 0.47
μ
F 3 VL1 − 0.12 3 VL1 3 VL1 V
Quadruply output voltage VL4 C1 to C5Note 1 = 0.47
μ
F 4 VL1 − 0.16 4 VL1 4 VL1 V
Reference voltage setup timeNote 2 tVWAIT1 5 ms
Voltage boost wait timeNote 3 tVWAIT2 C1 to C5Note 1 = 0.47
μ
F 500 ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47
μ
F ± 30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON =
1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
3.7.3 Capacitor split method
(1) 1/3 bias method
(TA = −40 to +105°C, 2.4 V ≤ VD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VL4 voltage VL4 C1 to C4 = 0.47
μ
FNote 2 VDD V
VL2 voltage VL2 C1 to C4 = 0.47
μ
FNote 2 2/3 VL4 −
0.1
2/3 VL4 2/3 VL4 +
0.1
V
VL1 voltage VL1 C1 to C4 = 0.47
μ
FNote 2 1/3 VL4 −
0.1
1/3 VL4 1/3 VL4 +
0.1
V
Capacitor split wait timeNote 1 tVWAIT 100 ms
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
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3.8 RAM Data Retention Characteristics
(TA = −40 to +105°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.44Note 5.5 V
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
RAM data retention mode
V
DDDR
Operation mode
3.9 Flash Memory Programming Characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 2.4 V ≤ VDD ≤ 5.5 V 1 24 MHz
Number of code flash rewritesNote 1, 2, 3 Cerwr Retained for 20 years
TA = 85°C Note 4
1,000 Times
Number of data flash rewritesNote 1, 2, 3 Retained for 1 year
TA = 25°C
1,000,000
Retained for 5 years
TA = 85°C Note 4
100,000
Retained for 20 years
TA = 85°C Note 4
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test.
4. This temperature is the average value at which data are retained.
Remark When updating data multiple times, use the flash memory as one for updating data.
3.10 Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
<R>
<R>
<R>
RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 119 of 123
3.11 Timing Specifications for Switching Flash Memory Programming Modes
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Time to complete the
communication for the initial setting
after the external reset is released
tSUINIT POR and LVD reset must be released before
the external reset is released.
100 ms
Time to release the external reset
after the TOOL0 pin is set to the low
level
tSU POR and LVD reset must be released before
the external reset is released.
10
μ
s
Time to hold the TOOL0 pin at the
low level after the external reset is
released
(excluding the processing time of
the firmware to control the flash
memory)
tHD POR and LVD reset must be released before
the external reset is released.
1 ms
RESET
TOOL0
<1> <2> <3>
t
SUINIT
723 μs + t
HD
processing
time
t
SU
<4>
00H reception
(TOOLRxD, TOOLTxD mode)
<1> The low level is input to the TOOL0 pin.
<2> The external reset is released (POR and LVD reset must be released before the external
reset is released.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and completion the
baud rate setting.
Remark t
SUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU: Time to release the external reset after the TOOL0 pin is set to the low level
tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
RL78/L13 4. PACKAGE DRAWINGS
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 120 of 123
4. PACKAGE DRAWINGS
4.1 64-pin Products
R5F10WLAAFA, R5F10WLCAFA, R5F10WLDAFA, R5F10WLEAFA, R5F10WLFAFA, R5F10WLGAFA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
detail of lead end
θ
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2 A
D
E
16
32
1
64 17
33
4948
S
y
e
Sxb
M
A3
S
0.145 +0.055
−0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
12.00±0.20
12.00±0.20
14.00±0.20
14.00±0.20
1.60 MAX.
0.10±0.05
1.40±0.05
0.25
c
θ
e
x
y
ZD
ZE
0.65
0.13
0.10
1.125
1.125
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
3°+5°
−3°
0.32+0.08
−0.07
b
2012 Renesas Electronics Corporation. All rights reserved.
RL78/L13 4. PACKAGE DRAWINGS
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 121 of 123
R5F10WLAAFB, R5F10WLCAFB, R5F10WLDAFB, R5F10WLEAFB, R5F10WLFAFB, R5F10WLGAFB,
R5F10WLAGFB, R5F10WLCGFB, R5F10WLDGFB, R5F10WLEGFB, R5F10WLFGFB, R5F10WLGGFB
Terminal cross section
b
1
c
1
b
p
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Index mark
*3
17
32
64
49
116
3348
F
*1
*2
x
b
p
H
E
E
H
D
D
Z
D
Z
E
Detail F
A
c
A
2
A
1
L
1
L
P-LFQFP64-10x10-0.50 0.3g
MASS[Typ.]
64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A
RENESAS CodeJEITA Package Code Previous Code
1.0
0.125
0.18
1.25
1.25
0.08
0.20
0.145
0.09
0.250.200.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
10.110.0
9.9
D10.110.0
9.9
E1.4
A
2
12.212.011.8 12.212.011.8 1.7
A0.15
0.1
0.05
0.65
0.5
0.35
L
x
8
°
0
°
c
0.5
e
0.08
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
e
yS
S
RL78/L13 4. PACKAGE DRAWINGS
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 122 of 123
4.2 80-pin Products
R5F10WMAAFA, R5F10WMCAFA, R5F10WMDAFA, R5F10WMEAFA, R5F10WMFAFA, R5F10WMGAFA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP80-14x14-0.65 PLQP0080JB-E P80GC-65-UBT-2 0.69
D
E
HD
HE
A
A2
bp
c
Lp
x
L1
0.13
0.886
14.00
14.00
17.20
17.20
1.40
0.10
Referance
Symbol
Min Nom Max
Dimension in Millimeters
A1 0.05
1.35
0.26
1.70
0.20
1.45
0.38
13.80
13.80
17.00
17.00
14.20
14.20
17.40
17.40
0.10 0.20
e0.65
0.736 1.036
1.60
0°8°
A3 0.25
0.125
0.32
0.145
L0.80
1.40 1.80
ZD 0.825
ZE 0.825
3°
y
S
y
e
Sxbp M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
E
A3
S
detail of lead end
20
40
1
80 21
41
D
A
B
AB
61
60
RL78/L13 4. PACKAGE DRAWINGS
R01DS0168EJ0210 Rev.2.10
Aug 12, 2016
Page 123 of 123
R5F10WMAAFB, R5F10WMCAFB, R5F10WMDAFB, R5F10WMEAFB, R5F10WMFAFB, R5F10WMGAFB,
R5F10WMAGFB, R5F10WMCGFB, R5F10WMDGFB, R5F10WMEGFB, R5F10WMFGFB, R5F10WMGGFB
C - 1
Revision History RL78/L13 Data Sheet
Rev.
Date
Description
Page
Summary
0.01 Apr 13, 2012 - First Edition issued
0.02 Oct 3 1 , 2012
- Change of the number of segment pins
• 64-pin products: 36 pins
• 80-pin products: 51 pins
2.10 Aug 12, 2016 1 Modification of features of 16-bit timer and 16-bit timer KB20 (IH) in 1.1 Features
5 Addition of product name (RL78/L13) and descript i on (Top View) in 1.3.1 64-pin
products
6 Addition of product name (RL78/L13) and descript i on (Top View) in 1.3.2 80-pin
products
10 Modificat i on of functional overview of main system clock in 1.6 Outline of Functions
15 Modificat i on of descripti on in Absolute Maximum Rati ngs (3/ 3)
17, 18 Modificati on of descripti on in 2.3.1 Pi n ch aracter i stics
38 Modification of remark 3 in 2.5.1 (4) During communication at same potential
(simplified I2C mode)
68 Modificat i on of the title and note, and addition of caution in 2.8 RAM Data Retention
Characteristics
70 Addition of Remark
74 Modificat i on of descripti on in Abs olute Maximum Rati ngs (T A = 25 °C) (3/3)
76 Modificat i on of descripti on in 3.3.1 Pin char acteristi cs
95 Modification of remark 3 in 3.5.1 (4) During communication at same potential
(simplified I2C mode)
118 Modificati on of the title and note, and addition of caution in 3.8 RAM Data Retention
Characteristics
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries i ncluding the United
States and Japan.
Caut ion: This pro duct uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device m ay malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Uncon nected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or lo w by using pull-up or pull-do wn circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shiel ding bag or conductive material. All test and me asurement
tools including work benches and flo ors should b e gr ound e d. T he operator should be gr oun ded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to b e taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and exter nal interface, as a rule, s witch on the external power supply after s witching on the in ternal
power supply. When s witching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device an d accord ing to related specifications governing the device.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
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Tel: +1-408-588-6000, Fax: +1-408-588-6130
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Tel: +1-905-237-2004
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Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
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No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India
Tel: +91-80-67208700, Fax: +91-80-67208777
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Tel: +82-2-558-3737, Fax: +82-2-558-5141
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