1
Data sheet acquired from Harris Semiconductor
SCHS222C
Features
Independent Asynchronous Inputs and Outputs
Expandable in Either Direction
Reset Capability
Status Indicators on Inputs and Outputs
Three-State Outputs
Shift-Out Independent of Three-State Control
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating T emperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il1µA at VOL, VOH
Applications
Bit-Rate Smoothing
CPU/Terminal Buffering
Data Communications
Peripheral Buffering
Line Printer Input Buffers
Auto-Dialers
CRT Buffer Memories
Radar Data Acquisition
Description
The ’HC40105 and ’HCT40105 are high-speed silicon-gate
CMOS devices that are compatible, except for “shift-out”
circuitry, with the CD40105B. They are low-power first-in-out
(FIFO) “elastic” storage registers that can store 16 four-bit
words. The 40105 is capable of handling input and output
data at different shifting rates. This feature makes it
particularly useful as a buffer between asynchronous
systems.
Each work position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceeding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD54HC40105F3A -55 to 125 16 Ld CERDIP
CD54HCT40105F3A -55 to 125 16 Ld CERDIP
CD74HC40105E -55 to 125 16 Ld PDIP
CD74HC40105M -55 to 125 16 Ld SOIC
CD74HC40105MT -55 to 125 16 Ld SOIC
CD74HC40105M96 -55 to 125 16 Ld SOIC
CD74HCT40105E -55 to 125 16 Ld PDIP
CD74HCT40105M -55 to 125 16 Ld SOIC
CD74HCT40105MT -55 to 125 16 Ld SOIC
CD74HCT40105M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC40105, CD74HC40105,
CD54HCT40105, CD74HCT40105
High-Speed CMOS Logic
4-Bit x 16-Word FIFO Register
[ /Title
(CD74
HC401
05,
CD74
HCT40
105)
/Sub-
ject
(High
Speed
CMOS
2
Pinout
CD54HC40105, CD54HCT40105
(CERDIP)
CD74HC40105, CD74HCT40105
(PDIP, SOIC)
TOP VIEW
Loading Data
Data can be entered whenever the DATA-IN READY (DIR)
flag is high, by a low to high transition on the SHIFT-IN (SI)
input. This input must go low momentarily before the next
word is accepted by the FIFO. The DIR flag will go low
momentarily, until the data have been transferred to the sec-
ond location. The flag will remain low when all 16-word loca-
tions are filled with valid data, and further pulses on the SI
input will be ignored until DIR goes high.
Unloading Data
As soon as the first word has rippled to the output, the data-
out ready output (DOR) goes HIGH and data of the first word
is available on the outputs. Data of other words can be
removed by a negative-going transition on the shift-out input
(SO). This negative-going transition causes the DOR signal
to go LOW while the next word moves to the output. As long
as valid data is available in the FIFO, the DOR signal will go
high again, signifying that the next word is ready at the
output. When the FIFO is empty, DOR will remain LOW, and
any further commands will be ignored until a “1” marker
ripples down to the last control register and DOR goes
HIGH. If during unloading SI is HIGH, (FIFO is full) data on
the data input of the FIFO is entered in the first location.
Master Reset
A high on the MASTER RESET (MR) sets all the control
logic marker bits to “0”. DOR goes low and DIR goes high.
The contents of the data register are not changed, only
declared invalid, and will be superseded when the first word
is loaded. Thus, MR does not clear data within the register
but only the control logic. If the shift-in flag (SI) is HIGH
during the master reset pulse, data present at the input (D0
to D3) are immediately moved into the first location upon
completion of the reset process.
Three-State Outputs
In order to facilitate data busing, three-state outputs (Q0 to
Q3) are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output. A HIGH on the three-state control flag (output
enable input OE) forces the outputs into the high-impedance
OFF-state mode. Note that the shift-out signal, unlike that in
the CD40105B, is independent of the three-state output
control. In the CD40105B, the three-state control must not
be shifted from High to Low when the shift-out signal is Low
(data loss would occur). In the high-speed CMOS version
this restriction has been eliminated.
Cascading
The 40105 can be cascaded to form longer registers simply
by connecting the DIR to SO and DOR to SI. In the cascaded
mode, a MASTER RESET pulse must be applied after the
supply voltage is turned on. For words wider than four bits, the
DIR and the DOR outputs must be gated together with AND
gates. Their outputs drive the SI and SO inputs in parallel, if
e xpanding is done in both directions (see Figures 12 and 13).
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
THREE-STATE
DIR
SI
D0
D1
D2
GND
D3
VCC
DOR
Q0
Q1
Q2
Q3
MR
SO
CONTROL
STATE
Q0
Q1
Q2
Q3
CONTROL
D0
D1
D2
D3
SHIFT OUT
4
1
5
6
7
3
15
13
12
11
10
MASTER 9
SHIFT IN
RESET
14
2
DATA-OUT
DATA-IN
READY
READY
GND = 8
VCC = 16
THREE-
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
3
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
4 x 16
DATA
REGISTER
4
5
6
7
D0
D1
D2
D3
13
12
11
10
Q0
Q1
Q2
Q3
1
THREE-STATE CONTROL
DATA-OUT READY (DOR)
2 CONTROL LOGIC 14
3 15
SHIFT OUT (SO)
9
MASTER
RESET
(MR)
DATA-IN READY (DIR)
SHIFT IN (SI)
INPUT
BUFFERS OUTPUT
BUFFERS
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
4
“S” overrides “R”.
†† “R” overrides “S”. FIGURE 2. LOGIC DIAGRAM
MR 9
3
SI
R Q
QS
F/F1
R Q
QS
† †
2
4
5
6
7
DIR
D0
D1
D2
D3
CL CL
POSITION 1
L1
4
LATCHES
R Q
QS
† †
F/Fs
2-15
14 x
14 x
R Q
QS
† †
F/F16
POSITION 2-15 POSITIONS 16
12
13
11
10Q3
Q2
Q1
Q0
R
QS
14
DOR
15
S0
OE 1
CL CL
14 x L1
4 x 14
LATCHES
CL CL
L16
4
LATCHES
E
THREE-
STATE
OUTPUT
BUFFERS
E
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
5
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
6
Three-State Leakage
Current IOZ VIL or VIH VO =
VCC or
GND
6--±0.5 - ±5-±10 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Three-State Leakage
Current IOZ VIL or VIH VO =
VCC or
GND
5.5 - - ±0.5 - ±5-±10 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
OE 0.75
SI, SO 0.4
Dn 0.3
MR 1.5
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
7
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
HC TYPES
SI Pulse Width
HIGH or LOW tW2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
6 14 - 17 - 20 - ns
SO Pulse Width
HIGH or LOW tW2 120 - 150 - 180 - ns
4.5 24 - 30 - 36 - ns
6 20 - 26 - 31 - ns
DIR Pulse Width
HIGH or LOW tW2 200 - 250 - 300 - ns
4.5 40 - 50 - 60 - ns
6 34 - 43 - 51 - ns
DOR Pulse Width
HIGH or LOW tW2 200 - 250 - 300 - ns
4.5 40 - 50 - 60 - ns
6 34 - 43 - 51 - ns
MR Pulse Width HIGH tW2 120 - 150 - 180 - ns
4.5 24 - 30 - 36 - ns
6 20 - 26 - 31 - ns
Removal Time
MR to SI tREM 2 50 - 65 - 75 - ns
4.5 10 - 13 - 15 - ns
6 9 - 11 - 13 - ns
Set-Up Time
Dn to SI tSU 2 5-5-5-ns
4.5 5 - 5 - 5 - ns
6 5-5-5-ns
Hold Time
Dn to SI tH2 125 - 155 - 190 - ns
4.5 25 - 31 - 38 - ns
6 21 - 26 - 32 - ns
Maximum Pulse Frequency
SI, SO fMAX 2 3-2-2-MHz
4.5 15 - 12 - 10 - MHz
6 18 - 14 - 12 - MHz
HCT TYPES
SI Pulse Width HIGH or LOW tW4.5 16 - 20 - 24 - ns
SO Pulse Width HIGH or
LOW tW4.5 16 - 20 - 24 - ns
DIR Pulse Width HIGH or
LOW tW4.5 40 - 50 - 60 - ns
DOR Pulse Width HIGH or
LOW tW4.5 40 - 50 - 60 - ns
MR Pulse Width HIGH tW4.5 24 - 30 - 36 - ns
Removal Time MR to SI tREM 4.5 15 - 19 - 22 - ns
Set-Up Time Dn to SI tSU 4.5 0 - 0 - 0 - ns
Hold Time Dn to SI tH4.5 25 - 31 - 38 - ns
Maximum Pulse Frequency
SI, SO fMAX 4.5 15 - 12 - 10 - MHz
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
8
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPHL,
tPLH CL= 50pF 2 - - 175 - 220 - 265 ns
MR to DIR, DOR CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 15 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns
SI to DIR tPHL,
tPLH CL= 50pF 2 - - 210 - 265 - 315 ns
CL= 50pF 4.5 - - 42 - 53 - 63 ns
CL= 15pF 5 - 18 - - - - - ns
CL= 50pF 6 - - 36 - 45 - 54 ns
SO to DOR tPHL,
tPLH CL= 50pF 2 - - 210 - 265 - 315 ns
CL= 50pF 4.5 - - 42 - 53 - 63 ns
CL= 15pF 5 - 18 - - - - - ns
CL= 50pF 6 - - 36 - 45 - 54 ns
SO to Qn tPHL,
tPLH CL= 50pF 2 - - 400 - 500 - 600 ns
CL= 50pF 4.5 - - 80 - 100 - 120 ns
CL= 15pF 5 - 35 - - - - - ns
CL= 50pF 6 - - 68 - 85 - 102 ns
Propagation Delay/Ripple thru
Delay
SI to DOR
tPLH CL= 50pF 2 - - 2000 - 2500 - 3000 ns
4.5 - - 400 - 500 - 600 ns
6 - - 340 - 425 - 510 ns
Propagation Delay/Ripple thru
Delay
SO to DIR
tPLH CL= 50pF 2 - - 2500 - 3125 - 3750 ns
4.5 - - 500 - 625 - 750 ns
6 - - 425 - 532 - 638 ns
Propagation Delay/Ripple thru
Delay
SI to Qn
tPLH CL= 50pF 2 - - 1500 - 1900 - 2250 ns
4.5 - - 300 - 380 - 450 ns
6 - - 260 - 330 - 380 ns
Three-State Output Enable
OE to QntPZH, tPZL CL= 50pF 2 - - 150 - 190 - 225 ns
4.5 - - 30 - 38 - 45 ns
6 - - 26 - 33 - 38 ns
Three-State Output Disable
OE to Qn tPHZ, tPLZ CL= 50pF 2 - - 140 - 175 - 210 ns
CL= 50pF 4.5 - - 28 - 35 - 42 ns
CL= 50pF 6 - - 24 - 30 - 36 ns
Output Transition Time tTLH,t
THL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Maximum SI, SO Frequency fMAX CL= 15pF 5 - 32 - - - - - MHz
Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD CL= 15pF 5 - 83 - - - - - pF
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
9
Three-State Output
Capacitance COCL= 50pF - - - 15 - 15 - 15 pF
HCT TYPES
Propagation Delay Time tPLH,
tPHL CL= 50pF 4.5 - - 36 - 45 - 54 ns
MR to DIR, DOR CL= 15pF 5 - 15 - - - - - ns
SI to DIR tPLH,
tPHL CL= 50pF 4.5 - - 42 - 53 - 63 ns
CL=15pF 5 - 18 - - - - - ns
SO to DOR tPLH,
tPHL CL= 50pF 4.5 - - 42 - 53 - 63 ns
CL=15pF 5 - 18 - - - - - ns
SO to Qn tPLH,
tPHL CL= 50pF 4.5 - - 80 - 100 - 120 ns
CL=15pF 5 - 35 - - - - - ns
Propagation Delay/Ripple thru
Delay
SI to DOR
tPLH CL= 50pF 4.5 - - 400 - 500 - 600 ns
Propagation Delay/Ripple thru
Delay
SO to DIR
tPLH CL= 50pF 4.5 - - 500 - 625 - 750 ns
Propagation Delay/Ripple thru
Delay
SI to Qn
tPLH CL= 50pF 4.5 - - 300 - 380 - 450 ns
Three-State Output Enable
OE to QntPZH, tPZL CL= 50pF 4.5 - - 35 - 44 - 53 ns
Three-State Output Disable
OE to Qn tPHZ, tPLZ CL= 50pF 4.5 - - 30 - 38 - 45 ns
Output Transition Time tTLH,t
THL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Maximum CP Frequency fMAX CL=15pF 5 - 32 - - - - - MHz
Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD CL=15pF 5 - 83 - - - - - pF
Three-State Output
Capacitance COCL= 50pF - - - 15 - 15 - 15 pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD=C
PD VCC2fi+Σ(CLVCC2fo) where fi= Input Frequency, fo= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
10
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 5. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
11
FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 9. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 10. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kto
VCC, CL = 50pF. FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms (Continued)
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
50% 10%
90%
GN
D
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GN
D
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
T
IED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZ
H
OUTPUT
RL = 1k
CL
50pF
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
12
NOTE: Pulse must be applied for cascading by 16 N bits.
FIGURE 12. EXPANSION, 8-BITS WIDE BY 16 N-BITS LONG USING HC/HCT40105
SI DOR
Q0
Q1
Q2
Q3
SO
MR
DIR
D3
D2
D1
D0
SI DOR
Q0
Q1
Q2
Q3
SO
MR
DIR
D3
D2
D1
D0
SI DOR
Q0
Q1
Q2
Q3
SO
MR
DIR
D3
D2
D1
D0
SI DOR
Q0
Q1
Q2
Q3
SO
MR
DIR
D3
D2
D1
D0
DATA OUT
READY
8-BIT
DATA
SHIFT OUT
SHIFT IN
8-BIT
DATA
DATA IN READY
MASTER RESET
(NOTE)
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
13
NOTES:
5. Data valid goes to high level in advance of the data out by a maximum of 38ns at VCC = 4.5V for CL = 50pF and TA = 25oC.
6. At VCC = 4.5V, ripple time from position 1 to position 16.
7. At VCC = 4.5V, ripple time from position 16 to position 1.
FIGURE 13. TIMING DIAGRAM FOR THE CD74HC/HCT40105
SHIFT-IN PULSES
HAVE NO EFFECT
MASTER
RESET
SHIFT IN
(DATA VALID)
INPUTS
SHIFT OUT
OUTPUTS
INPUT READY
(CLEAR OUT)
OUTPUT READY
(DATA VALID)
DATA IN
(Db)
THREE-STATE
(OUTPUT
ENABLE)
DATA OUT (UNKNOWN) HIGH Z
INVALID
180ns
(NOTE 7)
180ns
(NOTE 6)
(NOTE 5)
INPUTS
SHIFT-OUT PULSES
HAVE NO EFFECT
101110
1011 100011111000
(NOTE 5)
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54HC40105F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT40105F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC40105E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC40105EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC40105M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC40105MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT40105EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT40105M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT40105MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC40105M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT40105M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC40105M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT40105M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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