NZQA6V8AXV5T2G - ON Semiconductor

September, 2009 − Rev. 7

1Publication Order Number:

NZQA5V6AXV5/D

NZQA5V6AXV5 Series

Transient Voltage Suppressors

ESD Protection Diode with Low Clamping

Voltage

This integrated transient voltage suppressor device (TVS) is

designed for applications requiring transient overvoltage protection. It

is intended for use in sensitive equipment such as computers, printers,

business machines, communication systems, medical equipment, and

other applications. Its integrated design provides very effective and

reliable protection for four separate lines using only one package.

These devices are ideal for situations where board space is at a premium.

Features

•Low Clamping Voltage

•Small SOT−553 SMT Package

•Stand Off Voltage: 3 V

•Low Leakage Current

•Four Separate Unidirectional Configurations for Protection

•ESD Protection: IEC61000−4−2: Level 4 ESD Protection

MILSTD 883C − Method 3015−6: Class 3

•Complies to USB 1.1 Low Speed & Full Speed Specifications

•These are Pb−Free Devices

Benefits

•Provides Protection for ESD Industry Standards: IEC 61000, HBM

•Protects Four Lines Against Transient Voltage Conditions

•Minimize Power Consumption of the System

•Minimize PCB Board Space

Typical Applications

•Instrumentation Equipment

•Serial and Parallel Ports

•Microprocessor Based Equipment

•Notebooks, Desktops, Servers

•Cellular and Portable Equipment

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Characteristic Symbol Value Unit

Peak Power Dissipation (Note 1) PPK 20 W

Steady State Power − 1 Diode (Note 2) PD380 mW

Thermal Resistance,

Junction−to−Ambient

Above 25°C, Derate

RqJA 327

3.05

°C/W

mW/°C

Maximum Junction Temperature TJmax 150 °C

Operating Junction and Storage

Temperature Range

TJ Tstg −55 to

+150

°C

Lead Solder Temperature (10 seconds

duration)

TL260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Non−repetitive current per Figure 5.

2. Only 1 diode under power. For all 4 diodes under power, PD will be 25%.

Mounted on FR−4 board with min pad.

See Application Note AND8308/D for further description of

survivability specs.

SOT−553*

SOT−553

CASE 463B

PLASTIC

MARKING DIAGRAM

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Device Package Shipping†

ORDERING INFORMATION

NZQA5V6AXV5T1 SOT−553* 4000/Tape & Reel

NZQA6V8AXV5T1 SOT−553* 4000/Tape & Reel

NZQA6V8AXV5T3 16000/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

xx M G

xx = Device Code

M = Date Code*

G= Pb−Free Package

(Note: Microdot may be in either location)

SOT−553*

NZQA5V6AXV5T1G SOT−553* 4000/Tape & Reel

NZQA6V8AXV5T1G SOT−553* 4000/Tape & Reel

NZQA6V8AXV5T3G 16000/Tape & Reel

*This package is inherently Pb−Free.

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ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

QVBR Maximum Temperature Coefficient of VBR

IFForward Current

VFForward Voltage @ IF

ZZT Maximum Zener Impedance @ IZT

IZK Reverse Current

ZZK Maximum Zener Impedance @ IZK

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional

IPP

VRWM

VCVBR

ELECTRICAL CHARACTERISTICS (TA = 25°C)

Device

Marking

Breakdown

Voltage

VBR @ 1 mA (V)

Leakage

Current

IRM @ VRM

VC Max @ IPP

(Note 4)

Typ

Capacitance

@ 0 V Bias

(pF)

(Note 3)

Typ

Capacitance

@ 3 V Bias

(pF)

(Note 3) VC

Min Nom Max VRWM

IRWM

(mA)

(V)

IPP

(A) Typ Max Typ Max

Per

IEC61000−4−2

(Note 5)

NZQA5V6AXV5 5P 5.3 5.6 5.9 3.0 1.0 13 1.6 13 17 7.0 11.5 Figures 1 and 2

(See Below)

NZQA6V8AXV5 6H 6.47 6.8 7.14 4.3 1.0 13 1.6 12 15 6.7 9.5

3. Capacitance of one diode at f = 1 MHz, VR = 0 V, TA = 25°C

4. Surge current waveform per Figure 5.

5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

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IEC 61000−4−2 Spec.

Level

Test

Voltage

(kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

Figure 4. Diagram of ESD Test Setup

50 W

Cable

TVS Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

Figure 5. 8 X 20 ms Pulse Waveform

100

0020406080

t, TIME (ms)

% OF PEAK PULSE CURRENT

PULSE WIDTH (tP) IS DEFINED

AS THAT POINT WHERE THE

PEAK CURRENT DECAY = 8 ms

PEAK VALUE IRSM @ 8 ms

HALF VALUE IRSM/2 @ 20 ms

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TYPICAL ELECTRICAL CHARACTERISTICS − NZQA6V8AXV5

Figure 6. Pulse Width

100

11 10 100 1000

t, TIME (ms)

Ppk, PEAK SURGE POWER (W)

Figure 7. Power Derating Curve

TA, AMBIENT TEMPERATURE (°C)

1501251007550250

100

110

% OF RATED POWER OR IPP

Figure 8. Reverse Leakage versus

Temperature

0.16

0.02

−60 0 80 100

T, TEMPERATURE (°C)

IR, REVERSE LEAKAGE (mA)

−40 −20 604020

0.04

0.06

0.08

0.10

0.12

0.14

Figure 9. Capacitance

01 2 3 6

BIAS VOLTAGE (V)

TA = 25°C

TYPICAL CAPACITANCE

(pF)

1 MHz FREQUENCY

, FORWARD VOLTAGE (V)

1.81.61.41.21.00.80.6

0.1

0.01

0.001

, FORWARD CURRENT (A)

TA = 25°C

Figure 10. Forward Voltage

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PACKAGE DIMENSIONS

SOT−553, 5 LEAD

CASE 463B−01

ISSUE B

STYLE 2:

PIN 1. CATHODE

2. COMMON ANODE

3. CATHODE 2

4. CATHODE 3

5. CATHODE 4

1.35

0.0531

0.5

0.0197 ǒmm

inchesǓ

SCALE 20:1

0.5

0.0197

1.0

0.0394

0.45

0.0177

0.3

0.0118

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.08 (0.003) X

b5 PL

−X−

−Y−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH

THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM

THICKNESS OF BASE MATERIAL.

12 3

DIM

MIN NOM MAX MIN

MILLIMETERS

0.50 0.55 0.60 0.020

INCHES

b0.17 0.22 0.27 0.007

D1.50 1.60 1.70 0.059

E1.10 1.20 1.30 0.043

e0.50 BSC

L0.10 0.20 0.30 0.004

0.022 0.024

0.009 0.011

0.063 0.067

0.047 0.051

0.008 0.012

NOM MAX

1.50 1.60 1.70 0.059 0.063 0.067

0.08 0.13 0.18 0.003 0.005 0.007

0.020 BSC

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent

rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.

Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,

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or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an

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NZQA5V6AXV5/D

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