1MA03601433650037500CD021 - 3M - Datasheet.Directory

Features

•400 MHz ARM926EJ-S™ ARM® Thumb® Processor

– 32 Kbytes Data Cache, 32 Kbytes Instruction Cache, MMU

•Memories

– DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

– External Bus Interface supporting 4-bank DDR2/LPDD R, SDRAM/LPSDR, Static

Memories, CompactFlash, SLC NAND Flash with ECC

– One 64-Kbyte internal SRAM, single-cycle access at system speed or processor

speed through TCM interface

– One 64-Kbyte internal ROM, embedding bootstrap routine

•Peripherals

– LCD Controller supporting STN and TFT displays up to 1280*860

– ITU-R BT. 601/656 Image Sensor Interface

– USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-

Chip Transceiver

– 10/100 Mbps Ethernet MAC Controller

– Two High Sp eed Memory Card Hosts (SDIO, SDCard, MMC)

– AC'97 controller

– Two Master/Slave Serial Peripheral Interfaces

– Two Three-channel 16-bit Timer/Counters

– Two Synchronous Serial Controllers (I2S mode)

– Four-channel 16-bit PWM Controller

– Two Two-wire Interfaces

– Four USARTs with ISO7816, IrDA, Manchester and SPI modes

– 8-channel 10-bit ADC with 4-wire Touch Screen support

– Write Protected Registers

•System

– 133 MHz twelve 32-bit layer AHB Bus Matrix

– 37 DMA Channels

– Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash

– Reset Controller with on-chip Power-on Reset

– Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators

– Internal Low-power 32 kHz RC Os cillator

– One PLL for the system and one 480 MHz PLL optimized for USB High Speed

– Two Programmable External Clock Signals

– Advanced Interrupt Controller and Debug Unit

– Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock

•I/O

– Five 32-bit Parallel Input/Output Contr ollers

– 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with

Schmitt trig ger input

•Package

– 324-ball TFBGA, pitch 0.8 mm

AT91SAM

ARM-based

Embedded MPU

SAM9G45

6438J–ATARM–10-Aug-12

SAM9G45

1. Description

The ARM926EJ-S based SAM9G45 features the frequently demanded combination of user

interface functionality and high data rate connectivity, including LCD Controller, resistive touch-

screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro-

cessor running at 400 MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 has the

performance and bandwidth to the network or local storage media to provide an adequate user

experience.

The SAM9G45 supports DDR2 and NAND Flash memory interfaces for program and data stor-

age. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual

external bus interface and distributed memory including a 64-Kbyte SRAM which can be config-

ured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor

and the high speed peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory

interface and peripheral I/Os. This feature completely eliminates the need for any external level

shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing.

The SAM9G45 power management controller features efficient clock gating and a battery

backup section minimizing power consumption in active and standby modes.

6438J–ATARM–10-Aug-12

SAM9G45

2. Block Diagram

Figure 2-1. SAM9G45 Block Diagram

AIC

APB

PLLA

System Controller

PMC

PLLUTMI

PIT

WDT

RTT

OSC 32K

SHDC

RSTC

POR

DBGU

PDC

GPBR

Static

Memory

Controller

TWI0

TWI1

USART0

USART1

USART2

USART3

PDC PDC

4-CH

PWM

TC0

TC1

TC2

Peripheral

DMA

Controller

Peripheral

Bridge

ROM

64KB

OSC12M

PDC

PIOB

Multi-Layer AHB Matrix

POR

PIOC

RTC

PIOD

Transceiver

DDR2

LPDDR

8-CH

10Bit ADC

TouchScreen

AC97

PDC PDC

SSC0

SSC1

PIO

NAND Flash

Controller

ECC

ARM926EJ-S

JTAG / Boundary Scan

In-Circuit Emulator

MMU

Bus Interface

ICache

32 Kbytes

DCache

32 Kbytes

PIOE

PIOA

DDR2/

LPDDR/

SDRAM

Controller

FIFO

DTCM

SRAM

64KB

ITCM

DDR_D0-DDR_D15

DDR_A0-DDR_A13

DDR_CS

DDR_CKE

DDR_RAS, DDR_CAS

DDR_CLK,#DDR_CLK

DDR_DQS[0..1]

DDR_DQM[0..1]

DDR_VREF

DDR_WE

DDR_BA0, DDR_BA1

D0-D15

A0/NBS0

A2-A15, A18

A16/BA0

A17/BA1

NCS0

NCS1/SDCS

NRD

NWR0/NWE

NWR1/NBS1

NWR3/NBS3

SDCK, #SDCK, SDCKE

RAS, CAS

SDWE, SDA10

A1/NBS2/NWR2

NANDOE, NANDWE

A19-A24

NCS5/CFCS1

A25/CFRNW

NCS4/CFCS0

NWAIT

CFCE1-CFCE2

NCS2

NCS3/NANDCS

D16-D31

NPCS2

NPCS1

SPCK

MOSI

MISO

NPCS0

NPCS3

AC97CK

AC97FS

AC97RX

AC97TX

TSADTRIG

GPAD4-GPAD7

AD0XP

AD1XM

AD2YP

GNDAN

VDDANA

TSADVREF

AD3YM

TK0-TK1

TF0-TF1

TD0-TD1

RD0-RD1

RF0-RF1

RK0-RK1

TCLK0-TCLK2

TIOA0-TIOA2

TIOB0-TIOB2

PWM0-PWM3

SPI0_, SPI1_ SSC0_, SSC1_

RTS0-RTS3

SCK0-SCK3

TXD0-TXD3

RDX0-RDX3

CTS0-CTS3

TWCK0-TWCK1

TWD0-TWD1

MCI0_CK,MCI1_CK

MCI0_DA0-MCI0_DA7

MCI0_CDA,MCI1_CDA

ISI_PCK

ISI_DO-ISI_D11

ISI_HSYNC

LCDD0-LCDD23

LCDVSYNC,LCDHSYNC

LCDDOTCK

LDDEN,LCDCC

LCDPWR, LCDMOD

VBG

ISI_VSYNC

ISI_MCK

DFSDP/HFSDPB,DFSDM/HFSDMB

DHSDP/HHSDPB,DHSDM/HHSDMB

HFSDPA,HFSDMA

HHSDPA,HHSDMA

ETXCK-ERXCK

ETXEN-ETXER

ECRS-ECOL

ERXER-ERXDV

ERX0-ERX3

ETX0-ETX3

EMDC

EMDIO

TDI

NTRST

TDO

TMS

TCK

JTAGSEL

RTCK

BMS

LCD

DMADMADMA DMA

ISI

DMA

EMAC 8-CH

DMA

FIQ

IRQ

DRXD

DTXD

PCK0-PCK1

VDDBU

SHDN

WKUP

XIN

NRST

XOUT

XIN32

XOUT32

VDDCORE

TST

DQM[0..1]

DQS[0..1]

TRNG

DQM[2..3]

MCI1_DA0-MCI1_DA7

TC3

TC4

TC5

TCLK3-TCLK5

TIOA3-TIOA5

TIOB3-TIOB5

EBI

SPI0

SPI1

HS EHCI

USB HOST

PA P B

USB

MCI0/MCI1

SD/SDIO

CE ATA

6438J–ATARM–10-Aug-12

SAM9G45

3. Signal Description

Table 3-1 gives details on the signal names classified by peripheral.

Table 3-1. Signal Description List

Signal Name Function Type Active

Level Reference

Voltage Comments

Power Supplies

VDDIOM0 DDR2 I/O Lines Power Supply Power 1.65V to 1.95V

VDDIOM1 EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to3.6V

VDDIOP0 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V

VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V

VDDIOP2 ISI I/O Lines Power Supply Power 1.65V to 3.6V

VDDBU Backup I/O Lines Power Supply Power 1.8V to 3.6V

VDDANA Analog Power Supply Power 3.0V to 3.6V

VDDPLLA PLLA Power Supply Power 0.9V to 1.1V

VDDPLLUTMI PLLUTMI Power Supply Power 0.9V to 1.1V

VDDOSC Oscillator Power Supply Power 1.65V to 3.6V

VDDCORE Core Chip Power Supply Power 0.9V to 1.1V

VDDUTMIC UDPHS and UHPHS UTMI+ Core

Power Supply Power 0.9V to 1.1V

VDDUTMII UDPHS and UHPHS UTMI+ interface

Power Supply Power 3.0V to 3.6V

GNDIOM DDR2 and EBI I/O Lines Ground Ground

GNDIOP Peripherals and ISI I/O lines Ground Ground

GNDCORE Core Chip Ground Ground

GNDOSC PLLA, PLLUTMI and Oscillator

Ground Ground

GNDBU Backup Ground Ground

GNDUTMI UDPHS and UHPHS UTMI+ Core and

interface Ground Ground

GNDANA Analog Ground Ground

Clocks, Oscillato rs and PLLs

XIN Main Oscillator Input Input

XOUT Main Oscillator Output Output

XIN32 Slow Clock Oscillator Input Input

XOUT32 Slow Clock Oscillator Output Output

VBG Bias Voltage Reference for USB Analog

PCK0 - PCK1 Programmable Clock Output Output (1)

6438J–ATARM–10-Aug-12

SAM9G45

Shutdown , Wakeup Logic

SHDN Shut-Down Control Output VDDBU

Driven at 0V only.

0: The device is in backup

mode

1: The device is running (not in

backup mode).

WKUP Wake-Up Input Input VDDBU Accept between 0V and

VDDBU.

ICE and JTAG

TCK Test Clock Input VDDIOP0 No pull-up resistor, Schmitt

trigger

TDI Test Data In Input VDDIOP0 No pull-up resistor, Schmitt

trigger

TDO Test Data Out Output VDDIOP0

TMS Test Mode Select Input VDDIOP0 No pull-up resistor, Schmitt

trigger

JTAGSEL JTAG Selection Input VDDBU Pull-down resistor (15 kΩ).

RTCK Return Test Clock Output VDDIOP0

Reset/Test

NRST Microcontroller Reset (2) I/O Low VDDIOP0 Pull-Up resistor (100 kΩ),

Schmitt trigger

TST Test Mode Select Input VDDBU Pull-down resistor (15 kΩ),

Schmitt trigger

NTRST Test Reset Signal Input VDDIOP0

Pull-Up resistor (100 kΩ),

Schmitt trigger.

NRST is an open drain output.

BMS Boot Mode Select Input VDDIOP0 Must be connected to GND or

VDDIOP0.

Debug Unit - DBGU

DRXD Debug Receive Data Input (1)

DTXD Debug Transmit Data Output (1)

Advanced Interrupt Controller - AIC

IRQ External Interrupt Input Input (1)

FIQ Fast Interrupt Input Input (1)

PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE

PA0 - PA31 Parallel IO Controller A I/O (1) Pulled-up input at reset

(100kΩ)(3), Schmitt trigger

PB0 - PB31 Parallel IO Controller B I/O (1) Pulled-up input at reset

(100kΩ)(3), Schmitt trigger

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active

Level Reference

Voltage Comments

6438J–ATARM–10-Aug-12

SAM9G45

PC0 - PC31 Parallel IO Controller C I/O (1) Pulled-up input at reset

(100kΩ)(3), Schmitt trigger

PD0 - PD31 Parallel IO Controller D I/O (1) Pulled-up input at reset

(100kΩ)(3), Schmitt trigger

PE0 - PE31 Parallel IO Controller E I/O (1) Pulled-up input at reset

(100kΩ)(3), Schmitt trigger

DDR Memory Interface- DDR2/SDRAM/LPDDR Controller

DDR_D0 -

DDR_D15 Data Bus I/O VDDIOM0 Pulled-up input at reset

DDR_A0 -

DDR_A13 Address Bus Output VDDIOM0 0 at reset

DDR_CLK-

#DDR_CLK DDR differential clock input Output VDDIOM0

DDR_CKE DDR Clock Enable Output High VDDIOM0

DDR_CS DDR Chip Select Output Low VDDIOM0

DDR_WE DDR Write Enable Output Low VDDIOM0

DDR_RAS-

DDR_CAS Row and Column Signal Output Low VDDIOM0

DDR_DQM[0..1] Write Data Mask Output VDDIOM0

DDR_DQS[0..1] Data Strobe Output VDDIOM0

DDR_BA0 -

DDR_BA1 Bank Select Output VDDIOM0

DDR_VREF Reference Voltage Input VDDIOM0

External Bus Interface - EBI

D0 -D31 Data Bus I/O VDDIOM1 Pulled-up input at reset

A0 - A25 Address Bus Output VDDIOM1 0 at reset

NWAIT External Wait Signal Input Low VDDIOM1

Static Memory Controller - SMC

NCS0 - NCS5 Chip Select Lines Output Low VDDIOM1

NWR0 - NWR3 Write Signal Output Low VDDIOM1

NRD Read Signal Output Low VDDIOM1

NWE Write Enable Output Low VDDIOM1

NBS0 - NBS3 Byte Mask Signal Output Low VDDIOM1

CompactFlash Support

CFCE1 - CFCE2 CompactFlash Chip Enable Output Low VDDIOM1

CFOE CompactFlash Output Enable Output Low VDDIOM1

CFWE CompactFlash Write Enable Output Low VDDIOM1

CFIOR CompactFlash IO Read Output Low VDDIOM1

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active

Level Reference

Voltage Comments

6438J–ATARM–10-Aug-12

SAM9G45

CFIOW CompactFlash IO Write Output Low VDDIOM1

CFRNW CompactFlash Read Not Write Output VDDIOM1

CFCS0 -CFCS1 CompactFlash Chip Select Lines Output Low VDDIOM1

NAND Flash Support

NANDCS NAND Flash Chip Select Output Low VDDIOM1

NANDOE NAND Flash Output Enable Output Low VDDIOM1

NANDWE NAND Flash Write Enable Output Low VDDIOM1

DDR2/SDRAM/LPDDR Controller

SDCK,#SDCK DDR2/SDRAM differential clock Output VDDIOM1

SDCKE DDR2/SDRAM Clock Enable Output High VDDIOM1

SDCS DDR2/SDRAM Controller Chip Select Output Low VDDIOM1

BA0 - BA1 Bank Select Output VDDIOM1

SDWE DDR2/SDRAM Write Enable Output Low VDDIOM1

RAS - CAS Row and Column Signal Output Low VDDIOM1

SDA10 SDRAM Address 10 Line Output VDDIOM1

DQS[0..1] Data Strobe Output VDDIOM1

DQM[0..3] Write Data Mask Output VDDIOM1

High Speed Multimedia Card Interface - HSMCIx

MCIx_CK Multimedia Card Clock I/O (1)

MCIx_CDA Multimedia Card Slot A Command I/O (1)

MCIx_DA0 -

MCIx_DA7 Multimedia Card Slot A Data I/O (1)

Universal Synchronous Asynchronous Receiver Transmitter - USARTx

SCKx USARTx Serial Clock I/O (1)

TXDx USARTx Transmit Data Output (1)

RXDx USARTx Receive Data Input (1)

RTSx USARTx Request To Send Output (1)

CTSx USARTx Clear To Send Input (1)

Synchronous Serial Controller - SSCx

TDx SSC Transmit Data Output (1)

RDx SSC Receive Data Input (1)

TKx SSC Transmit Clock I/O (1)

RKx SSC Receive Clock I/O (1)

TFx SSC Transmit Frame Sync I/O (1)

RFx SSC Receive Frame Sync I/O (1)

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active

Level Reference

Voltage Comments

6438J–ATARM–10-Aug-12

SAM9G45

AC97 Controller - AC97C

AC97RX AC97 Receive Signal Input (1)

AC97TX AC97 Transmit Signal Output (1)

AC97FS AC97 Frame Synchronization Signal Output (1)

AC97CK AC97 Clock signal Input (1)

Time Counter - TCx

TCLKx TC Channel x External Clock Input Input (1)

TIOAx TC Channel x I/O Line A I/O (1)

TIOBx TC Channel x I/O Line B I/O (1)

Pulse Width Modulation Co ntroller - PWM

PWMx Pulse Width Modulation Output Output (1)

Serial Peripheral Interface - SPIx_

SPIx_MISO Master In Slave Out I/O (1)

SPIx_MOSI Master Out Slave In I/O (1)

SPIx_SPCK SPI Serial Clock I/O (1)

SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low (1)

SPIx_NPCS1-

SPIx_NPCS3 SPI Peripheral Chip Select Output Low (1)

Two-Wire Interface

TWDx Two-wire Serial Data I/O (1)

TWCKx Two-wire Serial Clock I/O (1)

USB Host High Speed Port - UHPHS

HFSDPA USB Host Port A Full Speed Data + Analog VDDUTMII

HFSDMA USB Host Port A Full Speed Data - Analog VDDUTMII

HHSDPA USB Host Port A High Speed Data + Analog VDDUTMII

HHSDMA USB Host Port A High Speed Data - Analog VDDUTMII

HFSDPB USB Host Port B Full Speed Data + Analog VDDUTMII Multiplexed with DFSDP

HFSDMB USB Host Port B Full Speed Data - Analog VDDUTMII Multiplexed with DFSDM

HHSDPB USB Host Port B High Speed Data + Analog VDDUTMII Multiplexed with DHSDP

HHSDMB USB Host Port B High Speed Data - Analog VDDUTMII Multiplexed with DHSDM

USB Device High Speed Port - UDPHS

DFSDM USB Device Full Speed Data - Analog VDDUTMII

DFSDP USB Device Full Speed Data + Analog VDDUTMII

DHSDM USB Device High Speed Data - Analog VDDUTMII

DHSDP USB Device High Speed Data + Analog VDDUTMII

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active

Level Reference

Voltage Comments

6438J–ATARM–10-Aug-12

SAM9G45

Ethernet 10/100

ETXCK Transmit Clock or Reference Clock Input (1) MII only, REFCK in RMII

ERXCK Receive Clock Input (1) MII only

ETXEN Transmit Enable Output (1)

ETX0-ETX3 Transmit Data Output (1) ETX0-ETX1 only in RMII

ETXER Transmit Coding Error Output (1) MII only

ERXDV Receive Data Valid Input (1) RXDV in MII, CRSDV in RMII

ERX0-ERX3 Receive Data Input (1) ERX0-ERX1 only in RMII

ERXER Receive Error Input (1)

ECRS Carrier Sense and Data Valid Input (1) MII only

ECOL Collision Detect Input (1) MII only

EMDC Management Data Clock Output (1)

EMDIO Management Data Input/Output I/O (1)

Image Sensor Interface

ISI_D0-ISI_D11 Image Sensor Data Input VDDIOP2

ISI_MCK Image sensor Reference clock output VDDIOP2

ISI_HSYNC Image Sensor Horizontal Synchro input VDDIOP2

ISI_VSYNC Image Sensor Vertical Synchro input VDDIOP2

ISI_PCK Image Sensor Data clock input VDDIOP2

LCD Controller - LCDC

LCDD0 -

LCDD23 LCD Data Bus Output VDDIOP1

LCDVSYNC LCD Vertical Synchronization Output VDDIOP1

LCDHSYNC LCD Horizontal Synchronization Output VDDIOP1

LCDDOTCK LCD Dot Clock Output VDDIOP1

LCDDEN LCD Data Enable Output VDDIOP1

LCDCC LCD Contrast Control Output VDDIOP1

LCDPWR LCD panel Power enable control Output VDDIOP1

LCDMOD LCD Modulation signal Output VDDIOP1

Touch Screen Analog-to-Digital Converter

AD0XP

Analog input channel 0 or

Touch Screen Top channel Analog VDDANA Multiplexed with AD0

AD1XM

Analog input channel 1 or

Touch Screen Bottom channel Analog VDDANA Multiplexed with AD1

AD2YP

Analog input channel 2 or

Touch Screen Right channel Analog VDDANA Multiplexed with AD2

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active

Level Reference

Voltage Comments

6438J–ATARM–10-Aug-12

SAM9G45

Notes: 1. Refer to peripheral multiplexing tables in Section 8.4 “Peripheral Signals Multiplexing on I/O Lines” for these signals.

2. When configured as an input, the NRST pin enables asynchronous reset of the device when asserted low. This allows con-

nection of a simple push button on the NRST pin as a system-user reset.

3. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all

the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter-

face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the

peripheral multiplexing tables.

AD3YM

Analog input channel 3 or

Touch Screen Left channel Analog VDDANA Multiplexed with AD3

GPAD4-GPAD7 Analog Inputs Analog VDDANA

TSADTRG ADC Trigger Input VDDANA

TSADVREF ADC Reference Analog VDDANA

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active

Level Reference

Voltage Comments

6438J–ATARM–10-Aug-12

SAM9G45

4. Package and Pinout

The SAM9G45 is delivered in a 324-ball TFBGA package.

4.1 Mechanical Overview of the 324-ball TFBGA Package

Figure 4-1 shows the orientation of the 324-ball TFBGA Package

Figure 4-1. Orientation of the 324-ball TFBGA Package

1 3 4 5 6 7 8 9 101112131415 1617218

Bottom VIEW

6438J–ATARM–10-Aug-12

SAM9G45

4.2 324-ball TFBGA Package Pinout

Table 4-1. SAM9G45 Pinout for 324-ball BGA Package

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 PC27 E10 NANDWE K1 PE21 P10 TMS

A2 PC28 E11 DQS1 K2 PE23 P11 VDDPLLA

A3 PC25 E12 D13 K3 PE26 P12 PB20

A4 PC20 E13 D11 K4 PE22 P13 PB31

A5 PC12 E14 A4 K5 PE24 P14 DDR_D7

A6 PC7 E15 A8 K6 PE25 P15 DDR_D3

A7 PC5 E16 A9 K7 PE27 P16 DDR_D4

A8 PC0 E17 A7 K8 PE28 P17 DDR_D5

A9 NWR3/NBS3 E18 VDDCORE K9 VDDIOP0 P18 DDR_D10

A10 NCS0 F1 PD22 K10 VDDIOP0 R1 PA18

A11 DQS0 F2 PD24 K11 GNDIOM R2 PA20

A12 RAS F3 SHDN K12 GNDIOM R3 PA24

A13 SDCK F4 PE1 K13 VDDIOM0 R4 PA30

A14 NSDCK F5 PE3 K14 DDR_A7 R5 PB4

A15 D7 F6 VDDIOM1 K15 DDR_A8 R6 PB13

A16 DDR_VREF F7 PC19 K16 DDR_A9 R7 PD0

A17 D0 F8 PC14 K17 DDR_A11 R8 PD9

A18 A14 F9 PC4 K18 DDR_A10 R9 PD18

B1 PC31 F10 NCS1/SDCS L1 PA0 R10 TDI

B2 PC29 F11 NRD L2 PE30 R11 RTCK

B3 PC30 F12 SDWE L3 PE29 R12 PB22

B4 PC22 F13 A0/NBS0 L4 PE31 R13 PB29

B5 PC17 F14 A1/NBS2/NWR2 L5 PA2 R14 DDR_D6

B6 PC10 F15 A3 L6 PA4 R15 DDR_D1

B7 PC11 F16 A6 L7 PA8 R16 DDR_D0

B8 PC2 F17 A5 L8 PD2 R17 HHSDMA

B9 SDA10 F18 A2 L9 PD13 R18 HFSDMA

B10 A17/BA1 G1 PD25 L10 PD29 T1 PA22

B11 DQM0 G2 PD23 L11 PD31 T2 PA25

B12 SDCKE G3 PE6 L12 VDDIOM0 T3 PA26

B13 D12 G4 PE0 L13 VDDIOM0 T4 PB0

B14 D8 G5 PE2 L14 DDR_A1 T5 PB6

B15 D4 G6 PE8 L15 DDR_A3 T6 PB16

B16 D3 G7 PE4 L16 DDR_A4 T7 PD1

B17 A15 G8 PE11 L17 DDR_A6 T8 PD11

B18 A13 G9 GNDCORE L18 DDR_A5 T9 PD19

C1 XIN32 G10 VDDIOM1 M1 PA1 T10 PD30

C2 GNDANA G11 VDDIOM1 M2 PA5 T11 BMS

C3 WKUP G12 VDDCORE M3 PA6 T12 PB8

C4 PC26 G13 VDDCORE M4 PA7 T13 PB30

C5 PC21 G14 DDR_DQM0 M5 PA10 T14 DDR_D2

C6 PC15 G15 DDR_DQS1 M6 PA14 T15 PB21

C7 PC9 G16 DDR_BA1 M7 PB14 T16 PB23

C8 PC3 G17 DDR_BA0 M8 PD4 T17 HHSDPA

C9 NWR0/NWE G18 DDR_DQS0 M9 PD15 T18 HFSDPA

C10 A16/BA0 H1 PD26 M10 NRST U1 PA27

C11 CAS H2 PD27 M11 PB11 U2 PA29

C12 D15 H3 VDDIOP1 M12 PB25 U3 PA28

6438J–ATARM–10-Aug-12

SAM9G45

C13 D10 H4 PE13 M13 PB27 U4 PB3

C14 D6 H5 PE5 M14 VDDIOM0 U5 PB7

C15 D2 H6 PE7 M15 DDR_D14 U6 PB17

C16 GNDIOM H7 PE9 M16 DDR_D15 U7 PD7

C17 A18 H8 PE10 M17 DDR_A0 U8 PD10

C18 A12 H9 GNDCORE M18 DDR_A2 U9 PD14

D1 XOUT32 H10 GNDIOP N1 PA3 U10 TCK

D2 PD20 H11 VDDCORE N2 PA9 U11 VDDOSC

D3 GNDBU H12 GNDIOM N3 PA12 U12 GNDOSC

D4 VDDBU H13 GNDIOM N4 PA15 U13 PB10

D5 PC24 H14 DDR_CS N5 PA16 U14 PB26

D6 PC18 H15 DDR_WE N6 PA17 U15 HHSDPB/DHSDP

D7 PC13 H16 DDR_DQM1 N7 PB18 U16 HHSDMB/DHSDM

D8 PC6 H17 DDR_CAS N8 PD6 U17 GNDUTMI

D9 NWR1/NBS1 H18 DDR_NCLK N9 PD16 U18 VDDUTMIC

D10 NANDOE J1 PE19 N10 NTRST V1 PA31

D11 DQM1 J2 PE16 N11 PB9 V2 PB1

D12 D14 J3 PE14 N12 PB24 V3 PB2

D13 D9 J4 PE15 N13 PB28 V4 PB5

D14 D5 J5 PE12 N14 DDR_D13 V5 PB15

D15 D1 J6 PE17 N15 DDR_D8 V6 PD3

D16 VDDIOM1 J7 PE18 N16 DDR_D9 V7 PD5

D17 A11 J8 PE20 N17 DDR_D11 V8 PD12

D18 A10 J9 GNDCORE N18 DDR_D12 V9 PD17

E1 PD21 J10 GNDCORE P1 PA11 V10 TDO

E2 TSADVREF J11 GNDIOP P2 PA13 V11 XOUT

E3 VDDANA J12 GNDIOM P3 PA19 V12 XIN

E4 JTAGSEL J13 GNDIOM P4 PA21 V13 VDDPLLUTMI

E5 TST J14 DDR_A12 P5 PA23 V14 VDDIOP2

E6 PC23 J15 DDR_A13 P6 PB12 V15 HFSDPB/DFSDP

E7 PC16 J16 DDR_CKE P7 PB19 V16 HFSDMB/DFSDM

E8 PC8 J17 DDR_RAS P8 PD8 V17 VDDUTMII

E9 PC1 J18 DDR_CLK P9 PD28 V18 VBG

Table 4-1. SAM9G45 Pinout for 324-ball BGA Package (Continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

6438J–ATARM–10-Aug-12

SAM9G45

5. Power Considerations

5.1 Power Supplies

The SAM9G45 has several types of power supply pins:

• VDDCORE pins: Power the core, including the processor, the embedded memories and the

peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical.

• VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V

(1.8V typical).

• VDDIOM1 pins: Power the External Bus Interface 1 I/O lines; voltage ranges between 1.65V

and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V typical).

• VDDIOP0, VDDIOP1, VDDIOP2 pins: Power the Peripherals I/O lines; voltage ranges from

1.65V to 3.6V.

• VDDBU pin: Powers the Slow Clock oscillator, the internal RC oscillator and a part of the

System Controller; voltage ranges from 1.8V to 3.6V.

• VDDPLLUTMI pin: Powers the PLLUTMI cell; voltage range from 0.9V to 1.1V.

• VDDUTMIC pin: Powers the USB device and host UTMI+ core; voltage range from 0.9V to

1.1V, 1.0V typical.

• VDDUTMII pin: Powers the USB device and host UTMI+ interface; voltage range from 3.0V to

3.6V, 3.3V typical.

• VDDPLLA pin: Powers the PLLA cell; voltage ranges from 0.9V to 1.1V.

• VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 1.65V to 3.6V

• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V to 3.6V, 3.3V

typical.

Some supply pins share common ground (GND) pins whereas others have separate grounds.

The respective power/ground pin assignments are as follows:

VDDCORE GNDCORE

VDDIOM0, VDDIOM1 GNDIOM

VDDIOP0, VDDIOP1, VDDIOP2 GNDIOP

VDDBU GNDBU

VDDUTMIC, VDDUTMII GNDUTMI

VDDPLLUTMI, VDDPLLA, VDDOSC, GNDOSC

VDDANA GNDANA

6438J–ATARM–10-Aug-12

SAM9G45

6. Memories

Figure 6-1. SAM9G45 Memory Mapping

Address Memory Space

Internal Memories

0x00000000

EBI Chip Select 0

0x10000000

EBI Chip Select 1

DDRSDRC1

0x20000000

EBI Chip Select 2

0x30000000

EBI Chip Select 3

NANDFlash

0x40000000

EBI Chip Select 4

Compact Flash Slot 0

0x50000000

EBI Chip Select 5

Compact Flash Slot 1

0x60000000

DDRSDRC0

Chip Select

0x70000000

Undefined (Abort)

0x80000000

Internal Peripherals

0xF0000000

0xFFFFFFFF

Internal Memories

Boot Memory

0x00000000

ITCM

0x00100000

DTCM

0x00200000

SRAM

0x00300000

ROM

0x00400000

LCDC

0x00500000

UDPHS (DMA)

0x00600000

UHP OHCI

0x00700000

UHP EHCI

0x00800000

Reserved

0x00900000

Undefined (Abort)

0x00A00000

0x0FFFFFFF

Internal Peripherals

Reserved

0xF0000000

UDPHS27

0xFFF78000

TC0 TC0

0xFFF7C000

+18

TC0 TC1

+0x40

+18

TC0 TC2

+0x80

HSMCI0 11

0xFFF80000

TWI0 12

0xFFF84000

TWI1 13

0xFFF88000

USART0 7

0xFFF8C000

USART1 8

0xFFF90000

USART2 9

0xFFF94000

USART310

0xFFF98000

SSC0 16

0xFFF9C000

SSC1 17

0xFFFA0000

SPI0 14

0xFFFA4000

SPI1 15

0xFFFA8000

AC97C 24

0xFFFAC000

TSADCC 20

0xFFFB0000

ISI26

0xFFFB4000

PWM 19

0xFFFB8000

EMAC 25

0xFFFBC000

Reserved

0xFFFC0000

Reserved

0xFFFC4000

Reserved

0xFFFC8000

TRNG 6

0xFFFCC000

HSMCI1 29

0xFFFD0000

TC1 TC3

0xFFFD4000

TC1 TC4

+0x40

TC1 TC5

+0x80

Reserved

0xFFFD8000

System controller

0xFFFFC000

0xFFFFFFFF

System Controller

Reserved

0xFFFF0000

DDRSDRC1

0xFFFFE400

DDRSDRC0

0xFFFFE600

SMC

0xFFFFE800

MATRIX

0xFFFFEA00

DMAC 21

0xFFFFEC00

DBGU

0xFFFFEE00

AIC 0;31

0xFFFFF000

PIOA 2

0xFFFFF200

PIOB 3

0xFFFFF400

PIOC 4

0xFFFFF600

PIOD +5

0xFFFFF800

PIOE +5

0xFFFFFA00

PMC

0xFFFFFC00

SYSC RSTC

0xFFFFFD00

SYSC SHDWC

+0x10

SYSC RTT

+0x20

SYSC PIT

+0x30

SYSC WDT

+0x40

SYSC SCKCR

+0x50

SYSC GPBR

+0x60

SYSC

Reserved

+0x70

RTC

0xFFFFFDB0

Reserved

0xFFFFFDC0

0xFFFFFFFF

offset

(+ : wired-or)

peripheral

block

ECC

0xFFFFE200

6438J–ATARM–10-Aug-12

SAM9G45

6.1 Memory Mapping

A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of

the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional

features.

Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to

6 are directed to the EBI that associates these banks to the external chip selects NCS0 to

NCS5.

The bank 7 is directed to the DDRSDRC0 that associates this bank to DDR_NCS chip select

and so dedicated to the 4-port DDR2/ LPDDR controller.

The bank 0 is reserved for the addressing of the internal memories, and a second level of

decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripherals

and provides access to the Advanced Peripheral Bus (APB).

Other areas are unused and performing an access within them provides an abort to the master

requesting such an access.

6.2 Embedded Memories

6.2.1 Internal SRAM

The SAM9G45 product embeds a total of 64Kbytes high-speed SRAM split in 4 blocks of 16

Kbytes connected to one slave of the matrix. After reset and until the Remap Command is per-

formed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. After

Remap, the SRAM also becomes available at address 0x0.

Figure 6-2. Internal SRAM Reset

The SAM9G45 device embeds two memory features. The processor Tightly Coupled Memory

Interface (TCM) that allows the processor to access the memory up to processor speed (PCK)

and the interface on the AHB side allowing masters to access the memory at AHB speed (MCK).

A wait state is necessary to access the TCM at 400 MHz. Setting the bit NWS_TCM in the bus

Matrix TCM Configuration Register of the matrix inserts a wait state on the ITCM and DTCM

accesses.

RAM

64K

0x00300000

RAM

64K

0x00000000

Remap

6438J–ATARM–10-Aug-12

SAM9G45

6.2.2 TCM Interface

On the processor side, this Internal SRAM can be allocated to two areas.

• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block

anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR

configuration register located in the Chip Configuration User Interface. This SRAM block is

also accessible by the ARM926 Masters and by the AHB Masters through the AHB bus

• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block

anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is

also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus.

• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap

Command is performed, this SRAM block is accessible through the AHB bus at address

0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes

accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926

Data Masters.

Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is soft-

ware programmable according to Table 6-1.

6.2.3 Internal ROM

The SAM9G45 embeds an Internal ROM, which contains the boot ROM and SAM-BA® program.

At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0

(BMS =1) after the reset and before the Remap Command.

Table 6-1. ITCM and DTCM Memory Configuration

SRAM A ITCM size (Kbytes)

seen at 0x100000 through AHB SRAM B DTCM size (Kbytes)

seen at 0x200000 through AHB SRAM C (Kbytes)

seen at 0x300000 through AHB

0064

0640

32 32 0

6438J–ATARM–10-Aug-12

SAM9G45

6.3 I/O Drive Selection and Delay Control

6.3.1 I/O Drive Selection

The aim of this control is to adapt the signal drive to the frequency. Two bits allow the user to

select High or Low drive for memories data/address/ctrl signals.

• Setting the bit [17], EBI_DRIVE, in the EBI_CSA register of the matrix allows to control the

drive of the EBI.

• Setting the bit [18], DDR_DRIVE, in the EBI_CSA register of the matrix allows to control the

drive of the DDR.

6.3.2 Delay Control

To avoid the simultaneous switching of all the I/Os, a delay can be inserted on the different EBI,

DDR2 and PIO lines.

The control of these delays is the following:

• DDRSDRC

DDR_D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the DDRSDRC user

interface

– DDR_D[0] <=> DELAY1[3:0],

– DDR_D[1] <=> DELAY1[7:4],...

– DDR_D[6] <=> DELAY1[27:24],

– DDR_D[7] <=> DELAY1[31:28]

– DDR_D[8] <=> DELAY2[3:0],

– DDR_D[9] <=> DELAY2[7:4],...,

– DDR_D[14] <=> DELAY2[27:24],

– DDR_D[15] <=> DELAY2[31:28]

DDR_A[13:0] controlled by 2 registers, DELAY3 and DELAY4, located in the DDRSDRC user

interface

– DDR_A[0] <=> DELAY3[3:0],

– DDR_A[1] <=> DELAY3[7:4], ...,

– DDR_A[6] <=> DELAY3[27:24],

– DDR_A[7] <=> DELAY3[31:28]

– DDR_A[8] <=> DELAY4[3:0],

– DDR_A[9] <=> DELAY4[7:4], ...,

– DDR_A[12] <=> DELAY4[19:16],

– DDR_A[13] <=> DELAY4[23:20]

• EBI (DDRSDRC\HSMC3\Nandflash)

D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the HSMC3 user interface

– D[0] <=> DELAY1[3:0],

– D[1] <=> DELAY1[7:4],...,

– D[6] <=> DELAY1[27:24],

– D[7] <=> DELAY1[31:28]

– D[8] <=> DELAY2[3:0],

– D[9] <=> DELAY2[7:4],...,

6438J–ATARM–10-Aug-12

SAM9G45

– D[14] <=> DELAY2[27:24],

– D[15] <=> DELAY2[31:28]

D[31,16]on PIOC[31:16] controlled by 2 registers, DELAY3 and DELAY4, located in the

HSMC3 user interface

– D[16] <=> DELAY3[3:0],

– D[17] <=> DELAY3[7:4],...,

– D[22] <=> DELAY3[27:24],

– PC[23] <=> DELAY3[31:28]

– D[24] <=> DELAY4[3:0],

– D[25] <=> DELAY4[7:4],...,

– D[30] <=> DELAY4[27:24],

– D[31] <=> DELAY4[31:28]

A[25:0], controlled by 4 registers, DELAY5, DELAY6, DELAY7and DELAY8, located in the

HSMC3 user interface

– A[0] <=> DELAY5[3:0],

– A[1] <=> DELAY5[7:4],...,

– A[6] <=> DELAY5[27:24],

– A[7] <=> DELAY5[31:28]

– A[8] <=> DELAY6[3:0],

– A[9] <=> DELAY6[7:4],...,

– A[14] <=> DELAY6[27:24],

– A[15] <=> DELAY6[31:28]

– A[16] <=> DELAY7[3:0],

– A[17] <=> DELAY7[7:4],

– A[18] <=> DELAY7[11:8]

A25 on PC[12] and A[24:19] on PC[7:2]

– A19 <=> DELAY7[15:12],

– A20 <=> DELAY7[19:16],...,

– A23 <=> DELAY7[31:28],

– A24 <=> DELAY8[3:0],

– A25 <=> DELAY8[7:4]

• PIOA User interface

The delay can only be inserted on the HSMCI0 and HSMCI1 I/O lines, so on PA[9:2] and

PA[30:23]. The delay is controlled by 2 registers, DELAY1 and DELAY2, located in the PIOA

user interface.

– PA[2] <=> DELAY1[3:0],

– PA[3] <=> DELAY1[7:4],...,

– PA[8] <=> DELAY1[27:24],

– PA[9] <=> DELAY1[31:28]

– PA[23] <=> DELAY2[3:0],

– PA[24] <=> DELAY2[7:4],...,

– PA[29] <=> DELAY2[27:24],

– PA[30] <=> DELAY2[31:28]

6438J–ATARM–10-Aug-12

SAM9G45

7. System Controller

The System Controller is a set of peripherals that allows handling of key elements of the system,

such as power, resets, clocks, time, interrupts, watchdog, etc.

The System Controller User Interface also embeds the registers that configure the Matrix and a

set of registers for the chip configuration. The chip configuration registers configure the EBI chip

select assignment and voltage range for external memories.

7.1 System Controller Mapping

The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address

space, between addresses 0xFFFF E800 and 0xFFFF FFFF.

However, all the registers of the System Controller are mapped on the top of the address space.

All the registers of the System Controller can be addressed from a single pointer by using the

standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 Kbyte.

Figure 7-1 on page 21 shows the System Controller block diagram.

Figure 6-1 on page 15 shows the mapping of the User Interfaces of the System Controller

peripherals.

6438J–ATARM–10-Aug-12

SAM9G45

7.2 System Controller Bloc k Diagram

Figure 7-1. SAM9G45 System Controller Block Diagram

NRST

SLCK

Advanced

Interrupt

Controller

Real-Time

Timer

Periodic

Interval

Timer

Reset

Controller

PA0-PA31

periph_nreset

System Controller

Watchdog

Timer

wdt_fault

WDRPROC

PIO

Controllers

Power

Management

Controller

XIN

XOUT

MAINCK

PLLACK

pit_irq

MCK

proc_nreset

wdt_irq

periph_irq[2..6]

periph_nreset

periph_clk[2..30]

PCK

MCK

pmc_irq

nirq

nfiq

rtt_irq

Embedded

Peripherals

periph_clk[2..6]

pck[0-1]

out

enable

ARM926EJ-S

SLCK

irq

fiq

irq0-irq2

fiq

periph_irq[6..30]

periph_irq[2..24]

int

periph_nreset

periph_clk[6..30]

jtag_nreset

por_ntrst

proc_nreset

periph_nreset

dbgu_txd

dbgu_rxd

pit_irq

dbgu_irq

pmc_irq

rstc_irq

wdt_irq

rstc_irq

SLCK

Boundary Scan

TAP Controller

jtag_nreset

debug

PCK

debug

idle

debug

Bus Matrix

MCK

periph_nreset

proc_nreset

backup_nreset

periph_nreset

idle

Debug

Unit

dbgu_irq

MCK

dbgu_rxd

periph_nreset

dbgu_txd

rtt_alarm

Shut-Down

Controller

SLCK

rtt0_alarm

backup_nreset

SHDN

WKUP

4 General-purpose

Backup Registers

backup_nreset

XIN32

XOUT32

PB0-PB31

PC0-PC31

VDDBU Powered

VDDCORE Powered

ntrst

VDDCORE

POR

12MHz

MAIN OSC

PLLA

VDDBU

POR

SLOW

CLOCK

OSC

UPLL

por_ntrst

VDDBU

rtt_irq

UPLLCK

USB High Speed

Device Port

UPLLCK

periph_nreset

periph_irq[24]

OSC

PD0-PD31

SCKCR

PE0-PE31

Real-Time

Clock

rtc_irq

SLCK

backup_nreset rtc_alarm USB High Speed

Host Port

UPLLCK

periph_nreset

periph_irq[25]

UHP48M

UHP12M

UHP48M

UHP12M

DDR sysclk

6438J–ATARM–10-Aug-12

SAM9G45

7.3 Chip Identification

The AT91SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip

ID Extension Register.

• Chip ID: 0x819B05A2

• Ext ID: 0x00000004

• JTAG ID: 05B2_703F

• ARM926 TAP ID: 0x0792603F

7.4 Backup Section

The SAM9G45 features a Backup Section that embeds:

• RC Oscillator

• Slow Clock Oscillator

• SCKR register

•RTT

•RTC

• Shutdown Controller

• 4 backup registers

• A part of RSTC

This section is powered by the VDDBU rail.

6438J–ATARM–10-Aug-12

SAM9G45

8. Peripherals

8.1 Peripheral Mapping

As shown in Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address

space between the addresses 0xFFF7 8000 and 0xFFFC FFFF.

Each User Peripheral is allocated 16K bytes of address space.

8.2 Peripheral Identifiers

Table 8-1 defines the Peripheral Identifiers of the SAM9G45. A peripheral identifier is required

for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the con-

trol of the peripheral clock with the Power Management Controller.

Table 8-1. SAM9G45 Peripheral Identifiers

Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt

0AICAdvanced Interrupt Controller FIQ

1SYSCSystem Controller Interrupt

2PIOAParallel I/O Controller A,

3 PIOB Parallel I/O Controller B

4 PIOC Parallel I/O Controller C

5 PIOD/PIOE Parallel I/O Controller D/E

6 TRNG True Random Number Generator

7US0USART 0

8US1USART 1

9US2USART 2

10 US3 USART 3

11 MCI0 High Speed Multimedia Card Interface 0

12 TWI0 Two-Wire Interface 0

13 TWI1 Two-Wire Interface 1

14 SPI0 Serial Peripheral Interface

15 SPI1 Serial Peripheral Interface

16 SSC0 Synchronous Serial Controller 0

17 SSC1 Synchronous Serial Controller 1

18 TC0..TC5 Timer Counter 0,1,2,3,4,5

19 PWM Pulse Width Modulation Controller

20 TSADCC Touch Screen ADC Controller

21 DMA DMA Controller

22 UHPHS USB Host High Speed

23 LCDC LCD Controller

24 AC97C AC97 Controller

25 EMAC Ethernet MAC

26 ISI Image Sensor Interface

27 UDPHS USB Device High Speed

29 MCI1 High Speed Multimedia Card Interface 1

30 Reserved

31 AIC Advanced Interrupt Controller IRQ

6438J–ATARM–10-Aug-12

SAM9G45

8.3 Peripheral Interrupts and Clock Control

8.3.1 System Interrupt

The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:

• The DDR2/LPDDR Controller

• The Debug Unit

• The Periodic Interval Timer

• The Real-Time Timer

• The Real-Time Clock

• The Watchdog Timer

• The Reset Controller

• The Power Management Controller

The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used

within the Advanced Interrupt Controller.

8.3.2 External Interrupts

All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a

dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.

6438J–ATARM–10-Aug-12

SAM9G45

8.4 Peripheral Signals Multiplexing on I/O Lines

The SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multi-

plexes the I/O lines of the peripheral set.

Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral

functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of

the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and

“Comments” have been inserted in this table for the user’s own comments; they may be used to

track how pins are defined in an application.

Note that some peripheral function which are output only, might be duplicated within the both

tables.

The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral

mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the

device is maintained in a static state as soon as the reset is released. As a result, the bit corre-

sponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.

If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-

tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling

memories, in particular the address lines, which require the pin to be driven as soon as the reset

is released. Note that the pull-up resistor is also enabled in this case.

To amend EMC, programmable delay has been inserted on PIO lines able to run at high speed.

6438J–ATARM–10-Aug-12

SAM9G45

8.4.1 PIO Controller A Multiplexing

Table 8-2. Multiplexing on PIO Controller A (PIOA)

I/O Line Peripheral A Peripheral B Reset

State Power

Supply Function Comments

PA0 MCI0_CK TCLK3 I/O VDDIOP0

PA1 MCI0_CDA TIOA3 I/O VDDIOP0

PA2 MCI0_DA0 TIOB3 I/O VDDIOP0

PA3 MCI0_DA1 TCKL4 I/O VDDIOP0

PA4 MCI0_DA2 TIOA4 I/O VDDIOP0

PA5 MCI0_DA3 TIOB4 I/O VDDIOP0

PA6 MCI0_DA4 ETX2 I/O VDDIOP0

PA7 MCI0_DA5 ETX3 I/O VDDIOP0

PA8 MCI0_DA6 ERX2 I/O VDDIOP0

PA9 MCI0_DA7 ERX3 I/O VDDIOP0

PA10 ETX0 I/O VDDIOP0

PA11 ETX1 I/O VDDIOP0

PA12 ERX0 I/O VDDIOP0

PA13 ERX1 I/O VDDIOP0

PA14 ETXEN I/O VDDIOP0

PA15 ERXDV I/O VDDIOP0

PA16 ERXER I/O VDDIOP0

PA17 ETXCK I/O VDDIOP0

PA18 EMDC I/O VDDIOP0

PA19 EMDIO I/O VDDIOP0

PA20 TWD0 I/O VDDIOP0

PA21 TWCK0 I/O VDDIOP0

PA22 MCI1_CDA SCK3 I/O VDDIOP0

PA23 MCI1_DA0 RTS3 I/O VDDIOP0

PA24 MCI1_DA1 CTS3 I/O VDDIOP0

PA25 MCI1_DA2 PWM3 I/O VDDIOP0

PA26 MCI1_DA3 TIOB2 I/O VDDIOP0

PA27 MCI1_DA4 ETXER I/O VDDIOP0

PA28 MCI1_DA5 ERXCK I/O VDDIOP0

PA29 MCI1_DA6 ECRS I/O VDDIOP0

PA30 MCI1_DA7 ECOL I/O VDDIOP0

PA31 MCI1_CK PCK0 I/O VDDIOP0

6438J–ATARM–10-Aug-12

SAM9G45

8.4.2 PIO Controller B Multiplexing

Table 8-3. Multiplexing on PIO Controller B (PIOB)

I/O Line Peripheral A Peripheral B Reset

State Power

Supply Function Comments

PB0 SPI0_MISO I/O VDDIOP0

PB1 SPI0_MOSI I/O VDDIOP0

PB2 SPI0_SPCK I/O VDDIOP0

PB3 SPI0_NPCS0 I/O VDDIOP0

PB4 TXD1 I/O VDDIOP0

PB5 RXD1 I/O VDDIOP0

PB6 TXD2 I/O VDDIOP0

PB7 RXD2 I/O VDDIOP0

PB8 TXD3 ISI_D8 I/O VDDIOP2

PB9 RXD3 ISI_D9 I/O VDDIOP2

PB10 TWD1 ISI_D10 I/O VDDIOP2

PB11 TWCK1 ISI_D11 I/O VDDIOP2

PB12 DRXD I/O VDDIOP0

PB13 DTXD I/O VDDIOP0

PB14 SPI1_MISO I/O VDDIOP0

PB15 SPI1_MOSI CTS0 I/O VDDIOP0

PB16 SPI1_SPCK SCK0 I/O VDDIOP0

PB17 SPI1_NPCS0 RTS0 I/O VDDIOP0

PB18 RXD0 SPI0_NPCS1 I/O VDDIOP0

PB19 TXD0 SPI0_NPCS2 I/O VDDIOP0

PB20 ISI_D0 I/O VDDIOP2

PB21 ISI_D1 I/O VDDIOP2

PB22 ISI_D2 I/O VDDIOP2

PB23 ISI_D3 I/O VDDIOP2

PB24 ISI_D4 I/O VDDIOP2

PB25 ISI_D5 I/O VDDIOP2

PB26 ISI_D6 I/O VDDIOP2

PB27 ISI_D7 I/O VDDIOP2

PB28 ISI_PCK I/O VDDIOP2

PB29 ISI_VSYNC I/O VDDIOP2

PB30 ISI_HSYNC I/O VDDIOP2

PB31 ISI_MCK PCK1 I/O VDDIOP2

6438J–ATARM–10-Aug-12

SAM9G45

8.4.3 PIO Controller C Multiplexing

Table 8-4. Multiplexing on PIO Controller C (PIOC)

I/O Line Peripheral A Peripheral B Reset

State Power

Supply Function Comments

PC0 DQM2 DQM2 VDDIOM1

PC1 DQM3 DQM3 VDDIOM1

PC2 A19 A19 VDDIOM1

PC3 A20 A20 VDDIOM1

PC4 A21/NANDALE A21 VDDIOM1

PC5 A22/NANDCLE A22 VDDIOM1

PC6 A23 A23 VDDIOM1

PC7 A24 A24 VDDIOM1

PC8 CFCE1 I/O VDDIOM1

PC9 CFCE2 RTS2 I/O VDDIOM1

PC10 NCS4/CFCS0 TCLK2 I/O VDDIOM1

PC11 NCS5/CFCS1 CTS2 I/O VDDIOM1

PC12 A25/CFRNW A25 VDDIOM1

PC13 NCS2 I/O VDDIOM1

PC14 NCS3/NANDCS I/O VDDIOM1

PC15 NWAIT I/O VDDIOM1

PC16 D16 I/O VDDIOM1

PC17 D17 I/O VDDIOM1

PC18 D18 I/O VDDIOM1

PC19 D19 I/O VDDIOM1

PC20 D20 I/O VDDIOM1

PC21 D21 I/O VDDIOM1

PC22 D22 I/O VDDIOM1

PC23 D23 I/O VDDIOM1

PC24 D24 I/O VDDIOM1

PC25 D25 I/O VDDIOM1

PC26 D26 I/O VDDIOM1

PC27 D27 I/O VDDIOM1

PC28 D28 I/O VDDIOM1

PC29 D29 I/O VDDIOM1

PC30 D30 I/O VDDIOM1

PC31 D31 I/O VDDIOM1

6438J–ATARM–10-Aug-12

SAM9G45

8.4.4 PIO Controller D Multiplexing

Table 8-5. Multiplexing on PIO Controller D (PIOD)

I/O Line Peripheral A Peripheral B Reset

State Power

Supply Function Comments

PD0 TK0 PWM3 I/O VDDIOP0

PD1 TF0 I/O VDDIOP0

PD2 TD0 I/O VDDIOP0

PD3 RD0 I/O VDDIOP0

PD4 RK0 I/O VDDIOP0

PD5 RF0 I/O VDDIOP0

PD6 AC97RX I/O VDDIOP0

PD7 AC97TX TIOA5 I/O VDDIOP0

PD8 AC97FS TIOB5 I/O VDDIOP0

PD9 AC97CK TCLK5 I/O VDDIOP0

PD10 TD1 I/O VDDIOP0

PD11 RD1 I/O VDDIOP0

PD12 TK1 PCK0 I/O VDDIOP0

PD13 RK1 I/O VDDIOP0

PD14 TF1 I/O VDDIOP0

PD15 RF1 I/O VDDIOP0

PD16 RTS1 I/O VDDIOP0

PD17 CTS1 I/O VDDIOP0

PD18 SPI1_NPCS2 IRQ I/O VDDIOP0

PD19 SPI1_NPCS3 FIQ I/O VDDIOP0

PD20 TIOA0 I/O VDDANA TSAD0

PD21 TIOA1 I/O VDDANA TSAD1

PD22 TIOA2 I/O VDDANA TSAD2

PD23 TCLK0 I/O VDDANA TSAD3

PD24 SPI0_NPCS1 PWM0 I/O VDDANA GPAD4

PD25 SPI0_NPCS2 PWM1 I/O VDDANA GPAD5

PD26 PCK0 PWM2 I/O VDDANA GPAD6

PD27 PCK1 SPI0_NPCS3 I/O VDDANA GPAD7

PD28 TSADTRG SPI1_NPCS1 I/O VDDIOP0

PD29 TCLK1 SCK1 I/O VDDIOP0

PD30 TIOB0 SCK2 I/O VDDIOP0

PD31 TIOB1 PWM1 I/O VDDIOP0

6438J–ATARM–10-Aug-12

SAM9G45

8.4.5 PIO Controller E Multiplexing

Table 8-6. Multiplexing on PIO Controller E (PIOE)

I/O Line Peripheral A Peripheral B Reset

State Power

Supply Function Comments

PE0 LCDPWR PCK0 I/O VDDIOP1

PE1 LCDMOD I/O VDDIOP1

PE2 LCDCC I/O VDDIOP1

PE3 LCDVSYNC I/O VDDIOP1

PE4 LCDHSYNC I/O VDDIOP1

PE5 LCDDOTCK I/O VDDIOP1

PE6 LCDDEN I/O VDDIOP1

PE7 LCDD0 LCDD2 I/O VDDIOP1

PE8 LCDD1 LCDD3 I/O VDDIOP1

PE9 LCDD2 LCDD4 I/O VDDIOP1

PE10 LCDD3 LCDD5 I/O VDDIOP1

PE11 LCDD4 LCDD6 I/O VDDIOP1

PE12 LCDD5 LCDD7 I/O VDDIOP1

PE13 LCDD6 LCDD10 I/O VDDIOP1

PE14 LCDD7 LCDD11 I/O VDDIOP1

PE15 LCDD8 LCDD12 I/O VDDIOP1

PE16 LCDD9 LCDD13 I/O VDDIOP1

PE17 LCDD10 LCDD14 I/O VDDIOP1

PE18 LCDD11 LCDD15 I/O VDDIOP1

PE19 LCDD12 LCDD18 I/O VDDIOP1

PE20 LCDD13 LCDD19 I/O VDDIOP1

PE21 LCDD14 LCDD20 I/O VDDIOP1

PE22 LCDD15 LCDD21 I/O VDDIOP1

PE23 LCDD16 LCDD22 I/O VDDIOP1

PE24 LCDD17 LCDD23 I/O VDDIOP1

PE25 LCDD18 I/O VDDIOP1

PE26 LCDD19 I/O VDDIOP1

PE27 LCDD20 I/O VDDIOP1

PE28 LCDD21 I/O VDDIOP1

PE29 LCDD22 I/O VDDIOP1

PE30 LCDD23 I/O VDDIOP1

PE31 PWM2 PCK1 I/O VDDIOP1

6438J–ATARM–10-Aug-12

SAM9G45

9. ARM926EJ-S Processor Overview

9.1 Description

The ARM926EJ-S™ processor is a member of the ARM9™ family of general-purpose micropro-

cessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-

tasking applications where full memory management, high performance, low die size and low

power are all important features.

The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets,

enabling the user to trade off between high performance and high code density. It also supports

8-bit Java instruction set and includes features for efficient execution of Java bytecode, provid-

ing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-

powered wireless and embedded devices. It includes an enhanced multiplier design for

improved DSP performance.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist

in both hardware and software debug.

The ARM926EJ-S provides a complete high performance processor subsystem, including:

• An ARM9EJ-S integer core

• A Memory Management Unit (MMU)

• Separate instruction and data AMBA AHB bus interfaces

• Separate instruction and data TCM interfaces

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9.2 Embedded Characteristics

• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java

acceleration

• Two Instruction Sets

– ARM High-performance 32-bit Instruction Set

– Thumb High Code Density 16-bit Instruction Set

• DSP Instruction Extensions

• 5-Stage Pipeline Architecture:

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

– Data Memory (M)

– Register Write (W)

• 32-Kbyte Data Cache, 32-Kbyte Instruction Cache

– Virtually-addressed 4-way Associative Cache

– Eight words per line

– Write-through and Write-back Operation

– Pseudo-random or Round-robin Replacement

• Write Buffer

– Main Write Buffer with 16-word Data Buffer and 4-address Buffer

– DCache Write-back Buffer with 8-word Entries and a Single Address Entry

– Software Control Drain

• Standard ARM v4 and v5 Memory Management Unit (MMU)

– Access Permission for Sections

– Access Permission for large pages and small pages can be specified separately for

each quarter of the page

– 16 embedded domains

• Bus Interface Unit (BIU)

– Arbitrates and Schedules AHB Requests

– Separate Masters for both instruction and data access providing complete Matrix

system flexibility

– Separate Address and Data Buses for both the 32-bit instruction interface and the

32-bit data interface

– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit

(Words)

• TCM Interface

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9.3 Block Diagram

Figure 9-1. ARM926EJ-S Internal Functional Block Diagram

CP15 System

Configuration

Coprocessor

External

Coprocessor

Interface

Trace Port

Interface

ARM9EJ-S

Processor Core

DTCM

Interface

Data TLB Instruction

TLB ITCM

Interface

Data Cache AHB Interface

and

Write Buffer

Instruction

Cache

Write Data

Read

Data

Instruction

Fetches

Data

Address

Instruction

Address

Data

Address

Instruction

Address

Instruction TCM

Data TCM

MMU

AMBA AHB

External Coprocessors ETM9

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9.4 ARM9EJ-S Processor

9.4.1 ARM9EJ-S Operating States

The ARM9EJ-S processor can operate in three different states, each with a specific instruction

set:

• ARM state: 32-bit, word-aligned ARM instructions.

• THUMB state: 16-bit, halfword-aligned Thumb instructions.

• Jazelle state: variable length, byte-aligned Jazelle instructions.

In Jazelle state, all instruction Fetches are in words.

9.4.2 Switching State

The operating state of the ARM9EJ-S core can be switched between:

• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC

• ARM state and Jazelle state using the BXJ instruction

All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or

Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle

states occurs automatically on return from the exception handler.

9.4.3 Instruction Pipelines

The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions

to the processor.

A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch,

Decode, Execute, Memory and Writeback stages.

A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch,

Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages.

9.4.4 M emo ry Access

The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words

must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and

bytes can be placed on any byte boundary.

Because of the nature of the pipelines, it is possible for a value to be required for use before it

has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S con-

trol logic automatically detects these cases and stalls the core or forward data.

9.4.5 Jazelle Technology

The Jazelle technology enables direct and efficient execution of Java byte codes on ARM pro-

cessors, providing high performance for the next generation of Java-powered wireless and

embedded devices.

The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java

Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb

instructions, it executes Java byte codes. The Java byte code decoder logic implemented in

ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without

any overhead, while less frequently used byte codes are broken down into optimized sequences

of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the

application and invisible to the operating system. All existing ARM registers are re-used in

Jazelle state and all registers then have particular functions in this mode.

6438J–ATARM–10-Aug-12

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Minimum interrupt latency is maintained across both ARM state and Java state. Since byte

codes execution can be restarted, an interrupt automatically triggers the core to switch from

Java state to ARM state for the execution of the interrupt handler. This means that no special

provision has to be made for handling interrupts while executing byte codes, whether in hard-

ware or in software.

9.4.6 ARM9EJ-S Operating Modes

In all states, there are seven operation modes:

• User mode is the usual ARM program execution state. It is used for executing most

application programs

• Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data

transfer or channel process

• Interrupt (IRQ) mode is used for general-purpose interrupt handling

• Supervisor mode is a protected mode for the operating system

• Abort mode is entered after a data or instruction prefetch abort

• System mode is a privileged user mode for the operating system

• Undefined mode is entered when an undefined instruction exception occurs

Mode changes may be made under software control, or may be brought about by external inter-

rupts or exception processing. Most application programs execute in User Mode. The non-user

modes, known as privileged modes, are entered in order to service interrupts or exceptions or to

access protected resources.

9.4.7 ARM9EJ-S Registers

The ARM9EJ-S core has a total of 37 registers.

• 31 general-purpose 32-bit registers

• 6 32-bit status registers

Table 9-1 shows all the registers in all modes.

Table 9-1. ARM9TDMI Modes and Registers Layout

User and

System Mode Supervisor

Mode Abort Mode Undefined

Mode Interrupt

Mode Fast Interrupt

Mode

R0 R0 R0 R0 R0 R0

R1 R1 R1 R1 R1 R1

R2 R2 R2 R2 R2 R2

R3 R3 R3 R3 R3 R3

R4 R4 R4 R4 R4 R4

R5 R5 R5 R5 R5 R5

R6 R6 R6 R6 R6 R6

R7 R7 R7 R7 R7 R7

R8 R8 R8 R8 R8 R8_FIQ

R9 R9 R9 R9 R9 R9_FIQ

R10 R10 R10 R10 R10 R10_FIQ

R11 R11 R11 R11 R11 R11_FIQ

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The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional

registers used to hold either data or address values. Register r14 is used as a Link register that

holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a pro-

gram counter (PC), whereas the Current Program Status Register (CPSR) contains condition

code flags and the current mode bits.

In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers

(r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding

banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val-

ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when

BL or BLX instructions are executed within interrupt or exception routines. There is another reg-

ister called Saved Program Status Register (SPSR) that becomes available in privileged modes

instead of CPSR. This register contains condition code flags and the current mode bits saved as

a result of the exception that caused entry to the current (privileged) mode.

In all modes and due to a software agreement, register r13 is used as stack pointer.

The use and the function of all the registers described above should obey ARM Procedure Call

Standard (APCS) which defines:

• Constraints on the use of registers

• Stack conventions

• Argument passing and result return

For more details, refer to ARM Software Development Kit.

The Thumb state register set is a subset of the ARM state set. The programmer has direct

access to:

• Eight general-purpose registers r0-r7

• Stack pointer, SP

• Link register, LR (ARM r14)

•PC

• CPSR

R12 R12 R12 R12 R12 R12_FIQ

R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ

R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ

PC PC PC PC PC PC

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_SVC SPSR_ABOR

SPSR_UNDE

FSPSR_IRQ SPSR_FIQ

Mode-specific banked registers

Table 9-1. ARM9TDMI Modes and Registers Layout

User and

System Mode Supervisor

Mode Abort Mode Undefined

Mode Interrupt

Mode Fast Interrupt

Mode

6438J–ATARM–10-Aug-12

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There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see

the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12).

9.4.7.1 S ta tus Reg i st er s

The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The

program status registers:

• hold information about the most recently performed ALU operation

• control the enabling and disabling of interrupts

• set the processor operation mode

Figure 9-2. Status Register Format

Figure 9-2 shows the status register format, where:

• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags

• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic

instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve

DSP operations.

The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by

an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the

status of the Q flag.

• The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:

– J = 0: The processor is in ARM or Thumb state, depending on the T bit

– J = 1: The processor is in Jazelle state.

• Mode: five bits to encode the current processor mode

9.4.7.2 Exceptions

9.4.7.3 E xc ep tio n Types an d Prior it i es

The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi-

leged mode. The types of exceptions are:

• Fast interrupt (FIQ)

• Normal interrupt (IRQ)

• Data and Prefetched aborts (Abort)

• Undefined instruction (Undefined)

• Software interrupt and Reset (Supervisor)

NZCVQ JIFT

Mode

Reserved

Mode bits

Thumb state bit

FIQ disable

IRQ disable

Jazelle state bit

Reserved

Sticky Overflow

Overflow

Carry/Borrow/Extend

Zero

Negative/Less than

31 30 29 28 27 24 7 6 5 0

6438J–ATARM–10-Aug-12

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When an exception occurs, the banked version of R14 and the SPSR for the exception mode

are used to save the state.

More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep-

tions according to the following priority order:

• Reset (highest priority)

• Data Abort

•FIQ

•IRQ

•Prefetch Abort

• BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)

The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.

Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort

occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and pro-

ceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to

resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer

error does not escape detection.

9.4.7.4 Exception Modes and Handling

Exceptions arise whenever the normal flow of a program must be halted temporarily, for exam-

ple, to service an interrupt from a peripheral.

When handling an ARM exception, the ARM9EJ-S core performs the following operations:

1. Preserves the address of the next instruction in the appropriate Link Register that cor-

responds to the new mode that has been entered. When the exception entry is from:

– ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction

into LR (current PC(r15) + 4 or PC + 8 depending on the exception).

– THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value

(current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the

program to resume from the correct place on return.

2. Copies the CPSR into the appropriate SPSR.

3. Forces the CPSR mode bits to a value that depends on the exception.

4. Forces the PC to fetch the next instruction from the relevant exception vector.

The register r13 is also banked across exception modes to provide each exception handler with

private stack pointer.

The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable

nesting of exceptions.

When an exception has completed, the exception handler must move both the return value in

the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies

according to the type of exception. This action restores both PC and the CPSR.

The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or

remove the requirement for register saving which minimizes the overhead of context switching.

The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be

completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as

invalid, but does not take the exception until the instruction reaches the Execute stage in the

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pipeline. If the instruction is not executed, for example because a branch occurs while it is in the

pipeline, the abort does not take place.

The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the

problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction

caused a Prefetch Abort.

A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until

the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for

example because a branch occurs while it is in the pipeline, the breakpoint does not take place.

9.4.8 ARM Instruction Set Overview

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions

ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition

code field (bits[31:28]).

For further details, see the ARM Technical Reference Manual.

Table 9-2 gives the ARM instruction mnemonic list.

Table 9-2. ARM Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move MVN Move Not

ADD Add ADC Add with Carry

SUB Subtract SBC Subtract with Carry

RSB Reverse Subtract RSC Reverse Subtract with Carry

CMP Compare CMN Compare Negated

TST Test TEQ Test Equivalence

AND Logical AND BIC Bit Clear

EOR Logical Exclusive OR ORR Logical (inclusive) OR

MUL Multiply MLA Multiply Accumulate

SMULL Sign Long Multiply UMULL Unsigned Long Multiply

SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply

Accumulate

MSR Move to Status Register MRS Move From Status Register

B Branch BL Branch and Link

BX Branch and Exchange SWI Software Interrupt

LDR Load Word STR Store Word

LDRSH Load Signed Halfword

LDRSB Load Signed Byte

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9.4.9 Ne w ARM Instruction Set

Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.

9.4.10 Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set.

The Thumb instruction set is divided into:

• Branch instructions

• Data processing instructions

• Load and Store instructions

LDRH Load Half Word STRH Store Half Word

LDRB Load Byte STRB Store Byte

LDRBT Load Register Byte with

Translation STRBT Store Register Byte with

Translation

LDRT Load Register with Translation STRT Store Register with Translation

LDM Load Multiple STM Store Multiple

SWP Swap Word SWPB Swap Byte

MCR Move To Coprocessor MRC Move From Coprocessor

LDC Load To Coprocessor STC Store From Coprocessor

CDP Coprocessor Data Processing

Table 9-2. ARM Instruction Mnemonic List (Continued)

Mnemonic Operation Mnemonic Operation

Table 9-3. New ARM Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

BXJ Branch and exchange to Java MRRC Move double from coprocessor

BLX (1) Branch, Link and exchange MCR2 Alternative move of ARM reg to

coprocessor

SMLAxy Signed Multiply Accumulate 16 *

16 bit MCRR Move double to coprocessor

SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data

Processing

SMLAWy Signed Multiply Accumulate 32 *

16 bit BKPT Breakpoint

SMULxy Signed Multiply 16 * 16 bit PLD Soft Preload, Memory prepare to

load from address

SMULWy Signed Multiply 32 * 16 bit STRD Store Double

QADD Saturated Add STC2 Alternative Store from

Coprocessor

QDADD Saturated Add with Double LDRD Load Double

QSUB Saturated subtract LDC2 Alternative Load to Coprocessor

QDSUB Saturated Subtract with double CLZ Count Leading Zeroes

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• Load and Store multiple instructions

• Exception-generating instruction

Table 5 shows the Thumb instruction set, for further details, see the ARM Technical Reference

Manual.

Table 9-4 gives the Thumb instruction mnemonic list.

Table 9-4. Thumb Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move MVN Move Not

ADDAdd ADCAdd with Carry

SUB Subtract SBC Subtract with Carry

CMP Compare CMN Compare Negated

TST Test NEG Negate

AND Logical AND BIC Bit Clear

EOR Logical Exclusive OR ORR Logical (inclusive) OR

LSL Logical Shift Left LSR Logical Shift Right

ASR Arithmetic Shift Right ROR Rotate Right

MUL Multiply BLX Branch, Link, and Exchange

B Branch BL Branch and Link

BX Branch and Exchange SWI Software Interrupt

LDR Load Word STR Store Word

LDRH Load Half Word STRH Store Half Word

LDRB Load Byte STRB Store Byte

LDRSH Load Signed Halfword LDRSB Load Signed Byte

LDMIA Load Multiple STMIA Store Multiple

PUSH Push Register to stack POP Pop Register from stack

BCC Conditional Branch BKPT Breakpoint

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9.5 CP15 Copr ocessor

Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the

items in the list below:

• ARM9EJ-S

• Caches (ICache, DCache and write buffer)

•TCM

•MMU

• Other system options

To control these features, CP15 provides 16 additional registers. See Table 9-5.

Notes: 1. Register locations 0,5, and 13 each provide access to more than one register. The register

accessed depends on the value of the opcode_2 field.

2. Register location 9 provides access to more than one register. The register accessed depends

on the value of the CRm field.

Table 9-5. CP15 Registers

0 ID Code(1) Read/Unpredictable

0 Cache type(1) Read/Unpredictable

0 TCM status(1) Read/Unpredictable

1 Control Read/write

2 Translation Table Base Read/write

3 Domain Access Control Read/write

4 Reserved None

5 Data fault Status(1) Read/write

5 Instruction fault status(1) Read/write

6 Fault Address Read/write

7 Cache Operations Read/Write

8 TLB operations Unpredictable/Write

9 cache lockdown(2) Read/write

9 TCM region Read/write

10 TLB lockdown Read/write

11 Reserved None

12 Reserved None

13 FCSE PID(1) Read/write

13 Context ID(1) Read/Write

14 Reserved None

15 Test configuration Read/Write

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9.5.1 CP15 Registers Access

CP15 registers can only be accessed in privileged mode by:

• MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register

to CP15.

• MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of

CP15 to an ARM register.

Other instructions like CDP, LDC, STC can cause an undefined instruction exception.

The assembler code for these instructions is:

MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.

The MCR, MRC instructions bit pattern is shown below:

• CRm[3:0]: Specified Coprocessor Action

Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 spe-

cific register behavior.

• opcode_2[7:5]

Determines specific coprocessor operation code. By default, set to 0.

• Rd[15:12]: ARM Register

Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.

• CRn[19:16]: Coprocessor Register

Determines the destination coprocessor register.

• L: Instruction Bit

0 = MCR instruction

1 = MRC instruction

• opcode_1[23:20]: Coprocessor Code

Defines the coprocessor specific code. Value is c15 for CP15.

• cond [31:28]: Condition

For more details, see Chapter 2 in ARM926EJ-S TRM.

31 30 29 28 27 26 25 24

cond 1110

23 22 21 20 19 18 17 16

opcode_1 L CRn

15 14 13 12 11 10 9 8

Rd 1111

76543210

opcode_2 1 CRm

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SAM9G45

9.6 Memory Management Unit (MMU)

The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir-

tual memory features required by operating systems like Symbian OS®, Windows CE®, and

Linux®. These virtual memory features are memory access permission controls and virtual to

physical address translations.

The Virtual Address generated by the CPU core is converted to a Modified Virtual Address

(MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The

MMU translates modified virtual addresses to physical addresses by using a single, two-level

page table set stored in physical memory. Each entry in the set contains the access permissions

and the physical address that correspond to the virtual address.

The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These

entries contain a pointer to either a 1 MB section of physical memory along with attribute infor-

mation (access permissions, domain, etc.) or an entry in the second level translation tables;

coarse table and fine table.

The second level translation tables contain two subtables, coarse table and fine table. An entry

in the coarse table contains a pointer to both large pages and small pages along with access

permissions. An entry in the fine table contains a pointer to large, small and tiny pages.

Table 7 shows the different attributes of each page in the physical memory.

The MMU consists of:

• Access control logic

• Translation Look-aside Buffer (TLB)

• Translation table walk hardware

9.6.1 Access Control Logic

The access control logic controls access information for every entry in the translation table. The

access control logic checks two pieces of access information: domain and access permissions.

The domain is the primary access control mechanism for a memory region; there are 16 of them.

It defines the conditions necessary for an access to proceed. The domain determines whether

the access permissions are used to qualify the access or whether they should be ignored.

The second access control mechanism is access permissions that are defined for sections and

for large, small and tiny pages. Sections and tiny pages have a single set of access permissions

whereas large and small pages can be associated with 4 sets of access permissions, one for

each subpage (quarter of a page).

Table 9-6. Mapping Details

Mapping Name Mapping Size Access Pe rmi ssi on By Subpage Size

Section 1M byte Section -

Large Page 64K bytes 4 separated subpages 16K bytes

Small Page 4K bytes 4 separated subpages 1K byte

Tiny Page 1K byte Tiny Page -

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9.6.2 Translation Look-aside Buffer (TLB)

The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going

through the translation process every time. When the TLB contains an entry for the MVA (Modi-

fied Virtual Address), the access control logic determines if the access is permitted and outputs

the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU

signals the CPU core to abort.

If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked

to retrieve the translation information from the translation table in physical memory.

9.6.3 Translation Table Walk Hardware

The translation table walk hardware is a logic that traverses the translation tables located in

physical memory, gets the physical address and access permissions and updates the TLB.

The number of stages in the hardware table walking is one or two depending whether the

address is marked as a section-mapped access or a page-mapped access.

There are three sizes of page-mapped accesses and one size of section-mapped access. Page-

mapped accesses are for large pages, small pages and tiny pages. The translation process

always begins with a level one fetch. A section-mapped access requires only a level one fetch,

but a page-mapped access requires an additional level two fetch. For further details on the

MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

9.6.4 MMU Faults

The MMU generates an abort on the following types of faults:

• Alignment faults (for data accesses only)

• Translation faults

• Domain faults

• Permission faults

The access control mechanism of the MMU detects the conditions that produce these faults. If

the fault is a result of memory access, the MMU aborts the access and signals the fault to the

CPU core.The MMU retains status and address information about faults generated by the data

accesses in the data fault status register and fault address register. It also retains the status of

faults generated by instruction fetches in the instruction fault status register.

The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and

the domain number of the aborted access when it happens. The fault address register (register 6

in CP15) holds the MVA associated with the access that caused the Data Abort. For further

details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

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SAM9G45

9.7 Caches and Write Buffer

The ARM926EJ-S contains a 32K Byte Instruction Cache (ICache), a 32K Byte Data Cache

(DCache), and a write buffer. Although the ICache and DCache share common features, each

still has some specific mechanisms.

The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged

using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty

bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache

pollution control, and line replacement.

A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly

known as wrapping. This feature enables the caches to perform critical word first cache refilling.

This means that when a request for a word causes a read-miss, the cache performs an AHB

access. Instead of loading the whole line (eight words), the cache loads the critical word first, so

the processor can reach it quickly, and then the remaining words, no matter where the word is

located in the line.

The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7

(cache operations) and CP15 register 9 (cache lockdown).

9.7.1 Instruction Cache (ICache)

The ICache caches fetched instructions to be executed by the processor. The ICache can be

enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.

When the MMU is enabled, all instruction fetches are subject to translation and permission

checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are

made and the physical address is flat-mapped to the modified virtual address. With the MVA use

disabled, context switching incurs ICache cleaning and/or invalidating.

When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see

Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM).

On reset, the ICache entries are invalidated and the ICache is disabled. For best performance,

ICache should be enabled as soon as possible after reset.

9.7.2 Data Cache (DCache) and Write Buffer

ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory band-

width and latency on data access performance. The operations of DCache and write buffer are

closely connected.

9.7.2.1 DCache

The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission

and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data

accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are

noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All

addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating

every time a context switch occurs.

The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and

uses it when writing modified lines back to external memory. This means that the MMU is not

involved in write-back operations.

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SAM9G45

Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other

one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the

cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide

whether all, half or none is written back to memory.

DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see

Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM).

The DCache supports write-through and write-back cache operations, selected by memory

region using the C and B bits in the MMU translation tables.

The DCache contains an eight data word entry, single address entry write-back buffer used to

hold write-back data for cache line eviction or cleaning of dirty cache lines.

The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and

Write Buffer operations are closely connected as their configuration is set in each section by the

page descriptor in the MMU translation table.

9.7.2.2 Write Buffer

The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buf-

fer. The write buffer is used for all writes to a bufferable region, write-through region and write-

back region. It also allows to avoid stalling the processor when writes to external memory are

performed. When a store occurs, data is written to the write buffer at core speed (high speed).

The write buffer then completes the store to external memory at bus speed (typically slower than

the core speed). During this time, the ARM9EJ-S processor can preform other tasks.

DCache and Write Buffer support write-back and write-through memory regions, controlled by C

and B bits in each section and page descriptor within the MMU translation tables.

9.7.2.3 Write-though Operation

When a cache write hit occurs, the DCache line is updated. The updated data is then written to

the write buffer which transfers it to external memory.

When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in

the write buffer which transfers it to external memory.

9.7.2.4 Write-back Operation

When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its

contents are not up-to-date with those in the external memory.

When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in

the write buffer which transfers it to external memory.

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SAM9G45

9.8 Tightly-Coupled Memory Interface

9.8.1 TCM Description

The ARM926EJ-S processor features a Tightly-coupled Memory (TCM) interface, which enables

separate instruction and data TCMs (ITCM and DTCM) to be directly reached by the processor.

TCMs are used to store real-time and performance critical code, they also provide a DMA sup-

port mechanism. Unlike AHB accesses to external memories, accesses to TCMs are fast and

deterministic and do not incur bus penalties.

The user has the possibility to independently configure each TCM size with values within the fol-

lowing ranges, [0K Byte, 64K Bytes] for ITCM size and [0K Byte, 64K Bytes] for DTCM size.

TCMs can be configured by two means: HMATRIX TCM register and TCM region register (regis-

ter 9) in CP15 and both steps should be performed. HMATRIX TCM register sets TCM size

whereas TCM region register (register 9) in CP15 maps TCMs and enables them.

The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable

code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to

PC-relative literal pools.

9.8.2 Enabling and Disabling TCMs

Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register.

Then enabling TCMs is performed by using TCM region register (register 9) in CP15. The user

should use the same sizes as those put in HMATRIX TCM register. For further details and pro-

gramming tips, please refer to chapter 2.3 in ARM926EJ-S TRM.

9.8.3 TCM Mapping

The TCMs can be located anywhere in the memory map, with a single region available for ITCM

and a separate region available for DTCM. The TCMs are physically addressed and can be

placed anywhere in physical address space. However, the base address of a TCM must be

aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is per-

formed by using TCM region register (register 9) in CP15. The user should input the right

mapping address for TCMs.

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SAM9G45

9.9 Bus Interface Unit

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB

requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables

parallel access paths between multiple AHB masters and slaves in a system. This is achieved by

using a more complex interconnection matrix and gives the benefit of increased overall bus

bandwidth, and a more flexible system architecture.

The multi-master bus architecture has a number of benefits:

• It allows the development of multi-master systems with an increased bus bandwidth and a

flexible architecture.

• Each AHB layer becomes simple because it only has one master, so no arbitration or master-

to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to

support request and grant, nor do they have to support retry and split transactions.

• The arbitration becomes effective when more than one master wants to access the same

slave simultaneously.

9.9.1 Supported Transfers

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or

bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into

packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not

support split and retry requests.

Table 8 gives an overview of the supported transfers and different kinds of transactions they are

used for.

Table 9-7. Supported Transfers

HBurst[2:0] Description

SINGLE Single transfer

Single transfer of word, half word, or byte:

• Data write (NCNB, NCB, WT, or WB that has missed in DCache)

• Data read (NCNB or NCB)

• NC instruction fetch (prefetched and non-prefetched)

• Page table walk read

INCR4 Four-word incrementing burst Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,

NCB, WT, or WB write.

INCR8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.

WRAP8 Eight-word wrapping burst Cache linefill

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SAM9G45

9.9.2 Thumb Instruction Fetches

All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses

on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.

9.9.3 Address Alignment

The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the

necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses

are aligned to word boundaries.

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SAM9G45

10. SAM9G45 Debug and Test

10.1 Description

The SAM9G45 features a number of complementary debug and test capabilities. A common

JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down-

loading code and single-stepping through programs. The Debug Unit provides a two-pin UART

that can be used to upload an application into internal SRAM. It manages the interrupt handling

of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica-

tion Channel.

A set of dedicated debug and test input/output pins gives direct access to these capabilities from

a PC-based test environment.

10.2 E mbedded Characteristics

• ARM926 Real-time In-circuit Emulator

– Two real-time Watchpoint Units

– Two Independent Registers: Debug Control Register and Debug Status Register

– Test Access Port Accessible through JTAG Protocol

– Debug Communications Channel

• Debug Unit

–Two-pin UART

– Debug Communication Channel Interrupt Handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on All Digital Pins.

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10.3 Block Diagram

Figure 10-1. Debug and Test Block Diagram

ICE-RT

ARM9EJ-S

PDC DBGU

PIO

DRXD

DTXD

TMS

TCK

TDI

JTAGSEL

TST

Reset

and

Test

TAP: Test Access Port

Boundary

Port

ICE/JTAG

TA P

ARM926EJ-S

POR

RTCK

NTRST

TDO

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SAM9G45

10.4 Application Examples

10.4.1 Debug Environment

Figure 10-2 on page 53 shows a complete debug environment example. The ICE/JTAG inter-

face is used for standard debugging functions, such as downloading code and single-stepping

through the program. A software debugger running on a personal computer provides the user

interface for configuring a Trace Port interface utilizing the ICE/JTAG interface.

Figure 10-2. Application Debug and Trace Environment Example

SAM9G45-based Application Board

ICE/JTAG

Interface

Host Debugger PC

ICE/JTAG

Connector

SAM9G45 Terminal

RS232

Connector

6438J–ATARM–10-Aug-12

SAM9G45

10.4.2 Test Environment

Figure 10-3 on page 54 shows a test environment example. Test vectors are sent and inter-

preted by the tester. In this example, the “board in test” is designed using a number of JTAG-

compliant devices. These devices can be connected to form a single scan chain.

Figure 10-3. Application Test Environment Example

10.5 Debug and Test Pin Description

JTAG

Interface

SAM9G45

Test Adaptor

Chip 2Chip n

Chip 1

ICE/JTAG

Tester

SAM9G45-based Application Board In Test

Table 10-1. Debug and Test Pin List

Pin Name Function Type Active Level

Reset/Test

NRST Microcontroller Reset Input/Output Low

TST Test Mode Select Input High

ICE and JTAG

NTRST Test Reset Signal Input Low

TCK Test Clock Input

TDI Test Data In Input

TDO Test Data Out Output

TMS Test Mode Select Input

RTCK Returned Test Clock Output

JTAGSEL JTAG Selection Input

Debug Unit

DRXD Debug Receive Data Input

DTXD Debug Transmit Data Output

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SAM9G45

10.6 Functional Description

10.6.1 Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure

that this pin is tied at low level to ensure normal operating conditions. Other values associated

with this pin are reserved for manufacturing test.

10.6.2 EmbeddedICE

The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a

host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core

embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through

an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core

without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can

be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers.

This data can be serially shifted out without affecting the rest of the system.

There are two scan chains inside the ARM9EJ-S processor which support testing, debugging,

and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG

port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly

between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE-RT, see the ARM document:

ARM9EJ-S Technical Reference Manual (DDI 0222A).

10.6.3 JTAG Signal Description

TMS is the Test Mode Select input which controls the transitions of the test interface state

machine.

TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan

TDO is the Test Data Output line which is used to serially output the data from the JTAG regis-

ters to the equipment controlling the test. It carries the sampled values from the boundary scan

chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit.

NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM

cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a

Power On Reset output. It is asserted on power on. If necessary, the user can also reset the

debug logic with the NTRST pin assertion during 2.5 MCK periods.

TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment

controlling the test and not by the tested device. It can be pulsed at any frequency. Note the

maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45

kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock.

RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock

handling by emulators. From some ICE Interface probes, this return signal can be used to syn-

chronize the TCK clock and take not care about the given ratio between the ICE Interface clock

and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in

boundary scan mode.

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10.6.4 Debug Unit

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several

debug and trace purposes and offers an ideal means for in-situ programming solutions and

debug monitor communication. Moreover, the association with two peripheral data controller

channels permits packet handling of these tasks with processor time reduced to a minimum.

The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals

that come from the ICE and that trace the activity of the Debug Communication Channel.The

Debug Unit allows blockage of access to the system through the ICE interface.

A specific register, the Debug Unit Chip ID Register, gives information about the product version

and its internal configuration.

The SAM9G45 Debug Unit Chip ID value is 0x819B 05A2 and the extended ID is 0x00000004

on 32-bit width.

For further details on the Debug Unit, see the Debug Unit section.

10.6.5 IEEE 1149.1 JTAG Boundary Scan

IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging

technology.

IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST

and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds

with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1

JTAG-compliant.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-

formed after JTAGSEL is changed.

A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.

10.6.6 JID Code Register

Access: Read-only

• VERSION[31:28]: Product Version Number

Set to 0x0.

• PART NUMBER[27:12]: Product Part Number

Product part Number is 5B27

• MANUFACTURER IDENTITY[11:1]

Set to 0x01F.

Bit[0] required by IEEE Std. 1149.1.

Set to 0x1.

JTAG ID Code value is 05B2_703F.

31 30 29 28 27 26 25 24

VERSION PART NUMBER

23 22 21 20 19 18 17 16

PART NUMBER

15 14 13 12 11 10 9 8

PART NUMBER MANUFACTURER IDENTITY

76543210

MANUFACTURER IDENTITY 1

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SAM9G45

11. Boot Strategies

The system always boots at address 0x0. To ensure maximum boot possibilities the memory

layout can be changed with two parameters.

• REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development.

This is done by software once the system has boot.

• BMS allows the user to layout to 0x0, when convenient, the ROM or an external memory. This

is done by hardware at reset.

Note: All the memory blocks can always be seen at their specified base addresses that are not

concerned by these parameters.

The SAM9G45 manages a boot memory that depends on the level on the BMS pin at reset. The

internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.

If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the

External Bus Interface.

• Boot on on-chip RC

• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit

data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.

For optimization purpose, nothing else is done. To speed up the boot sequence user pro-

grammed software should perform a complete configuration:

• Enable the 32768 Hz oscillator if best accuracy is needed

• Program the PMC (main oscillator enable or bypass mode)

• Program and Start the PLL

• Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to

the new clock

• Switch the system clock to the new value

If BMS is detected at 1, the boot memory is the embedded ROM and the boot program

described below is executed.

11.1 Boot Program

The Boot Program is contained in the embedded ROM. It is also called: “Rom Code” or “First

level bootloader”. At power on, if the BMS pin is detected at 1, the boot memory is the embed-

ded ROM and the Boot Program is executed.

The Boot Program consists of several steps. First, it performs device initialization. Then it

attempts to boot from external non volatile memories (NVM). And finally, if no valid program is

found in NVM, it executes a monitor called SAM-BA® Monitor.

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SAM9G45

11.2 Flow Diagram

The Boot Program implements the algorithm shown below in Figure 11-1.

Figure 11-1. Boot Program Algorithm Flow Diagram

SAM-BA Monitor

Co p y an d ru n i t

in internal SRAM

Ye s

Device Setup

Valid boot code

found in one

NVM

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SAM9G45

11.3 Device Initialization

11.3.1 Clock at Start Up

At boot start up, the processor clock (PCK) and the master clock (MCK) are found on the slow

clock. The slow clock can be an external 32 kHz crystal oscillator or the internal RC oscillator. By

default the slow clock is the internal RC oscillator. Its frequency is not precise and is between 20

kHz and 40 kHz. Its start up is much faster than an external 32 kHz quartz. If a battery supplies

the backup power and if the external 32 kHz clock was previously started up and selected, the

slow clock at boot is the external 32 kHz quartz oscillator. Refer to the Slow Clock Crystal Oscil-

lator description in the Clock Generator section of the datasheet.

11.3.2 Initialization Sequence

Initialization follows the steps described below:

1. Stack setup for ARM supervisor mode.

2. Main Oscillator Detection: (External crystal or external clock on XIN). The Main Oscil-

lator is disabled at startup (MOSCEN = 0). First it is bypassed (OSCBYPASS set at 1).

Then the MAINRDY bit is polled. Since this bit is raised, the Main Clock Frequency field

is analyzed (MAINF). If the value is bigger than 16, an external clock connected on XIN

is detected. If not, an external quartz connected between XIN and XOUT (whose fre-

quency is unknown at this moment) is detected.

3. Main Oscil lator Enabling: if an external clock is connected on XIN, the Main Oscillator

does not need to be started. Otherwise, the OSCBYPASS bit is not set. The Main Oscil-

lator is enabled (MOSCEN = 1) with the maximum start-up time and the MOSC bit is

polled to wait for stabilization.

4. Main Oscillator Selection: the Master Clock source is switched from Slow Clock to the

Main Oscillator without prescaler. The PMC Status Register is polled to wait for MCK

Ready. PCK and MCK are now the Main Oscillator clock.

5. C variable initialization: non zero-initialized data are initialized in RAM (copy from

ROM to RAM). Zero-initialized data are set to 0 in RAM.

6. PLLA initia lization: PLLA is configured to allow communication on the USB link for the

SAM-BA Monitor. Its configuration depends on the Main Oscillator source (external

clock or crystal) and on its frequency.

Table 11-1. External Clock and Crystal Frequencies allowed for Boot Sequence (in MHz)

Description 4 12 28 Other

Boot on External Memories Yes Yes Yes No

SAM-BA Monitor through DBGU Yes Yes Yes No

SAM-BA Monitor through USB No Yes No No

6438J–ATARM–10-Aug-12

SAM9G45

11.4 NVM Boot

11.4.1 NVM Bootloader Program Description

Figure 11-2. NVM bootloader program diagram

En d

Valid code detection in NVM

Ye s

Copy the valid code

from external NVM to internal SRAM.

Rest ore t he reset values for t he peripherals.

Perform the REMAP and set the PC to 0

to jump to the downloaded application

Initialize NVM

NVM contains valid code

Ye s

St ar t

Initialization OK ? Restore t he reset values

for the peripherals and

Jump to next boot solution

6438J–ATARM–10-Aug-12

SAM9G45

Figure 11-3. Remap Action after Download Completion

The NVM bootloader program initializes the NVM. It initializes the required PIO. It sets the right

peripheral depending on the NVM and tries to access the memory. If the initialization fails, it

restores the reset values for the PIO and peripherals and then the next NVM bootloader program

is executed.

If the initialization is successful, the NVM bootloader program reads the beginning of the NVM

and determines if the NVM contains valid code.

If the NVM does not contain valid code, the NVM bootloader program restores the reset value for

the peripherals and then the next NVM bootloader program is executed.

If valid code is found, this code is loaded from NVM into internal SRAM and executed by branch-

ing at address 0x0000_0000 after remap. This code may be the application code or a second-

level bootloader. All the calls to functions are PC relative and do not use absolute addresses.

11.4.2 Valid Code Detection

There are two kinds of valid code detection. Depending on the NVM bootloader, either one or

both of them is used.

11.4.2.1 ARM Exception Vectors Check

The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first

seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM

instructions for either branch or load PC with PC relative addressing.

Figure 11-4. LDR Opcode

REM A P

Internal

ROM

Internal

SRAM

0x0030_0000

0x0000_0000

Internal

ROM

0x0040_0000

Internal

SRAM

Internal

SRAM

0x0030_000

0x0000_000

Internal

ROM

0x0040_000

31 28 27 24 23 20 19 16 15 12 11 0

111001 I PU1W0 Rn Rd Oset

6438J–ATARM–10-Aug-12

SAM9G45

Figure 11-5. B Opcode

Unconditional instruction: 0xE for bits 31 to 28

Load PC with PC relative addressing instruction:

– Rn = Rd = PC = 0xF

– I==0 (12-bit immediate value)

– P==1 (pre-indexed)

– U offset added (U==1) or subtracted (U==0)

–W==1

The sixth vector, at offset 0x14, contains the size of the image to download. The user must

replace this vector with his/her own vector. This information is described below.

Figure 11-6. Structure of the ARM Vector 6

The value has to be smaller than 60 Kbytes. 60 Kbytes is the maximum size for a valid code.

This size is the internal SRAM size minus the stack size used by the ROM Code at the end of

the internal SRAM.

Example

An example of valid vectors follows:

00 ea000006 B 0x20

04 eafffffe B 0x04

08 ea00002f B _main

0c eafffffe B 0x0c

10 eafffffe B 0x10

14 00001234 B 0x14 <- Code size = 4660 bytes < 60 Kbytes

18 eafffffe B 0x18

11.4.2.2 boot.bin file check

The NVM bootloader program looks for a boot.bin file in the root directory of a FAT12/16/32 for-

matted NVM Flash.

31 28 27 24 23 0

11101010 Oset (24 bits)

31 0

Size of t he code t o download in byt es

6438J–ATARM–10-Aug-12

SAM9G45

11.4.3 NVM Bootloader Sequence

Figure 11-7. NVM Bootloader Sequence Diagram

11.4.3.1 NAND Flash Boot

The NAND Flash bootloader program uses the EBI CS3. It uses both valid code detections. First

it searches a boot.bin file. Then it analyzes the ARM exception vectors.

The first block must be guaranteed by the manufacturer. There is no ECC check.

After NAND Flash interface configuration, the Manufacturer ID is read. If it is different from 0xFF,

the Device ID is read, else, the NAND Flash boot is aborted. The Boot program contains a list of

SLC small block Device ID with their characteristics (size, bus width, voltage) (see Table 11-2). If

the device ID is not found in this list, the NAND Flash device is considered as an SLC large block

and its characteristics are obtained by reading the Extended Device ID byte 3.

SPI Flash Boot Ye s

TWI EEPROM Boot Ye s

NAND Flash Boot Copy from

NAND Flash to SRAM Run

Ye s NAND Flash Bootloader

SD Card Boot Copy from

SD Card to SRAM Run

Ye s SD Card Bootloader

Device

Setup

SAM-BA

Monitor

Copy from

SPI Flash to SRAM

Copy from

TWI EEPROM to SRAM

SPI Flash Bootloader

TWI EEPROM Bootloader

Run

6438J–ATARM–10-Aug-12

SAM9G45

Supported NAND Flash Devices

The supported SLC small block NAND Flash devices that are described below inTable 11-2.

The NAND Flash boot also supports all the SLC large block NAND Flash devices.

11.4.3.2 SD Card Boot

The SD Card bootloader uses MCI0. It uses only one valid code detection. It searches a boot.bin

file.

Supported SD Card devices

SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification

V2.0. This includes SDHC cards.

Table 11-2. Supported SLC Small Block NAND Flash

Device ID Size

(MBytes) PageSize

(Bytes) BlockSsize

(Bytes) Bus Width Voltage (V)

0x6E 1 256 4096 8 5

0x64 2 256 4096 8 5

0x6B 4 512 8196 8 5

0xE8 1 256 4096 8 3.3

0xEC 1 256 4096 8 3.3

0xEA 2 256 4096 8 3.3

0xE3 4 512 8196 8 3.3

0xE5 4 512 8196 8 3.3

0xD6 8 512 8196 8 3.3

0xE6 8 512 8196 8 3.3

0x33 16 512 16384 8 1.8

0x73 16 512 16384 8 3.3

0x43 16 512 16384 16 1.8

0x53 16 512 16384 16 3.3

0x45 32 512 16384 16 1.8

0x55 32 512 16384 16 3.3

0x36 64 512 16384 8 1.8

0x76 64 512 16384 8 3.3

0x46 64 512 16384 16 1.8

0x56 64 512 16384 16 3.3

0x78 128 512 16384 8 1.8

0x79 128 512 16384 8 3.3

0x72 128 512 16384 16 1.8

0x74 128 512 16384 16 3.3

6438J–ATARM–10-Aug-12

SAM9G45

11.4.3.3 SPI Flash Boot

Two kinds of SPI Flash are supported, SPI Serial Flash and SPI DataFlash.

The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial flash,

and then for SPI DataFlash.

It uses only one valid code detection: analysis of ARM exception vectors.

The SPI Flash read is done thanks to a Continuous Read command from address 0x0. This

command is 0xE8 for DataFlash and 0x0B for Serial Flash devices.

Supported DataFlash Devices

The SPI Flash Boot program supports all Atmel DataFlash devices.

Supported Serial Fla sh Devices

The SPI Flash Boot program supports all Serial Flash devices.

11.4.3.4 TWI EEPROM Boot

The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes

the ARM exception vectors.

Supported TWI EEPROM Devices

TWI EEPROM Boot supports all I2C-compatible TWI EEPROM memories using 7 bits device

address 0x50.

11.4.4 Hardware and Software Constraints

The NVM drivers use several PIOs in peripheral mode to communicate with devices. Care must

be taken when these PIOs are used by the application. The devices connected could be unin-

tentionally driven at boot time, and electrical conflicts between output pins used by the NVM

drivers and the connected devices may occur.

To assure correct functionality, it is recommended to plug in critical devices to other pins not

used by NVM.

Table 11-4 contains a list of pins that are driven during the boot program execution. These pins

are driven during the boot sequence for a period of less than 1 second if no correct boot program

is found.

Table 11-3. DataFlash Device

Device Density Page Size (bytes) Number of Pages

AT45DB011 1 Mbit 264 512

AT45DB021 2 Mbits 264 1024

AT45DB041 4 Mbits 264 2048

AT45DB081 8 Mbits 264 4096

AT45DB161 16 Mbits 528 4096

AT45DB321 32 Mbits 528 8192

AT45DB642 64 Mbits 1056 8192

6438J–ATARM–10-Aug-12

SAM9G45

Before performing the jump to the application in internal SRAM, all the PIOs and peripherals

used in the boot program are set to their reset state.

11.5 SAM-BA Monitor

If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA

Monitor program is launched.

The SAM-BA Monitor principle is to:

– Initialize DBGU and USB

– Check if USB Device enumeration has occurred.

– Check if characters have been received on the DBGU.

– Once the communication interface is identified, the application runs in an infinite

loop waiting for different commands as listed in Table .

Table 11-4. PIO Driven during Boot Program Execution

NVM Bootloader Peripheral Pin PIO Line

NAND

EBI CS3 SMC NANDCS PIOC14

EBI CS3 SMC NAND ALE A21

EBI CS3 SMC NAND CLE A22

EBI CS3 SMC Cmd/Addr/Data D[16:0]

SD Card

MCI0 MCI0_CK PIOA0

MCI0 MCI0_CD PIOA1

MCI0 MCI0_D0 PIOA2

MCI0 MCI0_D1 PIOA3

MCI0 MCI0_D2 PIOA4

MCI0 MCI0_D3 PIOA5

SPI Flash

SPI0 MOSI PIOB1

SPI0 MISO PIOB0

SPI0 SPCK PIOB2

SPI0 NPCS0 PIOB3

TWI0 EEPROM TWI0 TWD0 PIOA20

TWI0 TWCK0 PIOA21

SAM-BA Monitor DBGU DRXD PIOB12

DBGU DTXD PIOB13

6438J–ATARM–10-Aug-12

SAM9G45

Figure 11-8. SAM-BA Monitor Diagram

11.5.1 Command Li st

• Mode commands:

– Normal mode configures SAM-BA Monitor to send / receive data in binary format,

– Terminal mode configures SAM-BA Monitor to send / receive data in ascii format.

• Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.

–Address: Address in hexadecimal.

–Value: Byte, halfword or word to write in hexadecimal.

–Output: ‘>’.

Charact er(s) received

on DBGU ?

Run monitor

Wait for command

on the USB link

Run monitor

Wait for command

on the DBGU link

USB Enumerat ion

Successful ?

Ye s Ye s

Init DBGU and USB

No valid code in NVM

Table 11-5. Commands Available through the SAM-BA Monitor

Command Action Argument(s) Example

NSet normal mode No argument N#

TSet terminal mode No argument T#

OWrite a byte Address, Value# O200001,CA#

oRead a byte Address,# o200001,#

HWrite a half word Address, Value# H200002,CAFE#

hRead a half word Address,# h200002,#

WWrite a word Address, Value# W200000,CAFEDECA#

wRead a word Address,# w200000,#

SSend a file Address,# S200000,#

RReceive a file Address, NbOfBytes# R200000,1234#

GGo Address# G200200#

VDisplay version No argument V#

6438J–ATARM–10-Aug-12

SAM9G45

• Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.

–Address: Address in hexadecimal

–Output: The byte, halfword or word read in hexadecimal following by ‘>’

• Send a file (S): Send a file to a specified address

–Address: Address in hexadecimal

–Output: ‘>’.

Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the

end of the command execution.

• Receive a file (R): Receive data into a file from a specified address

–Address: Address in hexadecimal

–NbOfBytes: Number of bytes in hexadecimal to receive

–Output: ‘>’

•Go (G): Jump to a specified address and execute the code

–Address: Address to jump in hexadecimal

–Output: ‘>’once returned from the program execution. If the executed program does

not handle the link register at its entry and does not return, the prompt will not be

displayed.

• Get Version (V): Return the Boot Program version

–Output: version, date and time of ROM code followed by the prompt: ‘>’.

11.5.2 DBGU Serial Port

Communication is performed through the DBGU serial port initialized to 115200 Baud, 8 bits of

data, no parity, 1 stop bit.

11.5.2.1 Supported External Crystal/External Clocks

The SAM-BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both

external crystal and external clock.

11.5.2.2 Xmodem Protocol

The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal

performing this protocol can be used to send the application file to the target. The size of the

binary file to send depends on the SRAM size embedded in the product. In all cases, the size of

the binary file must be lower than the SRAM size because the Xmodem protocol requires some

SRAM memory in order to work.

The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-charac-

ter CRC-16 to guarantee detection of a maximum bit error.

Xmodem protocol with CRC is accurate provided both sender and receiver report successful

transmission. Each block of the transfer looks like:

<SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:

– <SOH> = 01 hex

– <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not

to 01)

– <255-blk #> = 1’s complement of the blk#.

– <checksum> = 2 bytes CRC16

6438J–ATARM–10-Aug-12

SAM9G45

Figure 11-9 shows a transmission using this protocol.

Figure 11-9. Xmodem Transfer Example

11.5.3 USB Device Port

11.5.3.1 Supporte d extern al crystal / ex te rnal clo cks

The only frequency supported by SAM-BA Monitor to allow USB communication is a 12 MHz

crystal or external clock.

11.5.3.2 USB class

The device uses the USB communication device class (CDC) drivers to take advantage of the

installed PC RS-232 software to talk over the USB. The CDC class is implemented in all

releases of Windows®, from Windows 98SE® to Windows XP®. The CDC document, available at

www.usb.org, describes how to implement devices such as ISDN modems and virtual COM

ports.

The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are

used by the host operating system to mount the correct driver. On Windows systems, the INF

files contain the correspondence between vendor ID and product ID.

11.5.3.3 Enumeration Process

The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests

to the device through the control endpoint. The device handles standard requests as defined in

the USB Specification.

Host Device

SOH 01 FE Data[128] CRC CRC

ACK

SOH 02 FD Dat a[128] CRC CRC

ACK

SOH 03 FC Data[100] CRC CRC

ACK

EOT

ACK

Table 11-6. Handled Standard Requests

Request Definition

GET_DESCRIPTOR Returns the current device configuration value.

SET_ADDRESS Sets the device address for all future device access.

SET_CONFIGURATION Sets the device configuration.

6438J–ATARM–10-Aug-12

SAM9G45

The device also handles some class requests defined in the CDC class.

Unhandled requests are STALLed.

11.5.3.4 Communication Endpoints

There are two communication endpoints and endpoint 0 is used for the enumeration process.

Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-

BA Boot commands are sent by the host through endpoint 1. If required, the message is split by

the host into several data payloads by the host driver.

If the command requires a response, the host can send IN transactions to pick up the response.

GET_CONFIGURATION Returns the current device configuration value.

GET_STATUS Returns status for the specified recipient.

SET_FEATURE Used to set or enable a specific feature.

CLEAR_FEATURE Used to clear or disable a specific feature.

Table 11-7. Handled Class Requests

Request Definition

SET_LINE_CODING Configures DTE rate, stop bits, parity and number of

character bits.

GET_LINE_CODING Requests current DTE rate, stop bits, parity and number

of character bits.

SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE

device is now present.

Table 11-6. Handled Standard Requests (Continued)

Request Definition

6438J–ATARM–10-Aug-12

SAM9G45

12. Reset Controller (RSTC)

12.1 Description

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys-

tem without any external components. It reports which reset occurred last.

The Reset Controller also drives independently or simultaneously the external reset and the

peripheral and processor resets.

12.2 E mbedded Characteristics

The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on

VDDCORE.

The Reset Controller is capable to return to the software the source of the last reset, either a

general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user

reset or a watchdog reset.

The Reset Controller controls the internal resets of the system and the NRST pin. The NRST pin

is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a

reset signal to the external components or asserted low externally to reset the microcontroller. It

will reset the Core and the peripherals except the Backup region. There is no constraint on the

length of the reset pulse and the reset controller can guarantee a minimum pulse length.

The NRST pin integrates a permanent pull-up resistor to VDDIOP0 of about 100 kΩ. NRST is an

open drain output.

The configuration of the Reset Controller is saved as supplied on VDDBU.

6438J–ATARM–10-Aug-12

SAM9G45

12.3 Block Diagram

Figure 12-1. Reset Controller Block Diagram

NRST

Startup

Counter

proc_nreset

wd_fault

periph_nreset

backup_neset

SLCK

Reset

State

Manager

Reset Controller

rstc_irq

NRST

Manager

exter_nreset

nrst_out

Main Supply

POR

WDRPROC

user_reset

Backup Supply

POR

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12.4 Functional Description

12.4.1 Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State

Manager. It runs at Slow Clock and generates the following reset signals:

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.

• backup_nreset: Affects all the peripherals powered by VDDBU.

• periph_nreset: Affects the whole set of embedded peripherals.

• nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on soft-

ware action. The Reset State Manager controls the generation of reset signals and provides a

signal to the NRST Manager when an assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling

external device resets.

The startup counter waits for the complete crystal oscillator startup. The wait delay is given by

the crystal oscillator startup time maximum value that can be found in the section Crystal Oscil-

lator Characteristics in the Electrical Characteristics section of the product documentation.

The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con-

troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.

12.4.2 NRST Ma nage r

The NRST Manager samples the NRST input pin and drives this pin low when required by the

Reset State Manager. Figure 12-2 shows the block diagram of the NRST Manager.

Figure 12-2. NRST Manager

12.4.2.1 NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low,

a User Reset is reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of

NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

External Reset Timer

URSTS

URSTEN

ERSTL

exter_nreset

URSTIEN

RSTC_MR

RSTC_SR

NRSTL

nrst_out

NRST

rstc_irq

Other

interrupt

sources

user_reset

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SAM9G45

The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.

As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only

when RSTC_SR is read.

The Reset Controller can also be programmed to generate an interrupt instead of generating a

reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.

12.4.2.2 NRST External Reset Contr o l

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this

occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the

field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts

2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs

and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.

This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that

the NRST line is driven low for a time compliant with potential external devices connected on the

system reset.

As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system

power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.

12.4.3 BMS Sampling

The product matrix manages a boot memory that depends on the level on the BMS pin at reset.

The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising

edge.

Figure 12-3. BMS Sampling

12.4.4 Reset States

The Reset State Manager handles the different reset sources and generates the internal reset

signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The

update of the field RSTTYP is performed when the processor reset is released.

12.4.4.1 General Reset

A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR

cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The pur-

pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the

SLCK

Core Supply

POR output

BMS sampling delay

= 3 cycles

BMS Signal

proc_nreset

XXX H or L

6438J–ATARM–10-Aug-12

SAM9G45

device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup

time.

After this time, the processor clock is released at Slow Clock and all the other signals remain

valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released

and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the

NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.

When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immedi-

ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown.

VDDBU only activates the backup_nreset signal.

The backup_nreset must be released so that any other reset can be generated by VDDCORE

(Main Supply POR output).

Figure 12-4 shows how the General Reset affects the reset signals.

Figure 12-4. General Reset State

SLCK

periph_nreset

proc_nreset

Backup Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles

Startup Time

MCK

Processor Startup

= 3 cycles

backup_nreset

Any

Freq.

RSTTYP XXX 0x0 = General Reset XXX

Main Supply

POR output

BMS Sampling

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12.4.4.2 Wake-up Reset

The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output

is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow-

ers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled

during 3 Slow Clock cycles, depending on the requirements of the ARM processor.

At the end of this delay, the processor and other reset signals rise. The field RSTTYP in

RSTC_SR is updated to report a Wake-up Reset.

The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is

backed-up, the programmed number of cycles is applicable.

When the Main Supply is detected falling, the reset signals are immediately asserted. This tran-

sition is synchronous with the output of the Main Supply POR.

Figure 12-5. Wake-up State

12.4.4.3 User Reset

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in

RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behav-

ior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset

and the Peripheral Reset are asserted.

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle

processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.

SLCK

periph_nreset

proc_nreset

Main Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 4 cycles (ERSTL = 1)

MCK

Processor Startup

= 3 cycles

backup_nreset

Any

Freq.

Resynch.

2 cycles

RSTTYP XXX 0x1 = WakeUp Reset XXX

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When the processor reset signal is released, the RSTTYP field of the Status Register

(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for

EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-

ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low

externally, the internal reset lines remain asserted until NRST actually rises.

Figure 12-6. User Reset State

12.4.4.4 Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These

commands are performed by writing the Control Register (RSTC_CR) with the following bits

at 1:

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.

• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory

system, and, in particular, the Remap Command. The Peripheral Reset is generally used for

debug purposes.

Except for Debug purposes, PERRST must always be used in conjunction with PROCRST

(PERRST and PROCRST set both at 1 simultaneously.)

• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field

ERSTL in the Mode Register (RSTC_MR).

The software reset is entered if at least one of these bits is set by the software. All these com-

mands can be performed independently or simultaneously. The software reset lasts 3 Slow

Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is

detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn-

chronously to SLCK.

SLCK

periph_nreset

proc_nreset

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup

= 3 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP Any XXX

Resynch.

2 cycles

0x4 = User Reset

6438J–ATARM–10-Aug-12

SAM9G45

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field

ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field

RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in

RSTTYP.

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog-

ress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left.

No other software reset can be performed while the SRCMP bit is set, and writing any value in

RSTC_CR has no effect.

Figure 12-7. Software Reset

12.4.4.5 Watchd o g Res et

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock

cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in

WDT_MR:

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST

line is also asserted, depending on the programming of the field ERSTL. However, the

resulting low level on NRST does not result in a User Reset state.

• If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a

processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog

Reset, and the Watchdog is enabled by default and with a period set to a maximum.

SLCK

periph_nreset

if PERRST=1

proc_nreset

if PROCRST=1

Write RSTC_CR

NRST

(nrst_out)

if EXTRST=1 EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP Any XXX 0x3 = Software Reset

Resynch.

1 cycle

SRCMP in RSTC_SR

6438J–ATARM–10-Aug-12

SAM9G45

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset

controller.

Figure 12-8. Watchdog Reset

12.4.5 Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources,

given in descending order:

• Backup Reset

• Wake-up Reset

• Watchdog Reset

• Software Reset

• User Reset

Particular cases are listed below:

• When in User Reset:

– A watchdog event is impossible because the Watchdog Timer is being reset by the

proc_nreset signal.

– A software reset is impossible, since the processor reset is being activated.

• When in Software Reset:

– A watchdog event has priority over the current state.

– The NRST has no effect.

• When in Watchdog Reset:

– The processor reset is active and so a Software Reset cannot be programmed.

– A User Reset cannot be entered.

Only if

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP Any XXX 0x2 = Watchdog Reset

6438J–ATARM–10-Aug-12

SAM9G45

12.4.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.

• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no

further software reset should be performed until the end of the current one. This bit is

automatically cleared at the end of the current software reset.

• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on

each MCK rising edge.

• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR

12-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the

URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the

RSTC_SR status register resets the URSTS bit and clears the interrupt.

Figure 12-9. Reset Controller Status and Interrupt

MCK

NRST

NRSTL

2 cycle

resynchronization 2 cycle

resynchronization

URSTS

read

RSTC_SR

Peripheral Access

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)

6438J–ATARM–10-Aug-12

SAM9G45

12.5 Reset Controller (RSTC) User Interface

Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.

Table 12-1. Register Mapping

Offset Register Name Access Reset Backup Reset

0x00 Control Register RSTC_CR Write-only -

0x04 Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000

0x08 Mode Register RSTC_MR Read-write - 0x0000_0001

6438J–ATARM–10-Aug-12

SAM9G45

12.5.1 Reset Contr oller Control Register

Name: RSTC_CR

Address: 0xFFFFFD00

Access Type: Write-only

• PROCRST: Processor Reset

0 = No effect.

1 = If KEY is correct, resets the processor.

• PERRST: Peri phe r al Rese t

0 = No effect.

1 = If KEY is correct, resets the peripherals.

• EXTRST: External Reset

0 = No effect.

1 = If KEY is correct, asserts the NRST pin.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––– –

76543210

––––EXTRSTPERRST–PROCRST

6438J–ATARM–10-Aug-12

SAM9G45

12.5.2 Reset Controller Status Register

Name: RSTC_SR

Address: 0xFFFFFD04

Access Type: Read-only

• URSTS: User Reset Status

0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.

1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

• RSTTYP: Reset Type

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.

• NRSTL: NRST Pin Level

Registers the NRST Pin Level at Master Clock (MCK).

• SRCMP: Software Reset Command in Progress

0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.

1 = A software reset command is being performed by the reset controller. The reset controller is busy.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––SRCMPNRSTL

15 14 13 12 11 10 9 8

––––– RSTTYP

76543210

–––––––URSTS

RSTTYP Reset Type Comments

0 0 0 General Reset Both VDDCORE and VDDBU rising

0 0 1 Wake Up Reset VDDCORE rising

0 1 0 Watchdog Reset Watchdog fault occurred

0 1 1 Software Reset Processor reset required by the software

1 0 0 User Reset NRST pin detected low

6438J–ATARM–10-Aug-12

SAM9G45

12.5.3 Reset Controller Mode Register

Name: RSTC_MR

Address: 0xFFFFFD08

Access Type: Read-write

• URSTEN: User Reset Enable

0 = The detection of a low level on the pin NRST does not generate a User Reset.

1 = The detection of a low level on the pin NRST triggers a User Reset.

• URSTIEN: User Reset Interrupt Enable

0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.

1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

• ERSTL: External Reset Length

This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This

allows assertion duration to be programmed between 60 µs and 2 seconds.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

–––––––

15 14 13 12 11 10 9 8

–––– ERSTL

76543210

– – URSTIEN – – – URSTEN

6438J–ATARM–10-Aug-12

SAM9G45

13. Real-time Timer (RTT)

13.1 Description

The Real-time Timer (RTT) is built around a 32-bit counter and used to count elapsed seconds.

It generates a periodic interrupt and/or triggers an alarm on a programmed value.

13.2 E mbedded Characteristics

• Real-Time Timer, allowing backup of time with different accuracies

– 32-bit Free-running back-up Counter

– Integrates a 16-bit programmable prescaler running on slow clock

– Alarm Register capable to generate a wake-up of the system through the Shut Down

Controller

13.3 Block Diagram

Figure 13-1. Real-time Timer

13.4 Functional Description

The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by

Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field

RTPRES of the Real-time Mode Register (RTT_MR).

Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz

signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corre-

sponding to more than 136 years, then roll over to 0.

SLCK

RTPRES

RTTINC

ALMS

16-bit

Divider

32-bit

Counter

ALMV

CRTV

RTT_MR

RTT_VR

RTT_AR

RTT_SR

RTTINCIEN

RTT_MR

ALMIEN

rtt_int

RTT_MR

set

RTT_SR

read

RTT_SR

reset

RTT_MR

reload

rtt_alarm

RTTRST

RTT_MR

RTTRST

6438J–ATARM–10-Aug-12

SAM9G45

The Real-time Timer can also be used as a free-running timer with a lower time-base. The best

accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but

may result in losing status events because the status register is cleared two Slow Clock cycles

after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow

Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the

interrupt must be disabled in the interrupt handler and re-enabled when the status register is

clear.

The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time

Value Register). As this value can be updated asynchronously from the Master Clock, it is advis-

able to read this register twice at the same value to improve accuracy of the returned value.

The current value of the counter is compared with the value written in the alarm register

RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in

RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF,

after a reset.

The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit

can be used to start a periodic interrupt, the period being one second when the RTPRES is pro-

grammed with 0x8000 and Slow Clock equal to 32.768 Hz.

Reading the RTT_SR status register resets the RTTINC and ALMS fields.

Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the

new programmed value. This also resets the 32-bit counter.

Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):

1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2

slow clock cycles after the write of the RTTRST bit in the RTT_MR register.

2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the

RTT_SR (Status Register).

6438J–ATARM–10-Aug-12

SAM9G45

Figure 13-2. RTT Counting

Prescaler

ALMVALMV-10 ALMV+1

RTPRES - 1

RTT

APB cycle

read RTT_SR

ALMS (RTT_SR)

APB Interface

SCLK

RTTINC (RTT_SR)

ALMV+2 ALMV+3

...

APB cycle

6438J–ATARM–10-Aug-12

SAM9G45

13.5 R eal-time Timer (RTT) User Interface

Table 13-1. Register Mapping

Offset Register Name Access Reset

0x00 Mode Register RTT_MR Read-write 0x0000_8000

0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF

0x08 Value Register RTT_VR Read-only 0x0000_0000

0x0C Status Register RTT_SR Read-only 0x0000_0000

6438J–ATARM–10-Aug-12

SAM9G45

13.5.1 Real-time Timer Mode Register

Address: 0xFFFFFD20

Access Type: Read/Write

• RTPRES: Real -time Timer Prescaler Value

Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:

RTPRES = 0: The prescaler period is equal to 216.

RTPRES ≠ 0: The prescaler period is equal to RTPRES.

• ALMIEN: Alarm Interrupt Enable

0 = The bit ALMS in RTT_SR has no effect on interrupt.

1 = The bit ALMS in RTT_SR asserts interrupt.

• RTTINCIEN: Real-time Timer Increment Interrupt Enable

0 = The bit RTTINC in RTT_SR has no effect on interrupt.

1 = The bit RTTINC in RTT_SR asserts interrupt.

• RTTRST: Real-time Timer Restart

1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––RTTRSTRTTINCIENALMIEN

15 14 13 12 11 10 9 8

RTPRES

76543210

RTPRES

6438J–ATARM–10-Aug-12

SAM9G45

13.5.2 Real-time Timer Alarm Register

Address: 0xFFFFFD24

Access Type: Read/Write

• ALMV: Alarm Value

Defines the alarm value (ALMV+1) compared with the Real-time Timer.

13.5.3 Real-time Timer Value Register

Address: 0xFFFFFD28

Access Type: Read-only

• CRTV: Current Real-time Value

Returns the current value of the Real-time Timer.

31 30 29 28 27 26 25 24

ALMV

23 22 21 20 19 18 17 16

ALMV

15 14 13 12 11 10 9 8

ALMV

76543210

ALMV

31 30 29 28 27 26 25 24

CRTV

23 22 21 20 19 18 17 16

CRTV

15 14 13 12 11 10 9 8

CRTV

76543210

CRTV

6438J–ATARM–10-Aug-12

SAM9G45

13.5.4 Real-time Timer Status Regi ster

Address: 0xFFFFFD2C

Access Type: Read-only

• ALMS: Real-time Ala rm Statu s

0 = The Real-time Alarm has not occurred since the last read of RTT_SR.

1 = The Real-time Alarm occurred since the last read of RTT_SR.

• RTTINC: Real-time Timer Increment

0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.

1 = The Real-time Timer has been incremented since the last read of the RTT_SR.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––RTTINCALMS

6438J–ATARM–10-Aug-12

SAM9G45

6438J–ATARM–10-Aug-12

SAM9G45

14. Real-time Clock (RTC)

14.1 Description

The Real-time Clock (RTC) peripheral is designed for very low power consumption.

It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calen-

dar, complemented by a programmable periodic interrupt. The alarm and calendar registers are

accessed by a 32-bit data bus.

The time and calendar values are coded in binary-coded decimal (BCD) format. The time format

can be 24-hour mode or 12-hour mode with an AM/PM indicator.

Updating time and calendar fields and configuring the alarm fields are performed by a parallel

capture on the 32-bit data bus. An entry control is performed to avoid loading registers with

incompatible BCD format data or with an incompatible date according to the current

month/year/century.

14.2 E mbedded Characteristics

• Low power consumption

• Full asynchronous design

• Two hundred year calendar

• Programmable Periodic Interrupt

• Alarm and update parallel load

• Control of alarm and update Time/Calendar Data In

6438J–ATARM–10-Aug-12

SAM9G45

14.3 Block Diagram

Figure 14-1. RTC Block Diagram

Bus Interface

32768 Divider Time

Crystal Oscillator: SLCK

Bus Interface

Date

RTC Interrupt

Entry

Control

Interrupt

Control

6438J–ATARM–10-Aug-12

SAM9G45

14.4 Product Dependencies

14.4.1 Power Management

The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller

has no effect on RTC behavior.

14.4.2 Interrupt

The RTC Interrupt is connected to interrupt source 1 (IRQ1) of the advanced interrupt controller.

This interrupt line is due to the OR-wiring of the system peripheral interrupt lines (System Timer,

Real Time Clock, Power Management Controller, Memory Controller, etc.). When a system

interrupt occurs, the service routine must first determine the cause of the interrupt. This is done

by reading the status registers of the above system peripherals successively.

14.5 Functional Description

The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year

(with leap years), month, date, day, hours, minutes and seconds.

The valid year range is 1900 to 2099, a two-hundred-year Gregorian calendar achieving full Y2K

compliance.

The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.

Corrections for leap years are included (all years divisible by 4 being leap years, including year

2000). This is correct up to the year 2099.

After a general reset (a backup reset), the calendar is initialized to Thursday, January 1, 1998.

14.5.1 Reference Clock

The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768

kHz crystal.

During low power modes of the processor (idle mode), the oscillator runs and power consump-

tion is critical. The crystal selection has to take into account the current consumption for power

saving and the frequency drift due to temperature effect on the circuit for time accuracy.

14.5.2 Timing

The RTC is updated in real time at one-second intervals in normal mode for the counters of sec-

onds, at one-minute intervals for the counter of minutes and so on.

Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain

that the value read in the RTC registers (century, year, month, date, day, hours, minutes, sec-

onds) are valid and stable, it is necessary to read these registers twice. If the data is the same

both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are

required.

14.5.3 Alarm

The RTC has five programmable fields: month, date, hours, minutes and seconds.

Each of these fields can be enabled or disabled to match the alarm condition:

• If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted

and an interrupt generated if enabled) at a given month, date, hour/minute/second.

• If only the “seconds” field is enabled, then an alarm is generated every minute.

6438J–ATARM–10-Aug-12

SAM9G45

Depending on the combination of fields enabled, a large number of possibilities are available to

the user ranging from minutes to 365/366 days.

14.5.4 Error Checking

Verification on user interface data is performed when accessing the century, year, month, date,

day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as

illegal date of the month with regard to the year and century configured.

If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is

set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable

value is programmed. This avoids any further side effects in the hardware. The same procedure

is done for the alarm.

The following checks are performed:

1. Century (check if it is in range 19 - 20)

2. Year (BCD entry check)

3. Date (check range 01 - 31)

4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”)

5. Day (check range 1 - 7)

6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is

not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 - 12)

7. Minute (check BCD and range 00 - 59)

8. Second (check BCD and range 00 - 59)

Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro-

grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The

entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine

the range to be checked.

14.5.5 Updating Time/Calendar

To update any of the time/calendar fields, the user must first stop the RTC by setting the corre-

sponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour,

minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month,

date, day).

Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Regis-

ter. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in

RTC_SCCR. The user can now write to the appropriate Time and Calendar register.

Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control

When entering programming mode of the calendar fields, the time fields remain enabled. When

entering the programming mode of the time fields, both time and calendar fields are stopped.

This is due to the location of the calendar logic circuity (downstream for low-power consider-

ations). It is highly recommended to prepare all the fields to be updated before entering

programming mode. In successive update operations, the user must wait at least one second

after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these

bits again. This is done by waiting for the SEC flag in the Status Register before setting

UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.

6438J–ATARM–10-Aug-12

SAM9G45

Figure 14-2. Update Sequence

Prepare TIme or Calendar Fields

Set UPDTIM and/or UPDCAL

bit(s) in RTC_CR

Read RTC_SR

ACKUPD

= 1 ?

Clear ACKUPD bit in RTC_SCCR

Update Time andor Calendar values in

RTC_TIMR/RTC_CALR

Clear UPDTIM and/or UPDCAL bit in

RTC_CR

Yes

Begin

End

Polling or

IRQ (if enabled)

6438J–ATARM–10-Aug-12

SAM9G45

14.6 R eal-time Clock (RTC) User Interface

Table 14-1. Register Mapping

Offset Register Name Access Reset

0x00 Control Register RTC_CR Read-write 0x0

0x04 Mode Register RTC_MR Read-write 0x0

0x0C Calendar Register RTC_CALR Read-write 0x01210720

0x10 Time Alarm Register RTC_TIMALR Read-write 0x0

0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000

0x18 Status Register RTC_SR Read-only 0x0

0x1C Status Clear Command Register RTC_SCCR Write-only ---

0x20 Interrupt Enable Register RTC_IER Write-only ---

0x24 Interrupt Disable Register RTC_IDR Write-only ---

0x28 Interrupt Mask Register RTC_IMR Read-only 0x0

0x2C Valid Entry Register RTC_VER Read-only 0x0

6438J–ATARM–10-Aug-12

SAM9G45

14.6.1 RTC Control Register

Name: RTC_CR

Address: 0xFFFFFDB0

Access Type: Read-write

• UPDTIM: Update Request Time Register

0 = No effect.

1 = Stops the RTC time counting.

Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and

acknowledged by the bit ACKUPD of the Status Register.

• UPDCAL: Update Request Calendar Register

0 = No effect.

1 = Stops the RTC calendar counting.

Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once

this bit is set.

• TIMEVSEL: Time Event Selection

The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.

0 = Minute change.

1 = Hour change.

2 = Every day at midnight.

3 = Every day at noon.

• CALEVSEL: Calendar Event Selection

The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL.

0 = Week change (every Monday at time 00:00:00).

1 = Month change (every 01 of each month at time 00:00:00).

2, 3 = Year change (every January 1 at time 00:00:00).

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––– CALEVSEL

15 14 13 12 11 10 9 8

–––––– TIMEVSEL

76543210

––––––UPDCALUPDTIM

100

6438J–ATARM–10-Aug-12

SAM9G45

14.6.2 RTC Mode Register

Name: RTC_MR

Address: 0xFFFFFDB4

Access Type: Read-write

• HRMOD: 12-/24-hour Mod e

0 = 24-hour mode is selected.

1 = 12-hour mode is selected.

All non-significant bits read zero.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––HRMOD

101

6438J–ATARM–10-Aug-12

SAM9G45

14.6.3 RTC Time Register

Name: RTC_TIMR

Address: 0xFFFFFDB8

Access Type: Read-write

• SEC: Current Second

The range that can be set is 0 - 59 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• MIN: Current Minute

The range that can be set is 0 - 59 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• HOUR: Current Hour

The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.

• AMPM: Ante Meridiem Post Meridiem Indicator

This bit is the AM/PM indicator in 12-hour mode.

0 = AM.

1 = PM.

All non-significant bits read zero.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–AMPM HOUR

15 14 13 12 11 10 9 8

–MIN

76543210

–SEC

102

6438J–ATARM–10-Aug-12

SAM9G45

14.6.4 RTC Calendar Register

Name: RTC_CALR

Address: 0xFFFFFDBC

Access Type: Read-write

• CENT: Current Century

The range that can be set is 19 - 20 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• YEAR: Current Year

The range that can be set is 00 - 99 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• MONTH: Current Month

The range that can be set is 01 - 12 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• DAY: Current Day in Current Week

The range that can be set is 1 - 7 (BCD).

The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.

• DATE: Current Day in Current Month

The range that can be set is 01 - 31 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

All non-significant bits read zero.

31 30 29 28 27 26 25 24

–– DATE

23 22 21 20 19 18 17 16

DAY MONTH

15 14 13 12 11 10 9 8

YEAR

76543210

–CENT

103

6438J–ATARM–10-Aug-12

SAM9G45

14.6.5 RTC Time Alarm Register

Name: RTC_TIMALR

Address: 0xFFFFFDC0

Access Type: Read-write

• SEC: Second Alarm

This field is the alarm field corresponding to the BCD-coded second counter.

• SECEN: Second Alarm Enable

0 = The second-matching alarm is disabled.

1 = The second-matching alarm is enabled.

• MIN: Minute Alarm

This field is the alarm field corresponding to the BCD-coded minute counter.

• MINEN: Minute Alarm Enable

0 = The minute-matching alarm is disabled.

1 = The minute-matching alarm is enabled.

• HOUR: Hour Alarm

This field is the alarm field corresponding to the BCD-coded hour counter.

• AMPM: AM/PM Indicator

This field is the alarm field corresponding to the BCD-coded hour counter.

• HOUREN: Hour Alarm Enable

0 = The hour-matching alarm is disabled.

1 = The hour-matching alarm is enabled.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

HOUREN AMPM HOUR

15 14 13 12 11 10 9 8

MINEN MIN

76543210

SECEN SEC

104

6438J–ATARM–10-Aug-12

SAM9G45

14.6.6 RTC Calendar Alarm Register

Name: RTC_CALALR

Address: 0xFFFFFDC4

Access Type: Read-write

• MONTH: Month Alarm

This field is the alarm field corresponding to the BCD-coded month counter.

• MTHEN: Month Alarm Enable

0 = The month-matching alarm is disabled.

1 = The month-matching alarm is enabled.

•DATE: Date Alarm

This field is the alarm field corresponding to the BCD-coded date counter.

• DATEEN: Date Alarm Enable

0 = The date-matching alarm is disabled.

1 = The date-matching alarm is enabled.

31 30 29 28 27 26 25 24

DATEEN – DATE

23 22 21 20 19 18 17 16

MTHEN – – MONTH

15 14 13 12 11 10 9 8

––––––––

76543210

––––––––

105

6438J–ATARM–10-Aug-12

SAM9G45

14.6.7 RTC Status Register

Name: RTC_SR

Address: 0xFFFFFDC8

Access Type: Read-only

• ACKUPD: Acknowledge for Update

0 = Time and calendar registers cannot be updated.

1 = Time and calendar registers can be updated.

• ALARM: Alarm Flag

0 = No alarm matching condition occurred.

1 = An alarm matching condition has occurred.

• SEC: Second Event

0 = No second event has occurred since the last clear.

1 = At least one second event has occurred since the last clear.

• TIMEV: Time Event

0 = No time event has occurred since the last clear.

1 = At least one time event has occurred since the last clear.

The time event is selected in the TIMEVSEL field in RTC_CTRL (Control Register) and can be any one of the following

events: minute change, hour change, noon, midnight (day change).

• CALEV: Calendar Event

0 = No calendar event has occurred since the last clear.

1 = At least one calendar event has occurred since the last clear.

The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week

change, month change and year change.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

– – – CALEV TIMEV SEC ALARM ACKUPD

106

6438J–ATARM–10-Aug-12

SAM9G45

14.6.8 RTC Status Clear Command Register

Name: RTC_SCCR

Address: 0xFFFFFDCC

Access Type: Write-only

• ACKCLR: Acknowledge Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• ALRCLR: Alarm Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• SECCLR: Second Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• TIMCLR: Time Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

• CALCLR: Calendar Clear

0 = No effect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

– – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR

107

6438J–ATARM–10-Aug-12

SAM9G45

14.6.9 RTC Interrupt Enable Register

Name: RTC_IER

Address: 0xFFFFFDD0

Access Type: Write-only

• ACKEN: Acknowledge Update Interrupt Enable

0 = No effect.

1 = The acknowledge for update interrupt is enabled.

• ALREN: Alarm Interrupt Enable

0 = No effect.

1 = The alarm interrupt is enabled.

• SECEN: Second Event Interrupt Enable

0 = No effect.

1 = The second periodic interrupt is enabled.

• TIMEN: Time Event Interrupt Enable

0 = No effect.

1 = The selected time event interrupt is enabled.

• CALEN: Calendar Event Interrupt Enable

0 = No effect.

• 1 = The selected calendar event interrupt is enabled.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

– – – CALEN TIMEN SECEN ALREN ACKEN

108

6438J–ATARM–10-Aug-12

SAM9G45

14.6.10 RTC Interrupt Disable Register

Name: RTC_IDR

Address: 0xFFFFFDD4

Access Type: Write-only

• ACKDIS: Acknowledge Update Interrupt Disable

0 = No effect.

1 = The acknowledge for update interrupt is disabled.

• ALRDIS: Alarm Interrupt Disable

0 = No effect.

1 = The alarm interrupt is disabled.

• SECDIS: Second Event Interrupt Disable

0 = No effect.

1 = The second periodic interrupt is disabled.

• TIMDIS: Time Event Interrupt Disable

0 = No effect.

1 = The selected time event interrupt is disabled.

• CALDIS: Calendar Event Interrupt Disable

0 = No effect.

1 = The selected calendar event interrupt is disabled.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

– – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS

109

6438J–ATARM–10-Aug-12

SAM9G45

14.6.11 RTC Interrupt Mask Register

Name: RTC_IMR

Address: 0xFFFFFDD8

Access Type: Read-only

• ACK: Acknowledge Update Interrupt Mask

0 = The acknowledge for update interrupt is disabled.

1 = The acknowledge for update interrupt is enabled.

• ALR: Alarm Interrupt Mask

0 = The alarm interrupt is disabled.

1 = The alarm interrupt is enabled.

• SEC: Second Event Interrupt Mask

0 = The second periodic interrupt is disabled.

1 = The second periodic interrupt is enabled.

• TIM: Time Even t In te rru p t Ma s k

0 = The selected time event interrupt is disabled.

1 = The selected time event interrupt is enabled.

• CAL: Calendar Event Interrupt Mask

0 = The selected calendar event interrupt is disabled.

1 = The selected calendar event interrupt is enabled.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––CALTIMSECALRACK

110

6438J–ATARM–10-Aug-12

SAM9G45

14.6.12 RTC Valid Entry Register

Name: RTC_VER

Address: 0xFFFFFDDC

Access Type: Read-only

• NVTIM: Non-va lid Time

0 = No invalid data has been detected in RTC_TIMR (Time Register).

1 = RTC_TIMR has contained invalid data since it was last programmed.

• NVCAL: Non-valid Calendar

0 = No invalid data has been detected in RTC_CALR (Calendar Register).

1 = RTC_CALR has contained invalid data since it was last programmed.

• NVTIMALR: Non-valid Time Alarm

0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).

1 = RTC_TIMALR has contained invalid data since it was last programmed.

• NVCALALR: Non-valid Calendar Alarm

0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).

1 = RTC_CALALR has contained invalid data since it was last programmed.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––NVCALALRNVTIMALRNVCALNVTIM

111

6438J–ATARM–10-Aug-12

SAM9G45

15. Periodic Interval Timer (PIT)

15.1 Description

The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is

designed to offer maximum accuracy and efficient management, even for systems with long

response time.

15.2 E mbedded Characteristics

• Includes a 20-bit Periodic Counter, with less than 1µs accuracy

• Includes a 12-bit Interval Overlay Counter

• Real Time OS or Linux/WinCE compliant tick generator

15.3 Block Diagram

Figure 15-1. Periodic Interval Timer

20-bit

Counter

MCK/16

PIV

PIT_MR

CPIV PIT_PIVR PICNT

12-bit

Adder

read PIT_PIVR

CPIV PICNT

PIT_PIIR

PITS

PIT_SR

set

reset

PITIEN

PIT_MR

pit_irq

MCK

Prescaler

= ?

112

6438J–ATARM–10-Aug-12

SAM9G45

15.4 Functional Description

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.

The PIT provides a programmable overflow counter and a reset-on-read feature. It is built

around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at

Master Clock /16.

The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the

field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to

0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis-

ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in

PIT_MR).

Writing a new PIV value in PIT_MR does not reset/restart the counters.

When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register

(PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging

the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last

read of PIT_PIVR.

When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register

(PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For exam-

ple, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer

interrupt clears the interrupt by reading PIT_PIVR.

The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on

reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates

the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until

the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.

The PIT is stopped when the core enters debug state.

113

6438J–ATARM–10-Aug-12

SAM9G45

Figure 15-2. Enabling/Disabling PIT with PITEN

15.5 Periodic Interval Timer (PIT) User Interface

MCK Prescaler

PIVPIV - 10

PITEN

CPIV 1

restarts MCK Prescaler

APB cycle

read PIT_PIVR

PICNT

PITS (PIT_SR)

MCK

APB Interface

APB cycle

Table 15-1. Register Mapping

Offset Register Name Access Reset

0x00 Mode Register PIT_MR Read-write 0x000F_FFFF

0x04 Status Register PIT_SR Read-only 0x0000_0000

0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000

0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000

114

6438J–ATARM–10-Aug-12

SAM9G45

15.5.1 Periodic Interval Timer Mode Register

Address: 0xFFFFFD30

Access Type: Read/Write

• PIV: Periodic Interval Value

Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to

(PIV + 1).

• PITEN: P eriod Interval Timer Enabled

0 = The Periodic Interval Timer is disabled when the PIV value is reached.

1 = The Periodic Interval Timer is enabled.

• PITIEN: Periodic Interval Timer Interrupt Enable

0 = The bit PITS in PIT_SR has no effect on interrupt.

1 = The bit PITS in PIT_SR asserts interrupt.

31 30 29 28 27 26 25 24

––––––PITIENPITEN

23 22 21 20 19 18 17 16

–––– PIV

15 14 13 12 11 10 9 8

PIV

76543210

PIV

115

6438J–ATARM–10-Aug-12

SAM9G45

15.5.2 Periodic Interval Timer Status Register

Address: 0xFFFFFD34

Access Type: Read-only

• PITS: Periodic Interval Timer Status

0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.

1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.

15.5.3 Periodic Interval Timer Value Regist er

Address: 0xFFFFFD38

Access Type: Read-only

Reading this register clears PITS in PIT_SR.

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––PITS

31 30 29 28 27 26 25 24

PICNT

23 22 21 20 19 18 17 16

PICNT CPIV

15 14 13 12 11 10 9 8

CPIV

76543210

CPIV

116

6438J–ATARM–10-Aug-12

SAM9G45

15.5.4 Periodic Interval Timer Image Register

Address: 0xFFFFFD3C

Access Type: Read-only

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

31 30 29 28 27 26 25 24

PICNT

23 22 21 20 19 18 17 16

PICNT CPIV

15 14 13 12 11 10 9 8

CPIV

76543210

CPIV

117

6438J–ATARM–10-Aug-12

SAM9G45

16. Watchdog Timer (WDT)

16.1 Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in

a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds

(slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition,

it can be stopped while the processor is in debug mode or idle mode.

16.2 E mbedded Characteristics

• 16-bit key-protected only-once-Programmable Counter

• Windowed, prevents the processor to be in a dead-lock on the watchdog access

16.3 Block Diagram

Figure 16-1. Watchdog Timer Block Diagram

set

reset

read WDT_SR

reset

wdt_fault

(to Reset Controller)

set

reset

WDFIEN

wdt_int

WDT_MR

SLCK

1/128

12-bit Down

Counter

Current

Value

WDD

WDT_MR

<= WDD

WDV

WDRSTT

WDT_MR

WDT_CR

reload

WDUNF

WDERR

reload

write WDT_MR

WDT_MR

WDRSTEN

118

6438J–ATARM–10-Aug-12

SAM9G45

16.4 Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in

a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.

The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in

the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock

divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow

Clock of 32.768 kHz).

After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of

the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup

Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must

either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must

reprogram it to meet the maximum Watchdog period the application requires.

The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset

resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode

parameters.

In normal operation, the user reloads the Watchdog at regular intervals before the timer under-

flow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The

Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow

Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result,

writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur,

the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode

(WDT_SR).

To prevent a software deadlock that continuously triggers the Watchdog, the reload of the

Watchdog must occur while the Watchdog counter is within a window between 0 and WDD,

WDD is defined in the WatchDog Mode Register WDT_MR.

Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD

results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the

WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted.

Note that this feature can be disabled by programming a WDD value greater than or equal to the

WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole

range [0; WDV] and does not generate an error. This is the default configuration on reset (the

WDD and WDV values are equal).

The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an inter-

rupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset

controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset

controller programmer Datasheet. In that case, the processor and the Watchdog Timer are

reset, and the WDERR and WDUNF flags are reset.

If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared,

and the “wdt_fault” signal to the reset controller is deasserted.

Writing the WDT_MR reloads and restarts the down counter.

While the processor is in debug state or in idle mode, the counter may be stopped depending on

the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.

119

6438J–ATARM–10-Aug-12

SAM9G45

Figure 16-2. Watchdog Behavior

WDV

WDD

WDT_CR = WDRSTT

Watchdog

Fault

Normal behavior

Watchdog Error Watchdog Underflow

FFF if WDRSTEN is 1

if WDRSTEN is 0

Forbidden

Window

Permitted

Window

120

6438J–ATARM–10-Aug-12

SAM9G45

16.5 Watchdog Timer (WDT) User Interface

16.5.1 Watchdog Timer Contr ol Register

Address: 0xFFFFFD40

Access Type: Write-only

• WDRSTT: Watchdog Restart

0: No effect.

1: Restarts the Watchdog.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

Table 16-1. Register Mapping

Offset Register Name Access Reset

0x00 Control Register WDT_CR Write-only -

0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF

0x08 Status Register WDT_SR Read-only 0x0000_0000

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––WDRSTT

121

6438J–ATARM–10-Aug-12

SAM9G45

16.5.2 Watchdog Timer Mode Register

Address: 0xFFFFFD44

Access Type: Read-write Once

• WDV: Watchdog Counter Value

Defines the value loaded in the 12-bit Watchdog Counter.

• WDFIEN: Watchdog Fault Interrupt Enable

0: A Watchdog fault (underflow or error) has no effect on interrupt.

1: A Watchdog fault (underflow or error) asserts interrupt.

• WDRSTEN: Watchdog Reset Enable

0: A Watchdog fault (underflow or error) has no effect on the resets.

1: A Watchdog fault (underflow or error) triggers a Watchdog reset.

• WDRPROC: Watchdog Reset Processor

0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.

1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.

• WDD: Watchdog Delta Value

Defines the permitted range for reloading the Watchdog Timer.

If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.

If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.

• WDDBGHLT: Watchdog Debug Halt

0: The Watchdog runs when the processor is in debug state.

1: The Watchdog stops when the processor is in debug state.

• WDIDLEHLT: Watchdog Idle Halt

0: The Watchdog runs when the system is in idle mode.

1: The Watchdog stops when the system is in idle state.

• WDDIS: Watchdog Disable

0: Enables the Watchdog Timer.

1: Disables the Watchdog Timer.

31 30 29 28 27 26 25 24

WDIDLEHLT WDDBGHLT WDD

23 22 21 20 19 18 17 16

WDD

15 14 13 12 11 10 9 8

WDDIS WDRPROC WDRSTEN WDFIEN WDV

76543210

WDV

122

6438J–ATARM–10-Aug-12

SAM9G45

16.5.3 Watchdog Timer Status Register

Address: 0xFFFFFD48

Access Type: Read-only

• WDUNF: Watchdog Underflow

0: No Watchdog underflow occurred since the last read of WDT_SR.

1: At least one Watchdog underflow occurred since the last read of WDT_SR.

• WDERR: Watchdog Error

0: No Watchdog error occurred since the last read of WDT_SR.

1: At least one Watchdog error occurred since the last read of WDT_SR.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––WDERRWDUNF

123

6438J–ATARM–10-Aug-12

SAM9G45

17. Shutdown Controller (SHDWC)

17.1 Description

The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up

detection on debounced input lines.

17.2 E mbedded Characteristics

The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut down

of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the

SHDN pin, and thus wakes up the system power supply.

17.3 Block Diagram

Figure 17-1. Shutdown Controller Block Diagram

Shutdown

Wake-up

Shutdown

Output

Controller

SHDN

WKUP0

SHDW

WKMODE0

Shutdown Controller

RTT Alarm

RTTWKEN

SHDW_MR

SHDW_CR

CPTWK0

WAKEUP0

RTTWK SHDW_SR

SHDW_SR

set

reset

read SHDW_SR

SLCK

124

6438J–ATARM–10-Aug-12

SAM9G45

Figure 17-2. Shutdown Controller Block Diagram

17.4 I/O Lines Description

17.5 Product Dependencies

17.5.1 Power Management

The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con-

troller has no effect on the behavior of the Shutdown Controller.

Shutdown

Wake-up

Shutdown

Output

Controller

SHDN

WKUP0

SHDW

WKMODE0

Shutdown Controller

RTC Alarm

RTT Alarm

RTTWKEN

RTCWKEN

SHDW_MR

SHDW_CR

CPTWK0

WAKEUP0

RTTWK

RTCWK

SHDW_SR

set

reset

read SHDW_SR

SLCK

Table 17-1. I/O Lines Description

Name Description Type

WKUP0 Wake-up 0 input Input

SHDN Shutdown output Output

125

6438J–ATARM–10-Aug-12

SAM9G45

17.6 Functional Description

The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU

and manages wake-up input pins and one output pin, SHDN.

A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter pro-

viding the main power supplies of the system, and especially VDDCORE and/or VDDIO. The

wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system.

The software is able to control the pin SHDN by writing the Shutdown Control Register

(SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock

cycles after the write of SHDW_CR. This register is password-protected and so the value written

should contain the correct key for the command to be taken into account. As a result, the system

should be powered down.

A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode

negative transition or any level change on WKUP0. The detection can also be disabled. Pro-

gramming is performed by defining WKMODE0.

Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters

pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the

SHDW_MR register. If the programmed level change is detected on a pin, a counter starts.

When the counter reaches the value programmed in the corresponding field, CPTWK0, the

SHDN pin is released. If a new input change is detected before the counter reaches the corre-

sponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register

(SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the

read of SHDW_SR.

The Shutdown Controller can be programmed so as to activate the wake-up using the RTT

alarm (the detection of the rising edge of the RTT alarm is synchronized with SLCK). This is

done by writing the SHDW_MR register using the RTTWKEN fields. When enabled, the detec-

tion of the RTT alarm is reported in the RTTWK bit of the SHDW_SR Status register. It is reset

after the read of SHDW_SR. When using the RTT alarm to wake up the system, the user must

ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no

rising edge of the status flag may be detected and the wake-up fails.

The Shutdown Controller can be programmed so as to activate the wake-up using the RTC

alarm (the detection of the rising edge of the RTC alarm is synchronized with SLCK). This is

done by writing the SHDW_MR register using the RTCWKEN field. When enabled, the detection

of the RTC alarm is reported in the RTCWK bit of the SHDW_SR Status register. It is reset after

the read of SHDW_SR. When using the RTC alarm to wake up the system, the user must

ensure that the RTC alarm status flag is cleared before shutting down the system. Otherwise, no

rising edge of the status flag may be detected and the wake-up fails fail.

126

6438J–ATARM–10-Aug-12

SAM9G45

17.7 Shutdown Controller (SHDWC) User Interface

17.7.1 Shutdown Cont rol Register

Address: 0xFFFFFD10

Access Type: Write-only

• SHDW: Shutdown Command

0 = No effect.

1 = If KEY is correct, asserts the SHDN pin.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

Table 17-2. Register Mapping

Offset Register Name Access Reset

0x00 Shutdown Control Register SHDW_CR Write-only -

0x04 Shutdown Mode Register SHDW_MR Read-write 0x0000_0003

0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––SHDW

127

6438J–ATARM–10-Aug-12

SAM9G45

17.7.2 Shutdown Mode Register

Address: 0xFFFFFD14

Access Type: Read/Write

• WKMODE0: Wake-up Mode 0

• CPTWK0: Counter on Wake-up 0

Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-

up event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released

(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.

• RTTWKEN: Real-time Timer Wake-up Enable

0 = The RTT Alarm signal has no effect on the Shutdown Controller.

1 = The RTT Alarm signal forces the de-assertion of the SHDN pin.

• RTCWKEN: Real-time Clock Wake-up Enable

0 = The RTC Alarm signal has no effect on the Shutdown Controller.

1 = The RTC Alarm signal forces the de-assertion of the SHDN pin.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––RTCWKENRTTWKEN

15 14 13 12 11 10 9 8

––––

76543210

CPTWK0 – – WKMODE0

WKMODE[1:0] Wake-up Input Transition Selection

0 0 None. No detection is performed on the wake-up input

0 1 Low to high level

1 0 High to low level

1 1 Both levels change

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SAM9G45

17.7.3 Shutdown Status Register

Address: 0xFFFFFD18

Access Type: Read-only

• WAKEUP0: Wake-up 0 Status

0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.

1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.

• RTTWK: Real-time Timer Wake-up

0 = No wake-up alarm from the RTT occurred since the last read of SHDW_SR.

1 = At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR.

• RTCWK: Real-time Clock Wake-up

0 = No wake-up alarm from the RTC occurred since the last read of SHDW_SR.

1 = At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––RTCWKRTTWK

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––WAKEUP0

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18. General Purpose Backup Registers (GPBR)

18.1 Description

The System Controller embeds Four general-purpose backup registers.

18.2 E mbedded Characteristics

• Four 32-bit general-purpose backup registers

18.3 General Purpose Backup Registers (GPBR) User Interface

Table 18-1. Register Mapping

Offset Register Name Access Reset

0x0 General Purpose Backup Register 0 SYS_GPBR0 Read-write –

... ... ... ... ...

0xc General Purpose Backup Register 3 SYS_GPBR3 Read-write –