MC14042BDR2G - ON Semiconductor - Datasheet.Directory

June, 2011 − Rev. 7

1Publication Order Number:

MC14042B/D

MC14042B

Quad Transparent Latch

The MC14042B Quad Transparent Latch is constructed with MOS

P−channel and N−channel enhancement mode devices in a single

monolithic structure. Each latch has a separate data input, but all four

latches share a common clock. The clock polarity (high or low) used to

strobe data through the latches can be reversed using the polarity

input. Information present at the data input is transferred to outputs Q

and Q during the clock level which is determined by the polarity input.

When the polarity input is in the logic “0” state, data is transferred

during the low clock level, and when the polarity input is in the logic

“1” state the transfer occurs during the high clock level.

Features

•Buffered Data Inputs

•Common Clock

•Clock Polarity Control

•Q and Q Outputs

•Double Diode Input Protection

•Supply Voltage Range = 3.0 Vdc to 1 8 Vdc

•Capable of Driving Two Low−power TTL Loads or One

Low−power Schottky TTL Load Over the Rated Temperature

Range

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation,

per Package (Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC14042BCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

14042BG

AWLYWW

A = Assembly Location

WL = Wafer Lot

YY, Y = Year

WW = Work Week

G = Pb−Free Indicator

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

16

1

16

MC14042B

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2

PIN ASSIGNMENT

TRUTH TABLE

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q2

D2

D3

Q3

VDD

Q1

Q2

D0

Q0

Q3

VSS

D1

POLARITY

CLOCK

Clock Polarity Q

0 0 Data

1 0 Latch

1 1 Data

0 1 Latch

LOGIC DIAGRAM

CLOCK

POLARITY

VDD = PIN 16

VSS = PIN 8

5

6

4

7

13

14

D3

D2

D1

D0 LATCH

1

LATCH

2

LATCH

3

LATCH

4

Q2

Q3

Q2

Q1

Q0

12

2

3

10

9

11

1

15

MC14042B

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ

(Note 2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

±0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎ

±1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.0

2.0

4.0

ÎÎÎÎ

−

ÎÎÎ

0.002

0.004

0.006

ÎÎÎÎ

1.0

2.0

4.0

ÎÎÎ

−

ÎÎÎ

30

60

120

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs all

buffers switching)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (1.0 mA/kHz) f + IDD

IT = (2.0 mA/kHz) f + IDD

IT = (3.0 mA/kHz) f + IDD

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.004.

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time, D to Q, Q

tPLH, tPHL = (1.7 ns/pF) CL + 135 ns

tPLH, tPHL = (0.66 ns/pF) CL + 57 ns

tPLH, tPHL = (0.5 ns/pF) CL + 35 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

220

90

60

ÎÎÎÎ

440

180

120

ÎÎÎ

no

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time, Clock to Q, Q

tPLH, tPHL = (1.7 ns/pF) CL + 135 ns

tPLH, tPHL = (0.66 ns/pF) CL + 57 ns

tPLH, tPHL = (0.5 ns/pF) CL + 35 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

220

90

60

ÎÎÎÎ

440

180

120

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width

ÎÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

300

100

80

ÎÎÎÎ

150

50

40

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Rise and Fall Time

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎÎ

15

5.0

4.0

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hold Time

ÎÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

100

50

40

ÎÎÎÎ

50

25

20

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Setup Time

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

50

30

25

ÎÎÎÎ

0

ÎÎÎÎ

−

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ORDERING INFORMATION

Device Package Shipping†

MC14042BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14042BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14042BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC14042B

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5

Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

(Data to Output)

VDD

VSS

PULSE

GENERATOR 1

16

5

6

4

7

13

14

CLOCK

POLARITY

D0

D1

D2

D3 Q3

Q3

Q2

Q1

Q0

15

1

12

11

9

10

3

2

8

For Power Dissipation test, each output

is loaded with capacitance CL.

1

f

20 ns 20 ns

DATA INPUT

Q OUTPUT

tPLH tPHL

tTLH tTHL

tTLH

tTHL

90%

50% 10%

50%

90%

10%

90%

10% 50%

tPHL

Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)

NOTE: CL connected to output under test.

20* ns 20 ns

90%

10%

PULSE

GENERATOR 1

PULSE

GENERATOR 2

VDD

16

5

6

4

7

13

14

CLOCK

POLARITY

D0

D1

D2

D3 Q3

Q3

Q2

Q1

Q0

VSS

8

15

1

12

11

9

10

3

2

50%

tWH

20 ns

90%

50%

tsu th

tPLH

90%

50%

10%

CLOCK INPUT

P.G. 1

DATA INPUT

P.G. 2

Q OUTPUT

*Input clock rise time is 20 ns except for maximum rise time test.

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PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

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PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE K NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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MC14042B/D

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