MC14042B Quad Transparent Latch The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic "0" state, data is transferred during the low clock level, and when the polarity input is in the logic "1" state the transfer occurs during the high clock level. http://onsemi.com MARKING DIAGRAMS PDIP-16 P SUFFIX CASE 648 Features * * * * * * * * Buffered Data Inputs Common Clock Clock Polarity Control Q and Q Outputs Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 1 8 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range These Devices are Pb-Free and are RoHS Compliant Parameter MC14042BCP AWLYYWWG 1 16 SOIC-16 D SUFFIX CASE 751B 14042BG AWLYWW 1 A WL YY, Y WW G MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol 16 Value Unit = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator -0.5 to +18.0 V ORDERING INFORMATION -0.5 to VDD + 0.5 V See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Input or Output Current (DC or Transient) per Pin 10 mA PD Power Dissipation, per Package (Note 1) 500 mW VDD Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) TA Ambient Temperature Range -55 to +125 C Tstg Storage Temperature Range -65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. (c) Semiconductor Components Industries, LLC, 2011 June, 2011 - Rev. 7 1 Publication Order Number: MC14042B/D MC14042B PIN ASSIGNMENT Q3 1 16 VDD Q0 2 15 Q3 Q0 3 14 D3 D0 4 13 D2 CLOCK 5 12 Q2 POLARITY 6 11 Q2 D1 7 10 Q1 VSS 8 9 Q1 TRUTH TABLE Clock Polarity Q 0 1 1 0 0 0 1 1 Data Latch Data Latch LOGIC DIAGRAM 5 D0 LATCH 1 4 CLOCK POLARITY Q0 2 Q0 3 6 D1 LATCH 2 7 Q1 10 Q1 9 D2 LATCH 3 13 VDD = PIN 16 VSS = PIN 8 Q2 11 Q2 12 D3 LATCH 4 14 Q3 1 Q3 15 http://onsemi.com 2 MC14042B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIII IIIIIIIII IIIII IIII IIIIIIIIIIIII IIIIII IIIIIIIIIIIIII IIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIII IIIIIII IIIIII IIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit "0" Level VOL 5.0 10 15 - - - 0.05 0.05 0.05 - - - 0 0 0 0.05 0.05 0.05 - - - 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 - - - 4.95 9.95 14.95 5.0 10 15 - - - 4.95 9.95 14.95 - - - Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 - - - 1.5 3.0 4.0 - - - 2.25 4.50 6.75 1.5 3.0 4.0 - - - 1.5 3.0 4.0 "1" Level VIH 5.0 10 15 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 - - - - - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 - - - - - 1.7 - 0.36 - 0.9 - 2.4 - - - - IOL 5.0 10 15 0.64 1.6 4.2 - - - 0.51 1.3 3.4 0.88 2.25 8.8 - - - 0.36 0.9 2.4 - - - mAdc Input Current Iin 15 - 0.1 - 0.00001 0.1 - 1.0 mAdc Input Capacitance (Vin = 0) Cin - - - - 5.0 7.5 - - pF Quiescent Current (Per Package) IDD 5.0 10 15 - - - 1.0 2.0 4.0 - - - 0.002 0.004 0.006 1.0 2.0 4.0 - - - 30 60 120 mAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs all buffers switching) IOH Vdc Vdc mAdc IT = (1.0 mA/kHz) f + IDD IT = (2.0 mA/kHz) f + IDD IT = (3.0 mA/kHz) f + IDD 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004. http://onsemi.com 3 mAdc MC14042B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time, D to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns tPLH, tPHL Propagation Delay Time, Clock to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns tPLH, tPHL Clock Pulse Width tWH Clock Pulse Rise and Fall Time Hold Time Min Typ (Note 6) Max 5.0 10 15 - - - 100 50 40 200 100 80 5.0 10 15 - - - 220 90 60 440 180 120 5.0 10 15 - - - 220 90 60 440 180 120 5.0 10 15 300 100 80 150 50 40 - - - 5.0 10 15 - - - - - - 15 5.0 4.0 5.0 10 15 100 50 40 50 25 20 - - - 5.0 10 15 50 30 25 0 0 0 - - - Unit ns no ns ns tTLH, tTHL th Setup Time VDD ms ns tsu ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ORDERING INFORMATION Package Shipping MC14042BCPG PDIP-16 (Pb-Free) 500 Units / Rail MC14042BDG SOIC-16 (Pb-Free) 48 Units / Rail MC14042BDR2G SOIC-16 (Pb-Free) 2500 Units / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC14042B VDD 1 f 16 20 ns 5 6 4 PULSE GENERATOR 1 7 13 2 3 10 9 11 12 1 15 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 CLOCK POLARITY D0 D1 D2 14 D3 20 ns 90% 50% DATA INPUT tPLH tPHL 90% Q OUTPUT For Power Dissipation test, each output is loaded with capacitance CL. VSS tTHL Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram (Data to Output) VDD 16 PULSE GENERATOR 1 5 PULSE GENERATOR 2 4 CLOCK 6 POLARITY D0 7 D1 13 D2 14 D3 NOTE: CL connected to output under test. 20* ns 8 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 2 3 10 9 11 12 1 15 VSS 20 ns 90% 50% CLOCK INPUT P.G. 1 10% tWH 20 ns 90% 50% DATA INPUT P.G. 2 tsu th tPLH Q OUTPUT 90% 50% 10% *Input clock rise time is 20 ns except for maximum rise time test. Figure 2. AC Test Circuit and Timing Diagram (Clock to Output) http://onsemi.com 5 tTHL tPHL 90% 10% 8 50% 10% tTLH Q OUTPUT 10% 50% tTLH MC14042B PACKAGE DIMENSIONS PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14042B PACKAGE DIMENSIONS SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE K -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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