OPA330
OPA2330
OPA4330
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SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
50μV V
OS
, 0.25μV/°C, 35μA
CMOS OPERATIONAL AMPLIFIERS
Zerø-Drift Series
Check for Samples: OPA330,OPA2330,OPA4330
1FEATURES DESCRIPTION
23•UNMATCHED PRICE PERFORMANCE The OPA330 series of CMOS operational amplifiers
offer precision performance at a very competitive
•LOW OFFSET VOLTAGE: 50μV (max) price. These devices are members of the Zerø-Drift
•ZERO DRIFT: 0.25μV/°C (max) family of amplifiers which use a proprietary
•LOW NOISE: 1.1μVPP, 0.1Hz to 10Hz auto-calibration technique to simultaneously provide
•QUIESCENT CURRENT: 35μA (max) low offset voltage (50μV max) and near-zero drift
over time and temperature at only 35μA (max) of
•SUPPLY VOLTAGE: 1.8V to 5.5V quiescent current. The OPA330 family features
•RAIL-TO-RAIL INPUT/OUTPUT rail-to-rail input and output in addition to near flat 1/f
•INTERNAL EMI FILTERING noise, making this amplifier ideal for many
applications and much easier to design into a system.
•microSIZE PACKAGES: WCSP, SC70, QFN These devices are optimized for low-voltage
operation as low as +1.8V (±0.9V) and up to +5.5V
APPLICATIONS (±2.75V).
•BATTERY-POWERED INSTRUMENTS The OPA330 (single version) is available in the
•TEMPERATURE MEASUREMENTS WCSP-5, SC70-5, SOT23-5, and SOIC-8 packages.
•TRANSDUCER APPLICATIONS The OPA2330 (dual version) is offered in DFN-8
•ELECTRONIC SCALES (3mm ×3mm), MSOP-8, and SOIC-8 packages. The
•MEDICAL INSTRUMENTATION OPA4330 is offered in the standard SOIC-14 and
TSSOP-14 packages, as well as in the space-saving
•HANDHELD TEST EQUIPMENT VQFN-14 package. All versions are specified for
•CURRENT SENSE operation from –40°C to +125°C.
PRODUCT FAMILY PACKAGE COMPARISON
PACKAGE-LEADS
NO OF
DEVICE CHANNELS WCSP SOIC SOT23 SC70 MSOP QFN TSSOP
OPA330 1 5 8 5 5 – – –
OPA2330 2 –8– – 8 8 –
OPA4330 4 –14 – – – 14 14
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoStar, NanoFree are trademarks of Texas Instruments Incorporated.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. ©2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
SOT23-5 DBV OCFQ
SC70-5 DCK CHL
OPA330 SOIC-8 D O330A
WCSP-5 YFF OEH
SOIC-8 D O2330A
OPA2330 DFN-8 DRB OCGQ
MSOP-8 DGK OCGQ
SOIC-14 D O4330A
OPA4330 TSSOP-14 PW O4330A
QFN-14 RGY 4330A
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. OPA330, OPA2330, OPA4330 UNIT
Supply Voltage, VS= (V+) –(V–) +7 V
Signal Input Terminals, Voltage(2) (V–)–0.3 to (V+) + 0.3 V
Signal Input Terminals, Current(2) ±10 mA
Output Short-Circuit(3) Continuous
Operating Temperature –40 to +150 °C
Storage Temperature –65 to +150 °C
Junction Temperature +150 °C
Human Body Model (HBM) 4000 V
ESD Charged Device Model (CDM) 1000 V
Ratings: Machine Model (MM) 400 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should
be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.
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SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
THERMAL INFORMATION OPA330AID(R) OPA330AIDBVR(T) OPA330AIDCKR(T) OPA330AIYFF
THERMAL METRIC(1) D DBV DCK YFF UNITS
8 PINS 5 PINS 5 PINS 5 PINS
θJA Junction-to-ambient thermal resistance 140.1 220.8 298.4 130
θJCtop Junction-to-case (top) thermal resistance 89.8 97.5 65.4 54
θJB Junction-to-board thermal resistance 80.6 61.7 97.1 51 °C/W
ψJT Junction-to-top characterization parameter 28.7 7.6 0.8 1
ψJB Junction-to-board characterization parameter 80.1 61.1 95.5 50
θJCbot Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION OPA2330AID(R) OPA2330AIDGKR(T) OPA2330AIDRBR(T)
THERMAL METRIC(1) D DGK DRB UNITS
8 PINS 8 PINS 8 PINS
θJA Junction-to-ambient thermal resistance 124.0 180.3 46.7
θJCtop Junction-to-case (top) thermal resistance 73.7 48.1 26.3
θJB Junction-to-board thermal resistance 64.4 100.9 22.2 °C/W
ψJT Junction-to-top characterization parameter 18.0 2.4 1.6
ψJB Junction-to-board characterization parameter 63.9 99.3 22.3
θJCbot Junction-to-case (bottom) thermal resistance n/a n/a 10.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION OPA4330AID OPA4330AIPW OPA4330AIRGY
THERMAL METRIC(1) D PW RGY UNITS
14 PINS 14 PINS 14 PINS
θJA Junction-to-ambient thermal resistance 83.8 120.8 49.2
θJCtop Junction-to-case (top) thermal resistance 70.7 34.3 75.3
θJB Junction-to-board thermal resistance 59.5 62.8 61.9 °C/W
ψJT Junction-to-top characterization parameter 11.6 1.0 1.2
ψJB Junction-to-board characterization parameter 37.7 56.5 19.3
θJCbot Junction-to-case (bottom) thermal resistance n/a n/a 4.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): OPA330 OPA2330 OPA4330
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS= +1.8V to +5.5V
Boldface limits apply over the specified temperature range, TA=–40°C to +125°C.
At TA= +25°C, RL= 10kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
OPA330, OPA2330, OPA4330
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS VS= +5V 8 50 μV
vs Temperature dVOS/dT 0.02 0.25 μV/°C
vs Power Supply PSRR VS= +1.8V to +5.5V 1 10 μV/V
Long-Term Stability(1) See (1)
Channel Separation, dc 0.1 μV/V
INPUT BIAS CURRENT
Input Bias Current IB±200 ±500 pA
Input Bias Current: OPA330YFF, OPA4330 ±70 ±300 pA
over Temperature ±300 pA
Input Offset Current IOS ±400 ±1000 pA
Input Offset Current: OPA330YFF, OPA4330 ±140 ±600 pA
NOISE
Input Voltage Noise Density enf = 1kHz 55 nV/√Hz
Input Voltage Noise f = 0.01Hz to 1Hz 0.3 μVPP
Input Voltage Noise f = 0.1Hz to 10Hz 1.1 μVPP
Input Current Noise inf = 10Hz 100 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V–)–0.1 (V+) + 0.1 V
Common-Mode Rejection Ratio CMRR (V–)–0.1V <VCM <(V+) + 0.1V 100 115 dB
Common-Mode Rejection Ratio: (V–)–0.1V <VCM <(V+) + 0.1V, VS= 5.5V 100 115 dB
OPA330YFF, OPA4330
INPUT CAPACITANCE
Differential 2 pF
Common-Mode 4 pF
OPEN-LOOP GAIN
(V–) + 100mV <VO<(V+) –100mV,
Open-Loop Voltage Gain AOL 100 115 dB
RL= 10kΩ
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW CL= 100pF 350 kHz
Slew Rate SR G = +1 0.16 V/μs
OUTPUT
Voltage Output Swing from Rail 30 100 mV
Short-Circuit Current ISC ±5 mA
Capacitive Load Drive CLSee Typical Characteristics
Open-Loop Output Impedance f = 350kHz, IO= 0 2 kΩ
POWER SUPPLY
Specified Voltage Range VS1.8 5.5 V
Quiescent Current Per Amplifier IQIO= 0 21 35 μA
Turn-On Time VS= +5V 100 μs
(1) 300-hour life test at +150°C demonstrated randomly distributed variation of approximately 1μV.
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Product Folder Link(s): OPA330 OPA2330 OPA4330
1
2
3
5
4
V+
-IN
OUT
V-
+IN
1
2
3
5
4
V+
OUT
+IN
V-
-IN
IN-
IN+
OUT
VS-
V +
S
C3
B2
A3
C1
A1
1
2
3
4
8
7
6
5
NC(1)
V+
OUT
NC(1)
NC(1)
-IN
+IN
V-
OPA330
OPA2330
OPA4330
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SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS: VS= +1.8V to +5.5V (continued)
Boldface limits apply over the specified temperature range, TA=–40°C to +125°C.
At TA= +25°C, RL= 10kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
OPA330, OPA2330, OPA4330
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE RANGE
Specified Range –40 +125 °C
Operating Range –40 +150 °C
Storage Range –65 +150 °C
Thermal Resistance θJA °C/W
SOT23-5 200 °C/W
MSOP-8, SOIC-8, TSSOP-14 150 °C/W
DFN-8 50 °C/W
SC70-5 250 °C/W
WCSP-5 130 °C/W
PIN CONFIGURATIONS
OPA330 OPA330
SOT23-5 SC70-5
(TOP VIEW) (TOP VIEW)
OPA330 OPA330
SOIC-8 WCSP-5
(TOP VIEW) (TOP VIEW)
(1) NC denotes no internal connection.
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Product Folder Link(s): OPA330 OPA2330 OPA4330
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
A
B
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
Exposed
Thermal
DiePad
on
Underside(2)
1
2
3
4
5
6
7
V+
+INB
-INB
OUTB
+INA
-INA
OUTA
+INC
-INC
OUTC
+IND
-IND
OUTD
V-
14
13
12
11
10
9
8
DA
B C
14
1
8
7
-INA
+INA
V+
+INB
-INB
-IND
+IND
V-
+INC
-INC
OUTA
OUTB
OUTD
OUTC
Exposed
ThermalDie
Padon
Underside(2)
2
3
5
6
4
13
12
10
9
11
1
2
3
4
5
6
7 8
14
13
12
11
10
9
V+
+INB
-INB
OUTB
+INA
-INA
OUTA
+INC
-INC
OUTC
+IND
-IND
OUTD
V-
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
PIN CONFIGURATIONS, CONTINUED
OPA2330 OPA2330
SOIC-8, MSOP-8 DFN-8
(TOP VIEW) (TOP VIEW)
OPA4330 OPA4330
SOIC-14 QFN-14
(TOP VIEW) (TOP VIEW)
OPA4330
TSSOP-14
(TOP VIEW)
(2) Connect thermal die pad to V–.
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A (dB)
OL
10
120
100
80
60
40
20
0
-20
Phase( )°
250
200
150
100
50
0
-50
-100
100k10k1k100
Frequency(Hz)
1M
Phase
Gain
CMRR(dB)
1
140
120
100
80
60
40
20
0
100k10k1k10010
Frequency(Hz)
1M
PSRR(dB)
1
120
100
80
60
40
20
0
10k 100k1k10010
Frequency(Hz)
1M
+PSRR
-PSRR
OutputSwing(V)
0
3
2
1
0
-1
-2
-3
1
OutputCurrent(mA)
107 8 965432
- °40 C
- °40 C
- °40 C
+25 C°
+25 C°
+25 C°
+125 C°
+125 C°
V = 2.75V±
S
V = 0.9V±
S
210
205
200
195
190
-190
-195
-200
-205
-210
0 1 2 3 4 5
Common-ModeVoltage(V)
I (pA)
B
-IB
+IB
OPA330
OPA2330
OPA4330
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SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS
At TA= +25°C, CL= 0pF, RL= 10kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION OPEN-LOOP GAIN vs FREQUENCY
Figure 1. Figure 2.
COMMON-MODE REJECTION RATIO vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY
Figure 3. Figure 4.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
Figure 5. Figure 6.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): OPA330 OPA2330 OPA4330
I (pA)
B
-50
250
200
150
100
50
0
50
100
150
200
250-
-
-
-
-
-25
Temperature( C)°
1251007550250
V =5.5V
S
V =1.8V
S
-IB
-IB
+IB
+IB
I ( A)m
Q
-50
25
20
15
10
5
0
-25
Temperature( C)°
1251007550250
V =1.8V
S
V =5.5V
S
OutputVoltage(1V/div)
Time(50 s/div)m
G=1
R =10kW
L
OutputVoltage(50mV/div)
Time(5 s/div)m
G=+1
R =10kW
L
2V/div
0
1V/div
0
Time(50 s/div)m
Input
Output
10kW
1kW
OPA330
+2.5V
-2.5V
2V/div
0
1V/div
0
Time(50 s/div)m
Input
Output
10kW
1kW
OPA330
+2.5V
-2.5V
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, CL= 0pF, RL= 10kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
INPUT BIAS CURRENT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE
Figure 7. Figure 8.
LARGE-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE
Figure 9. Figure 10.
POSITIVE OVER-VOLTAGE RECOVERY NEGATIVE OVER-VOLTAGE RECOVERY
Figure 11. Figure 12.
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SettlingTime( s)m
1
600
500
400
300
200
100
0
10
Gain(dB)
100
0.001%
0.01%
4VStep
Overshoot(%)
10
40
35
30
25
20
15
10
5
0
100
LoadCapacitance(pF)
1000
500nV/div
1s/div
VoltageNoise(nV/ )ÖHz
1
1000
100
10
CurrentNoise(fA/ )ÖHz
1000
100
10
1k10010
Frequency(Hz)
10k
CurrentNoise
VoltageNoise
Continueswithno1/f(flicker)noise.
InputBiasCurrent( A)m
50
40
30
20
10
0
10
20
30
40
50
-
-
-
-
-
-1V
InputDifferentialVoltage(mV)
-400-600 -200 0 400200 600 800-800
NormalOperatingRange
(seethe
sectioninthe
ApplicationsInformation)
InputDifferential
Voltage
Over-DrivenConditionOver-DrivenCondition
OPA330
OPA2330
OPA4330
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SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, CL= 0pF, RL= 10kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
SETTLING TIME vs CLOSED-LOOP GAIN SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
Figure 13. Figure 14.
CURRENT AND VOLTAGE NOISE SPECTRAL DENSITY
0.1Hz TO 10Hz NOISE vs FREQUENCY
Figure 15. Figure 16.
INPUT BIAS CURRENT vs INPUT DIFFERENTIAL VOLTAGE
Figure 17.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): OPA330 OPA2330 OPA4330
CORE
-In
+In
Clamp
10kW
10kW
5kW
OPA330
10mAmax
+5V
VIN
VOUT
IOVERLOAD
Current-limitingresistor
requiredifinputvoltage
exceedssupplyrailsby
³0.3V.
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
APPLICATIONS INFORMATION
The OPA330, OPA2330, and OPA4330 are unity-gain INPUT DIFFERENTIAL VOLTAGE
stable, precision operational amplifiers free from The typical input bias current of the OPA330 during
unexpected output and phase reversal. The use of normal operation is approximately 200pA. In
proprietary Zerø-Drift circuitry gives the benefit of low over-driven conditions, the bias current can increase
input offset voltage over time and temperature, as significantly (see Figure 17).The most common cause
well as lowering the 1/f noise component. As a result of an over-driven condition occurs when the op amp
of the high PSRR, these devices work well in is outside of the linear range of operation. When the
applications that run directly from battery power output of the op amp is driven to one of the supply
without regulation. The OPA330 family is optimized rails the feedback loop requirements cannot be
for low-voltage, single-supply operation. These satisfied and a differential input voltage develops
miniature, high-precision, low quiescent current across the input pins. This differential input voltage
amplifiers offer high-impedance inputs that have a results in activation of parasitic diodes inside the front
common-mode range 100mV beyond the supplies end input chopping switches that combine with 10kΩ
and a rail-to-rail output that swings within 100mV of electromagnetic interference (EMI) filter resistors to
the supplies under normal test conditions. The create the equivalent circuit shown in Figure 19.
OPA330 series are precision amplifiers for Notice that the input bias current remains within
cost-sensitive applications. specification within the linear region.
OPERATING VOLTAGE
The OPA330 series op amps can be used with single
or dual supplies from an operating range of VS=
+1.8V (±0.9V) up to +5.5V (±2.75V). Supply voltages
greater than +7V can permanently damage the
device. See the Absolute Maximum Ratings table.
Key parameters that vary over the supply voltage or Figure 19. Equivalent Input Circuit
temperature range are shown in the Typical
Characteristics section of this data sheet. INTERNAL OFFSET CORRECTION
INPUT VOLTAGE The OPA330, OPA2330, and OPA4330 op amps use
The OPA330, OPA2330, and OPA4330 input an auto-calibration technique with a time-continuous
common-mode voltage range extends 0.1V beyond 125kHz op amp in the signal path. This amplifier is
the supply rails. The OPA330 is designed to cover zero-corrected every 8μs using a proprietary
the full range without the troublesome transition technique. Upon power-up, the amplifier requires
region found in some other rail-to-rail amplifiers. approximately 100μs to achieve specified VOS
accuracy. This design has no aliasing or flicker noise.
Typically, input bias current is about 200pA; however,
input voltages exceeding the power supplies can EMI SUSCEPTIBILITY AND INPUT FILTERING
cause excessive current to flow into or out of the
input pins. Momentary voltages greater than the Operational amplifiers vary in their susceptibility to
power supply can be tolerated if the input current is EMI. If conducted EMI enters the operational
limited to 10mA. This limitation is easily accomplished amplifier, the dc offset observed at the amplifier
with an input resistor, as shown in Figure 18.output may shift from its nominal value while the EMI
is present. This shift is a result of signal rectification
associated with the internal semiconductor junctions.
While all operational amplifier pin functions can be
affected by EMI, the input pins are likely to be the
most susceptible. The OPA330 operational amplifier
family incorporates an internal input low-pass filter
that reduces the amplifier response to EMI. Both
common-mode and differential mode filtering are
provided by the input filter. The filter is designed for a
cutoff frequency of approximately 8MHz (–3dB), with
a roll-off of 20dB per decade.
Figure 18. Input Current Protection
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VOUT
R =20kW
P
OpAmpV =GND-
OPA330
VIN
V+=+5V
-5V
Additional
Negative
Supply
R1
VEX
VOUT
VREF
R1
OPA330
R
R
R R
+5V
OPA330
ADS1100
Load
V
I C
2
R1
4.99kW
R3
4.99kW
R4
48.7kW
R2
49.9kW
+5V
3V
REF3130
R7
1.18kW
RSHUNT
1W
R6
71.5kWRN
56W
RN
56W
(PGAGain=4)
FS=3.0V
StrayGround-LoopResistance
ILOAD
OPA330
OPA2330
OPA4330
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SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
ACHIEVING OUTPUT SWING TO THE OP The OPA330, OPA2330, and OPA4330 have an
AMP NEGATIVE RAIL output stage that allows the output voltage to be
pulled to its negative supply rail, or slightly below,
Some applications require output voltage swings from using the technique previously described. This
0V to a positive full-scale voltage (such as +2.5V) technique only works with some types of output
with excellent accuracy. With most single-supply op stages. The OPA330, OPA2330, and OPA4330 have
amps, problems arise when the output signal been characterized to perform with this technique; the
approaches 0V, near the lower output swing limit of a recommended resistor value is approximately 20kΩ.
single-supply op amp. A good single-supply op amp Note that this configuration will increase the current
may swing close to single-supply ground, but will not consumption by several hundreds of microamps.
reach ground. The output of the OPA330, OPA2330, Accuracy is excellent down to 0V and as low
and OPA4330 can be made to swing to ground, or as –2mV. Limiting and nonlinearity occurs
slightly below, on a single-supply power source. To below –2mV, but excellent accuracy returns as the
do so requires the use of another resistor and an output is again driven above –2mV. Lowering the
additional, more negative, power supply than the op resistance of the pull-down resistor will allow the op
amp negative supply. A pull-down resistor may be amp to swing even further below the negative rail.
connected between the output and the additional Resistances as low as 10kΩcan be used to achieve
negative supply to pull the output down below the excellent accuracy down to –10mV.
value that the output would otherwise achieve, as
shown in Figure 20.APPLICATION CIRCUITS
Figure 21 shows the basic configuration for a bridge
amplifier.
A low-side current shunt monitor is shown in
Figure 22.
Figure 20. For VOUT Range to Ground
Figure 21. Single Op Amp Bridge Amplifier
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 22. Low-Side Current Monitor
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): OPA330 OPA2330 OPA4330
OPA330
3V
1MW60kW
100kW
1MW
NTC
Thermistor
IN-
IN+
OUT
VS-
V +
S
C3
B2
A3
C1
A1
YFFPACKAGE
WCSP-5
(TOPVIEW)
(Bumpsidedown;
nottoscale)
ActualSize:
ExactSize(max):
0,862mmx1,156mm
YFFPACKAGE
WCSP-5EnlargedImage
(TopView)
(Bumpsidedown)
PackageMarkingCode:
YMD=year/month/day
TBD=indicatesOPA330AIYFF
S=forengineeringpurposesonly
YMDTBDS
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
RNare operational resistors used to isolate the Following these guidelines reduces the likelihood of
ADS1100 from the noise of the digital I2C bus. junctions being at different temperatures, which can
Because the ADS1100 is a 16-bit converter, a precise cause thermoelectric voltages of 0.1μV/°C or higher,
reference is essential for maximum accuracy. If depending on materials used.
absolute accuracy is not required, and the 5V power
supply is sufficiently stable, the REF3130 may be OPA330 WCSP
omitted. The OPA330 YFF package is a lead- (Pb-) free,
Figure 23 shows the OPA330 in a typical thermistor die-level, wafer chip-scale package (WCSP). Unlike
circuit. devices that are in plastic packages, these devices
have no molding compound, lead frame, wire bonds,
or leads. Using standard surface-mount assembly
procedures, the WCSP can be mounted to a printed
circuit board (PCB) without additional underfill.
Figure 24 and Figure 25 detail the pinout and
package marking, respectively. See the NanoStar™
and NanoFree™300μm Solder Bump WCSP
Application Note (SBVA017) for more detailed
information on package characteristics and PCB
design.
Figure 23. Thermistor Measurement
GENERAL LAYOUT GUIDELINES
Attention to good layout practice is always
recommended. Keep traces short and, when
possible, use a printed circuit board (PCB) ground
plane with surface-mount components placed as
close to the device pins as possible. Place a 0.1μF
capacitor closely across the supply pins. These
guidelines should be applied throughout the analog
circuit to improve performance and provide benefits
such as reducing the electromagnetic interference Figure 24. WCSP Pin Description
(EMI) susceptibility.
For lowest offset voltage and precision performance,
circuit layout and mechanical conditions should be
optimized. Avoid temperature gradients that create
thermoelectric (Seebeck) effects in the thermocouple
junctions formed from connecting dissimilar
conductors. These thermally-generated potentials can
be made to cancel by assuring they are equal on
both input terminals. Other layout and design
considerations include:
•Use low thermoelectric-coefficient conditions
(avoid dissimilar metals).
•Thermally isolate components from power Figure 25. YFF Package Marking
supplies or other heat sources.
•Shield op amp and input circuitry from air
currents, such as cooling fans.
12 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA330 OPA2330 OPA4330
OPA330
OPA2330
OPA4330
www.ti.com
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
PHOTOSENSITIVITY The QFN and DFN package can be easily mounted
using standard PCB assembly techniques. See
Although the OPA330 YFF package has a protective Application Note QFN/SON PCB Attachment
backside coating that reduces the amount of light (SLUA271) and Application Report Quad Flatpack
exposure on the die, unless fully shielded, ambient No-Lead Logic Packages (SCBA017), both available
light can reach the active region of the device. Input for download at www.ti.com.
bias current for the package is specified in the
absence of light. Depending on the amount of light The exposed leadframe die pad on the bottom of
exposure in a given application, an increase in bias the package should be connected to V–.
current, and possible increases in offset voltage
should be expected. Fluorescent lighting may QFN AND DFN LAYOUT GUIDELINES
introduce noise or hum because of the time-varying The leadframe die pad should be soldered to a
light output. Best layout practices include end-product thermal pad on the PCB. A mechanical data sheet
packaging that provides shielding from possible light showing an example layout is attached at the end of
sources during operation. this data sheet. Refinements to this layout may be
required based on assembly process requirements.
QFN AND DFN PACKAGES Mechanical drawings located at the end of this data
The OPA4330 is offered in a QFN package. The sheet list the physical dimensions for the package
OPA2330 is available in a DFN-8 package (also and pad. The five holes in the landing pattern are
known as SON), which is a QFN package with lead optional, and are intended for use with thermal vias
contacts on only two sides of the bottom of the that connect the leadframe die pad to the heatsink
package. These leadless, near-chip-scale packages area on the PCB.
maximize board space and enhance thermal and Soldering the exposed pad significantly improves
electrical characteristics through an exposed pad. board-level reliability during temperature cycling, key
QFN and DFN packages are physically small, have a push, package shear, and similar board-level tests.
smaller routing area, improved thermal performance, Even with applications that have low-power
and improved electrical parasitics, with a pinout dissipation, the exposed pad must be soldered to the
scheme that is consistent with other commonly-used PCB to provide structural integrity and long-term
packages, such as SOIC and MSOP. Additionally, the reliability.
absence of external leads eliminates bent-lead
issues.
©2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): OPA330 OPA2330 OPA4330
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008–REVISED FEBRUARY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2010) to Revision E Page
•Changed document status from Mixed Status to Production Data ....................................................................................... 1
•Deleted footnote 2 from the Package Information table ....................................................................................................... 2
•Added remaining thermal information data ........................................................................................................................... 3
Changes from Revision C (October 2009) to Revision D Page
•Added last Applications bullet ............................................................................................................................................... 1
•Deleted footnote 1 from Product Family Package Comparison table ................................................................................... 1
•Deleted footnote 2 and shading from all packages except QFN-14; moved WCSP-5, SOIC-14, and TSSOP-14
packages to Production Data status; and added package marking information to Package Information table ................... 2
•Added OPA330YFF, OPA4330 Input Bias Current parameter to Electrical Characteristics table ....................................... 4
•Added Input Voltage Range, OPA330YFF, OPA4330 Common-Mode Rejection Ratio parameter to Electrical
Characteristics table ............................................................................................................................................................. 4
•Moved TSSOP-14 thermal resistance to MSOP-8, SOIC-8 thermal resistance parameter in Electrical Characteristics
table ...................................................................................................................................................................................... 5
•Deleted SOIC-14 and QFN-14 rows from Temperature Range section in Electrical Characteristics table .......................... 5
14 Submit Documentation Feedback ©2008–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA330 OPA2330 OPA4330
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA2330AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
OPA2330AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
OPA2330AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
OPA2330AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
OPA2330AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2330AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA330AIDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDCKT ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA330AIYFFR ACTIVE DSBGA YFF 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
OPA330AIYFFT ACTIVE DSBGA YFF 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
OPA4330AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4330AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4330AIPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4330AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4330AIRGYR ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4330AIRGYT ACTIVE VQFN RGY 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA2330AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2330AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2330AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2330AIDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA2330AIDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA330AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA330AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA330AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA330AIDCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
OPA330AIDCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
OPA330AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA330AIYFFR DSBGA YFF 5 3000 180.0 8.4 0.97 1.27 0.73 4.0 8.0 Q1
OPA330AIYFFT DSBGA YFF 5 250 180.0 8.4 0.97 1.27 0.73 4.0 8.0 Q1
OPA4330AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4330AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
OPA4330AIRGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
OPA4330AIRGYT VQFN RGY 14 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2330AIDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
OPA2330AIDGKT VSSOP DGK 8 250 364.0 364.0 27.0
OPA2330AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA2330AIDRBR SON DRB 8 3000 367.0 367.0 35.0
OPA2330AIDRBT SON DRB 8 250 210.0 185.0 35.0
OPA330AIDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA330AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA330AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA330AIDCKR SC70 DCK 5 3000 203.0 203.0 35.0
OPA330AIDCKT SC70 DCK 5 250 203.0 203.0 35.0
OPA330AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA330AIYFFR DSBGA YFF 5 3000 210.0 185.0 35.0
OPA330AIYFFT DSBGA YFF 5 250 210.0 185.0 35.0
OPA4330AIDR SOIC D 14 2500 367.0 367.0 38.0
OPA4330AIPWR TSSOP PW 14 2000 367.0 367.0 35.0
OPA4330AIRGYR VQFN RGY 14 3000 367.0 367.0 35.0
OPA4330AIRGYT VQFN RGY 14 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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