OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com 50V VOS, 0.25V/C, 35A CMOS OPERATIONAL AMPLIFIERS Zero-Drift Series Check for Samples: OPA330, OPA2330, OPA4330 FEATURES DESCRIPTION * * * * * * * * * The OPA330 series of CMOS operational amplifiers offer precision performance at a very competitive price. These devices are members of the Zero-Drift family of amplifiers which use a proprietary auto-calibration technique to simultaneously provide low offset voltage (50V max) and near-zero drift over time and temperature at only 35A (max) of quiescent current. The OPA330 family features rail-to-rail input and output in addition to near flat 1/f noise, making this amplifier ideal for many applications and much easier to design into a system. These devices are optimized for low-voltage operation as low as +1.8V (0.9V) and up to +5.5V (2.75V). 1 23 UNMATCHED PRICE PERFORMANCE LOW OFFSET VOLTAGE: 50V (max) ZERO DRIFT: 0.25V/C (max) LOW NOISE: 1.1VPP, 0.1Hz to 10Hz QUIESCENT CURRENT: 35A (max) SUPPLY VOLTAGE: 1.8V to 5.5V RAIL-TO-RAIL INPUT/OUTPUT INTERNAL EMI FILTERING microSIZE PACKAGES: WCSP, SC70, QFN APPLICATIONS * * * * * * * BATTERY-POWERED INSTRUMENTS TEMPERATURE MEASUREMENTS TRANSDUCER APPLICATIONS ELECTRONIC SCALES MEDICAL INSTRUMENTATION HANDHELD TEST EQUIPMENT CURRENT SENSE The OPA330 (single version) is available in the WCSP-5, SC70-5, SOT23-5, and SOIC-8 packages. The OPA2330 (dual version) is offered in DFN-8 (3mm x 3mm), MSOP-8, and SOIC-8 packages. The OPA4330 is offered in the standard SOIC-14 and TSSOP-14 packages, as well as in the space-saving VQFN-14 package. All versions are specified for operation from -40C to +125C. PRODUCT FAMILY PACKAGE COMPARISON PACKAGE-LEADS DEVICE NO OF CHANNELS WCSP SOIC SOT23 SC70 MSOP QFN TSSOP OPA330 1 5 8 5 5 - - - OPA2330 2 - 8 - - 8 8 - OPA4330 4 - 14 - - - 14 14 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. (c) 2008-2011, Texas Instruments Incorporated OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING SOT23-5 DBV OCFQ SC70-5 DCK CHL SOIC-8 D O330A WCSP-5 YFF OEH SOIC-8 D O2330A OCGQ OPA330 OPA2330 OPA4330 (1) DFN-8 DRB MSOP-8 DGK OCGQ SOIC-14 D O4330A TSSOP-14 PW O4330A QFN-14 RGY 4330A For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply Voltage, VS = (V+) - (V-) Signal Input Terminals, Voltage (2) Signal Input Terminals, Current (2) OPA330, OPA2330, OPA4330 UNIT +7 V (V-) -0.3 to (V+) + 0.3 V 10 mA Output Short-Circuit (3) Continuous Operating Temperature -40 to +150 C Storage Temperature -65 to +150 C Junction Temperature +150 C Human Body Model (HBM) 4000 V Charged Device Model (CDM) 1000 V Machine Model (MM) 400 V ESD Ratings: (1) (2) (3) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should be current limited to 10mA or less. Short-circuit to ground, one amplifier per package. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com THERMAL INFORMATION THERMAL METRIC (1) OPA330AID(R) OPA330AIDBVR(T) OPA330AIDCKR(T) D DBV DCK OPA330AIYFF YFF 8 PINS 5 PINS 5 PINS 5 PINS JA Junction-to-ambient thermal resistance 140.1 220.8 298.4 130 JCtop Junction-to-case (top) thermal resistance 89.8 97.5 65.4 54 JB Junction-to-board thermal resistance 80.6 61.7 97.1 51 JT Junction-to-top characterization parameter 28.7 7.6 0.8 1 JB Junction-to-board characterization parameter 80.1 61.1 95.5 50 JCbot Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a (1) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. THERMAL INFORMATION THERMAL METRIC (1) OPA2330AID(R) OPA2330AIDGKR(T) D DGK OPA2330AIDRBR(T) DRB 8 PINS 8 PINS 8 PINS JA Junction-to-ambient thermal resistance 124.0 180.3 46.7 JCtop Junction-to-case (top) thermal resistance 73.7 48.1 26.3 JB Junction-to-board thermal resistance 64.4 100.9 22.2 JT Junction-to-top characterization parameter 18.0 2.4 1.6 JB Junction-to-board characterization parameter 63.9 99.3 22.3 JCbot Junction-to-case (bottom) thermal resistance n/a n/a 10.1 (1) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. THERMAL INFORMATION THERMAL METRIC (1) OPA4330AID OPA4330AIPW D PW OPA4330AIRGY RGY 14 PINS 14 PINS 14 PINS JA Junction-to-ambient thermal resistance 83.8 120.8 49.2 JCtop Junction-to-case (top) thermal resistance 70.7 34.3 75.3 JB Junction-to-board thermal resistance 59.5 62.8 61.9 JT Junction-to-top characterization parameter 11.6 1.0 1.2 JB Junction-to-board characterization parameter 37.7 56.5 19.3 JCbot Junction-to-case (bottom) thermal resistance n/a n/a 4.6 (1) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 3 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V Boldface limits apply over the specified temperature range, TA = -40C to +125C. At TA = +25C, RL = 10k connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OPA330, OPA2330, OPA4330 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE Input Offset Voltage VOS vs Temperature dVOS/dT vs Power Supply PSRR VS = +5V VS = +1.8V to +5.5V Long-Term Stability (1) 8 50 V 0.02 0.25 V/C 1 10 V/V See Channel Separation, dc (1) V/V 0.1 INPUT BIAS CURRENT Input Bias Current IB Input Bias Current: OPA330YFF, OPA4330 500 70 300 300 over Temperature Input Offset Current 200 IOS Input Offset Current: OPA330YFF, OPA4330 pA pA pA 400 1000 pA 140 600 pA NOISE Input Voltage Noise Density f = 1kHz 55 nV/Hz Input Voltage Noise f = 0.01Hz to 1Hz 0.3 VPP Input Voltage Noise f = 0.1Hz to 10Hz 1.1 VPP f = 10Hz 100 fA/Hz Input Current Noise en in INPUT VOLTAGE RANGE Common-Mode Voltage Range (V-) - 0.1 VCM (V+) + 0.1 V (V-) - 0.1V < VCM < (V+) + 0.1V 100 115 dB (V-) - 0.1V < VCM < (V+) + 0.1V, VS = 5.5V 100 115 dB Differential 2 pF Common-Mode 4 pF 115 dB Common-Mode Rejection Ratio CMRR Common-Mode Rejection Ratio: OPA330YFF, OPA4330 INPUT CAPACITANCE OPEN-LOOP GAIN Open-Loop Voltage Gain AOL (V-) + 100mV < VO < (V+) - 100mV, RL = 10k 100 FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate GBW SR CL = 100pF 350 kHz G = +1 0.16 V/s OUTPUT Voltage Output Swing from Rail 30 100 Short-Circuit Current ISC 5 Capacitive Load Drive CL See Typical Characteristics Open-Loop Output Impedance f = 350kHz, IO = 0 mV mA 2 k POWER SUPPLY Specified Voltage Range Quiescent Current Per Amplifier Turn-On Time (1) 4 VS IQ 1.8 IO = 0 21 VS = +5V 100 5.5 V 35 A s 300-hour life test at +150C demonstrated randomly distributed variation of approximately 1V. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V (continued) Boldface limits apply over the specified temperature range, TA = -40C to +125C. At TA = +25C, RL = 10k connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OPA330, OPA2330, OPA4330 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE RANGE Specified Range -40 +125 C Operating Range -40 +150 C Storage Range -65 +150 JA Thermal Resistance C C/W SOT23-5 200 C/W MSOP-8, SOIC-8, TSSOP-14 150 C/W DFN-8 50 C/W SC70-5 250 C/W WCSP-5 130 C/W PIN CONFIGURATIONS OPA330 SOT23-5 (TOP VIEW) OUT 1 V- 2 +IN 3 OPA330 SC70-5 (TOP VIEW) 5 V+ 4 -IN +IN 1 V- 2 -IN 3 OPA330 SOIC-8 (TOP VIEW) (1) V+ 4 OUT OPA330 WCSP-5 (TOP VIEW) C3 (1) 1 8 NC -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC NC 5 C1 OUT INB2 VSA3 VS+ (1) (1) A1 IN+ NC denotes no internal connection. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 5 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com PIN CONFIGURATIONS, CONTINUED OPA2330 SOIC-8, MSOP-8 (TOP VIEW) 8 V+ 7 OUT B A -IN A 2 +IN A 3 6 -IN B V- 4 5 +IN B B OUT A 1 -IN A 2 +IN A 3 V- 4 OPA4330 SOIC-14 (TOP VIEW) +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C 9 -IN C -IN B 6 OUT B 7 D C 8 OUT C -IN A 2 +IN A 3 V+ 4 +IN B 5 -IN B 6 OPA4330 TSSOP-14 (TOP VIEW) 6 OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C (2) OUT D -IN D 14 13 V+ 7 OUT B 6 -IN B 5 +IN B Exposed Thermal Die Pad on Underside 13 -IN D 12 +IN D 11 V- 10 +IN C 9 -IN C (2) 8 2 OUT C OUT D -IN A OUT A 14 1 1 B 8 OPA4330 QFN-14 (TOP VIEW) OUT A A Exposed Thermal Die Pad on (2) Underside 7 1 OUT B OUT A OPA2330 DFN-8 (TOP VIEW) Connect thermal die pad to V-. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, CL = 0pF, RL = 10k connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OFFSET VOLTAGE PRODUCTION DISTRIBUTION OPEN-LOOP GAIN vs FREQUENCY 120 250 100 200 AOL (dB) 150 Phase 60 100 40 50 Phase () Population 80 Gain 20 0 0 -50 -100 10 24.00 18.00 21.00 12.00 15.00 6.00 9.00 0 3.00 -3.00 -9.00 -6.00 -15.00 -12.00 -21.00 -18.00 -24.00 -20 100 1k 10k 100k 1M Frequency (Hz) Offset Voltage (mV) Figure 1. Figure 2. COMMON-MODE REJECTION RATIO vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY 140 120 120 100 +PSRR PSRR (dB) CMRR (dB) 100 80 60 -PSRR 80 60 40 40 20 20 0 0 1 10 100 1k 10k 100k 1 1M 10 100 Frequency (Hz) 10k 100k 1M Frequency (Hz) Figure 3. Figure 4. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 3 INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 210 VS = 2.75V VS = 0.9V 2 205 200 -40C +25C +125C 0 -IB 195 1 +25C IB (pA) Output Swing (V) 1k -40C -1 190 -190 +125C +25C -195 +IB -200 -2 -205 -40C -3 -210 0 1 2 3 4 5 6 7 8 9 10 0 1 Output Current (mA) Figure 5. 2 3 4 5 Common-Mode Voltage (V) Figure 6. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 7 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, CL = 0pF, RL = 10k connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. INPUT BIAS CURRENT vs TEMPERATURE 250 QUIESCENT CURRENT vs TEMPERATURE 25 -IB 200 VS = 5.5V -IB 150 20 100 VS = 1.8V VS = 5.5V VS = 1.8V 0 -50 15 IQ (mA) IB (pA) 50 10 -100 +IB -150 5 -200 +IB -250 -50 0 -25 0 25 50 75 100 125 -50 -25 25 50 75 Figure 8. LARGE-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE Output Voltage (50mV/div) Output Voltage (1V/div) Time (5ms/div) Figure 9. Figure 10. POSITIVE OVER-VOLTAGE RECOVERY NEGATIVE OVER-VOLTAGE RECOVERY 0 Input 2V/div Input 1V/div Output 10kW 0 0 10kW +2.5V +2.5V 1kW 1kW 1V/div 125 G = +1 RL = 10kW Time (50ms/div) 8 100 Figure 7. G=1 RL = 10kW 2V/div 0 Temperature (C) Temperature (C) 0 Output OPA330 OPA330 -2.5V -2.5V Time (50ms/div) Time (50ms/div) Figure 11. Figure 12. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, CL = 0pF, RL = 10k connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. SETTLING TIME vs CLOSED-LOOP GAIN SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 40 600 4V Step 35 30 400 Overshoot (%) Settling Time (ms) 500 300 200 0.001% 25 20 15 10 100 5 0.01% 0 0 1 10 10 100 100 1000 Load Capacitance (pF) Gain (dB) Figure 13. Figure 14. 0.1Hz TO 10Hz NOISE CURRENT AND VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 500nV/div 1000 Continues with no 1/f (flicker) noise. Current Noise 100 100 Voltage Noise 10 10 1 1s/div Current Noise (fA/OHz) Voltage Noise (nV/OHz) 1000 10 100 1k 10k Frequency (Hz) Figure 15. Figure 16. INPUT BIAS CURRENT vs INPUT DIFFERENTIAL VOLTAGE 50 Input Bias Current (mA) 40 30 Normal Operating Range (see the Input Differential Voltage section in the Applications Information) 20 10 0 -10 -20 -30 Over-Driven Condition Over-Driven Condition -40 -50 -1V -800 -600 -400 -200 0 200 400 600 800 Input Differential Voltage (mV) Figure 17. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 9 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com APPLICATIONS INFORMATION The OPA330, OPA2330, and OPA4330 are unity-gain stable, precision operational amplifiers free from unexpected output and phase reversal. The use of proprietary Zero-Drift circuitry gives the benefit of low input offset voltage over time and temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these devices work well in applications that run directly from battery power without regulation. The OPA330 family is optimized for low-voltage, single-supply operation. These miniature, high-precision, low quiescent current amplifiers offer high-impedance inputs that have a common-mode range 100mV beyond the supplies and a rail-to-rail output that swings within 100mV of the supplies under normal test conditions. The OPA330 series are precision amplifiers for cost-sensitive applications. INPUT DIFFERENTIAL VOLTAGE The typical input bias current of the OPA330 during normal operation is approximately 200pA. In over-driven conditions, the bias current can increase significantly (see Figure 17).The most common cause of an over-driven condition occurs when the op amp is outside of the linear range of operation. When the output of the op amp is driven to one of the supply rails the feedback loop requirements cannot be satisfied and a differential input voltage develops across the input pins. This differential input voltage results in activation of parasitic diodes inside the front end input chopping switches that combine with 10k electromagnetic interference (EMI) filter resistors to create the equivalent circuit shown in Figure 19. Notice that the input bias current remains within specification within the linear region. OPERATING VOLTAGE The OPA330 series op amps can be used with single or dual supplies from an operating range of VS = +1.8V (0.9V) up to +5.5V (2.75V). Supply voltages greater than +7V can permanently damage the device. See the Absolute Maximum Ratings table. Key parameters that vary over the supply voltage or temperature range are shown in the Typical Characteristics section of this data sheet. 10kW Clamp +In CORE -In 10kW Figure 19. Equivalent Input Circuit INTERNAL OFFSET CORRECTION INPUT VOLTAGE The OPA330, OPA2330, and OPA4330 input common-mode voltage range extends 0.1V beyond the supply rails. The OPA330 is designed to cover the full range without the troublesome transition region found in some other rail-to-rail amplifiers. Typically, input bias current is about 200pA; however, input voltages exceeding the power supplies can cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input current is limited to 10mA. This limitation is easily accomplished with an input resistor, as shown in Figure 18. Current-limiting resistor required if input voltage exceeds supply rails by 0.3V. IOVERLOAD 10mA max +5V VOUT OPA330 VIN 5kW The OPA330, OPA2330, and OPA4330 op amps use an auto-calibration technique with a time-continuous 125kHz op amp in the signal path. This amplifier is zero-corrected every 8s using a proprietary technique. Upon power-up, the amplifier requires approximately 100s to achieve specified VOS accuracy. This design has no aliasing or flicker noise. EMI SUSCEPTIBILITY AND INPUT FILTERING Operational amplifiers vary in their susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output may shift from its nominal value while the EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA330 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of approximately 8MHz (-3dB), with a roll-off of 20dB per decade. Figure 18. Input Current Protection 10 Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com ACHIEVING OUTPUT SWING TO THE OP AMP NEGATIVE RAIL Some applications require output voltage swings from 0V to a positive full-scale voltage (such as +2.5V) with excellent accuracy. With most single-supply op amps, problems arise when the output signal approaches 0V, near the lower output swing limit of a single-supply op amp. A good single-supply op amp may swing close to single-supply ground, but will not reach ground. The output of the OPA330, OPA2330, and OPA4330 can be made to swing to ground, or slightly below, on a single-supply power source. To do so requires the use of another resistor and an additional, more negative, power supply than the op amp negative supply. A pull-down resistor may be connected between the output and the additional negative supply to pull the output down below the value that the output would otherwise achieve, as shown in Figure 20. The OPA330, OPA2330, and OPA4330 have an output stage that allows the output voltage to be pulled to its negative supply rail, or slightly below, using the technique previously described. This technique only works with some types of output stages. The OPA330, OPA2330, and OPA4330 have been characterized to perform with this technique; the recommended resistor value is approximately 20k. Note that this configuration will increase the current consumption by several hundreds of microamps. Accuracy is excellent down to 0V and as low as -2mV. Limiting and nonlinearity occurs below -2mV, but excellent accuracy returns as the output is again driven above -2mV. Lowering the resistance of the pull-down resistor will allow the op amp to swing even further below the negative rail. Resistances as low as 10k can be used to achieve excellent accuracy down to -10mV. APPLICATION CIRCUITS Figure 21 shows the basic configuration for a bridge amplifier. V+ = +5V OPA330 A low-side current shunt monitor is shown in Figure 22. VOUT VIN RP = 20kW VEX R1 Op Amp V- = GND -5V Additional Negative Supply +5V R R R R VOUT OPA330 Figure 20. For VOUT Range to Ground R1 VREF Figure 21. Single Op Amp Bridge Amplifier +5V REF3130 3V Load R1 4.99kW R2 49.9kW R6 71.5kW V ILOAD RSHUNT 1W RN 56W OPA330 R3 4.99kW Stray Ground-Loop Resistance R4 48.7kW ADS1100 R7 1.18kW RN 56W 2 IC (PGA Gain = 4) FS = 3.0V NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors. Figure 22. Low-Side Current Monitor Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 11 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 RN are operational resistors used to isolate the ADS1100 from the noise of the digital I2C bus. Because the ADS1100 is a 16-bit converter, a precise reference is essential for maximum accuracy. If absolute accuracy is not required, and the 5V power supply is sufficiently stable, the REF3130 may be omitted. Figure 23 shows the OPA330 in a typical thermistor circuit. 100kW 1MW 3V 1MW 60kW NTC Thermistor OPA330 www.ti.com Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause thermoelectric voltages of 0.1V/C or higher, depending on materials used. OPA330 WCSP The OPA330 YFF package is a lead- (Pb-) free, die-level, wafer chip-scale package (WCSP). Unlike devices that are in plastic packages, these devices have no molding compound, lead frame, wire bonds, or leads. Using standard surface-mount assembly procedures, the WCSP can be mounted to a printed circuit board (PCB) without additional underfill. Figure 24 and Figure 25 detail the pinout and package marking, respectively. See the NanoStarTM and NanoFreeTM 300m Solder Bump WCSP Application Note (SBVA017) for more detailed information on package characteristics and PCB design. Figure 23. Thermistor Measurement YFF PACKAGE WCSP-5 (TOP VIEW) GENERAL LAYOUT GUIDELINES Attention to good layout practice is always recommended. Keep traces short and, when possible, use a printed circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1F capacitor closely across the supply pins. These guidelines should be applied throughout the analog circuit to improve performance and provide benefits such as reducing the electromagnetic interference (EMI) susceptibility. 12 C1 INB2 VSA3 A1 IN+ VS+ (Bump side down; not to scale) Figure 24. WCSP Pin Description YFF PACKAGE WCSP-5 Enlarged Image (Top View) Actual Size: Exact Size (max): 0,862 mm x 1,156 mm YMDTBDS For lowest offset voltage and precision performance, circuit layout and mechanical conditions should be optimized. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring they are equal on both input terminals. Other layout and design considerations include: * Use low thermoelectric-coefficient conditions (avoid dissimilar metals). * Thermally isolate components from power supplies or other heat sources. * Shield op amp and input circuitry from air currents, such as cooling fans. C3 OUT Package Marking Code: YMD = year/month/day TBD = indicates OPA330AIYFF S = for engineering purposes only (Bump side down) Figure 25. YFF Package Marking Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com PHOTOSENSITIVITY Although the OPA330 YFF package has a protective backside coating that reduces the amount of light exposure on the die, unless fully shielded, ambient light can reach the active region of the device. Input bias current for the package is specified in the absence of light. Depending on the amount of light exposure in a given application, an increase in bias current, and possible increases in offset voltage should be expected. Fluorescent lighting may introduce noise or hum because of the time-varying light output. Best layout practices include end-product packaging that provides shielding from possible light sources during operation. QFN AND DFN PACKAGES The OPA4330 is offered in a QFN package. The OPA2330 is available in a DFN-8 package (also known as SON), which is a QFN package with lead contacts on only two sides of the bottom of the package. These leadless, near-chip-scale packages maximize board space and enhance thermal and electrical characteristics through an exposed pad. QFN and DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SOIC and MSOP. Additionally, the absence of external leads eliminates bent-lead issues. The QFN and DFN package can be easily mounted using standard PCB assembly techniques. See Application Note QFN/SON PCB Attachment (SLUA271) and Application Report Quad Flatpack No-Lead Logic Packages (SCBA017), both available for download at www.ti.com. The exposed leadframe die pad on the bottom of the package should be connected to V-. QFN AND DFN LAYOUT GUIDELINES The leadframe die pad should be soldered to a thermal pad on the PCB. A mechanical data sheet showing an example layout is attached at the end of this data sheet. Refinements to this layout may be required based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability. Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 13 OPA330 OPA2330 OPA4330 SBOS432E - AUGUST 2008 - REVISED FEBRUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (June 2010) to Revision E Page * Changed document status from Mixed Status to Production Data ....................................................................................... 1 * Deleted footnote 2 from the Package Information table ....................................................................................................... 2 * Added remaining thermal information data ........................................................................................................................... 3 Changes from Revision C (October 2009) to Revision D Page * Added last Applications bullet ............................................................................................................................................... 1 * Deleted footnote 1 from Product Family Package Comparison table ................................................................................... 1 * Deleted footnote 2 and shading from all packages except QFN-14; moved WCSP-5, SOIC-14, and TSSOP-14 packages to Production Data status; and added package marking information to Package Information table ................... 2 * Added OPA330YFF, OPA4330 Input Bias Current parameter to Electrical Characteristics table ....................................... 4 * Added Input Voltage Range, OPA330YFF, OPA4330 Common-Mode Rejection Ratio parameter to Electrical Characteristics table ............................................................................................................................................................. 4 * Moved TSSOP-14 thermal resistance to MSOP-8, SOIC-8 thermal resistance parameter in Electrical Characteristics table ...................................................................................................................................................................................... 5 * Deleted SOIC-14 and QFN-14 rows from Temperature Range section in Electrical Characteristics table .......................... 5 14 Submit Documentation Feedback (c) 2008-2011, Texas Instruments Incorporated Product Folder Link(s): OPA330 OPA2330 OPA4330 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp OPA2330AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM OPA2330AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM OPA2330AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM OPA2330AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM OPA2330AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA2330AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) OPA330AIDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA330AIYFFR ACTIVE DSBGA YFF 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM OPA330AIYFFT ACTIVE DSBGA YFF 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM OPA4330AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4330AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4330AIPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4330AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4330AIRGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4330AIRGYT ACTIVE VQFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing OPA2330AIDGKR VSSOP DGK 8 OPA2330AIDGKT VSSOP DGK OPA2330AIDR SOIC D OPA2330AIDRBR SON OPA2330AIDRBT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 OPA330AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA330AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA330AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA330AIDCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA330AIDCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA330AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA330AIYFFR DSBGA YFF 5 3000 180.0 8.4 0.97 1.27 0.73 4.0 8.0 Q1 OPA330AIYFFT DSBGA YFF 5 250 180.0 8.4 0.97 1.27 0.73 4.0 8.0 Q1 OPA4330AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4330AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4330AIRGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 OPA4330AIRGYT VQFN RGY 14 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2330AIDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 OPA2330AIDGKT VSSOP DGK 8 250 364.0 364.0 27.0 OPA2330AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA2330AIDRBR SON DRB 8 3000 367.0 367.0 35.0 OPA2330AIDRBT SON DRB 8 250 210.0 185.0 35.0 OPA330AIDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 OPA330AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 OPA330AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 OPA330AIDCKR SC70 DCK 5 3000 203.0 203.0 35.0 OPA330AIDCKT SC70 DCK 5 250 203.0 203.0 35.0 OPA330AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA330AIYFFR DSBGA YFF 5 3000 210.0 185.0 35.0 OPA330AIYFFT DSBGA YFF 5 250 210.0 185.0 35.0 OPA4330AIDR SOIC D 14 2500 367.0 367.0 38.0 OPA4330AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 OPA4330AIRGYR VQFN RGY 14 3000 367.0 367.0 35.0 OPA4330AIRGYT VQFN RGY 14 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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