+
–
IN –
OUT
IN +
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
LF353 Wide-Bandwidth JFET-Input Dual Operational Amplifier
1
1 Features
1• Low Input Bias Current 50 pA Typical
• Low Input Noise Current 0.01 pA/√Hz Typical
• Low Supply Current 3.6 mA Typical
• High Input Impedance 1012 ΩTypical
• Internally-Trimmed Offset Voltage
• Gain Bandwidth 3 MHz Typical
• High Slew Rate 13 V/µs Typical
2 Applications
• Motor Integrated Systems: UPS
• Drives and Control Solutions: AC Inverter and VF
Drives
• Renewables: Solar Inverters
• Pro Audio Mixers
• Oscilloscopes
3 Description
This LF353 device is a low-cost, high-speed, JFET-
input operational amplifier with very low input offset
voltage. It requires low supply current yet maintains a
large gain-bandwidth product and a fast slew rate. In
addition, the matched high-voltage JFET input
provides very low input bias and offset currents.
The LF353 can be used in applications such as high-
speed integrators, digital-to-analog converters,
sample-and-hold circuits, and many other circuits.
The LF353 is characterized for operation from 0°C to
70°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LF353D SOIC (8) 4.90 mm × 3.91 mm
LF353P PDIP (8) 9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Symbol
2
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
www.ti.com
Product Folder Links: LF353
Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 6
7 Parameter Measurement Information .................. 7
8 Detailed Description.............................................. 8
8.1 Overview................................................................... 8
8.2 Functional Block Diagram......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application.................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support................. 12
12.1 Documentation Support ........................................ 12
12.2 Community Resources.......................................... 12
12.3 Trademarks........................................................... 12
12.4 Electrostatic Discharge Caution............................ 12
12.5 Glossary................................................................ 12
13 Mechanical, Packaging, and Orderable
Information........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 1994) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
1
2
3
4
8
7
6
5
1OUT
1IN –
1IN +
VCC –
VCC +
2OUT
2IN –
2IN +
3
LF353
www.ti.com
SLOS012C –MARCH 1987–REVISED MARCH 2016
Product Folder Links: LF353
Submit Documentation FeedbackCopyright © 1987–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
D or P Package
8-Pin SOIC or PDIP
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
1OUT 1 O Output
1IN- 2 I Inverting input
1IN+ 3 I Noninverting input
VCC- 4 — Negative supply voltage
2IN+ 5 I Noninverting input
2IN- 6 I Inverting input
2OUT 7 O Output
VCC+ 8 — Positive supply voltage
4
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
www.ti.com
Product Folder Links: LF353
Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC+ Supply voltage 18 V
VCC– Supply voltage –18 V
VID Differential input voltage ±30 V
VI Input voltage(2) ±15 V
Duration of output short circuit Unlimited s
Continuous total power dissipation 500 mW
Lead temperature 1.6 mm (1/16 inch) from case for 10 s 260 °C
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC+ Supply voltage 3.5 18 V
VCC– Supply voltage –3.5 –18 V
VCM Common-mode voltage VCC– + 4 VCC+ – 4 V
TAOperating temperature 0 70 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1) LF353
UNITD (SOIC) P (PDIP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 106.6 55.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.5 45 °C/W
RθJB Junction-to-board thermal resistance 46.5 32.2 °C/W
ψJT Junction-to-top characterization parameter 9.8 22.6 °C/W
ψJB Junction-to-board characterization parameter 46.1 32.2 °C/W
5
LF353
www.ti.com
SLOS012C –MARCH 1987–REVISED MARCH 2016
Product Folder Links: LF353
Submit Documentation FeedbackCopyright © 1987–2016, Texas Instruments Incorporated
(1) Full range is 0°C to 70°C
(2) Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse
techniques must be used that will maintain the junction temperatures as close to the ambient temperature as possible.
(3) Supply-voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously.
6.5 Electrical Characteristics
TA= 0°C to 70°C, VCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VIC = 0, RS= 10 kΩTA= 25°C 5 10 mV
Full range(1) 13
αVIO Average temperature coefficient
of inputs offset voltage VIC = 0, RS= 10 kΩ10 µV/°C
IIO Input offset current(2) VIC = 0 TA= 25°C 25 100 pA
TA= 70°C 4 nA
IIB Input bias current(2) VIC = 0 TA= 25°C 50 200 pA
TA= 70°C 8 nA
VICR Common-mode input voltage
range Lower limit of range –11 –12 V
Upper limit of range 11 15
VOM Maximum peak output voltage
swing RL= 10 kΩ±12 ±13.5 V
AVD Large-signal differential voltage VO= ±10 V, RL= 2 kΩTA= 25°C 25 100 V/mV
Full range(1) 15
riInput resistance TJ= 25°C 1012 Ω
CMRR Common-mode rejection ratio RS≤10 kΩ70 100 dB
kSVR Supply-voltage rejection ratio See (3) 70 100 dB
ICC Supply current 3.6 6.5 mA
6.6 Switching Characteristics
VCC± = ±15 V, TA= 25°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO1/VO2 Crosstalk attenuation f = 1 kHz 120 dB
SR Slew rate 8 13 V/µs
B1 Unity-gain bandwidth 3 MHz
VnEquivalent input noise voltage f = 1 kHz, RS= 20 Ω18 nV/√Hz
InEquivalent input noise current f = 1 kHz 0.01 pA/√Hz
6
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
www.ti.com
Product Folder Links: LF353
Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated
6.7 Typical Characteristics
Figure 1. Maximum Peak Output Voltage vs Frequency Figure 2. Maximum Peak Output Voltage vs Load
Resistance
Figure 3. Large-Signal Differential Voltage Amplification
and Phase Shift vs Frequency
8
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
www.ti.com
Product Folder Links: LF353
Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The LF353 device is a JFET-input operational amplifier with low input bias and offset currents and fast slew rate.
Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on
a single monolithic chip. The output is protected against shorts due to the resistive 200-Ωoutput impedance.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 13-V/μs slew rate.
8.4 Device Functional Modes
These devices are powered on when the supply is connected. This device can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.
V
RF
A =
RI
-
V
1.8
A = 3.6
0.5
= -
-
V
VOUT
A =
VIN
Vsup+
+VOUT
RF
VIN
RI
Vsup-
9
LF353
www.ti.com
SLOS012C –MARCH 1987–REVISED MARCH 2016
Product Folder Links: LF353
Submit Documentation FeedbackCopyright © 1987–2016, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LF353 has two independent amplifiers that have very low input bias current which allow using higher
resistance resistors in the feedback network. The upper input common mode range goes to the upper supply rail.
The lower common mode range does not include the negative supply rail. Output resistance is 200 ohms to
protect the device from accidental shorts.
9.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on
the input, and makes it a negative voltage. In the same manner, it also makes negative voltages positive.
Figure 5. Inverting Amplifier
9.2.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
9.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2.
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩrange is desirable
because the amplifier circuit uses currents in the mA range. This ensures the part does draw too much current.
For this example, choose 10 kΩfor RI and 36 kΩfor RF, as shown in Equation 3.
(3)
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 0.5 1 1.5 2
Volts
Time (ms)
VIN
VOUT
10
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
www.ti.com
Product Folder Links: LF353
Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated
Typical Application (continued)
9.2.3 Application Curve
Figure 6. Input and Output Voltages of the Inverting Amplifier
10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a
dual-supply can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Example.
+
RIN
RG RF
VOUT
VIN
NC
VCC+
IN1í
IN1+
VCCí
NC
OUT
NC
RG
RIN
RF
GND
VIN
VS-GND
VS+
GND
Run the input traces as far
away from the supply lines
as possible
Only needed for
dual-supply
operation
Place components close to
device and to each other to
reduce parasitic errors
Use low-ESR, ceramic
bypass capacitor
(or GND for single supply) Ground (GND) plane on another layerVOUT
11
LF353
www.ti.com
SLOS012C –MARCH 1987–REVISED MARCH 2016
Product Folder Links: LF353
Submit Documentation FeedbackCopyright © 1987–2016, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use the following layout guidelines:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Figure 7. Operational Amplifier Board Layout for Noninverting Configuration
Figure 8. Operational Amplifier Schematic for Noninverting Configuration
12
LF353
SLOS012C –MARCH 1987–REVISED MARCH 2016
www.ti.com
Product Folder Links: LF353
Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see Circuit Board Layout Techniques (SLOA089).
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LF353D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LF353
LF353DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LF353
LF353DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LF353
LF353DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LF353
LF353P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 LF353P
LF353PE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 LF353P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LF353DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LF353DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LF353DR SOIC D 8 2500 367.0 367.0 35.0
LF353DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2016
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
