K70P256M150SF3
K70 Sub-Family
Supports the following:
MK70FX512VMJ15,
MK70FN1M0VMJ15
Key features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 150 MHz Arm® Cortex®-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 1024 KB program flash memory on non-
FlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– DDR controller interface
– NAND flash controller interface
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to 128
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Tamper detect and secure storage
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– Graphic LCD controller
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Two 8-channel motor control/general purpose/PWM
timers
– Two 2-channel quadrature decoder/general purpose
timers
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
NXP Semiconductors Document Number K70P256M150SF3
Data Sheet: Technical Data Rev. 7, 02/2018
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Communication interfaces
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– USB Device Charger detect (USBDCD)
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital Host Controller (SDHC)
– Two I2S modules
K70 Sub-Family, Rev. 7, 02/2018
2 NXP Semiconductors
Table of Contents
1 Ordering parts.......................................................................................5
1.1 Determining valid orderable parts............................................... 5
2 Part identification................................................................................. 5
2.1 Description...................................................................................5
2.2 Format..........................................................................................5
2.3 Fields............................................................................................5
2.4 Example....................................................................................... 6
3 Terminology and guidelines.................................................................6
3.1 Definitions................................................................................... 6
3.2 Examples......................................................................................6
3.3 Typical-value conditions..............................................................7
3.4 Relationship between ratings and operating requirements.......... 7
3.5 Guidelines for ratings and operating requirements......................8
4 Ratings..................................................................................................8
4.1 Thermal handling ratings.............................................................8
4.2 Moisture handling ratings............................................................ 9
4.3 ESD handling ratings...................................................................9
4.4 Voltage and current operating ratings..........................................9
5 General................................................................................................. 10
5.1 AC electrical characteristics........................................................ 10
5.2 Nonswitching electrical specifications........................................ 10
5.2.1 Voltage and current operating requirements............... 10
5.2.2 LVD and POR operating requirements....................... 12
5.2.3 Voltage and current operating behaviors.....................13
5.2.4 Power mode transition operating behaviors................ 16
5.2.5 Power consumption operating behaviors.....................17
5.2.6 EMC radiated emissions operating behaviors............. 20
5.2.7 Designing with radiated emissions in mind.................21
5.2.8 Capacitance attributes..................................................21
5.3 Switching specifications.............................................................. 21
5.3.1 Device clock specifications......................................... 21
5.3.2 General switching specifications.................................22
5.4 Thermal specifications.................................................................24
5.4.1 Thermal operating requirements..................................24
5.4.2 Thermal attributes........................................................24
5.5 Power sequencing........................................................................ 25
6 Peripheral operating requirements and behaviors................................ 25
6.1 Core modules............................................................................... 25
6.1.1 Debug trace timing specifications............................... 25
6.1.2 JTAG electricals.......................................................... 26
6.2 System modules........................................................................... 29
6.3 Clock modules............................................................................. 29
6.3.1 MCG specifications.....................................................29
6.3.2 Oscillator electrical specifications...............................32
6.3.3 32 kHz oscillator electrical characteristics..................34
6.4 Memories and memory interfaces................................................34
6.4.1 Flash (FTFE) electrical specifications.........................34
6.4.2 EzPort switching specifications...................................39
6.4.3 NAND flash controller specifications......................... 40
6.4.4 DDR controller specifications..................................... 43
6.4.5 Flexbus switching specifications.................................46
6.5 Security and integrity modules.................................................... 48
6.5.1 DryIce Tamper Electrical Specifications.....................48
6.6 Analog..........................................................................................49
6.6.1 ADC electrical specifications......................................49
6.6.2 CMP and 6-bit DAC electrical specifications............. 56
6.6.3 12-bit DAC electrical characteristics...........................58
6.6.4 Voltage reference electrical specifications..................61
6.7 Timers.......................................................................................... 62
6.8 Communication interfaces........................................................... 62
6.8.1 Ethernet switching specifications................................62
6.8.2 USB electrical specifications.......................................65
6.8.3 USB DCD electrical specifications............................. 65
6.8.4 USB VREG electrical specifications...........................66
6.8.5 ULPI timing specifications..........................................66
6.8.6 CAN switching specifications..................................... 67
6.8.7 DSPI switching specifications (limited voltage
range)...........................................................................67
6.8.8 DSPI switching specifications (full voltage range).....69
6.8.9 Inter-Integrated Circuit Interface (I2C) timing............71
6.8.10 UART switching specifications...................................72
6.8.11 SDHC specifications................................................... 72
6.8.12 I2S/SAI switching specifications................................ 73
6.9 Human-machine interfaces (HMI)...............................................80
6.9.1 TSI electrical specifications........................................ 80
6.9.2 LCDC electrical specifications....................................81
7 Dimensions...........................................................................................84
7.1 Obtaining package dimensions.................................................... 84
8 Pinout................................................................................................... 84
8.1 Pins with active pull control after reset....................................... 84
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 3
8.2 K70 Signal Multiplexing and Pin Assignments...........................84
8.3 K70 Pinouts..................................................................................94
9 Revision History...................................................................................95
K70 Sub-Family, Rev. 7, 02/2018
4 NXP Semiconductors
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: PK70 and MK70
2Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
K## Kinetis family • K70
A Key attribute • F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
FFF Program flash memory size • 512 = 512 KB
• 1M0 = 1 MB
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Ordering parts
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 5
Field Description Values
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) • 15 = 150 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK70FN1M0VMJ15
3Terminology and guidelines
3.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent
chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
K70 Sub-Family, Rev. 7, 02/2018
6 NXP Semiconductors
3.2 Examples
Operating rating:
Operating requirement:
Operating behavior that includes a typical value:
EXAMPLE
EXAMPLEEXAMPLE
EXAMPLE
3.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD Supply voltage 3.3 V
Terminology and guidelines
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 7
3.4 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
4Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Ratings
K70 Sub-Family, Rev. 7, 02/2018
8 NXP Semiconductors
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage1–0.3 3.8 V
VDD_INT Core supply voltage –0.3 3.8 V
VDD_DDR DDR I/O supply voltage –0.3 3.8 V
IDD Digital supply current — 300 mA
IDD_INT Core supply current — 185 mA
IDD_DDR DDR supply current — 220 mA
VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2–0.3 5.5 V
VDDDR DDR input voltage –0.3 VDD_DDR + 0.3 V
VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB1_DP USB1_DP input voltage –0.3 3.63 V
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Ratings
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 9
Symbol Description Min. Max. Unit
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VUSB1_DM USB1_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. It applies for all port pins except Tamper pins.
2. It covers digital pins except Tamper pins and DDR pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
General
K70 Sub-Family, Rev. 7, 02/2018
10 NXP Semiconductors
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage max [VDD_DDR, 1.71 V] 3.6 V
VDD_INT Core supply voltage 1.71 VDD V
VDD_DDR DDR voltage — memory I/O buffers
• DDR1
• DDR2/LPDDR1
2.3
1.71
2.7
1.9
V
V
VREF_DDR Input reference voltage (DDR1/DDR2/
LPDDR1)
0.49 × VDD_DDR VDD_DDR V1
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage (digital pins except
Tamper pins and DDR pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage (digital pins except Tamper
pins and DDR pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VIH_DDR Input high voltage (DDR pins)
• DDR1
• DDR2
• LPDDR1
VREF_DDR + 0.15
VREF_DDR + 0.125
0.7 × VDD_DDR
—
—
—
V
V
V
VIL_DDR Input low voltage (DDR pins)
• DDR1
• DDR2
• LPDDR1
—
—
—
VREF_DDR – 0.15
VREF_DDR – 0.125
0.3 × VDD_DDR
V
V
V
VHYS Input hysteresis (digital pins except Tamper
pins and DDR pins)
0.06 × VDD — V
IICDIO Digital pin (except Tamper pins) negative DC
injection current — single pin
• VIN < VSS-0.3V
-5 — mA
2
IICAIO Analog3, EXTAL0/XTAL0, and EXTAL1/
XTAL1 pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current
injection)
• VIN > VDD+0.3V (Positive current
injection)
-5
—
—
+5
mA
4
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General
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 11
Table 1. Voltage and current operating requirements (continued)
Symbol Description Min. Max. Unit Notes
IICcont Contiguous pin DC injection current —
regional limit, includes sum of negative
injection currents or sum of positive injection
currents of 16 contiguous pins
• Negative current injection
• Positive current injection
-25
—
—
+25
mA
VODPU Open drain pullup voltage level VDD VDD V5
VRAM VDD (VDD_INT) voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT
register file
VPOR_VBAT — V
1. For DDR1/DDR2, connect VREF_DDR to the same reference voltage used for the memory. For LPDDR1, connect VREF_DDR
to the VDD_DDR voltage.
2. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection
current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
4. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5. Open drain outputs must be pulled to VDD.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1.74
1.84
1.80
1.90
1.86
1.96
V
V
1
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General
K70 Sub-Family, Rev. 7, 02/2018
12 NXP Semiconductors
Table 2. LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW3L
VLVW4L
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.94
2.04
2.00
2.10
2.06
2.16
V
V
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period
factory trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT Output high current total for all ports — — 100 mA
IOHT_io60 Output high current total for fast digital ports — — 100 mA
VOH_DDR Output high voltage for DDR pins
• DDR1 (IOH = -16.2 mA)
• DDR2 half strength (IOH = -5.36 mA)
• DDR2 full strength (IOH = -13.4 mA)
• LPDDR1 half strength (IOH = -0.1 mA)
• LPDDR1 full strength (IOH = -0.1 mA)
VDD_DDR -
0.36
VDD_DDR -
0.28
VDD_DDR -
0.28
0.9 x
VDD_DDR
0.9 x
VDD_DDR
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
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General
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 13
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IOHT_DDR Output high current total for DDR pins
• DDR1
• DDR2
• LPDDR1
—
—
—
—
—
—
100
56
39
mA
mA
mA
VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
VBAT – 0.5
VBAT – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
VBAT – 0.5
VBAT – 0.5
—
—
—
—
V
V
IOH_Tamper Output high current total for Tamper pins — — 100 mA
VOL Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1 mA
—
—
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — — 100 mA
IOLT_io60 Output low current total for fast digital ports — — 100 mA
VOL_DDR Output low voltage for DDR pins
• DDR1 (IOL = 16.2 mA)
• DDR2 half strength (IOL = 5.36 mA)
• DDR2 full strength (IOL = 13.4 mA)
• LPDDR1 half strength (IOL = 0.1 mA)
• LPDDR1 full strength (IOL = 0.1 mA)
—
—
—
—
—
—
—
—
—
—
0.37
0.28
0.28
0.1 x
VDD_DDR
0.1 x
VDD_DDR
V
V
V
V
V
IOLT_DDR Output low current total for DDR pins
• DDR1
• DDR2
• LPDDR1
— — 100
56
39
mA
mA
mA
VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
—
—
—
—
0.5
0.5
V
V
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General
K70 Sub-Family, Rev. 7, 02/2018
14 NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IOL_Tamper Output low current total for Tamper pins — — 100 mA
IINA Input leakage current, analog pins and digital
pins configured as analog inputs
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
—
—
—
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
1, 2
IIND Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
• All digital pins
• VIN = VDD
• All digital pins except PTD7
• PTD7
—
—
—
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
2, 3
IIND Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
18
12
8
3
26
19
13
6
μA
μA
μA
μA
2, 3, 4
IIND Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
1
50
μA
2, 3
ZIND Input impedance examples, digital pins
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
2, 5
IIN_DDR Input leakage current (per DDR pin) for full
temperature range
— — 1 μA
IIN_DDR Input leakage current (per DDR pin) at 25°C — — 0.025 μA
IIN_Tamper Input leakage current (per Tamper pin) for full
temperature range
— — 1 μA
IIN_Tamper Input leakage current (per Tamper pin) at 25°C — — 0.025 μA
RPU Internal pullup resistors (except Tamper pins) 20 — 50 kΩ 6
RPD Internal pulldown resistors (except Tamper pins) 20 — 50 kΩ 7
RODT On-die termination (ODT) resistance for DDR2
• Rtt1(eff) - 75 Ω
• Rtt2(eff) - 150 Ω
60
120
—
—
90
180
Ω
Ω
General
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 15
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Characterized, not tested in production.
5. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See
Figure 2.
6. Measured at VDD supply voltage = VDD min and Vinput = VSS
7. Measured at VDD supply voltage = VDD min and Vinput = VDD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
—
—
300
1.7 V / (VDD
slew rate)
μs
1
• VLLS1 → RUN — 160 μs
• VLLS2 → RUN — 114 μs
Table continues on the next page...
General
K70 Sub-Family, Rev. 7, 02/2018
16 NXP Semiconductors
Table 5. Power mode transition operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
• VLLS3 → RUN — 114 μs
• LLS → RUN — 5.0 μs
• VLPS → RUN — 5 μs
• STOP → RUN — 4.8 μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
58.01
57.93
83.95
84.14
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
89.26
89.23
116.53
117.26
mA
mA
3
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 40.18 65.25 mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
— 18.08 42.96 mA 4
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
1.25
2.93
7.08
1.62
4.39
10.74
mA
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 1.03 4.48 mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 1.58 4.96 mA 5
IDD_VLPW Very-low-power wait mode current at 3.0 V — 0.64 4.29 mA 5
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C —
—
0.22
0.78
0.38
1.33
mA
mA
Table continues on the next page...
General
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 17
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• @ 70°C
• @ 105°C
— 2.18 3.56 mA
IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.22
0.78
2.16
0.37
1.33
3.52
mA
mA
mA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
4.09
20.98
84.95
5.58
28.93
111.15
μA
μA
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.68
8.8
37.28
4.22
10.74
43.61
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.46
7.04
30.68
4.02
8.99
37.04
μA
μA
μA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.89
1.28
3.10
1.10
1.85
4.30
μA
μA
μA
6
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies.
General
K70 Sub-Family, Rev. 7, 02/2018
18 NXP Semiconductors
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
General
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 19
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol Description Frequency
band (MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 21 dBμV 1, 2, 3
VRE2 Radiated emissions voltage, band 2 50–150 24 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 29 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 28 dBμV
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 72 MHz, fBUS = 72 MHz
3. Determined according to IEC Standard JESD78, IC Latch-Up Test
General
K70 Sub-Family, Rev. 7, 02/2018
20 NXP Semiconductors
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
CIN_D_io60 Input capacitance: fast digital pins — 9 pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock — 150 MHz
fSYS_USBFS System and core clock when Full Speed USB in
operation
20 — MHz
fSYS_USBHS System and core clock when High Speed USB in
operation
60 — MHz
fENET System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
5
50
—
—
MHz
fBUS Bus clock — 75 MHz
FB_CLK FlexBus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fDDR DDR clock — 150 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
Table continues on the next page...
General
K70 Sub-Family, Rev. 7, 02/2018
NXP Semiconductors 21
Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
fFLASH Flash clock — 0.5 MHz
fLPTMR LPTMR clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
14
8
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
—
—
—