PLD Programming Information - Cypress Semiconductor

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PLD Programming Information

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

December 1991 – Revised March 17, 1997

1PLD Programming

Info rmatio n

Introduction

PLDs, or programmable logic devices, provide an attractive

alternative to logic implemented with discrete devices. Cy-

press Semic onductor is in the enviable po sition of being able

to offer PLDs in several different process technologies, thus

assuring our customers of a wide range of options for lead-

ing-edge s peed as well as very low power c onsumption. Cy-

press optimizes the mix o f technology and device a rchitecture

to insure that the programmable logic requirements of today’s

highest-performanc e electronics systems can be fully su pport-

ed by a single PLD vendor.

Cypress offers a wide variety of PLDs based on our lead-

ing-edge CMOS EPROM process techn ology . This te chnology

facilitates the lowest power co nsumption and the highest lo gic

density of any nonvolatile PLD technology on the market to-

day, at speeds that are as fast as state-of-the-art bipolar tech-

nology would provide. Furthermore, these devices offer the

user the option of device erasure and reprogrammability in

windowed packages. Cypress offers PLDs based on CMOS

Flash technology which features elect rical erasure and repro-

grammability. Thus Cypress offers solutions for

state-of-the-art systems regardless of what the optimal bal-

ance is between speed, power, and density for any particular

system.

Programmable Technology

EPROM Process Technology

EPROM technology employs a floating or isolated gate be-

tween the normal co nt rol gate and the source/drain region of

a transistor. This gate may be charged with electrons during

the programming operati on, permanently turning off the tran-

sistor. The state of the floatin g gate, charged or uncharged, is

permanent because the gate is isolated in an extremely pure

oxide. The charge may be removed if the device is irradiated

with ultra violet ener gy in the form of li ght. Thi s ultra violet light

allows the electrons on the gate to recombine and discharge

the gate. This process is repeatable and therefore can be used

during the processing of the device, repeatedly if necessary,

to assure programming function and performance.

Two Tra n sistor Cell s

Cypre ss uses a two-transistor EPROM cell. One transistor is

optimized for reliable programming, and one transistor is opti -

mized for high speed. The floating gates are c onnected su ch

that charge injected on the floating gate of the programming

tra nsistor is conducted to the read transistor biasing it off.

Flash Process Technology

The Flash cell is programmed in the same manner as the

EPROM cell, and is electrically erased via Fowler-Nordheim

tunneling. This n ext-generation PLD technology will combi ne

a number of key advantages for future Cypress PLDs. The

principal advantages will be leading-edge speed, low CMOS

pow er cons umption, and electrical alterability for simplified in-

ventory management.

Programming Algorithm—EPROM and Flash

Technology

Byte Addressing and Programming

Most Cy press programmab le logic devices are address ed and

programmed on a byte or extended byte basis where an ex-

tended byte is a field that is as wide as the outp ut p ath of the

device . Each dev ice or family of devices ha s a un iqu e address

map that is available in the product datasheet. Each byte or

extended byte is written int o th e addressed location from the

pins that serve as the output pins in normal oper ation. To pro-

gram a cell, a 1 or HIGH is placed on the input pin and a 0 or

LOW is placed on pins corresponding to cells that are not to

be program med. Data is also r ead from these pins in parallel

for verification after programming. A 1 or HIGH during program

verify operation indicates an unprogrammed cell, while a 0 or

LOW indicates that the cell accessed has been programmed.

Blank Chec k

Before pro gramming, all programmable logic devices may be

chec ked in a conventional mann er t o determine that they have

not been previously programmed. This is accomplished in a

program verify m ode of operat ion by reading the contents of

the array. During this operat ion, a 1 or HIGH outp ut indicates

that the addressed cell is unprogrammed, while a 0 or LOW

indicates a programmed cell.

Programming the Data Array

Pro gramming is a ccomplished by applying a supervolta ge to

one pin of the device causing it to enter the programming

mode of operation. This also pro vi des the programming volt-

age for the cells to be programmed. In this mod e of operation ,

the address l ines of the device are u sed to a ddress e ach loc a-

tion to be programmed, and the dat a is presented on the pins

normally used for reading the contents of the device. Each

device has a read/write pin in the programming mode. This

signal causes a write operation when switched to a supervolt-

age and a read operation w hen switched to a logic 0 or LOW.

In the logic H IGH or 1 state, th e device is in a program inhibit

condition and the output pins are in a high-impedance state.

During a write operation, the data on the output pins is written

into the address ed array loca tion. In a read ope ration, the con-

tents of the addressed location are present on the output pins

and may be verified. Programmin g therefore is a ccomplished

by placing data on the output pins and writing it into the ad-

dressed location. Verification of data is accomplished by ex-

amining the information on the output pins during a read oper-

ation.

The timing for actual programming is supplied in the unique

program ming specification for e ach device.

Phantom Operating Modes

All Cypre ss programmable logic d evices on the EPROM and

BiCMOS technology contain a Phantom array for post assem-

bly testing. Th is array is accessed, programmed, and operated

in a special Phantom mode of operation. In this mode, the

normal ar ray is disconnect ed from control of the logic, and in

its place the Phantom array is connected. In normal operation

the Phantom array is disconnected and control is o nly via the

normal array. This special feature allows every device to be

PLD Programming Information

of any circuitry othe r than circui try embodi ed in a Cypress Semicondu ctor product. Nor does it convey or imply any li cense under patent o r other rights. Cypress Semicondu ctor does not authori ze

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes a ll risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

tested for both functionalit y and performance after packaging

and, if desired, by the user before programming and use. The

Phantom mode s are ente red through the use of sup ervoltages

and are unique for each device or family of devices. See spe-

cific datasheets for details.

Special Features

Cypress programmable logic devices, depending on the de-

vice, have several special features. For example, the security

mechanism defeats the verify operation and therefore secures

the contents of the device against unauthorized tampering or

access. In advanced devices such as the PALCE22V10,

PLDC20G10, and CY7C335, th e macrocells are programma-

ble through the use of the architecture bit s. Thi s allo ws users

to more ef fec tively tailor the device architecture to their unique

system requirements. Specific programmi ng is detailed in the

device datasheet.

Programmers

All of Cypress’s programmable logic devices can be pro-

grammed on the Cypress

Impulse3

 programmer. Many

third-party programmers also support these products. In addi-

tion, all CY7C370i In-System Reprogrammable devices can

be programmed with the InSRkit on-board programmer for

the PC.

Document #: 38–00164–C

Impulse3

, In-System Reprogrammable, and InSRkit a re trademarks of Cypress Semiconductor Corporation.