SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 x 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Dynamic Port-B Bus Sizing of 36 Bits (Long Word), 18 Bits (Word), and 9 Bits (Byte) Selection of Big- or Little-Endian Format for Word and Byte Bus Sizes Three Modes of Byte-Order Swapping on Port B Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic EFA, FFA, AEA, and AFA Flags Synchronized by CLKA D D D D D D D D EFB, FFB, AEB, and AFB Flags Synchronized by CLKB Passive Parity Checking on Each Port Parity Generation Can Be Selected for Each Port Low-Power Advanced BiCMOS Technology Supports Clock Frequencies up to 50 MHz Fast Access Times of 12 ns Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9560901QYA and 5962-9560901NXD Package Options Include 132-Pin Ceramic Quad Flat (HFP) and 120-Pin Plastic Quad Flat (PCB) Packages description The SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 50 MHz and has read-access times as fast as 12 ns. Two independent 64 x 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port. The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface. The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. The SN54ABT3614 is characterized for operation over the full military temperature range of -55C to 125C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA GND MBF2 MBA FS1 FS0 ODD/EVEN RST GND BE SW1 SW0 SIZ1 SIZ0 MBF1 GND PEFB PGB VCC W/RB CLKB ENB CSB FFB AFB HFP PACKAGE (TOP VIEW) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118 131 129 127 125 123 121 119 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC GND AEA EFA A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23 NC - No internal connection 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23 PCB PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EFB AEB AFB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND BE SW1 SW0 SIZ1 SIZ0 MBF1 PEFB PGB VCC W/RB CLKB ENB CSB FFB A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 EFA AEA POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 functional block diagram CLKA CSA W/RA ENA MBA Port-A Control Logic MBF1 ODD/ EVEN Write Pointer Output Register Device Control Bus Matching and Byte Swapping RST PGB Parity Generation Input Register Mail1 Register 64 x 36 SRAM PEFB Parity Gen/Check 36 Read Pointer Status-Flag Logic FFA AFA EFB AEB FIFO1 36 Programmable-Flag Offset Register FS0 FS1 A0-A35 B0-B35 FIFO2 Status-Flag Logic PGA PEFA Parity Gen/Check 36 Write Pointer 64 x 36 SRAM Input Register Parity Generation Output Register Read Pointer FFB AFB Bus Matching and Byte Swapping EFA AEA Mail2 Register MBF2 Port-B Control Logic 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CLKB CSB W/RB ENB BE SIZ0 SIZ1 SW0 SW1 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 Terminal Functions TERMINAL NAME I/O A0-A35 I/O DESCRIPTION Port-A data. The 36-bit bidirectional data port for side A. AEA O (port A) Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words in FIFO2 is less than or equal to value in offset register X. AEB O (port B) Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words in FIFO1 is less than or equal to value in offset register X. AFA O (port A) Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty locations in FIFO1 is less than or equal to the value in offset register X. AFB O (port B) Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty locations in FIFO2 is less than or equal to the value in offset register X. B0-B35 I/O Port-B data. The 36-bit bidirectional data port for side B. BE I Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the most-significant bytes on B0-B35 for use, and a high selects the least-significant bytes. CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA. CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data-port sizing operations are also synchronous to the low-to-high transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB. CSA I Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is high. CSB I Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is high. EFA O (port A) Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EFA is forced low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty FIFO2 memory. EFB O (port B) Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO1 memory. ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. FFA O (port A) Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high transition of CLKA after reset. FFB O (port B) Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after reset. FS1, FS0 I Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the almost-empty flag and almost-full flag offset. MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0-A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output register data for output. MBF1 O Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset. MBF2 O Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high when the device is reset. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION ODD/EVEN I Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. PEFA PEFB 6 O (port A) O (port B) Port-A parity-error flag. When any byte applied to terminals A0-A35 fails parity, PEFA is low. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most-significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of ODD/EVEN. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/RA low, MBA high, and PGA high, the PEFA flag is forced high, regardless of the state of the A0-A35 inputs. Port-B parity-error flag. When any valid byte applied to terminals B0-B35 fails parity, PEFB is low. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35, with the most-significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state of ODD/EVEN. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/RB low, SIZ1 and SIZ0 high, and PGB high, the PEFB flag is forced high, regardless of the state of the B0-B35 inputs. PGA I Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated is selected by the state of ODD/EVEN. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most-significant bit of each byte. PGB I Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated is selected by the state of ODD/EVEN. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most-significant bit of each byte. RST I Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low. The low-to-high transition of RST latches the status of the FS1 and FS0 inputs to select almost-full flag and almost-empty flag offset. SIZ0, SIZ1 I (port B) Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read. SW0, SW1 I (port B) Port-B byte-swap selects. At the beginning of each long-word transfer, one of four modes of byte-order swapping is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection. W/RA I Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a low-to-high transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is high. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 detailed description reset The SN54ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after power up before data is written to its memory. A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1. Table 1. Flag Programming FS1 FS0 RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) H H 16 H L 12 L H 8 L L 4 FIFO write/read operation The state of the port-A data (A0-A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0-A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the A0-A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FFA is high. Data is read from FIFO2 to the A0-A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2). Table 2. Port-A Enable Function Table CSA W/RA ENA MBA CLKA A0-A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L In high-impedance state FIFO1 write L H H H In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H Active, mail2 register Mail2 read (set MBF2 high) The state of the port-B data (B0-B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0-B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the B0-B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high, and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0-B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 FIFO write/read operation (continued) Table 3. Port-B Enable Function Table CSB W/RB ENB SIZ1, SIZ0 CLKB B0-B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H One, both low In high-impedance state FIFO2 write L H H Both high In high-impedance state Mail2 write L L L One, both low X Active, FIFO1 output register None L L H One, both low Active, FIFO1 output register FIFO1 read L L L Both high X Active, mail1 register None L L H Both high Active, mail1 register Mail1 read (set MBF1 high) The setup- and hold-time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select can change states during the setup- and hold-time window of the cycle. synchronized FIFO flags Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the 1996 High-Performance FIFO Memories Data Book, literature number SCAD003). EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. Table 4. FIFO1 Flag Operation NUMBER OF 36-BIT WORDS IN FIFO1 SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA EFB AEB AFA FFA 0 L L H H 1 to X H L H H (X + 1) to [64 - (X + 1)] H H H H (64 - X) to 63 H H L H 64 H H L L X is the value in the almost-empty flag and almost-full flag offset register. Table 5. FIFO2 Flag Operation NUMBER OF 36-BIT WORDS IN FIFO2 SYNCHRONIZED TO CLKA SYNCHRONIZED TO CLKB EFA AEA AFB FFB 0 L L H H 1 to X H L H H (X + 1) to [64 - (X + 1)] H H H H (64 - X) to 63 H H L H 64 H H L L X is the value in the almost-empty flag and almost-full flag offset register. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 empty flags (EFA, EFB) The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when the fourth byte or second word of the last long word is read. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty-flag synchronizing clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to the FIFO output register in the following cycle. A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 13 and 14). full flags (FFA, FFB) The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full-flag synchronizing clock; therefore, a full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data can be written in the following clock cycle. A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 15 and 16). almost-empty flags (AEA, AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or fewer long words in memory and is high when the FIFO contains (X + 1) or more long words. Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 17 and 18). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 almost-full flags (AFA, AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An almost-full flag is low when the FIFO contains (64 - X) or more long words in memory and is high when the FIFO contains [64 - (X + 1)] or fewer long words. Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 - (X + 1)] or fewer words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64 - (X + 1)]. An almost-full flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to [64 - (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words in memory to [64 - (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 19 and 20). mailbox registers Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data-transfer operation. A low-to-high transition on CLKA writes A0-A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB writes B0-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0 and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low. When the port-A data outputs (A0-A35) are active, the data on the bus comes from the FIFO2 output register when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0-B35) are active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both port-B bus-size select (SIZ1 and SIZ0) inputs are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only when new data is written to the register. dynamic bus sizing The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths. The levels applied to SIZ0 and SIZ1 and the big-endian select (BE) input are stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to Figure 1. Only 36-bit long-word data is written to or read from the two FIFO memories on the SN54ABT3614. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. Port-B bus sizing does not apply to mail-register operations. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 A35 BYTE ORDER ON PORT A: BE SIZ1 SIZ0 X L L A27 A26 A B35 A18 A17 B B27 B26 A A9 A8 C B18 B17 B A0 Write to FIFO1/Read From FIFO2 D B9 B8 C B0 Read From FIFO1/Write to FIFO2 D (a) LONG WORD SIZE B35 BE SIZ1 SIZ0 L L H B27 B26 A B35 B18 IIIIII IIIIII IIIIII IIIIII B17 B B27 B26 C B18 B9 B17 D B9 B8 B0 B8 1st: Read From FIFO1/Write to FIFO2 B0 2nd: Read From FIFO1/Write to FIFO2 (b) WORD SIZE - BIG ENDIAN IIIIII IIIIII IIIIII IIIIII B35 BE SIZ1 SIZ0 H L H B27 B26 B35 B27 B26 B18 B18 B17 B9 B8 C B17 B0 1st: Read From FIFO1/Write to FIFO2 D B9 B8 A B0 2nd: Read From FIFO1/Write to FIFO2 B (c) WORD SIZE - LITTLE ENDIAN B35 BE SIZ1 SIZ0 L H L III III III III III III III III III III III III B27 B26 A B35 B27 B26 B B35 B27 B26 C B35 B27 B26 D B18 B18 B18 B18 IIIIII IIIIII III III IIIIII IIIIII III III IIIIII IIIIII III III IIIIII IIIIII IIIIII B17 B17 B17 B17 B9 B9 B9 B9 B8 B8 B8 B8 B0 1st: Read From FIFO1/Write to FIFO2 B0 2nd: Read From FIFO1/Write to FIFO2 B0 3rd: Read From FIFO1/Write to FIFO2 B0 4th: Read From FIFO1/Write to FIFO2 (d) BYTE SIZE - BIG ENDIAN Figure 1. Dynamic Bus Sizing POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 IIIIII IIIIII III III IIIIII IIIIII III IIIIII III IIIIII III III IIIIII IIIIII IIIIII B35 BE SIZ1 SIZ0 H H L B35 B35 B35 B27 B26 B27 B26 B27 B26 B27 B26 B18 B18 B18 B18 III III III III III III III III III III III III B17 B17 B17 B17 B9 B9 B9 B9 B8 B0 1st: Read From FIFO1/Write to FIFO2 D B8 B0 2nd: Read From FIFO1/Write to FIFO2 C B8 B0 3rd: Read From FIFO1/Write to FIFO2 B B8 B0 A 4th: Read From FIFO1/Write to FIFO2 (e) BYTE SIZE - LITTLE ENDIAN Figure 1. Dynamic Bus Sizing (Continued) bus-matching FIFO1 reads Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1. Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1 read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread long-word data. When reading data from FIFO1 in byte or word format, the unused B0-B35 outputs remain inactive but static with the unused FIFO1 output register bits holding the last data value to decrease power consumption. bus-matching FIFO2 writes Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes, with a long-word bus size, immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner shown in Figure 1. Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 port-B mail-register access In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed immediately and any bus-sizing operation that can be underway is unaffected by the the mail-register access. After the mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q. CLKB MUX G1 1 SIZ0_Q D Q SIZ0 SIZ1 SIZ1_Q BE_Q 1 BE Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register byte swapping The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is rearranged within the long word, but the bit order within the bytes remains constant. Byte arrangement is chosen by the port-B swap select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first word of a new long-word read from FIFO1 or written to FIFO2 is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for a FIFO1 read rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1. Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes load the data according to Figure 1, then swap the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 A35 SW1 SW0 L L A27 A26 A18 A17 A9 A8 A0 A B C D A B C D B35 B27 B26 B18 B17 B9 B8 B0 A18 A17 A9 A8 A0 (a) NO SWAP A35 SW1 SW0 L H A27 A26 A B C D D C B A B35 B27 B26 B18 B17 B9 B8 B0 A17 A9 A8 A0 (b) BYTE SWAP A35 SW1 SW0 H L A27 A26 A18 A B C D C D A B B35 B27 B26 B18 B17 B9 B8 B0 A17 A9 A8 A0 (c) WORD SWAP A35 SW1 SW0 H H B35 A27 A26 A18 A B C D B A D C B27 B26 B18 B17 B9 B8 (d) BYTE-WORD SWAP Figure 3. Byte Swapping (Long-Word Size Example) 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 B0 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 parity checking The port-A data inputs (A0-A35) and port-B data inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low level on the port-A parity-error flag (PEFA). A parity failure on one or more bytes of the port-B data inputs that are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB). Oddor even-parity checking can be selected, and the parity-error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding port parity-error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, and its valid bytes are those used in a port-B bus-size implementation. When odd/even parity is selected, a port parity-error flag (PEFA, PEFB) is low if any valid byte on the port has an odd/even number of low levels applied to the bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is held high regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB high, and W/RB low, both SIZ0 and SIZ1 high, and PGB high, the port-B parity-error flag (PEFB) is held high, regardless of the levels applied to the B0-B35 inputs. parity generation A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the SN54ABT3614 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most-significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte, regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most-significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register; therefore, the port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN) have setup- and hold-time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the port-B clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new long word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip select (CSA, CSB) is low, enable (ENA, ENB) is high, write/read select (W/RA, W/RB) input is low, the mail register is selected (MBA is high for port A; both SIZ0 and SIZ1 are high for port B), and port parity-generate select (PGA, PGB) is high. Generating parity for mail-register data does not change the contents of the register. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKA th(RS) CLKB tsu(RS) th(FS) tsu(FS) RST IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII FS1, FS0 0,1 tpd(C-FF) tpd(C-FF) FFA tpd(C-EF) EFA tpd(C-FF) tpd(C-FF) FFB tpd(C-EF) EFB MBF1, MBF2 tpd(R-F) tpd(C-AE) AEA tpd(C-AF) AFA tpd(C-AE) AEB tpd(C-AF) AFB Figure 4. Device Reset Loading the X Register With the Value of Eight 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tc tw(CLKH) tw(CLKL) CLKA FFA CSA W/RA MBA ENA High III III IIIIIII III IIIIII IIIIIII III IIIIII IIIIIII III IIIIII IIIIIII III IIIIII IIIIIII IIIIIII IIIIII IIIIII IIIIIII IIIIII IIIIIIIIIIIIII II II IIIIIIII IIIIII IIIIIIIIIIII I tsu(EN) th(EN) tsu(EN) th(EN) tsu(EN) th(EN) tsu(EN) th(EN) tsu(D) A0-A35 ODD/ EVEN th(EN) tsu(EN) th(D) W1 W2 tpd(D-PE) PEFA th(EN) tsu(EN) No Operation tpd(D-PE) Valid Valid Written to FIFO1 Figure 5. Port-A Write Cycle for FIFO1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB FFB High tsu(EN) IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIII IIIIIII IIII IIIIIIIIII IIIIII IIIIIIIIIIII II IIIIII IIIIIIIIIIIIIIIIIII II IIIIII IIIIII IIIIIIIIIIII II IIIIII IIIIII IIIIIIIIIIII IIIIIIIIII IIIIII IIIIIIIIIIII IIIIIIIIII IIIIII IIIIIIIIIIII II II IIIIIIIIIIIII IIIIII IIIIIIIIII IIIIIIIIIIIII IIIIII IIIIIIIIII CSB tsu(EN) W/RB tsu(EN) th(EN) tsu(SW) th(SW) th(EN) tsu(EN) ENB SW1, SW0 tsu(SZ) th(SZ) BE tsu(SZ) SIZ1, SIZ0 th(SZ) (0, 0) (0, 0) tsu(D) Not (1, 1) th(D) B0-B35 ODD/ EVEN tpd(C-PE) tpd(D-PE) PEFB Valid Valid SIZ0 = H and SIZ1 = H writes data to the mail2 register. DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2 SWAP MODE DATA WRITTEN TO FIFO2 DATA READ FROM FIFO2 SW1 SW0 B35-B27 B26-B18 B17-B9 B8-B0 A35-A27 A26-A18 A17-A9 A8-A0 L L A B C D A B C D L H D C B A A B C D H L C D A B A B C D H H B A D C A B C D Figure 6. Port-B Long-Word Write Cycle for FIFO2 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB FFB High tsu(EN) th(EN) CSB IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIII IIIII IIIIIIIIIII IIIIII IIIII IIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIII III IIIIII IIIIIIIIIIIII III IIIIII IIIIIIIIIIIII III IIIIII IIIIII IIIII III IIIIII IIIIII IIIII IIIIIIIIIII IIIIII IIIII IIIIIIIIIII IIIIII IIIII IIIIIIIIIII IIIIII IIIII IIIIIIIIIII IIIIII IIIII II II IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIII IIIIII III tsu(EN) W/RB tsu(EN) th(EN) tsu(SW) th(SW) tsu(EN) th(EN) ENB SW1, SW0 tsu(SZ) th(SZ) tsu(SZ) th(SZ) tsu(SZ) th(SZ) tsu(SZ) th(SZ) BE (0, 1) SIZ1, SIZ0 Little Endian Not (1, 1) (0, 1) tsu(D) th(D) tsu(D) th(D) B0-B17 Big Endian B18-B35 ODD/EVEN tpd(C-PE) tpd(D-PE) Valid PEFB Valid SIZ0 = H and SIZ1 = H writes data to the mail2 register. NOTE A: PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for big-endian bus, and B17-B9 and B8-B0 for little-endian bus. DATA SWAP TABLE FOR WORD WRITES TO FIFO2 SWAP MODE SW1 DATA WRITTEN TO FIFO2 WRITE NO. NO SW0 L L L H H L H H BIG ENDIAN DATA READ FROM FIFO2 LITTLE ENDIAN B35-B27 B26-B18 B17-B9 B8-B0 1 A B C D 2 C D A B 1 D C B A 2 B A D C 1 C D A B 2 A B C D 1 B A D C 2 D C B A A35-A27 A26-A18 A17-A9 A8-A0 A B C D A B C D A B C D A B C D Figure 7. Port-B Word Write Cycle for FIFO2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB FFB High tsu(EN) th(EN) CSB IIIIIII IIIIIII IIIIIII IIII IIII IIII IIII IIIIIII IIII IIII IIII IIII IIIIIII IIIIIIIIIIIIIIIIIII IIIIIII II IIII IIIIIIIIIIIIIIIIIII IIII IIII IIIIIIII II IIII IIII IIII IIIIIIII II IIII IIII IIII III III IIIIIII IIII IIII III III IIIIIII IIII IIII III III IIIIIII IIII IIII III II II II II IIIIIIIIIIIII III III II IIIIIIIIIIIII III III II tsu(EN) W/RB ENB SW1, SW0 tsu(SZ) BE Little Endian Big Endian B0-B8 B27-B35 ODD/EVEN th(EN) tsu(SW) th(EN) th(SZ) tsu(SZ) th(SZ) th(SZ) tsu(SZ) tsu(SZ) SIZ1, SIZ0 tsu(EN) (1, 0) th(EN) th(SZ) (1, 0) (1, 0) tsu(D) th(D) tsu(D) th(D) tpd(C-PE) PEFB tsu(EN) tpd(D-PE) (1, 0) Not (1, 1) tpd(D-PE) Valid tpd(D-PE) Valid Valid SIZ0 = H and SIZ1 = H writes data to the mail2 register. NOTE A: PEFB indicates parity error for the following bytes: B35-B27 for big-endian bus and B17-B9 for little-endian bus. Figure 8. Port-B Byte Write Cycle for FIFO2 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Valid SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 DATA SWAP TABLE FOR BYTE WRITES TO FIFO2 SWAP MODE SW1 DATA WRITTEN TO FIFO2 WRITE NO. BIG ENDIAN LITTLE ENDIAN B35-B27 B8-B0 A D 2 B C 3 C B 4 D A 1 D A 2 C B 3 B C 4 A D 1 C B 2 D A 3 A D 4 B C 1 B C 2 A D 3 D A 4 C B SW0 1 L L H H L H L H DATA READ FROM FIFO2 A35-A27 A26-A18 A17-A9 A8-A0 A B C D A B C D A B C D A B C D Figure 8. Port-B Byte Write Cycle for FIFO2 (Continued) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB EFB High IIIIIIII IIIIIIII IIIIIIIIII IIIIIIIIII II IIIIII II II IIIIIIIIII IIIIIIIIII CSB W/RB tsu(EN) ENB tsu(SW) SW1, SW0 tsu(SZ) th(SZ) BE tsu(SZ) SIZ1, SIZ0 th(SZ) (0, 0) Not (1, 1) th(EN) tsu(EN) ten B0-B35 th(EN) No Operation th(SW) Not (1, 1) (0, 0) tsu(PG) PGB, ODD/ EVEN IIIII IIIII IIIIII IIIIII IIIII IIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIII IIIIIIIIIIII IIIIII IIIIIIIIIIII th(PG) ta Previous Data tdis W2 ta W1 SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0-B35. Data read from FIFO1 DATA SWAP TABLE FOR LONG-WORD READS FROM FIFO1 DATA WRITTEN TO FIFO1 SWAP MODE A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 A B C D L L A B C D L H A B C D H L A B C D H H DATA READ FROM FIFO1 B35-B27 B26-B18 B17-B9 B8-B0 A B C D D C B A C D A B B A D C Figure 9. Port-B Long-Word Read Cycle for FIFO1 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB High EFB IIIIIIII IIIIIIII IIIIIIIIIII IIIIIIIIII III IIIIII III III IIIIIIIIII IIIIIIIIII CSB W/RB tsu(EN) th(EN) ENB tsu(SW) SW1, SW0 tsu(SZ) BE th(SZ) Not (1, 1) (0, 1) (0, 1) tsu(PG) PGB, ODD/ EVEN ten Little Endian B0-B17 No Operation th(SW) th(SZ) tsu(SZ) SIZ1, SIZ0 IIII IIII IIIII IIIII IIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII III III IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII Not (1, 1) th(PG) ta ta Previous Data Read 1 ta Big Endian B18-B35 tdis Read 2 ta Previous Data tdis Read 1 Read 2 SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0-B35. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads. DATA SWAP TABLE FOR WORD READS FROM FIFO1 DATA WRITTEN TO FIFO1 SWAP MODE A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 A B C D L L A A A B B B C C C D D D L H H H L H DATA READ FROM FIFO1 READ NO NO. BIG ENDIAN B35-B27 LITTLE ENDIAN B26-B18 B17-B9 B8-B0 1 A B C D 2 C D A B 1 D C B A 2 B A D C 1 C D A B 2 A B C D 1 B A D C 2 D C B A Figure 10. Port-B Word Read Cycle for FIFO1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB EFB High CSB IIIIII IIIIII IIIIIII IIIIIII IIIIIII III III III III III III IIIIIII IIIIIII W/RB tsu(EN) ENB tsu(SW) SW1, SW0 tsu(SZ) th(SZ) BE tsu(SZ) SIZ1, SIZ0 th(SZ) (1, 0) IIIII IIIII IIIII IIIIIIIIIIII III IIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIII IIIIIIII IIIIIIIIIIIII IIII IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII th(EN) (1, 0) Not (1, 1) tsu(PG) PGB, ODD/EVEN ten No Operation th(SW) (1, 0) Not (1, 1) th(PG) Not (1, 1) ta B0-B8 ta Read 1 Previous Data ta B27-B35 Not (1, 1) (1, 0) ta Read 1 ta Read 2 ta Read 2 Previous Data SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0-B35. NOTE A: Unused bytes hold last FIFO1 output register data for byte-size reads. Figure 11. Port-B Byte Read Cycle for FIFO1 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ta Read 3 ta Read 3 tdis Read 4 tdis Read 4 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 DATA SWAP TABLE FOR BYTE READS FROM FIFO1 DATA WRITTEN TO FIFO1 A35-A27 A26-A18 A17-A9 SWAP MODE A8-A0 SW1 DATA READ FROM FIFO1 READ NO. BIG ENDIAN LITTLE ENDIAN B35-B27 B8-B0 A D 2 B C 3 C B 4 D A 1 D A 2 C B 3 B C 4 A D 1 C B 2 D A 3 A D 4 B C 1 B C 2 A D 3 D A 4 C B SW0 1 A A A A B B B B C C C C D D D D L L H H L H L H Figure 11. Port-B Byte Read Cycle for FIFO1 (Continued) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tc tw(CLKH) tw(CLKL) CLKA EFA High CSA W/RA IIII IIIIII MBA tsu(EN) ENA IIIIIII IIIIIII III III IIIIIII IIIIIII tpd(M-DV) ten A0-A35 PGA, ODD/EVEN Read from FIFO2 tsu(PG) tsu(EN) tsu(EN) IIIIIII IIIIIII IIIIII IIIIIII IIIIIII IIIIII th(EN) th(EN) ta Previous Data th(PG) No Operation ta W1 W2 tdis IIIII IIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIII tsu(PG) th(PG) Figure 12. Port-A Read Cycle for FIFO2 26 th(EN) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tc tw(CLKH) tw(CLKL) CLKA CSA W/RA Low High tsu(EN) IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII th(EN) MBA tsu(EN) th(EN) ENA FFA High tsu(D) A0-A35 th(D) W1 tsk1 tc tw(CLKH) 1 CLKB tw(CLKL) 2 tpd(C-EF) tpd(C-EF) FIFO1 Empty EFB CSB Low W/RB Low SIZ1, SIZ0 Low th(EN) IIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII tsu(EN) ENB ta W1 B0-B35 tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of EFB high may occur one CLKB cycle later than shown. NOTE A: Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, EFB is set low by the last word or byte read from FIFO1, respectively. Figure 13. EFB-Flag Timing and First Data Read When FIFO1 Is Empty POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tc tw(CLKH) tw(CLKL) CLKB CSB W/RB SIZ1, SIZ0 Low High tsu(EN) IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIII th(EN) tsu(EN) ENB FFB th(EN) High tsu(D) B0-B35 th(D) W1 tc tsk1 tw(CLKL) tw(CLKH) 1 CLKA 2 tpd(C-EF) tpd(C-EF) FIFO2 Empty EFA CSA Low W/RA Low MBA Low IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII th(EN) tsu(EN) ENA ta A0-A35 W1 tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, the transition of EFA high may occur one CLKA cycle later than shown. NOTE A: Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. Figure 14. EFA-Flag Timing and First Data Read When FIFO2 Is Empty 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tc tw(CLKH) tw(CLKL) CLKB CSB Low W/RB Low SIZ1, SIZ0 Low IIII III IIII III tsu(EN) ENB EFB th(EN) High ta B0-B35 Previous Word in FIFO1 Output Register Next Word From FIFO1 tsk1 tc tw(CLKH) tw(CLKL) 1 CLKA 2 tpd(C-FF) tpd(C-FF) FIFO1 Full FFA CSA Low W/RA High IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII tsu(EN) MBA tsu(EN) ENA tsu(D) A0-A35 IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII th(EN) th(EN) th(D) To FIFO1 tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, FFA may transition high one CLKA cycle later than shown. NOTE A: Port-B size of long word is selected for the FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced from the rising CLKB edge that reads the first word or byte of the long word, respectively. Figure 15. FFA-Flag Timing and First Available Write When FIFO1 Is Full POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tc tw(CLKH) tw(CLKL) CLKA CSA Low W/RA Low MBA Low IIII III IIII III tsu(EN) ENA EFA High th(EN) ta A0-A35 Previous Word in FIFO2 Output Register Next Word From FIFO2 tsk1 tc tw(CLKH) tw(CLKL) 1 CLKB 2 tpd(C-FF) FFB CSB Low W/RB High SIZ1, SIZ0 ENB tpd(C-FF) FIFO2 Full IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIII tsu(EN) th(EN) tsu(EN) th(EN) tsu(D) B0-B35 th(D) To FIFO2 tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, FFB may transition high one CLKB cycle later than shown. NOTE A: Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, FFB is set low by the last word or byte write of the long word, respectively. Figure 16. FFB-Flag Timing and First Available Write When FIFO2 Is Full 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKA IIIIIIIIII IIIIIIIIII tsu(EN) ENA th(EN) tsk2 CLKB 1 2 tpd(C-AE) AEB tpd(C-AE) X Long Words in FIFO1 (X + 1) Long Words in FIFO1 th(EN) IIIII IIII tsu(EN) ENB tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk2, AEB may transition high one CLKB cycle later than shown. NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L) B. Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AEB is set low by the first word or byte read of the long word, respectively. Figure 17. AEB When FIFO1 Is Almost Empty CLKB IIIIIIIIII IIIIIIIIII tsu(EN) ENB th(EN) tsk2 CLKA 1 2 tpd(C-AE) AEA X Long Words in FIFO2 tpd(C-AE) (X + 1) Long Words in FIFO2 th(EN) IIIIIIIIII IIIIIIIIII tsu(EN) ENA tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk2, AEA may transition high one CLKA cycle later than shown. NOTES: A. FIFO2 write (CSB = L, W/RB = H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L) B. Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk2 is referenced from the rising CLKB edge that writes the last word or byte of the long word, respectively. Figure 18. AEA When FIFO2 Is Almost Empty POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 tsk2 CLKA 1 IIIIIIIIII IIIIIIIIII tsu(EN) ENA th(EN) tpd(C-AF) AFA 2 tpd(C-AF) (64 - X) Long Words in FIFO1 [64 - (X + 1)] Long Words in FIFO1 CLKB th(EN) IIIII IIIII tsu(EN) ENB tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk2, AFA may transition high one CLKB cycle later than shown. NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L) B. Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk2 is referenced from the first word or byte read of the long word, respectively. Figure 19. AFA When FIFO1 Is Almost Full tsk2 CLKB 1 IIIIIIIIII IIIIIIIIII tsu(EN) ENB tpd(C-AF) AFB 2 th(EN) [64 - (X + 1)] Long Words in FIFO2 tpd(C-AF) (64 - X) Long Words in FIFO2 CLKA IIIII IIIII IIIII IIIII tsu(EN) ENA th(EN) tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk2, AFB may transition high one CLKA cycle later than shown. NOTES: A. FIFO2 write (CSB = L, W/RB= H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L) B. Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AFB is set low by the last word or byte write of the long word, respectively. Figure 20. AFB When FIFO2 Is Almost Full 32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKA th(EN) tsu(EN) CSA IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII W/RA MBA ENA tsu(D) A0-A35 IIII IIII IIII IIII IIIIIIIIIIIIIIIIIIIII th(D) W1 CLKB tpd(C-MF) tpd(C-MF) MBF1 CSB IIIII IIIIIIIII IIIIIIIII IIIIII W/RB SIZ1, SIZ0 ENB tpd(M-DV) ten th(EN) IIII III IIII III III III tsu(EN) tpd(C-MR) tdis W1 (remains valid in mail1 register after read) B0-B35 FIFO1 Output Register NOTE A: Port-B parity generation off (PGB = L) Figure 21. Mail1 Register and MBF1 Flag POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 CLKB th(EN) tsu(EN) CSB W/RB IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII tsu(SZ) SIZ1, SIZ0 ENB tsu(D) B0-B35 III III III III III IIIIIIIIIIIIIIIIIIIIII th(SZ) th(D) W1 CLKA tpd(C-MF) tpd(C-MF) MBF2 CSA W/RA MBA IIII IIII IIIIII IIIIII IIII IIII IIII IIII IIII IIII tsu(EN) ENA th(EN) tpd(M-DV) ten tpd(C-MR) W1 (remains valid in mail2 register after read) A0-A35 FIFO2 Output Register NOTE A: Port-A parity generation off (PGA = L) Figure 22. Mail2 Register and MBF2 Flag 34 tdis POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 ODD/EVEN W/RA IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIIII MBA PGA tpd(O-PE) PEFA tpd(O-PE) Valid Valid tpd(E-PE) tpd(E-PE) Valid Valid NOTE A: ENA is high and CSA is low. Figure 23. ODD/EVEN, W/RA, MBA, and PGA to PEFA ODD/EVEN W/RB IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII SIZ1, SIZ0 PGB tpd(O-PE) PEFB Valid tpd(O-PE) tpd(E-PE) Valid Valid IIIIII IIIIII tpd(E-PE) Valid NOTE A: ENB is high and CSB is low. Figure 24. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 35 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 ODD/ EVEN CSA Low W/RA IIIIIII IIIIIII IIIIIII IIIIIII MBA PGA A8, A17, A26, A35 ten tpd(E-PB) tpd(M-DV) tpd(O-PB) Generated Parity tpd(E-PB) Generated Parity Mail2 Data Mail2 Data NOTE A: ENA is high. Figure 25. Parity-Generation Timing When Reading From the Mail2 Register ODD/ EVEN CSB Low W/RB IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII SIZ1, SIZ0 PGB B8, B17, B26, B35 ten tpd(E-PB) tpd(M-DV) tpd(O-PB) Generated Parity tpd(E-PB) Generated Parity Mail1 Data NOTE A: ENB is high. Figure 26. Parity-Generation Timing When Reading From the Mail1 Register 36 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Mail1 Data SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. recommended operating conditions MIN MAX 4.5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current -4 mA IOL TA Low-level output current 8 mA 125 C High-level input voltage 2 Operating free-air temperature -55 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.4 UNIT VOH VOL VCC = 4.5 V, VCC = 4.5 V, IOH = -4 mA IOL = 8 mA II IOZ VCC = 5.5 V, VCC = 5.5 V, VI = VCC or 0 VO = VCC or 0 ICC VCC = 5.5 V, IO = 0 mA, Ci VI = 0, VO = 0, f = 1 MHz 4 pF f = 1 MHz 8 pF VI = VCC or GND V V A 50 A Outputs high 30 Outputs low 130 Outputs disabled Co 0.5 50 mA 30 All typical values are at VCC = 5 V, TA = 25C. ICC is measured in the A-to-B direction. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 37 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 4 through 27) MIN MAX UNIT 50 MHz fclock tc Clock frequency, CLKA or CLKB 20 ns tw(CLKH) tw(CLKL) Pulse duration, CLKA and CLKB high 8 ns Pulse duration, CLKA and CLKB low 8 ns tsu(D) tsu(EN) Setup time, A0-A35 before CLKA and B0-B35 before CLKB 5 ns Setup time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, and ENB before CLKB 5 ns tsu(SZ) tsu(SW) Setup time, SIZ0, SIZ1, and BE before CLKB 5 ns Setup time, SW0 and SW1 before CLKB 7 ns tsu(PG) tsu(RS) Setup time, ODD/EVEN and PGA before CLKA; ODD/EVEN and PGB before CLKB Setup time, RST low before CLKA or CLKB 6 ns 6 ns tsu(FS) th(D) Setup time, FS0 and FS1 before RST high 6 ns Hold time, A0-A35 after CLKA and B0-B35 after CLKB 3 ns th(EN) th(SZ) Hold time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, and ENB after CLKB 3 ns Hold time, SIZ0, SIZ1, and BE after CLKB 2 ns th(SW) th(PG) Hold time, SW0 and SW1 after CLKB 7 ns Hold time, ODD/EVEN and PGA after CLKA; ODD/EVEN and PGB after CLKB Hold time, RST low after CLKA or CLKB 1 ns 6 ns Hold time, FS0 and FS1 after RST high 4 ns Skew time between CLKA and CLKB for EFA, EFB, FFA, and FFB 8 th(RS) th(FS) tsk1 Clock cycle time, CLKA or CLKB ns tsk2 Skew time between CLKA and CLKB for AEA, AEB, AFA, and AFB 16 ns Applies only for a clock edge that does a FIFO read Requirement to count the clock edge as one of at least four needed to reset a FIFO Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle. 38 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Figures 4 through 27) PARAMETER fmax ta MIN MAX 50 UNIT MHz Access time, CLKA to A0-A35 and CLKB to B0-B35 2 12 ns tpd(C-FF) tpd(C-EF) Propagation delay time, CLKA to FFA and CLKB to FFB 2 12 ns Propagation delay time, CLKA to EFA and CLKB to EFB 2 12 ns tpd(C-AE) tpd(C-AF) Propagation delay time, CLKA to AEA and CLKB to AEB 2 12 ns Propagation delay time, CLKA to AFA and CLKB to AFB 2 12 ns Propagation delay time, CLKA to MBF1 low or MBF2 high and CLKB to MBF2 low or MBF1 high 1 12 ns tpd(C-MR) tpd(C-PE) Propagation delay time, CLKA to B0-B35 and CLKB to A0-A35 3 13 ns Propagation delay time, CLKB to PEFB 2 12 ns tpd(M-DV) tpd(D-PE) Propagation delay time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid 1 11.5 ns Propagation delay time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 12.5 ns tpd(O-PE) tpd(O-PB) Propagation delay time, ODD/EVEN to PEFA and PEFB 3 14 ns Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 12 ns tpd(E-PE) Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB 1 23 ns tpd(E-PB) Propagation delay time, MBA or PGA to parity bits (A8, A17, A26, A35); SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35) 3 19 ns tpd(R-F) Propagation delay time, RST to (MBF1, MBF2) high 1 20 ns ten Enable time, CSA and W/RA low to A0-A35 active and CSB low and W/RB high to B0-B35 active 2 12 ns tdis Disable time, CSA or W/RA high to A0-A35 at high impedance and CSB high or W/RB low to B0-B35 at high impedance 1 9 ns tpd(C-MF) Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are high Writing data to the mail2 register when the A0-A35 outputs are active and MBA is high Applies only when a new port-B bus size is implemented by the rising CLKB edge Applies only when reading data from a mail register POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 39 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION 5V 1.1 k From Output Under Test 680 30 pF (see Note A) LOAD CIRCUIT 3V High-Level Input 3V Timing Input 1.5 V 1.5 V GND GND Data, Enable Input tw th tsu 3V 3V 1.5 V Low-Level Input 1.5 V GND 1.5 V 1.5 V GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 3V 1.5 V 1.5 V GND tPLZ tPZL Low-Level Output 3V 3V 1.5 V VOL 1.5 V Input 1.5 V GND tPZH VOH High-Level Output 1.5 V 0V tPHZ VOH In-Phase Output 1.5 V VOL NOTES: A. Includes probe and jig capacitance B. tPZL and tPZH are the same as ten C. tPLZ and tPHZ are the same as tdis Figure 27. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 40 tpd tpd * DALLAS, TEXAS 75265 SN54ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F - AUGUST 1995 - REVISED MAY 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 400 fdata = 1/2 fclock TA = 25C CL = 0 pF I CC(f) - Supply Current - mA 350 300 VCC = 5.5 V VCC = 5 V 250 200 VCC = 4.5 V 150 100 50 0 0 10 20 30 40 50 60 70 80 fclock - Clock Frequency - MHz Figure 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 41 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 5962-9560901NXD ACTIVE HLQFP PCB Pins Package Eco Plan (2) Qty 120 90 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN54ABT3614 : * Catalog: SN74ABT3614 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 MECHANICAL DATA MHTQ004A - JANUARY 1995 - REVISED JANUARY 1998 PCB (S-PQFP-G120) PLASTIC QUAD FLATPACK (DIE DOWN) 0,23 0,13 0,40 90 0,07 M 61 Heat Slug 91 60 120 31 0,13 NOM 1 30 11,60 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0- 7 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040202 / C 12/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced molded plastic package with a heat slug (HSL) Falls within JEDEC MS-026 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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