SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D
Two Independent 64 × 36 Clocked FIFOs
Buffering Data in Opposite Directions
D
Mailbox-Bypass Register for Each FIFO
D
Dynamic Port-B Bus Sizing of 36 Bits (Long
Word), 18 Bits (Word), and 9 Bits (Byte)
D
Selection of Big- or Little-Endian Format for
Word and Byte Bus Sizes
D
Three Modes of Byte-Order Swapping on
Port B
D
Almost-Full and Almost-Empty Flags
D
Microprocessor Interface Control Logic
D
EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
D
EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
D
Passive Parity Checking on Each Port
D
Parity Generation Can Be Selected for Each
Port
D
Low-Power Advanced BiCMOS Technology
D
Supports Clock Frequencies up to 50 MHz
D
Fast Access Times of 12 ns
D
Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9560901QYA
and 5962-9560901NXD
D
Package Options Include 132-Pin Ceramic
Quad Flat (HFP) and 120-Pin Plastic Quad
Flat (PCB) Packages
description
The SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory . It supports clock
frequencies up to 50 MHz and has read-access times as fast as 12 ns. Two independent 64 × 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
stored in memory . FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice
of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size
selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port
and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN54ABT3614 is characterized for operation over the full military temperature range of –55°C to 125°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GND
AEA
EFA
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
HFP PACKAGE
(TOP VIEW)
AFA
FFA
ENA
CLKA
W/RA
PGA
PEFA
GND
MBF2
MBA
FS0
ODD/EVEN
RST
GND
BE
SW1
SW0
SIZ1
SIZ0
MBF1
GND
PGB
W/RB
CLKB
ENB
CSB
FFB
AFB
A24
A25
A26
GND
A27
CC
A29
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
GND
B32
B31
B30
B29
B28
B27
GND
B26
B25
B24
V
VCC
CSA
VCC
VCC
FS1
PEFB
VCC
VCC
A28
B33
NC – No internal connection
18
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51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 7576 7778 79 80 81 8283
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1132
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126125
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119118117
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
93
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36
35
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91
92
60
A24
A25
A26
A27
A28
GND
A30
A31
A32
A34
A35
GND
B35
B34
B33
B32
B31
B30
GND
B29
B28
B27
B26
B25
B24
B23
AFA
FFA
CSA
CLKA
W/RA
PEFA
MBF2
MBA
FS1
FS0
ODD/EVEN
RST
GND
SW1
SW0
SIZ0
MBF1
PEFB
PGB
W/RB
CLKB
ENB
CSB
CC
V
CC
V
CC
V
BE
PCB PACKAGE
(TOP VIEW)
A33
CC
V
FFB
SIZ1
PGA
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
AFB
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
A29
ENA
1
2
3
4
5
6
7
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9
10
11
12
13
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15
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17
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Port-A
Control
Logic
AFA FIFO1
Programmable-Flag
Offset Register
Read
Pointer
64 × 36
SRAM
Port-B
Control
Logic
BE
Parity
Gen/Check
Write
Pointer
Mail2
Register
FIFO2 Status-Flag
Logic
Status-Flag
Logic
Write
Pointer
CLKA
CSA
W/RA
ENA
MBA
FFA
FS0
A0–A35
EFA
AEA
Device
Control
64 × 36
SRAM
Output Register
Mail1
Register
Read
Pointer
Input Register
Output Register
FS1
MBF2
AEB
CLKB
CSB
ENB
36
36
RST
MBF1
EFB
B0–B35
FFB
AFB
PEFB
PGB
ODD/
EVEN
Input Register
W/RB
Parity
Gen/Check
PEFA
PGA
Parity
Generation
Parity
Generation
SIZ0
SIZ1
SW0
SW1
Bus Matching and
Byte Swapping
Bus Matching and
Byte Swapping
36
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME I/O DESCRIPTION
A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
AEA O
(port A) Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words
in FIFO2 is less than or equal to value in offset register X.
AEB O
(port B) Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words
in FIFO1 is less than or equal to value in offset register X.
AFA O
(port A) Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty
locations in FIFO1 is less than or equal to the value in of fset register X.
AFB O
(port B) Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty
locations in FIFO2 is less than or equal to the value in of fset register X.
B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
BE IBig-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the
most-significant bytes on B0–B35 for use, and a high selects the least-significant bytes.
CLKA IPort-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of
CLKA.
CLKB I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. Port-B byte swapping and data-port sizing operations are also synchronous
to the low-to-high transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of
CLKB.
CSA IPort-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
CSB IPort-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
EFA O
(port A)
Port-A empty flag. EF A is synchronized to the low-to-high transition of CLKA. When EF A is low , FIFO2 is empty and
reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EF A is
forced low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded
into empty FIFO2 memory.
EFB O
(port B)
Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and
reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is
forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded
into empty FIFO1 memory.
ENA IPort-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB IPort-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FFA O
(port A)
Port-A full flag. FF A is synchronized to the low-to-high transition of CLKA. When FF A is low , FIFO1 is full and writes
to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high
transition of CLKA after reset.
FFB O
(port B)
Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low , FIFO2 is full and writes
to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high
transition of CLKB after reset.
FS1, FS0 IFlag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the almost-empty flag and almost-full flag offset.
MBA IPort-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When
the A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level
selects FIFO2 output register data for output.
MBF1 OMail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register . Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a
port-B read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset.
MBF2 OMail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register . Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a
port-A read is selected and MBA is high. MBF2 is set high when the device is reset.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME I/O DESCRIPTION
ODD/EVEN IOdd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low . ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
PEFA O
(port A)
Port-A parity-error flag. When any byte applied to terminals A0–A35 fails parity, PEFA is low . Bytes are organized
as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The
type of parity checked is determined by the state of ODD/EVEN.
The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/RA low , MBA
high, and PGA high, the PEFA flag is forced high, regardless of the state of the A0–A35 inputs.
PEFB O
(port B)
Port-B parity-error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are
organized as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each byte serving as the parity
bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by
the state of ODD/EVEN.
The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/RB low, SIZ1
and SIZ0 high, and PGB high, the PEFB flag is forced high, regardless of the state of the B0–B35 inputs.
PGA IPort-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity
generated is selected by the state of ODD/EVEN. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.
The generated parity bits are output in the most-significant bit of each byte.
PGB IPort-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity
generated is selected by the state of ODD/EVEN. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.
The generated parity bits are output in the most-significant bit of each byte.
RST I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low. The
low-to-high transition of RST latches the status of the FS1 and FS0 inputs to select almost-full flag and almost-empty
flag of fset.
SIZ0, SIZ1 I
(port B)
Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the
following low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can
be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write
or read.
SW0, SW1 I
(port B)
Port-B byte-swap selects. At the beginning of each long-word transfer, one of four modes of byte-order swapping
is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swapping is possible with any bus-size selection.
W/RA I Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
W/RB I Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is high.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
reset
The SN54ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EF A, EFB) low , the almost-empty flags (AEA, AEB) low , and the almost-full flags (AFA, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
Table 1. Flag Programming
FS1 FS0 RST ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H ↑16
H L ↑12
L H ↑8
L L ↑4
FIFO write/read operation
The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the
A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FF A is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).
Table 2. Port-A Enable Function Table
CSA W/RA ENA MBA CLKA A0–A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑In high-impedance state FIFO1 write
L H H H ↑In high-impedance state Mail1 write
L L L L X Active, FIFO2 output register None
L L H L ↑Active, FIFO2 output register FIFO2 read
L L L H X Active, mail2 register None
L L H H ↑Active, mail2 register Mail2 read (set MBF2 high)
The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The B0–B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the
B0–B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high,
and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high transition of CLKB
when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FIFO write/read operation (continued)
Table 3. Port-B Enable Function Table
CSB W/RB ENB SIZ1, SIZ0 CLKB B0–B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H One, both low ↑In high-impedance state FIFO2 write
L H H Both high ↑In high-impedance state Mail2 write
L L L One, both low XActive, FIFO1 output register None
L L H One, both low ↑Active, FIFO1 output register FIFO1 read
L L L Both high XActive, mail1 register None
L L H Both high ↑Active, mail1 register Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously
to one another (see the application report
Metastability Performance of Clocked FIFOs
in the 1996
High-Performance FIFO Memories Data Book
, literature number SCAD003). EFA, AEA, FFA, and AFA are
synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the
relationship of each port flag to FIFO1 and FIFO2.
Table 4. FIFO1 Flag Operation
NUMBER OF 36-BIT
WORDS IN FIFO1†
SYNCHRONIZED
TO CLKB SYNCHRONIZED
TO CLKA
WORDS
IN
FIFO1†
EFB AEB AFA FFA
0 L L H H
1 to X H L H H
(X + 1) to [64 – (X + 1)] H H H H
(64 – X) to 63 H H L H
64 H H L L
†X is the value in the almost-empty flag and almost-full flag offset register.
Table 5. FIFO2 Flag Operation
NUMBER OF 36-BIT
WORDS IN FIFO2†
SYNCHRONIZED
TO CLKA SYNCHRONIZED
TO CLKB
WORDS
IN
FIFO2†
EFA AEA AFB FFB
0 L L H H
1 to X H L H H
(X + 1) to [64 – (X + 1)] H H H H
(64 – X) to 63 H H L H
64 H H L L
†X is the value in the almost-empty flag and almost-full flag offset register.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
empty flags (EFA, EFB)
The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag
is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and
attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when
the fourth byte or second word of the last long word is read.
The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state
machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when
the FIFO SRAM status is empty , empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output
register in a minimum of three cycles of the empty-flag synchronizing clock; therefore, an empty flag is low if
a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that
reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is
set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to
the FIFO output register in the following cycle.
A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 13 and 14).
full flags (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high,
a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full
flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full,
full–1, or full–2. From the time a word is read from a FIFO, the previous memory location is ready to be written
in a minimum of three cycles of the full-flag synchronizing clock; therefore, a full flag is low if less than two cycles
of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The
second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data
can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater , after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 15 and 16).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is
defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of
four preset values during a device reset (see
reset
). An almost-empty flag is low when the FIFO contains X or
fewer long words in memory and is high when the FIFO contains (X + 1) or more long words.
T wo low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that
filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of
the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater ,
after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent synchronizing clock cycle can
be the first synchronization cycle (see Figures 17 and 18).
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the value of
the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during
a device reset (see
reset
). An almost-full flag is low when the FIFO contains (64 – X) or more long words in
memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words.
Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 – (X + 1)]
or fewer words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of long words in memory to [64 – (X + 1)]. An almost-full flag is set high by the second low-to-high
transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to
[64 – (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization
cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words in memory to
[64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB
writes B0–B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0
and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (A0–A35) are active, the data on the bus comes from the FIFO2 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0–B35) are
active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are
low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high
by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both port-B bus-size select
(SIZ1 and SIZ0) inputs are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A
read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after
it is read and changes only when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1
or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big
endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to CLKB to communicate with peripherals of various bus widths.
The levels applied to SIZ0 and SIZ1 and the big-endian select (BE) input are stored on each CLKB low-to-high
transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to
Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN54ABT3614.
Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2
RAM. Port-B bus sizing does not apply to mail-register operations.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Read From FIFO1/Write to FIFO2
Write to FIFO1/Read From FIFO2
(a) LONG WORD SIZE
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1st: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2nd: Read From FIFO1/Write to FIFO2
(b) WORD SIZE – BIG ENDIAN
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1st: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2nd: Read From FIFO1/Write to FIFO2
(c) WORD SIZE – LITTLE ENDIAN
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1st: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2nd: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3rd: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4th: Read From FIFO1/Write to FIFO2
(d) BYTE SIZE – BIG ENDIAN
BYTE ORDER ON PORT A:
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
XLL
BE SIZ1 SIZ0
ABCD
ABCD
AB
CD
CD
AB
A
B
C
D
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
LLH
BE SIZ1 SIZ0
HLH
BE SIZ1 SIZ0
LHL
BE SIZ1 SIZ0
Figure 1. Dynamic Bus Sizing
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2nd: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3rd: Read From FIFO1/Write to FIFO2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4th: Read From FIFO1/Write to FIFO2
(e) BYTE SIZE – LITTLE ENDIAN
1st: Read From FIFO1/Write to FIFO2
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
D
C
B
A
HHL
BE SIZ1 SIZ0
Figure 1. Dynamic Bus Sizing (Continued)
bus-matching FIFO1 reads
Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIFO1 output register . If byte or word size is implemented on port B,
only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size
implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1.
Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIFO1 in byte or word format, the unused B0–B35 outputs remain inactive but static
with the unused FIFO1 output register bits holding the last data value to decrease power consumption.
bus-matching FIFO2 writes
Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes, with a long-word bus size,
immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write
before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port-B mail-register access
In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZ0, SIZ1) inputs
also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately and any bus-sizing operation that can be underway is unaffected by the the mail-register access.
After the mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The
logic diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are
accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of
SIZ0_Q, SIZ1_Q, and BE_Q.
MUX
CLKB
SIZ0
SIZ1
BE
SIZ0_Q
SIZ1_Q
BE_Q
DQ
G1
1
1
Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register
byte swapping
The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous
to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order
swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is
rearranged within the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap select (SW0, SW1) inputs on a CLKB rising edge that reads
a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first
word of a new long-word read from FIFO1 or written to FIFO2 is maintained until the entire long word is
transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example
of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for
a FIFO1 read rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes load the data according to Figure 1,
then swap the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(a) NO SWAP
(b) BYTE SWAP
(c) WORD SWAP
(d) BYTE-WORD SWAP
LL
SW1 SW0
LH
SW1 SW0
HL
SW1 SW0
HH
SW1 SW0
A35 A27 A26 A18 A17 A9 A8 A0
AB C D
AB C D
AB C D
AB C D
AB C D
DC B A
CD A B
BA D C
B35 B27 B26 B18 B17 B9 B8 B0
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
Figure 3. Byte Swapping (Long-Word Size Example)
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
parity checking
The port-A data inputs (A0–A35) and port-B data inputs (B0–B35) each have four parity trees to check the parity
of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low
level on the port-A parity-error flag (PEFA). A parity failure on one or more bytes of the port-B data inputs that
are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB). Odd-
or even-parity checking can be selected, and the parity-error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding port
parity-error flag (PEF A, PEFB) output. Port-A bytes are arranged as A0–A8, A9–A17, A18–A26, and A27–A35.
Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35, and its valid bytes are those used in
a port-B bus-size implementation. When odd/even parity is selected, a port parity-error flag (PEFA, PEFB) is
low if any valid byte on the port has an odd/even number of low levels applied to the bits.
The four parity trees used to check the A0–A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is
held high regardless of the levels applied to the A0–A35 inputs. Likewise, the parity trees used to check the
B0–B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = high).
When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB high, and W/RB
low , both SIZ0 and SIZ1 high, and PGB high, the port-B parity-error flag (PEFB) is held high, regardless of the
levels applied to the B0–B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN54ABT3614 to generate parity bits for port reads from a FIFO or mailbox register . Port-A bytes are arranged
as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte used as the parity bit.
Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte,
regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on
the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the
most-significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register; therefore, the port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN)
have setup- and hold-time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB)
and ODD/EVEN have setup and hold-time constraints to the port-B clock (CLKB). These timing constraints only
apply for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0–B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0–A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip
select (CSA, CSB) is low, enable (ENA, ENB) is high, write/read select (W/RA, W/RB) input is low, the mail
register is selected (MBA is high for port A; both SIZ0 and SIZ1 are high for port B), and port parity-generate
select (PGA, PGB) is high. Generating parity for mail-register data does not change the contents of the register.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
tpd(C-AF)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌ
CLKA
CLKB
RST
0,1
th(FS)
tsu(FS)
th(RS)
tsu(RS)
FS1, FS0
FFA
tpd(C-FF) tpd(C-FF)
EFA
tpd(C-EF)
tpd(C-AE)
AEA
AFA
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎ
MBF1,
MBF2
tpd(R-F)
tpd(C-FF) tpd(C-FF)
FFB
EFB
tpd(C-AF)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tpd(C-AE)
AEB
AFB
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
tpd(C-EF)
Figure 4. Device Reset Loading the X Register With the Value of Eight
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌÌ
tsu(D)
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏ
ÌÌÌÌÌÌÌ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
CLKA
FFA
CSA
W2†
tsu(EN)
tw(CLKL)
ÌÌÌÌÌÌ
tc
tw(CLKH)
th(EN)
th(EN)
tsu(EN) tsu(EN)
ÌÌÌ
ÌÌÌ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
W/RA
MBA
ENA
A0–A35 W1†
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
tsu(EN) th(EN)
tsu(EN) th(EN)
tsu(EN) th(EN)
th(D)
th(EN)
No Operation
ÌÌ
ODD/
EVEN
ÌÌÌÌÌÌÌÌÌÌÌÌ
Ì
Valid
ÌÌÌÌÌÌ
PEFA Valid
ÌÌ
tpd(D-PE) tpd(D-PE)
High
†Written to FIFO1
Figure 5. Port-A Write Cycle for FIFO1
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌ
SIZ1,
SIZ0
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
tsu(EN)
ÌÌÌÌÌÌ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
W/RB
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏ
ÌÌÌÌÌÌ
CLKB
FFB
CSB
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
tsu(EN)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ENB
B0–B35
tsu(EN)
tsu(EN) th(EN)
tsu(D) th(D)
th(EN)
ODD/
EVEN
Valid
PEFB
Valid
tpd(C-PE) tpd(D-PE)
High
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
SW1,
SW0
tsu(SW) th(SW)
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
(0, 0)
Not (1, 1)†
(0, 0)
tsu(SZ) th(SZ)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
BE
ÌÌ
th(SZ)
tsu(SZ)
ÌÌ
ÌÌ
†SIZ0 = H and SIZ1 = H writes data to the mail2 register.
DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2
SWAP MODE DATA WRITTEN TO FIFO2 DATA READ FROM FIFO2
SW1 SW0 B35–B27 B26–B18 B17–B9 B8–B0 A35–A27 A26–A18 A17–A9 A8–A0
L L A B C D A B C D
L H D C B A A B C D
H L C D A B A B C D
H H B A D C A B C D
Figure 6. Port-B Long-Word Write Cycle for FIFO2
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÏÏÏÏÏ
ÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
SIZ1, SIZ0
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
W/RB
CLKB
FFB
CSB
ENB
(0, 1)
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
(0, 1) Not (1, 1)†
BE
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
B0–B17
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
B18–B35
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
Little
Endian
Big
Endian
ODD/EVEN
PEFB
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
Valid Valid
tpd(C-PE) tpd(D-PE)
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
SW1, SW0
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
High
tsu(D) th(D)
tsu(D) th(D)
tsu(SZ) th(SZ)
tsu(SZ) th(SZ)
tsu(SW) th(SW)
tsu(EN) th(EN) tsu(EN) th(EN)
tsu(EN)
tsu(EN) th(EN)
tsu(SZ) th(SZ)
tsu(SZ) th(SZ)
†SIZ0 = H and SIZ1 = H writes data to the mail2 register.
NOTE A: PEFB indicates parity error for the following bytes: B35–B27 and B26–B18 for big-endian bus, and B17–B9 and B8–B0 for little-endian
bus.
DATA SWAP TABLE FOR WORD WRITES TO FIFO2
SWAP MODE
WRITE
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
SWAP
MODE
WRITE
NO
BIG ENDIAN LITTLE ENDIAN
DATA
READ
FROM
FIFO2
SW1 SW0
NO
.B35–B27 B26–B18 B17–B9 B8–B0 A35–A27 A26–A18 A17–A9 A8–A0
L
L
1 A B C D
A
B
C
D
L
L
2 C D A B
A
B
C
D
L
H
1 D C B A
A
B
C
D
L
H
2 B A D C
A
B
C
D
H
L
1 C D A B
A
B
C
D
H
L
2 A B C D
A
B
C
D
H
H
1 B A D C
A
B
C
D
H
H
2 D C B A
A
B
C
D
Figure 7. Port-B Word Write Cycle for FIFO2
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
tpd(C-PE)
ÌÌÌ
tpd(D-PE)
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
SIZ1, SIZ0
W/RB
CLKB
FFB
CSB
ENB
BE
B0–B8
B27–B35
Little
Endian
Big
Endian
ODD/EVEN
PEFB Valid
SW1, SW0
ÌÌÌ
ÌÌÌ
Valid
ÌÌÌÌ
ÌÌÌÌ
Valid
Valid
ÌÌ
ÌÌ
ÌÌ
ÌÌ
tpd(D-PE) tpd(D-PE)
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tsu(D) th(D)
ÌÌÌ
ÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
(1, 0) (1, 0) (1, 0)
Not (1, 1)†
ÌÌÌÌ
(1, 0)
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tsu(D) th(D)
tsu(SZ) th(SZ)
tsu(SZ) th(SZ)
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
tsu(SZ) th(SZ)
tsu(SZ) th(SZ)
ÏÏÏÏ
ÏÏÏÏ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tsu(SW) th(EN)
tsu(EN) th(EN) tsu(EN) th(EN)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
High
tsu(EN)
tsu(EN) th(EN)
†SIZ0 = H and SIZ1 = H writes data to the mail2 register.
NOTE A: PEFB indicates parity error for the following bytes: B35–B27 for big-endian bus and B17–B9 for little-endian bus.
Figure 8. Port-B Byte Write Cycle for FIFO2
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2
SWAP MODE
WRITE
DATA WRITTEN
TO FIFO2
DATA READ FROM FIFO2
SWAP
MODE
WRITE
NO. BIG
ENDIAN LITTLE
ENDIAN
DATA
READ
FROM
FIFO2
SW1 SW0 B35–B27 B8–B0 A35–A27 A26–A18 A17–A9 A8–A0
1 A D
L
L
2 B C
A
B
C
D
L
L
3 C B
A
B
C
D
4 D A
1 D A
L
H
2 C B
A
B
C
D
L
H
3 B C
A
B
C
D
4 A D
1 C B
H
L
2 D A
A
B
C
D
H
L
3 A D
A
B
C
D
4 B C
1 B C
H
H
2 A D
A
B
C
D
H
H
3 D A
A
B
C
D
4 C B
Figure 8. Port-B Byte Write Cycle for FIFO2 (Continued)
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÌÌÌÌÌÌ
SIZ1,
SIZ0
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌ
W/RB
ÏÏÏÏÏÏ
ÌÌÌÌÌÌ
CLKB
EFB
CSB
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ENB
B0–B35
tsu(EN) th(EN)
PGB,
ODD/
EVEN
High
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
SW1,
SW0
tsu(SW) th(SW)
(0, 0) Not (1, 1)†
(0, 0)
tsu(SZ) th(SZ)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
BE
ÌÌ
th(SZ)
tsu(SZ)
tsu(EN) th(EN)
Not (1, 1)†
th(PG)
ten Previous Data W1‡W2‡
tatatdis
No Operation
tsu(PG)
†SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.
‡Data read from FIFO1
DATA SWAP TABLE FOR LONG-WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1 SWAP MODE DATA READ FROM FIFO1
A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0 B35–B27 B26–B18 B17–B9 B8–B0
A B C D L L A B C D
A B C D L H D C B A
A B C D H L C D A B
A B C D H H B A D C
Figure 9. Port-B Long-Word Read Cycle for FIFO1
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌ
ÌÌÌ
ÎÎÎÎ
ÎÎÎÎ
ÌÌÌÌÌÌ
SIZ1,
SIZ0
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
W/RB
ÏÏÏÏÏ
ÌÌÌÌÌ
CLKB
EFB
CSB
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ENB
B0–B17
tsu(EN) th(EN)
PGB,
ODD/
EVEN
High
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
SW1,
SW0
tsu(SW) th(SW)
(0, 1) Not (1, 1)†
(0, 1)
tsu(SZ) th(SZ)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
BE
ÌÌÌ
th(SZ)
tsu(SZ)
Not (1, 1)†
tsu(PG) th(PG)
ten
Previous Data Read 1 Read 2
tatatdis
No Operation
Little
Endian‡
Big
Endian‡B18–B35 Previous Data Read 1 Read 2
tatatdis
†SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.
‡Unused word B0–B17 or B18–B35 holds last FIFO1 output register data for word-size reads.
DATA SWAP TABLE FOR WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
READ
DATA READ FROM FIFO1
DATA
WRITTEN
TO
FIFO1
SWAP
MODE
READ
NO
BIG ENDIAN LITTLE ENDIAN
A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0
NO
.B35–B27 B26–B18 B17–B9 B8–B0
A
B
C
D
L
L
1 A B C D
A
B
C
D
L
L
2 C D A B
A
B
C
D
L
H
1 D C B A
A
B
C
D
L
H
2 B A D C
A
B
C
D
H
L
1 C D A B
A
B
C
D
H
L
2 A B C D
A
B
C
D
H
H
1 B A D C
A
B
C
D
H
H
2 D C B A
Figure 10. Port-B Word Read Cycle for FIFO1
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
(1, 0)
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÌÌÌÌ
SIZ1, SIZ0
W/RB
CLKB
EFB
CSB
ENB
BE
SW1, SW0
Not (1, 1)†
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÎÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
High
tsu(EN) th(EN)
ÎÎÎÎÎ
ÎÎÎÎÎ
No
Operation
tsu(SW) th(SW)
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tsu(SZ)
tsu(SZ)
(1, 0)
Not (1, 1)†(1, 0) (1, 0)
Not (1, 1)†Not (1, 1)†
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
PGB,
ODD/EVEN
tsu(PG) th(PG)
B0–B8 Read 1 Read 2
ten tatatata
Read 3 Read 4
tdis
B27–B35 Read 1 Read 2
Previous Data
tatatata
Read 3 Read 4
tdis
th(SZ)
th(SZ)
Previous Data
†SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.
NOTE A: Unused bytes hold last FIFO1 output register data for byte-size reads.
Figure 11. Port-B Byte Read Cycle for FIFO1
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
READ
DATA READ
FROM FIFO1
DATA
WRITTEN
TO
FIFO1
SWAP
MODE
READ
NO. BIG
ENDIAN LITTLE
ENDIAN
A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0 B35–B27 B8–B0
1 A D
A
B
C
D
L
L
2 B C
A
B
C
D
L
L
3 C B
4 D A
1 D A
A
B
C
D
L
H
2 C B
A
B
C
D
L
H
3 B C
4 A D
1 C B
A
B
C
D
H
L
2 D A
A
B
C
D
H
L
3 A D
4 B C
1 B C
A
B
C
D
H
H
2 A D
A
B
C
D
H
H
3 D A
4 C B
Figure 11. Port-B Byte Read Cycle for FIFO1 (Continued)
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
tsu(EN) tsu(EN)
No
Operation
tsu(EN)
ÏÏÏÏ
ÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Ì
Ì
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
tpd(M-DV)
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
CLKA
EFA
CSA
W1†
tw(CLKL)
tc
tw(CLKH)
th(EN)
W/RA
MBA
ENA
A0–A35 W2†
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ta
ten tatdis
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÌÌÌÌÌ
ÌÌÌÌÌ
PGA,
ODD/EVEN
tsu(PG) tsu(PG)
th(PG) th(PG)
th(EN) th(EN)
Previous Data
High
†Read from FIFO2
Figure 12. Port-A Read Cycle for FIFO2
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
th(EN)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th(EN)
tsu(EN)
CLKA
EFB
W1
A0–A35
MBA
ENA
CSA
W/RA
FFA
CLKB
CSB
W/RB
SIZ1, SIZ0
ENB
W1
B0–B35
tc
th(EN)
tsu(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
ÎÎÎÎ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tw(CLKH) tw(CLKL)
tpd(C-EF)
FIFO1 Empty
ta
12
ÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Low
High
tw(CLKL)
tw(CLKH)
High
tsu(EN)
th(D)
tsu(D)
tsk1†tc
Low
Low
Low
tpd(C-EF)
†tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of EFB high may occur one CLKB cycle later than shown.
NOTE A: Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, EFB is set low by the last word
or byte read from FIFO1, respectively.
Figure 13. EFB-Flag Timing and First Data Read When FIFO1 Is Empty
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏ
ÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th(EN)
tsu(EN)
CLKB
EFA
W1
B0–B35
SIZ1, SIZ0
ENB
CSB
W/RB
FFB
CLKA
CSA
W/RA
MBA
ENA
W1
A0–A35
tc
th(EN)
tsu(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tw(CLKH) tw(CLKL)
tpd(C-EF)
FIFO2 Empty
ta
12
Low
High
tw(CLKL)
tw(CLKH)
High
th(EN)
tsu(EN)
th(D)
tsu(D)
tsk1†tc
Low
Low
Low
tpd(C-EF)
†tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk1, the transition of EF A high may occur one CLKA cycle later than shown.
NOTE A: Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced to the rising
CLKB edge that writes the last word or byte of the long word, respectively.
Figure 14. EFA-Flag Timing and First Data Read When FIFO2 Is Empty
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKB
FFA
B0–B35
SIZ1, SIZ0
ENB
CSB
W/RB
EFB
CLKA
CSA
W/RA
MBA
ENA
A0–A35
tsu(EN) th(EN)
tc
th(EN)
tsu(EN)
tpd(C-FF)
FIFO1 Full
tc
tsk1†
ÏÏÏ
ÏÏÏ
ÎÎÎÎ
ÎÎÎÎ
ta
Previous Word in FIFO1 Output Register Next Word From FIFO1
tw(CLKH) tw(CLKL)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
To FIFO1
Low
Low
Low
Low
High
th(EN)
tsu(EN)
th(D)
tsu(D)
High
tw(CLKH) tw(CLKL)
tpd(C-FF)
12
†tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk1, FFA may transition high one CLKA cycle later than shown.
NOTE A: Port-B size of long word is selected for the FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced from
the rising CLKB edge that reads the first word or byte of the long word, respectively.
Figure 15. FFA-Flag Timing and First Available Write When FIFO1 Is Full
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tsu(EN) th(EN)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎ
CLKA
FFB
A0–A35
MBA
ENA
CSA
W/RA
EFA
CLKB
CSB
W/RB
SIZ1, SIZ0
ENB
B0–B35
tw(CLKH)
tsu(EN) th(EN)
tc
th(EN)
tsu(EN)
tpd(C-FF)
FIFO2 Full
tc
tsk1†
ÏÏÏ
ÏÏÏ
ÎÎÎÎ
ÎÎÎÎ
ta
Previous Word in FIFO2 Output Register Next Word From FIFO2
tw(CLKH) tw(CLKL)
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
To FIFO2
Low
Low
Low
th(D)
tsu(D)
High
Low
High
tw(CLKL)
tpd(C-FF)
12
†tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk1, FFB may transition high one CLKB cycle later than shown.
NOTE A: Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, FFB is set low by the last word
or byte write of the long word, respectively.
Figure 16. FFB-Flag Timing and First Available Write When FIFO2 Is Full
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tsu(EN)
CLKA
AEB
ENB
ENA
th(EN)
tsu(EN)
tsk2†
tpd(C-AE)
X Long Words in FIFO1
1
ÎÎÎÎÎ
ÎÎÎÎÎ
CLKB 2
tpd(C-AE)
th(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÎÎÎÎÎ
(X + 1) Long Words in FIFO1
†tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, AEB may transition high one CLKB cycle later than shown.
NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L)
B. Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AEB is set low by the first
word or byte read of the long word, respectively.
Figure 17. AEB When FIFO1 Is Almost Empty
tsu(EN)
CLKB
AEA
ENA
ENB
th(EN)
tsu(EN)
tsk2‡
tpd(C-AE)
1
ÎÎÎÎÎ
ÎÎÎÎÎ
CLKA 2
tpd(C-AE)
th(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÎÎÎÎÎ
ÎÎÎÎÎ
X Long Words in FIFO2 (X + 1) Long Words in FIFO2
‡tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk2, AEA may transition high one CLKA cycle later than shown.
NOTES: A. FIFO2 write (CSB = L, W/RB = H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L)
B. Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk2 is referenced from
the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 18. AEA When FIFO2 Is Almost Empty
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tpd(C-AF) tpd(C-AF)
tsu(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
CLKA
AFA
ENB
ENA
tsu(EN) th(EN)
[64 – (X + 1)] Long Words in FIFO1
ÎÎÎÎÎ
ÎÎÎÎÎ
th(EN)
tsk2
†
12
ÏÏÏÏÏ
ÎÎÎÎÎ
CLKB
(64 – X) Long Words in FIFO1
†tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, AFA may transition high one CLKB cycle later than shown.
NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L)
B. Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk2 is referenced from
the first word or byte read of the long word, respectively.
Figure 19. AFA When FIFO1 Is Almost Full
tpd(C-AF) tpd(C-AF)
tsu(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
CLKB
AFB
ENA
ENB
tsu(EN) th(EN)
[64 – (X + 1)] Long Words in FIFO2
ÎÎÎÎÎ
ÎÎÎÎÎ
th(EN)
tsk2
‡
12
ÏÏÏÏÏ
ÏÏÏÏÏ
ÎÎÎÎÎ
ÎÎÎÎÎ
CLKA
(64 – X) Long Words in FIFO2
‡tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk2, AFB may transition high one CLKA cycle later than shown.
NOTES: A. FIFO2 write (CSB = L, W/RB= H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L)
B. Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AFB is set low by the last
word or byte write of the long word, respectively.
Figure 20. AFB When FIFO2 Is Almost Full
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌ
ÎÎÎÎÎÎÎ
CLKA
CSA
W/RA
tsu(EN)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(D)
MBA
ENA
A0–A35 W1
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÎÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
th(EN)
tsu(D)
CLKB
th(EN)
CSB
tsu(EN)
tpd(C-MF)
tpd(C-MF)
MBF1
ÏÏÏÏÏ
W/RB
ÎÎÎÎÎÎ
SIZ1, SIZ0
ENB
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏ
ÏÏÏ
B0–B35 FIFO1 Output Register
ÌÌÌ
ÌÌÌ
W1 (remains valid in mail1 register after read)
ten tpd(C-MR) tdis
tpd(M-DV)
NOTE A: Port-B parity generation off (PGB = L)
Figure 21. Mail1 Register and MBF1 Flag
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌ
ÌÌÌ
CLKB
CSB
W/RA
SIZ1, SIZ0
ENB
A0–A35
CLKA
CSA
MBF2
W/RB
MBA
ENA
B0–B35
ÌÌÌÌÌÌÌ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tsu(EN)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(D)
W1
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÌÌÌ
th(EN)
tsu(D)
th(EN)
tsu(EN)
tpd(C-MF)
tpd(C-MF)
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏÏ
ÏÏÏÏ
FIFO2 Output Register
ÌÌÌÌ
ÌÌÌÌ
W1 (remains valid in mail2 register after read)
ten tpd(C-MR) tdis
tpd(M-DV)
th(SZ)
tsu(SZ)
NOTE A: Port-A parity generation off (PGA = L)
Figure 22. Mail2 Register and MBF2 Flag
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MBA
tpd(E-PE)
tpd(E-PE)
Valid
tpd(O-PE)
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ODD/EVEN
W/RA
PGA
PEFA Valid
tpd(O-PE)
Valid Valid
NOTE A: ENA is high and CSA is low.
Figure 23. ODD/EVEN, W/RA, MBA, and PGA to PEFA
tpd(E-PE)
tpd(E-PE)
Valid
tpd(O-PE)
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ODD/EVEN
W/RB
PGB
PEFB
SIZ1,
SIZ0
Valid
tpd(O-PE)
Valid Valid
NOTE A: ENB is high and CSB is low.
Figure 24. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎÎÎÎ
ten
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ODD/
EVEN
CSA
PGA
A8, A17,
A26, A35
MBA
Generated Parity
Low
W/RA
ÎÎÎÎÎÎÎ
Mail2
Data
tpd(E-PB) tpd(O-PB)
Generated Parity
tpd(E-PB)
Mail2 Data
tpd(M-DV)
NOTE A: ENA is high.
Figure 25. Parity-Generation Timing When Reading From the Mail2 Register
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ten
ÌÌÌÌÌÌÌ
ODD/
EVEN
CSB
PGB
B8, B17,
B26, B35
SIZ1,
SIZ0
Generated Parity
Low
W/RB
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Mail1
Data
tpd(E-PB) tpd(O-PB)
Generated Parity
tpd(E-PB)
Mail1 Data
tpd(M-DV)
NOTE A: ENB is high.
Figure 26. Parity-Generation Timing When Reading From the Mail1 Register
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
recommended operating conditions
MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –4 mA
IOL Low-level output current 8 mA
TAOperating free-air temperature –55 125 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VOH VCC = 4.5 V, IOH = –4 mA 2.4 V
VOL VCC = 4.5 V, IOL = 8 mA 0.5 V
IIVCC = 5.5 V, VI = VCC or 0 ±50 µA
IOZ VCC = 5.5 V, VO = VCC or 0 ±50 µA
§
Outputs high 30
ICC
§
VCC = 5.5 V, IO = 0 mA, VI = VCC or GND Outputs low 130 mA
Outputs disabled 30
CiVI = 0, f = 1 MHz 4 pF
CoVO = 0, f = 1 MHz 8 pF
‡All typical values are at VCC = 5 V, TA = 25°C.
§ICC is measured in the A-to-B direction.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 4 through 27)
MIN MAX UNIT
fclock Clock frequency, CLKA or CLKB 50 MHz
tcClock cycle time, CLKA or CLKB 20 ns
tw(CLKH) Pulse duration, CLKA and CLKB high 8 ns
tw(CLKL) Pulse duration, CLKA and CLKB low 8 ns
tsu(D) Setup time, A0–A35 before CLKA↑and B0–B35 before CLKB↑5 ns
tsu(EN) Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB, W/RB, and ENB before CLKB↑5 ns
tsu(SZ) Setup time, SIZ0, SIZ1, and BE before CLKB↑5 ns
tsu(SW) Setup time, SW0 and SW1 before CLKB↑7 ns
tsu(PG) Setup time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before CLKB↑†6 ns
tsu(RS) Setup time, RST low before CLKA↑ or CLKB↑‡6 ns
tsu(FS) Setup time, FS0 and FS1 before RST high 6 ns
th(D) Hold time, A0–A35 after CLKA↑and B0–B35 after CLKB↑3 ns
th(EN) Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, and ENB after CLKB↑3 ns
th(SZ) Hold time, SIZ0, SIZ1, and BE after CLKB↑2 ns
th(SW) Hold time, SW0 and SW1 after CLKB↑7 ns
th(PG) Hold time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after CLKB↑†1 ns
th(RS) Hold time, RST low after CLKA↑ or CLKB↑‡6 ns
th(FS) Hold time, FS0 and FS1 after RST high 4 ns
tsk1§Skew time between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB 8 ns
tsk2§Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 16 ns
†Applies only for a clock edge that does a FIFO read
‡Requirement to count the clock edge as one of at least four needed to reset a FIFO
§Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 4 through 27)
PARAMETER MIN MAX UNIT
fmax 50 MHz
taAccess time, CLKA↑ to A0–A35 and CLKB↑ to B0–B35 2 12 ns
tpd(C-FF) Propagation delay time, CLKA↑ to FFA and CLKB↑ to FFB 2 12 ns
tpd(C-EF) Propagation delay time, CLKA↑ to EFA and CLKB↑ to EFB 2 12 ns
tpd(C-AE) Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB 2 12 ns
tpd(C-AF) Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB 2 12 ns
tpd(C-MF) Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high 1 12 ns
tpd(C-MR) Propagation delay time, CLKA↑ to B0–B35† and CLKB↑ to A0–A35‡3 13 ns
tpd(C-PE)§Propagation delay time, CLKB↑ to PEFB 2 12 ns
tpd(M-DV) Propagation delay time, MBA to A0–A35 valid and SIZ1, SIZ0 to B0–B35 valid 1 11.5 ns
tpd(D-PE) Propagation delay time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 12.5 ns
tpd(O-PE) Propagation delay time, ODD/EVEN to PEFA and PEFB 3 14 ns
tpd(O-PB)
Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 12 ns
tpd(E-PE) Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1,
SIZ0, or PGB to PEFB 1 23 ns
tpd(E-PB)
Propagation delay time, MBA or PGA to parity bits (A8, A17, A26, A35); SIZ1, SIZ0, or PGB to
parity bits (B8, B17, B26, B35) 3 19 ns
tpd(R-F) Propagation delay time, RST to (MBF1, MBF2) high 1 20 ns
ten Enable time, CSA and W/RA low to A0–A35 active and
CSB low and W/RB high to B0–B35 active 2 12 ns
tdis Disable time, CSA or W/RA high to A0–A35 at high impedance and
CSB high or W/RB low to B0–B35 at high impedance 1 9 ns
†Writing data to the mail1 register when the B0–B35 outputs are active and SIZ1, SIZ0 are high
‡Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high
§Applies only when a new port-B bus size is implemented by the rising CLKB edge
Applies only when reading data from a mail register
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
1.5 V1.5 V
3 V
3 V
GND
GND
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data,
Enable
Input
1.5 V 1.5 V 3 V
3 V
GND
GND
High-Level
Input
Low-Level
Input
tw
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
tpd tpd
Input 1.5 V 1.5 V
1.5 V1.5 V
3 V
GND
VOH
VOL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL
VOH
tPLZ ≈ 3 V
tPHZ
1.5 V 1.5 V 3 V
GND
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tPZL
1.5 V
≈ 0 V
1.5 V
tPZH
Output
Enable
Low-Level
Output
High-Level
Output
From Output
Under Test
30 pF
(see Note A)
680 Ω
1.1 kΩ
5 V
LOAD CIRCUIT
NOTES: A. Includes probe and jig capacitance
B. tPZL and tPZH are the same as ten
C. tPLZ and tPHZ are the same as tdis
Figure 27. Load Circuit and Voltage Waveforms
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
– Supply Current – mA
CC(f)
SUPPLY CURRENT
vs
CLOCK FREQUENCY
fclock – Clock Frequency – MHz
150
100
50
001020304050
200
250
300
60 70 80
350
400 fdata = 1/2 fclock
TA = 25°C
CL = 0 pF
VCC = 5.5 V
VCC = 5 V
VCC = 4.5 V
I
Figure 28
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-9560901NXD ACTIVE HLQFP PCB 120 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT3614 :
•Catalog: SN74ABT3614
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
MECHANICAL DATA
MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCB (S-PQFP-G120) PLASTIC QUAD FLATPACK (DIE DOWN)
4040202/C 12/96
60
31 0,13 NOM
Gage Plane
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,23
61
30
90
1
11,60 TYP
0,13
91
120
SQ
SQ
15,80
16,20
13,80
1,60 MAX
1,45
1,35
14,20
0,08
0,40 M
0,07
0°–7°
Heat Slug
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced molded plastic package with a heat slug (HSL)
D. Falls within JEDEC MS-026
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