SLVS312A - JULY 2000 - REVISED DECEMBER 2002 D Overvoltage Protection and Lockout for D D D D D D D D D D OR P PACKAGE (TOP VIEW) 12 V, 5 V, 3.3 V Undervoltage Protection and Lockout for 5 V and 3.3 V Fault Protection Output With Open-Drain Output Stage Open-Drain Power Good Output Signal for Power Good Input, 3.3 V and 5 V Power Good Delay; 300-ms TPS3510, 150-ms TPS3511 75-ms Delay for 5-V and 3.3-V Power Supply Short-Circuit Turnon Protection 2.3-ms PSON Control to FPO Turnoff Delay 38-ms PSON Control Debounce 73-s Width Noise Deglitches Wide Supply Voltage Range From 4 V to 15 V PGI GND FPO PSON 1 8 2 7 3 6 4 5 PGO VDD VS5 VS33 description The TPS3510/1 is designed to minimize external components of personal-computer switching power supply systems. It provides protection circuits, power good indicator, fault protection output (FPO) and PSON control. Overvoltage protection (OVP) monitors 3.3 V, 5 V, and 12 V (12-V signal detects via VDD pin). Undervoltage protection (UVP) monitors 3.3 V and 5 V. When an OV or UV condition is detected, the power good output (PGO) is set to low and FPO is latched high. PSON from low to high resets the protection latch. UVP function is enabled 75 ms after PSON is set low and debounced. Furthermore, there is a 2.3-ms delay (and an additional 38-ms debounce) at turnoff. There is no delay during turnon. Power good feature monitors PGI, 3.3 V and 5 V and issues a power good signal when the output is ready. The TPS3510/1 is characterized for operation from -40C to 85C. typical application 5 VSB PGI PGO 12 V PSON (From Motherboard) 1 8 PGO PGI 2 7 VDD GND 3 6 VS5 FPO 4 5 PSON VS33 0.5 V Drop VSB 5V 3.3 V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated !" #!$% &"' &! #" #" (" " ") !" && *+' &! # ", &" " "%+ %!&" ", %% #""' POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 FUNCTION TABLE PGI PSON UV CONDITION (3.3 V OR 5 V) <0.95 V L no <0.95 V L no OV CONDITION (3.3 V, 5 V, OR 12 V) FPO PGO no L L yes H L <0.95 V L yes no L L 0.95 V<PGI<1.15 V L no no L L 0.95 V<PGI<1.15 V L no yes H L 0.95 V<PGI<1.15 V L yes no H L PGI > 1.15 V L no no L H PGI > 1.15 V L no yes H L PGI > 1.15 V L yes no H L x H x x H L x = don't care FPO = L means: fault IS NOT latched FPO = H means: fault IS latched PGO = L means: fault PGO = H means: NO fault 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 functional block diagram VDD 12 V OV + _ POR VS5 R 5 V OV + _ S 73-s Debounce FPO Q VS33 2.3-ms Delay 73-s Debounce VDD 3.3 V OV 38-ms Debounce + _ 3.3 V UV + _ 75-ms Delay VDD 5 V UV + _ + _ PGO PGI1 Band-Gap Reference 1.15 V PGI PSON 150-s Debounce Delay PGI2 + _ 150-s Debounce and 4.8-ms Delay Band-Gap Reference 0.95 V 300 ms for TPS3510 and 150 ms for TPS3511 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 timing diagram VDD PSON FPO PGI 3.3 V, 5 V 12 V PGO td1 td1 tb PG OFF Delay td1 td2 Protect Occur PSON On PSON On PSON Off Terminal Functions TERMINAL 4 NAME NO. FPO 3 GND 2 I/O O DESCRIPTION Inverted fault protection output, open drain output stage Ground PGI 1 I Power good input PGO 8 O Power good output, open drain output stage PSON 4 I ON/OFF control VDD VS33 7 I Supply voltage/12 V overvoltage protection input pin 5 I 3.3 V over/undervoltage protection VS5 6 I 5 V over/undervoltage protection POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 AC Off SLVS312A - JULY 2000 - REVISED DECEMBER 2002 detailed description power good and power good delay A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that the 5-V and 3.3-V outputs are above the under-voltage threshold limit. At this time the converter should be able to provide enough power to ensure continuous operation within the specification. Conversely, when either the 5-V or the 3.3-V output voltages fall below the under-voltage threshold, or when ac power has been removed for a time sufficiently long so that power supply operation is no longer ensured, PGO should be de-asserted to a low state. Figure 1 represents the timing characteristics of the power good (PGO), dc enable (PSON), and the 5 V/3.3 V supply rails. PSON On Off 75% 5-V/3.3-V Output 10% PGO t5 t4 t3 t2 Figure 1. Timing of PSON and PGO Although there is no requirement to meet specific timing parameters, the following signal timings are recommended: 2 ms t2 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 10 ms Furthermore motherboards should be designed to comply with the previously recommended timing. If timings other than these are implemented or required, this information should be clearly specified. The TPS3510/1 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a power-good delay. If the voltage signals at PGI, VS33, and VS5 rise above the under-voltage threshold, the open-drain power-good output (PGO) goes high after a delay of 150 ms or 300 ms. When the PGI voltage or either the 3.3-V and 5-V power rails drops below the under-voltage threshold, PGO is disabled immediately (after 150-s debounce). power supply remote on/off (PSON) and fault protect output (FPO) Since the latest personal computer generation focuses on easy turnon and power saving functions, the PC power supply requires two characteristics. One is a dc power supply remote on/off function, the other is standby voltage to achieve very low power consumption of the PC system. Thus the main power needs to be shut down. The power supply remote on/off (PSON) is an active low signal that turns on all of the main power rails including 3.3 V, 5 V, -5 V, 12 V, and -12 V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver current and should be held at 0 V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 power supply remote on/off (PSON) and fault protect output (FPO)(continued) When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs of the main power rails should not deliver current but are held at 0 V. Toggling the power supply remote on/off (PSON) from low to high resets the fault-protection latch. During this fault condition only the standby power is not affected. When PSON goes from high to low or low to high, the 38-ms debounce block is active to avoid a glitch on the input that disables/enables the FPO output. During this period the under-voltage function is disabled for 75 ms to prevent turnon failure. At turnoff, there is an additional delay of 2.3 ms from PSON to FPO. Power should be delivered to the rails only if the PSON signal is held at ground potential, thus FPO is active-low. The FPO pin can be connected to 5 V (or up to 15 V) through a pullup resistor. undervoltage protection The TPS3510/1 provides under-voltage protection (UVP) for the 3.3-V and 5-V rails. When an undervoltage condition appears at either one of the 3.3-V (VS33) or 5-V (VS5) input pins for more than 146 s, the FPO output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or VDD is removed. The need for undervoltage protection is often overlooked in off-line switching power supply system design. But it is very important in battery-powered or hand-held equipment since the TTL or CMOS logic often results in malfunction. In flyback or forward-type off-line switching power supplies, usually designed for low power, the overload protection design is very simple. Most of these types of power supplies are only sensing the input current for an overload condition. The trigger point needs to be set much higher than the maximum load in order to prevent false turnon. However, this causes one critical problem. If the connected load is larger than the maximum allowable load but smaller than the trigger point, the system always becomes overheated with failure and damage occurring. overvoltage protection The overvoltage protection (OVP) of TPS3510/1 monitors 3.3 V, 5 V, and 12 V (12 V is sensed via the VDD pin). When an overvoltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 s, the FPO output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or VDD is removed. During fault conditions, most power supplies have the potential to deliver higher output voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages to be high enough to cause internal or external damage of the system. To protect the system under these abnormal conditions, it is common practice to provide overvoltage protection within the power supply. Because TTL and CMOS circuits are very vulnerable to overvoltages, it is becoming industry standard to provide overvoltage protection on all 3.3-V and 5-V outputs. However, not only the 3.3-V and 5-V rails for the logic circuits on the motherboard need to be protected, but also the 12-V peripheral devices such as the hard disk, floppy disk, and CD-ROM players etc., need to be protected. short-circuit power supply turnon During safety testing the power supply might have tied the output voltage direct to ground. If this happens during the normal operating, this is called a short-circuit or over-current condition. When it happens before the power supply turns on, this is called a short-circuit power supply turnon. It can happen during the design period, in the production line, at quality control inspection or at the end user. The TPS3510/1 provides an undervoltage protection function with a 75-ms delay after PSON is set low. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Output voltage VO: FPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V PGO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING P 1092 mW 8.74 mW/C 699 mW 568 mW D 730 mW 5.84 mW/C 467 mW 379 mW recommended operating conditions at specified temperature range MIN Supply voltage, VDD 4 PSON, VS5, VS33 Input voltage, VI voltage VO Output voltage, NOM MAX 15 UNIT V 7 VDD + 0.3 V (max = 7 V) PGI FPO 15 PGO 7 FPO 20 O tp t sink ccurrent, Output rrent IO,sink PGO 10 Supply voltage rising time, tr See Note 2 1 Operating free-air temperature range, TA -40 V V mA ms 85 C NOTE 2: VDD rising and falling slew rate must be less than 14 V/ms. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) overvoltage protection PARAMETER TEST CONDITIONS Overvoltage threshold ILKG VOL MIN TYP MAX VS33 3.7 3.9 4.1 VS5 5.7 6.1 6.5 VDD 13.2 13.8 14.4 Leakage current (FPO) V(FPO) = 5 V Low-level output voltage (FPO) VDD = 5 V, VDD = 5 V Noise deglitch time OVP 5 Isink = 20 mA UNIT V A 0.7 V 35 73 110 s PGI and PGO PARAMETER MIN TYP MAX PGI1 TEST CONDITIONS 1.1 1.15 1.2 PGI2 0.9 0.95 1 2 2.2 2.4 3.3 3.5 3.7 VPGI Inp t threshold voltage Input oltage (PGI) VIT Under oltage threshold Undervoltage ILKG VOL Leakage current (PGO) PGO = 5 V Low-level output voltage (PGO) VDD = 4 V, VS33 VS5 Short-circuit protection delay Isink = 10 mA 3.3 V, 5 V td1 TP3511 Delay time V ms 75 114 450 100 150 225 3.2 4.8 7.2 PGI to PGO 88 150 225 PGI to FPO 180 296 445 82 146 220 PGI to FPO Noise deglitch time A 300 VDD = 5 V VDD = 5 V UVP to FPO V 5 49 PGI to PGO V 0.4 200 TP3510 UNIT ms s PSON control PARAMETER II VIH Input pullup current VIL tb Low-level input voltage td2 Delay time (PSON to FPO) TEST CONDITIONS MIN PSON = 0 V High-level input voltage TYP MAX 2.4 Debounce time (PSON) VDD = 5 V VDD = 5 V UNIT A 120 V 1.2 V 24 38 57 ms tb+1.1 tb+2.3 tb+4 ms MAX UNIT total device PARAMETER IDD 8 TEST CONDITIONS Supply current PSON = 5 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN TYP 1 mA SLVS312A - JULY 2000 - REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE INPUT CURRENT (PSON) vs INPUT VOLTAGE (PSON) 400 20 VDD = 4 V TA = -40C 0 TA = 85C TA = 25C 200 I I - Input Current - A I DD - Supply Current - A 300 100 TA = 0C 0 -100 -20 -40 -60 -80 TA = -40C TA = 0C TA = 25C TA = 85C -100 -200 PGI = 1.4 V PSON = 5 V -120 -300 0 2.5 5 10 7.5 12.5 -140 15 0 1 VDD - Supply Voltage - V 2 Figure 2 7 800 VOL- Low-Level Output Voltage - mV VOL - Low-Level Output Voltage - V 6 LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) VDD = 4 V PSON = GND 3 TA = 85C 2 TA = 25C TA = -40C 1 TA = 0C VDD = 4 V PSON = GND Exploded View 700 600 TA = 85C 500 400 300 0 20 40 60 80 100 IOL - Low-Level Output Current - mA 120 TA = -40C TA = 25C 200 TA = 0C 100 0 5 Figure 3 LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) 4 4 3 VI - Input Voltage - V 0 0 5 10 15 20 IOL - Low-Level Output Current - mA Figure 4 25 Figure 5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLVS312A - JULY 2000 - REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) 4 600 VOL - Low-Level Output Voltage - mV VOL - Low-Level Output Voltage - V VDD = 4 V PSON = GND TA = 85C 3 2 TA = -40C TA = 25C 1 TA = 0C 0 0 25 50 75 100 125 IOL - Low-Level Output Current - mA VDD = 4 V PSON = GND Exploded View 500 400 TA = 85C 300 TA = 25C 200 TA = -40C 100 TA = 0C 0 150 0 5 10 15 IOL - Low-Level Output Current - mA Normalized Input Threshold Voltage - VIT(TA)/VIT(25 C) Figure 6 Figure 7 NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD 1.001 VDD = 4 V PSON = GND 1 0.999 0.998 0.997 0.996 0.995 0.994-40 -15 10 35 60 TA - Free-Air Temperature - C Figure 8 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 85 20 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS3510D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3510DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3510DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3510DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3510P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS3510PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS3511D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3511DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3511DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3511DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3511P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS3511PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS3510DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3511DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3510DR SOIC D 8 2500 340.5 338.1 20.6 TPS3511DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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