Quad, Current-Output,
Serial-Input 16-/14-Bit DACs
AD5544/AD5554
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2000–2011 Analog Devices, Inc. All rights reserved.
FEATURES
AD5544: 16-bit resolution
INL of ±1 LSB (B Grade)
AD5554: 14-bit resolution
INL of ±0.5 LSB (B Grade)
2 mA full-scale current ± 20%, with VREF = ±10 V
0.9 μs settling time to ±0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
Midscale or zero-scale reset
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
Temperature range: −40°C to +125°C
Compact 28-lead SSOP and 32-lead LFCSP
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER R
16
DAC A
REGISTER R
2:4
DECODE
DAC A
B
C
D
POWER-ON
RESET
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
EN
V
DD
R
FB
A
I
OUT
A
A
GND
A
A
GND
F
V
SS
LDAC
MSB
RS
DGND
CLK
CS
SDI
SDO
V
REF
A
BC
R
FB
B
I
OUT
B
A
GND
B
R
FB
C
I
OUT
C
A
GND
C
R
FB
D
I
OUT
D
A
GND
D
AD5544
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
DAC B
REGISTER R
DAC C
REGISTER R
DAC D
REGISTER R
D
00943-001
DAC A
DAC B
DAC D
DAC C
Figure 1.
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current output, digital-
to-analog converters (DACs) are designed to operate from a
2.7 V to 5.5 V supply range.
The applied external reference input voltage (VREFx) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
(SDI), a chip select (CS), and clock (CLK) signals. In addition,
a serial data out pin (SDO) allows for daisy-chaining when multiple
packages are used. A common, level-sensitive, load DAC strobe
(LDAC) input allows the simultaneous update of all DAC outputs
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.
The MSB pin allows system reset assertion (RS) to force all registers
to zero code when MSB = 0 or to half-scale code when MSB = 1.
The AD5544 is packaged in the compact 28-lead SSOP and 32-
lead LFCSP. The AD5554 is packed in the compact 28-lead SSOP.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2 0 10,000 30,000 50,000 70,000
00943-002
INL ERRO R (L S B)
CODE
20,000 40,000 60,000
Figure 2. AD5544 INL vs. Code Plot (TA = 25°C)
AD5544/AD5554
Rev. E | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5544 Electrical Characteristics ............................................. 3
AD5554 Electrical Characteristics ............................................. 4
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 12
Digital-to-Analog Converter (DAC) ....................................... 12
Serial Data Interface ....................................................................... 14
Truth Tables................................................................................. 15
Power-On Reset.......................................................................... 16
ESD Protection Circuits ............................................................ 16
Power Supply Sequence............................................................. 16
Layout and Power Supply Bypassing ....................................... 17
Grounding................................................................................... 17
Applications Information .............................................................. 18
Reference Selection .................................................................... 18
Amplifier Selection .................................................................... 18
Evaluation Board for the AD5544................................................ 20
System Demonstration Platform.............................................. 20
Operating the Evaluation Board .............................................. 20
Evaluation Board Schematics ................................................... 21
Evaluation Board Layout........................................................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
6/11—Rev. D to Rev. E
Added 32-Lead LFCSP.................................................. Throughout
Changes to Table 1, Supply Characteristics Parameters.............. 3
Changes to Table 2, Supply Characteristics Parameters.............. 5
Added Figure 6, Renumbered Subsequent Figures, Changes
to Table 4............................................................................................ 7
Changed Applications Section to Applications Information
Section, Added Reference Selection and Amplifier Selection
Sections ............................................................................................ 19
Added Evaluation Board for the AD5544 Section ..................... 21
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 18
9/09—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Figure 12........................................................................ 9
Changes to Figure 19...................................................................... 10
Changes to Table 8 and Table 9..................................................... 13
Changes to Ordering Guide .......................................................... 16
8/09—Rev. B to Rev. C
Change to Table 1 ............................................................................. 3
Change to Table 2 ............................................................................. 4
8/09—Rev. A to Rev. B
Changes to Features Section ............................................................1
Changes to Figure 2...........................................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Moved Timing Diagram...................................................................5
Added Figure 4; Renumbered Sequentially ...................................5
Change to Table 3 ..............................................................................6
Changes to Table 4.............................................................................7
Changes to Typical Performance Characteristics Section ...........8
Changes to Figure 19...................................................................... 10
Moved Table 5, Table 6, and Table 7 ............................................ 12
Moved Truth Tables Section ......................................................... 13
Deleted Figure 27; Renumbered Sequentially ............................ 14
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide.......................................................... 16
12/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change to Electrical Characteristics Tables...................................4
Change to Pin Description Table.................................................. 10
Addition of Power Supply Sequence Section.............................. 19
Addition of Layout and Power Supply Bypassing Section ........ 19
Addition of Grounding Section.................................................... 19
Addition of Figure 32..................................................................... 19
4/00—Revision 0: Initial Version
AD5544/AD5554
Rev. E | Page 3 of 28
SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, VREFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature
range of −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Condition/Comments Min Typ Max Unit
STATIC PERFORMANCE1
Resolution N 1 LSB = VREFx/216 = 153 μV when VREF = 10 V 16 Bits
Relative Accuracy INL AD5544BRSZ ±1 LSB
AD5544ARSZ ±2 LSB
AD5544BCPZ ±1 LSB
AD5544ACPZ-1 ±4 LSB
Differential Nonlinearity DNL AD5544BRSZ ±1 LSB
AD5544ARSZ ±1.5 LSB
AD5544BCPZ ±1 LSB
AD5544ACPZ-1 ±1 LSB
Output Leakage Current IOUTx Data = 0x0000, TA = 25°C 10 nA
Data = 0x0000, TA = 85°C 20 nA
Full-Scale Gain Error GFSE Data = 0xFFFF ±0.75 ±3 mV
Full-Scale Tempco2 TCVFS 1 ppm/°C
Feedback Resistor RFBx VDD = 5 V 4 6 8 kΩ
REFERENCE INPUT
VREFx Range VREFx −15 +15 V
Input Resistance RREFx 4 6 8 kΩ
Input Resistance Match RREFx Channel-to-channel 0.35 %
Input Capacitance2 C
REFx 5 pF
ANALOG OUTPUT
Output Current IOUTx Data = 0xFFFF 1.25 2.5 mA
Output Capacitance2 C
OUTx Code dependent 35 pF
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage VIL 0.8 V
Logic Input High Voltage VIH 2.4 V
Input Leakage Current IIL 1 μA
Input Capacitance2 C
IL 10 pF
Logic Output Low Voltage VOL I
OL = 1.6 mA 0.4 V
Logic Output High Voltage VOH I
OH = 100 μA 4 V
INTERFACE TIMING2, 3
Clock Width High tCH 25 ns
Clock Width Low tCL 25 ns
CS to Clock Setup tCSS 0 ns
Clock to CS Hold tCSH 25 ns
Clock to SDO Propagation
Delay
tPD 2 20 ns
Load DAC Pulse Width tLDAC 25 ns
Data Setup tDS 20 ns
Data Hold tDH 20 ns
Load Setup tLDS 5 ns
Load Hold tLDH 25 ns
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE 2.7 5.5 V
Positive Supply Current IDD Logic inputs = 0 V 5 μA
Negative Supply Current ISS Logic inputs = 0 V, VSS = −5 V 0.001 9 μA
AD5544/AD5554
Rev. E | Page 4 of 28
Parameter Symbol Test Condition/Comments Min Typ Max Unit
Power Dissipation PDISS Logic inputs = 0 V 1.25 mW
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%
AC CHARACTERISTICS4
Output Voltage Settling Time tS To ±0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000 0.9 μs
Reference Multiplying
Bandwidth (BW)
BW − 3 dB VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF, 12 MHz
DAC Glitch Impulse Q VREFx = 8 V, data = 0x0000 to 0x8000 to 0x0000 −1 nV-sec
Feedthrough Error VOUTx/VREFx Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz −65 dB
Crosstalk Error VOUTA/VREFB Data = 0x0000, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
−90 dB
Digital Feedthrough Q CS = 1, fCLK = 1 MHz 0.6 nV-sec
Total Harmonic Distortion THD VREFx = 5 V p-p, data = 0xFFFF, f = 1 kHz −98 dB
Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 7 nV/√Hz
1 All static performance tests (except IOUTx) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier.
AD5554 ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, VREFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature
range of −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Condition/Comments Min Typ Max Unit
STATIC PERFORMANCE1
Resolution N 1 LSB = VREFx/214 = 610 μV when VREFx = 10 V 14 Bits
Relative Accuracy INL ±0.5 LSB
Differential Nonlinearity DNL ±1 LSB
Output Leakage Current IOUTx Data = 0x0000, TA = 25°C 10 nA
Data = 0x0000, TA = 85°C 20 nA
Full-Scale Gain Error GFSE Data = 0x3FFF ±2 ±10 mV
Full-Scale Tempco2 TCVFS 1 ppm/°C
Feedback Resistor RFBx VDD = 5 V 4 6 8 kΩ
REFERENCE INPUT
VREFx Range VREFx −15 +15 V
Input Resistance RREFx 4 6 8 kΩ
Input Resistance Match RREFx Channel-to-channel 1 %
Input Capacitance2 C
REFx 5 pF
ANALOG OUTPUT
Output Current IOUTx Data = 0x3FFF 1.25 2.5 mA
Output Capacitance2 C
OUTx Code dependent 80 pF
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage VIL 0.8 V
Logic Input High Voltage VIH 2.4 V
Input Leakage Current IIL 1 μA
Input Capacitance2 C
IL 10 pF
Logic Output Low Voltage VOL I
OL = 1.6 mA 0.4 V
Logic Output High Voltage VOH I
OH = 100 μA 4 V
INTERFACE TIMING2, 3
Clock Width High tCH 25 ns
Clock Width Low tCL 25 ns
CS to Clock Setup tCSS 0 ns
Clock to CS Hold tCSH 25 ns
AD5544/AD5554
Rev. E | Page 5 of 28
Parameter Symbol Test Condition/Comments Min Typ Max Unit
Clock to SDO Propagation
Delay
tPD 2 20 ns
Load DAC Pulse Width tLDAC 25 ns
Data Setup tDS 20 ns
Data Hold tDH 20 ns
Load Setup tLDS 5 ns
Load Hold tLDH 25 ns
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE 2.7 5.5 V
Positive Supply Current IDD Logic inputs = 0 V 5 μA
Negative Supply Current ISS Logic inputs = 0 V, VSS = −5 V 0.001 9 μA
Power Dissipation PDISS Logic inputs = 0 V 1.25 mW
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%
AC CHARACTERISTICS4
Output Voltage Settling Time tS To ±0.1% of full scale, data = 0x0000 to 0x3FFF to 0x0000 0.9 μs
Reference Multiplying
Bandwidth (BW)
BW − 3 dB VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF 12 MHz
DAC Glitch Impulse Q VREFx = 8 V, data = 0x0000 to 0x2000 to 0x0000 −1 nV-sec
Feedthrough Error VOUTx/VREFx Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz −65 dB
Crosstalk Error VOUTA/VREFB Data = 0x0000, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
−90 dB
Digital Feedthrough Q CS = 1, fCLK = 1 MHz 0.6 nV-sec
Total Harmonic Distortion THD VREFx = 5 V p-p, data = 0x3FFF, f = 1 kHz −98 dB
Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 7 nV/√Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 RFB terminal is
tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier,.
AD5544/AD5554
Rev. E | Page 6 of 28
TIMING DIAGRAMS
t
LDH
t
LDS
t
LDAC
t
CSH
t
PD
t
CL
t
CH
t
DH
t
DS
t
CSS
SDI
CLK
CS
LDAC
SDO
INPUT
REG
LD
A1 A0 D15 D14 D13 D12 D11 D10 D1 D0
00943-004
Figure 3. AD5544 Timing Diagram
t
LDH
t
LDS
t
LDAC
t
CSH
t
PD
t
CL
t
CH
t
DH
t
DS
t
CSS
SDI
CLK
SDO
INPUT
REG
LD
A1 A0 D13 D12 D11 D10 D09 D08 D1 D0
CS
LDAC
00943-005
Figure 4. AD5554 Timing Diagram
AD5544/AD5554
Rev. E | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V, +8 V
VSS to GND +0.3 V, −7 V
VREFx to GND −18 V, +18 V
Logic Input and Output to GND −0.3 V, +8 V
V(IOUTx) to GND −0.3 V, VDD + 0.3 V
AGNDx to DGND −0.3 V, +0.3 V
Input Current to Any Pin Except Supplies ±50 mA
Package Power Dissipation (TJ max − TA)/θJA
Thermal Resistance θJA
28-Lead SSOP 100°C/W
32-Lead LFCSP 32.5°C/W
Maximum Junction Temperature (TJ Max) 150°C
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Vapor Phase, 60 Sec 215°C
Infrared, 15 Sec 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
AD5544/AD5554
Rev. E | Page 8 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5544/
AD5554
TOP VIEW
(Not to Scale)
A
GND
AA
GND
D
I
OUT
AI
OUT
D
V
REF
AV
REF
D
R
FB
AR
FB
D
MSB DGND
V
SS
V
DD
A
GND
F
CLK SDO
SDI NC
R
FB
BR
FB
C
V
REF
BV
REF
C
I
OUT
BI
OUT
C
A
GND
BA
GND
C
NC = NO CONNECT
LDAC
CS
RS
00943-003
Figure 5. TSSOP Pin Configuration
NOTES
1. NC = NO CONNE
C
T.
2
. CONNECT EXPOSED PAD TO AGND.
24 DGND
23 V
SS
22 A
GND
F
21 LDAC
20 SDO
19 NC
18 R
FB
C
17 V
REF
C
1
2
3
4
5
6
7
8
A
GND
A
I
OUT
A
V
REF
A
R
FB
A
MSB
RS
V
DD
CS
9
10
11
12
13
14
15
16
CLK
SDI
R
FB
B
V
REF
B
I
OUT
B
A
GND
B
A
GND
C
I
OUT
C
32
31
30
29
28
27
26
25
NC
NC
NC
NC
A
GND
D
I
OUT
D
V
REF
D
R
FB
D
AD5544
TOP VIEW
(Not to Scale)
00943-035
Figure 6. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 1 AGNDA DAC A Analog Ground.
2 2 IOUTA DAC A Current Output.
3 3 VREFA DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be
tied to the VDD pin.
4 4 RFBA Establish the voltage output for DAC A by connecting to an external amplifier output.
5 5 MSB MSB Bit. Set pin during a reset pulse (RS) or at system power-on if tied to ground or VDD.
6 6 RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code
(0x8000 for the AD5544 and 0x2000 for the AD5554), determined by the voltage on the MSB pin.
Register data = 0x0000 when MSB = 0.
7 7 VDD Positive Power Supply Input. Specified range of operation: 5 V ± 10%.
8 8 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data
to the input register when CS/LDAC returns high. Does not affect LDAC operation.
9 9 CLK Clock Input. Positive edge clocks data into the shift register.
10 10 SDI Serial Data Input. Input data loads directly into the shift register.
11 11 RFBB Establish the voltage output for DAC B by connecting to an external amplifier output.
12 12 VREFB DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be
tied to the VDD pin.
13 13 IOUTB DAC B Current Output.
14 14 AGNDB DAC B Analog Ground.
15 15 AGNDC DAC C Analog Ground.
16 16 IOUTC DAC C Current Output.
17 17 VREFC DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be
tied to the VDD pin.
18 18 RFBC Establish the voltage output for DAC C by connecting to an external amplifier output.
19 19 NC No Connect. Leave the pin unconnected.
20 20 SDO Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock
pulses for the AD5544 and 17 clock pulses for the AD5554 after input at the SDI pin.
21 21 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 8 and Table 9 for operation.
22 22 AGNDF High Current Analog Force Ground.
23 23 VSS Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
24 24 DGND Digital Ground Pin.
25 25 RFBD Establish the voltage output for DAC D by connecting to an external amplifier output.
AD5544/AD5554
Rev. E | Page 9 of 28
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
26 26 VREFD DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be
tied to the VDD pin.
27 27 IOUTD DAC D Current Output.
28 28 AGNDD DAC D Analog Ground.
N/A 29 NC Do not connect.
N/A 30 NC Do not connect.
N/A 31 NC Do not connect.
N/A 32 NC Do not connect.
N/A 33 EPAD Connect the exposed pad to AGNDx.
AD5544/AD5554
Rev. E | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–2000 –1500 –1000 –500 0 500 1000 1500 2000
0xF000
0x8000
0x7FFF
0x0FFF
00943-009
OFFSET VOLTAGE (µV)
INL (LSB)
V
DD
= 5V
V
REF
= 10V
0.10
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
0 10,000 30,000 50,000 70,000
00943-006
DNL ERROR (LSB)
CODE
0.05
20,000 40,000 60,000
Figure 7. AD5544 DNL vs. Code, TA = 25°C Figure 10. AD5544 Integral Nonlinearity Error vs. Op Amp Offset
–1.00
–0.75
–0.50
–0.25
0
0.50
0.25
0.75
1.00
–1000 –750 –500 –250 0 250 500 750 1000
0xF000
0x8000
0x0FFF
00943-011
OP AMP OFFSET (µV)
DNL (LSB)
VDD = 5V
VREF = 10V
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0 4000 10,000 14,000 18,000
00943-007
INL ERROR (LSB)
CODE
8000 12,000 16,0002000 6000
Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset
Figure 8. AD5554 INL vs. Code, TA = 25°C
–1500 –1000 –500 0 500 1000 1500
–20
–15
–10
–5
0
5
10
00943-013
OP AMP OFFSET (µV)
GAIN ERROR (LSB)
V
DD
= 5V
V
REF
= 10V
0.10
0.05
0
–0.05
–0.10
–0.15
0 4000 10,000 14,000 18,000
00943-008
DNL ERROR (LSB)
CODE
8000 12,000 16,0002000 6000
Figure 12. AD5544 Gain Error vs. Op Amp Offset
Figure 9. AD5554 DNL vs. Code, TA = 25°C
AD5544/AD5554
Rev. E | Page 11 of 28
0.4 0.5 0.6 0.7 0.9 1.0 1.1 1.20.8
TIME (µs)
V
OUT
(V)
0
0943–012
–4.08
–4.06
–4.04
–4.02
–4.00
–3.98
–3.96
–3.94
–3.92
–3.90
–
3.88
Figure 13. AD5544 Midscale Transition
0
0943-018
5V/DI
V
VDD = 5V
VREF = 10V
VOUT
LDAC
Figure 14. AD5544 Large Signal Settling Time
–0.2
–0.1
0
0.1
–20
–16
–12
–8
–4
0
4
–2 20 46810
00943-019
TIME (µs)
V
OUT
(V)
LDAC (V)
Figure 15. AD5544 Small Signal Settling Time
10,000
1000
100
10
1
1k 100M10k
I
DD
(µA)
100k 1M 10M
CLOCK FREQUENCY (Hz)
ZERO SCALE
MIDSCALE
FULL SCALE
0x5555
00943-015
Figure 16. AD5544 Power Supply Current vs. Clock Frequency
0
10
20
30
40
50
60
70
80
90
100
100 1k 10k 100k 1M
00943-020
FREQUENCY (Hz)
PSRR (dB)
V
DD
= 5V
V
REF
= 10V
Figure 17. AD5544/AD5554 Power Supply Rejection vs. Frequency
0
50
100
150
200
250
300
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT (V)
SUPPLY CURRENT (µA)
00943-017
Figure 18. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage
AD5544/AD5554
Rev. E | Page 12 of 28
THEORY OF OPERATION
The AD5544 and the AD5554 contain four 16-bit and 14-bit,
current output DACs, respectively. Each DAC has its own inde-
pendent multiplying reference input. Both the AD5544 and the
AD5554 use a 3-wire, SPI-compatible serial data interface, with
a configurable asynchronous RS pin for half-scale (MSB = 1) or
zero-scale (MSB = 0) preset. In addition, an LDAC strobe enables
4-channel, simultaneous updates for hardware synchronized
output voltage changes.
DIGITAL-TO-ANALOG CONVERTER (DAC)
Each part contains four current-steering R-R ladder DACs.
Figure 19 shows a typical equivalent DAC. Each DAC contains
a matching feedback resistor for use with an external I-to-V
converter amplifier. The RFBx pin connects to the output of the
external amplifier. The IOUTx terminal connects to the inverting
input of the external amplifier. The AGNDx pin should be Kelvin-
connected to the load point, requiring full 16-bit accuracy. These
DACs are designed to operate with both negative and positive
reference voltage.
The VDD power pin is used only by the logic to drive the DAC
switches on and off. Note that a matching switch is used in series
with the internal 5 kΩ feedback resistor. If users attempt to
measure the value of RFB, power must be applied to VDD to achieve
continuity. An additional VSS bias pin is used to guard the substrate
during high temperature applications, minimizing zero-scale
leakage currents that double every 10°C. The DAC output
voltage is determined by VREF and the digital data (D) in the
following equations:
(
5544ADthefor
536,65D
VV REFOUT ×−=
)
(1)
(
5554ADthefor
384,16D
VV REFOUT ×−=
)
(2)
Note that the output polarity is opposite the VREF polarity for dc
reference voltages.
V
REF
X
V
SS
DGND
V
DD
R
FB
X
I
OUT
X
A
GND
F
A
GND
X
RR
R2R2R2R 5kΩ
S1S2
FROM OTHER DACS A
GND
R
00943-025
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, AND V
DD
MUST BE POWERED.
Figure 19. Typical Equivalent DAC Channel
These DACs are also designed to accommodate ac reference input
signals. Both the AD5544 and the AD5554 accommodate input
reference voltages in the range of −15 V to +15 V. The reference
voltage inputs exhibit a constant nominal input resistance of 5 kΩ ±
30%. On the other hand, the IOUTA, IOUTB, IOUTC, and IOUTD
DAC outputs are code dependent and produce various output
resistances and capacitances. The choice of external amplifier
should take into account the variation in impedance generated by
the AD5544/AD5554 on the inverting input node of the amplifier.
The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications,
an external feedback compensation capacitor, CFB, may be needed
to provide a critically damped output response for step changes in
reference input voltages. Figure 20 shows the gain vs. frequency
performance at various attenuation settings using a 23 pF external
feedback capacitor connected across the IOUTx and RFBx terminals
for the AD5544 and the AD5554, respectively. To maintain good
analog performance, power supply bypassing of 0.01 μF, in parallel
with 1 μF, is recommended. Under these conditions, a clean power
supply with low ripple voltage capability should be used. Switching
power supplies is usually not suitable for this application due to
the higher ripple voltage and PSS frequency-dependent charac-
teristics. It is best to derive the supply of the AD5544/AD5554
from system analog supply voltages. Do not use the digital
supply (see Figure 21).
00943-026
FREQUENCY (Hz)
GAIN (dB)
2
0
–2
–4
–6
–8
100k 1M 10M 100M
Figure 20. AD5554 Reference Multiplying Bandwidth vs. Code
AD5544/AD5554
Rev. E | Page 13 of 28
V
REF
X
V
SS
DGND
V
DD
R
FB
X
I
OUT
X
A
GND
F
A
GND
X
RR R
R2R2R2R 5kΩ
S1S2
FROM OTHER DACS A
GND
AD5544
+
A1
15V
V
EE
V
CC
V
OUT
LOAD
2R
R
5V
15V
ANALOG
POWER
SUPPLY
+
00943-028
DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
AND V
DD
MUST BE POWERED.
Figure 21. Recommended Kelvin-Sensed Hookup
AD5544/AD5554
Rev. E | Page 14 of 28
SERIAL DATA INTERFACE
The AD5544/AD5554 use a 3-wire (CS, SDI, CLK), SPI-compatible
serial data interface. Serial data of the / is clocked
into the serial input register in an 18-bit and 16-bit data-word
format, respectively. The MSB bits are loaded first. defines
the 18 data-word bits for the , and defines the
16 data-word bits for the . Data is placed on the SDI pin
and clocked into the register on the positive clock edge of CLK,
subject to the data setup and data hold time requirements specified
in the interface timing specifications (see and ).
AD5544 AD5554
Table 5
AD5544 Table 6
AD5554
Tabl e 1 Table 2
Data can be clocked in only while the CS chip select pin is active
low. For the , only the last 18 bits clocked into the serial
register are interrogated when the
AD5544
CS pin returns to the logic high
state; extra data bits are ignored. For the , only the last
16 bits clocked into the serial register are interrogated when the
AD5554
CS pin returns to the logic high state. Because most microcon-
trollers output serial data in 8-bit bytes, three right-justified data
bytes can be written to the . Keeping the AD5544 CS line low
between the first, second, and third byte transfers results in a
successful serial register update.
Similarly, two right-justified data bytes can be written to the
AD5554. Keeping the CS line low between the first and second
byte transfer results in a successful serial register update.
When the data is properly aligned in the shift register, the posi-
tive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of Address Bit A1
and Address Bit A0. For the , , , ,
and define the characteristics of the software serial
interface.
AD5544 Tabl e 5 Table 7 Tabl e 8
Figure 3
For the AD5554, Table 6, Table 7, Table 9, and Figure 4 define
the characteristics of the software serial interface. Figure 22 and
Figure 23 show the equivalent logic interface for the key digital
control pins for the AD5544. The AD5554 has a similar configu-
ration, except that it has 14 data bits. Two additional pins, RS and
MSB, provide hardware control over the preset function and
DAC register loading. If these functions are not needed, the RS
pin can be tied to logic high. The asynchronous input RS pin
forces all input and the DAC registers to either the zero-code
state (MSB = 0) or the half-scale state (MSB = 1).
Table 5. AD5544 Serial Input Register Data Format (Data Is Loaded in the MSB-First Format)1
MSB LSB
B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the positive edge of the CS line returns to logic high. At this point, an
internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0.
Any extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be
tied logic low to disable the DAC registers.
Table 6. AD5554 Serial Input Register Data Format (Data Is Loaded in the MSB-First Format)1
MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the positive edge of the CS line returns to logic high. At this point, an
internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0.
Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be
tied logic low to disable the DAC registers.
Table 7. Address Decode
A1 A0 DAC Decoded
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
AD5544/AD5554
Rev. E | Page 15 of 28
TRUTH TABLES
Table 8. AD55441 Control Logic Truth Table
CS CLK LDAC RS MSB2 Serial Shift Register Function3 Input Register Function DAC Register
High X High High X No effect Latched Latched
Low Low High High X No effect Latched Latched
Low ￪+3 High High X Shift register data advanced one bit Latched Latched
Low High High High X No effect Latched Latched
￪+3 Low High High X No effect Selected DAC updated with
current shift register contents4
Latched
High X Low High X No effect Latched Transparent
High X High High X No effect Latched Latched
High X ￪+3 High X No effect Latched Latched
High X High Low 0 No effect Latched data = 0x0000 Latched data = 0x0000
High X High Low High No effect Latched data = 0x8000 Latched data = 0x8000
1 For the AD5544, data appears at the SDO pin 19 clock pulses after input at the SDI pin.
2 X = don’t care.
3 ￪
+ is a positive logic transition.
4 At power-on, both the input register and the DAC register are loaded with all 0s.
Table 9. AD55541 Control Logic Truth Table
CS CLK
LDAC RS MSB2 Serial Shift Register Function3 Input Register Function3 DAC Register
High X High High X No effect Latched Latched
Low L High High X No effect Latched Latched
Low ￪+3 High High X Shift register data advanced one bit Latched Latched
Low High High High X No effect Latched Latched
￪+3 Low High High X No effect Selected DAC updated with
current shift register contents4
Latched
High X Low High X No effect Latched Transparent
High X High High X No effect Latched Latched
High X ￪+3 High X No effect Latched Latched
High X High Low 0 No effect Latched data = 0x0000 Latched data = 0x0000
High X High Low High No effect Latched data = 0x2000 Latched data = 0x2000
1 For the AD5554, data appears at the SDO pin 17 clock pulses after input at the SDI pin.
2 X = don’t care.
3 ￪
+ is a positive logic transition.
4 At power-on, both the input register and the DAC register are loaded with all 0s.
AD5544/AD5554
Rev. E | Page 16 of 28
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
DAC A
B
C
D
2:4
DECODE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
EN
16
DAC D
REGISTER R
DAC C
REGISTER R
DAC B
REGISTER R
DAC A
REGISTER R
POWER-
ON
RESET
DAC B
DAC C
DAC D
DAC A
AD5544
V
REF
A
B
C
D
V
DD
R
FB
A
I
OUT
A
A
GND
A
R
FB
B
I
OUT
B
A
GND
B
R
FB
C
I
OUT
C
A
GND
C
R
FB
D
I
OUT
D
A
GND
D
A
GND
F
DGND MSB V
SS
SET
MSB
SET
MSB
SDO
SDI
CLK
CS
RS
LDAC
00943-029
Figure 22. System Level Digital Interfacing
EN
SHIFT REGISTER
ADDRESS
DECODE R
A
B
C
D
TO INPUT REGISTER
19
TH
/17
TH
CLOCK
SDO
SDI
CLK
CS
0
0943-030
Figure 23. AD5544/AD5554 Equivalent Logic Interface
POWER-ON RESET
When the VDD power supply is turned on, an internal reset strobe
forces all the input and DAC registers to the zero-code state or
half-scale state, depending on the MSB pin voltage. The VDD power
supply should have a smooth positive ramp without drooping to
have consistent results, especially in the region of VDD = 1.5 V to
2.3 V. The VSS supply has no effect on the power-on reset perform-
ance. The DAC register data stays at a zero-scale or half-scale
setting until a valid serial register data load takes place.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zener
diodes that are connected to ground (DGND) and VDD, as
shown in Figure 24.
V
DD
DIGITAL
INPUTS
5kΩ
DGND
0
0943-031
Figure 24. Equivalent ESD Production Circuits
POWER SUPPLY SEQUENCE
As standard practice, it is recommended that VDD, VSS, and ground
be powered up prior to any reference. The ideal power-up sequence
is as follows: AGNDx, DGND, VDD, VSS, VREFx, and the digital inputs.
A noncompliance power-up sequence may elevate the reference
current, but the devices resume normal operation once VDD and
VSS are powered up.
AD5544/AD5554
Rev. E | Page 17 of 28
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic
capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capaci-
tors should also be applied at VDD to minimize any transient
disturbance and filter any low frequency ripple (see Figure 25).
Users should not apply switching regulators for VDD due to the
power supply rejection ratio (PSRR) degradation over frequency.
A
GND
X
V
SS
DGND
AD5544/AD555
4
0
0943-032
V
DD
C3
10µF
+C1
0.1µF
C4
10µF
C2
0.1µF
V
SS
V
DD
Figure 25. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDx pins of the AD5544/AD5554 serve as
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 25).
AD5544/AD5554
Rev. E | Page 18 of 28
APPLICATIONS INFORMATION REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
The AD5544/AD5554 are, inherently, two-quadrant multiplying
DACs. That is, they can be easily set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
In some applications, it may be necessary to generate the full
four-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an additional external ampli-
fier (A2) configured as a summing amplifier (see Figure 26). AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
A2
A1
ONE CHANNEL
AD5544
I
OUT
X
R
FB
XV
REF
X
V
DD
V
SS
A
GND
FA
GND
X
V
OUT
10kΩ
10kΩ
5kΩ
AD588
V
REF
10V
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
–10V < V
OUT
< +10V
00943-0-033
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Figure 26. Four-Quadrant Multiplying Application Circuit
In this circuit, the first and second amplifiers (A1 and A2)
provide a total gain of 2, which increases the output voltage span
to 20 V. Biasing the external amplifier with a 10 V offset from
the reference voltage results in a full four-quadrant multiplying
circuit. The transfer equation of this circuit shows that both
negative and positive output voltages are created as the input
data (D) is incremented from code zero (VOUT = −10 V) to
midscale (VOUT = 0 V) to full scale (VOUT = 10 V).
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
()
5544ADthefor1
768,32 REFOUT V
D
V−×
⎟
⎠
⎞
⎜
⎝
⎛− (3)
(
5554ADthefor1
8192 REF
OUT V
D
V−×
⎟
⎠
⎞
⎜
⎝
⎛−
)
(4)
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
AD5544/AD5554
Rev. E | Page 19 of 28
Table 10. Suitable Analog Devices Precision References
Part No. Output Voltage (V) Initial Tolerance (%)
Maximum Temperature
Drift (ppm/°C) ISS (mA) Output Noise (μV p-p) Package(s)
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-5, SC70-5
ADR02 5.0 0.06 3 1 10 SOIC-8
ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5
ADR03 2.5 0.1 3 1 6 SOIC-8
ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5
ADR06 3.0 0.1 3 1 10 SOIC-8
ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5
ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8
ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8
ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8
ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8
ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8
ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8
ADR391 2.5 0.16 9 0.12 5 TSOT-5
ADR395 5.0 0.10 9 0.12 8 TSOT-5
Table 11. Suitable Analog Devices Precision Op Amps
Part No. Supply Voltage (V)
VOS Maximum
(μV)
IB Maximum
(nA)
0.1 Hz to 10 Hz
Noise (μV p-p)
Supply
Current (μA) Package(s)
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8, PDIP-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8
AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8
AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8
ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5
AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5
AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8
AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5
AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5
AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8
Table 12. Suitable Analog Devices High Speed Op Amps
Part No. Supply Voltage (V) BW at ACL (MHz)
Slew Rate
(V/μs) VOS (Max) (μV) IB (Max) (nA) Package(s)
AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5
AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8
AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8
AD8392 10 to 24 65 900 5000 15,000 TSSOP-28, LFCSP-32
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
ADA4899 5 to 12 600 310 35 100 LFCSP-8, SOIC-8
AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8
AD8058 3 to 12 325 850 5000, 500 SOIC-8, MSOP-8
AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8
AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8
AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8
AD5544/AD5554
Rev. E | Page 20 of 28
EVALUATION BOARD FOR THE AD5544
0
0943-101
The EVAL-AD5544SDZ is used in conjunction with an SDP1Z
system demonstration platform board available from Analog
Devices, which is purchased separately from the evaluation
board. The USB-to-SPI communication to the AD5544 is
completed using this Blackfin®-based demonstration board.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and
software evaluation tool for use in conjunction with product
evaluation boards. The SDP board is based on the Blackfin
ADSP-BF527 processor with USB connectivity to the PC
through a USB 2.0 high speed port. For more information about
this device, see the system demonstration platform web page.
OPERATING THE EVALUATION BOARD
The evaluation board requires ±12 V and +5 V supplies.
The +12 V VDD and −12 V VSS are used to power the output
amplifier, and the +5 V is used to power the DAC (DVDD).
00943-100
Figure 28. Evaluation Board Software—AD5544 Quad DAC
Figure 27. Evaluation Board Software—Device Selection Window
AD5544/AD5554
Rev. E | Page 24 of 28
EVALUATION BOARD LAYOUT
00943-105
Figure 32. Silkscreen
00943-106
Figure 33. Component Side
AD5544/AD5554
Rev. E | Page 25 of 28
00943-107
Figure 34. Solder Side
AD5544/AD5554
Rev. E | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-150-AH
060106-A
28 15
14
1
10.50
10.20
9.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 35. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
32
9
16
17
24
25
8
EXPOSED
PAD
PIN 1
INDICATOR
3.65
3.50 SQ
3.45
S
EATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 MIN
Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-11)
Dimensions shown in millimeters
AD5544/AD5554
Rev. E | Page 27 of 28
ORDERING GUIDE
Model1 RES Bit INL LSB DNL LSB
Temperature
Range Package Description
Package
Option
AD5544ARS 16 ±2 ±1.5 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5544ARSZ 16 ±2 ±1.5 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5544ARSZ-REEL7 16 ±2 ±1.5 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5544BRSZ 16 ±1 ±1 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5544BRSZ-REEL7 16 ±1 ±1 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5544ACPZ-1-R2 16 ±4 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11
AD5544ACPZ-1-RL7 16 ±4 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11
AD5544BCPZ-R2 16 ±1 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11
AD5544BCPZ-RL7 16 ±1 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11
AD5554BRSZ 14 ±0.5 ±1 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
EVAL-AD5544SDZ Evaluation Board
1 Z = RoHS Compliant Part.
AD5544/AD5554
Rev. E | Page 28 of 28
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2000–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00943-0-6/11(E)
