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EFM32GG380 DATASHEET
F1024/F512
•ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
•Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.8 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 80 µA/MHz @ 3 V Sleep Mode
• 219 µA/MHz @ 3 V Run Mode, with code executed from flash
•1024/512 KB Flash
• Read-while-write support
•128 KB RAM
•81 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•12 Channel DMA Controller
•12 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
•Hardware AES with 128/256-bit keys in 54/75 cycles
•Timers/Counters
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Backup Power Domain
• RTC and retention registers in a separate power domain, avail-
able in all energy modes
• Operation from backup battery when main power drains out
•External Bus Interface for up to 4x256 MB of external
memory mapped space
• TFT Controller with Direct Drive
•Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host & OTG support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
•Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sen-
sors and capacitive buttons
•Ultra efficient Power-on Reset and Brown-Out Detec-
tor
•Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
•Pre-Programmed USB/UART Bootloader
•Temperature range -40 to 85 ºC
•Single power supply 1.98 to 3.8 V
•LQFP100 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32GG380 devices.
Table 1.1. Ordering Information
Ordering Code Flash (kB) RAM (kB) Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC) Package
EFM32GG380F512-QFP100 512 128 48 1.98 - 3.8 -40 - 85 LQFP100
EFM32GG380F1024-QFP100 1024 128 48 1.98 - 3.8 -40 - 85 LQFP100
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32GG microcontroller is well suited for
any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32GG380 devices. For a complete feature set and
in-depth information on the modules, the reader is referred to the EFM32GG Reference Manual.
A block diagram of the EFM32GG380 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
Clock Management Energy Management
Serial Interfaces
I/ O Ports
Core and Memory
Timers and Triggers Analog Interfaces Security
32- bit bus
Peripheral Reflex System
ARM Cortex™- M3 processor
Flash
Program
Memory
LESENSE
High Freq
RC
Oscillator
High Freq.
Crystal
Oscillator
Timer/
Counter
Low Energy
Timer
Pulse
Counter
Real Time
Counter
Low Freq.
Crystal
Oscillator
Low Freq.
RC
Oscillator
Watchdog
Timer
RAM
Memory
Ext. Bus
Interface
General
Purpose
I/ O
Memory
Protection
Unit
DMA
Controller
Debug
Interface
w/ ETM
External
Interrupts
Pin
Reset
Hardware
AES
GG380F512/1024
ADC
DAC
Analog
Comparator
Operational
Amplifier
USART
Low
Energy
UART
I
2
C
UART
Power- on
Reset
Voltage
Regulator
Back- up
Power
Domain
Voltage
Comparator
Brown- out
Detector
TFT
Driver
Back- up
RTC
Pin
Wakeup
Ultra Low Freq.
RC
Oscillator
USB
Aux High Freq.
RC
Oscillator
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32 Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embed-
ded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer
pin which can be used to output profiling information, data trace and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller.
The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is
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divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32GG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32GG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32GG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH,
ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables
seamless access from software without manually manipulating the IO settings each time a read or write
is performed. The data and address lines are multiplexed in order to reduce the number of pins required
to interface the external devices. The timing is adjustable to meet specifications of the external devices.
The interface is limited to asynchronous devices.
2.1.11 TFT Direct Drive
The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller
supports programmable display and port sizes and offers accurate control of frequency and setup and
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hold timing. Direct Drive is supported for TFT displays which do not have their own frame buffer. In
that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory
device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers
through the EBI interface.
2.1.12 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device,
On-the-go (OTG) Dual Role Device or Host-only configuration. In OTG mode the USB supports both
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-
speed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal dedicated
Descriptor-Based Scatter/Garther DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in
addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for
supplying 5V to VBUS when operating as host.
2.1.13 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.15 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0042 is pre-programmed in the device at factory. The
bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART
without the need for a debugger. The autobaud feature, interface and commands are described further
in the application note.
2.1.16 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module.
It supports full- and half-duplex asynchronous UART communication.
2.1.17 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.18 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
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2.1.19 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.20 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz
crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy
Modes and it can also run in backup mode, making it operational even if the main power should drain out.
2.1.21 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.22 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 – EM3.
2.1.23 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.24 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.25 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.26 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be
combined into one differential output. The DAC may be used for a number of different applications such
as sensor interfaces or sound output.
2.1.27 Operational Amplifier (OPAMP)
The EFM32GG380 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general
purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set
to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable
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and the OPAMP has various internal configurations such as unity gain, programmable gain using internal
resistors etc.
2.1.28 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support
for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE
is capable of supporting a wide range of sensors and measurement schemes, and can for instance mea-
sure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable
FSM which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in
applications with a strict energy budget.
2.1.29 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,
and a set of retention registers, available in all energy modes. This power domain can be configured to
automatically change power source to a backup battery when the main power drains out. The backup
power domain enables the EFM32GG380 to keep track of time and retain data, even if the main power
source should drain out.
2.1.30 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.31 General Purpose Input/Output (GPIO)
In the EFM32GG380, there are 81 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32GG380 is a subset of the feature set described in the EFM32GG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
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Module Configuration Pin Connections
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
USB Full configuration USB_VBUS, USB_VBUSEN,
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY,
EBI_ALE, EBI_BL[1:0], EBI_CS[3:0],
EBI_CSTFT, EBI_DCLK, EBI_DTEN,
EBI_HSNC, EBI_NANDREn,
EBI_NANDWEn, EBI_REn, EBI_VSNC,
EBI_WEn
I2C0 Full configuration I2C0_SDA, I2C0_SCL
I2C1 Full configuration I2C1_SDA, I2C1_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
UART1 Full configuration U1_TX, U1_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
TIMER3 Full configuration TIM3_CC[2:0]
RTC Full configuration NA
BURTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP Full configuration Outputs: OPAMP_OUTx,
OPAMP_OUTxALT, Inputs:
OPAMP_Px, OPAMP_Nx
AES Full configuration NA
GPIO 81 pins Available pins are shown in
Table 4.3 (p. 62)
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2.3 Memory Map
The EFM32GG380 memory map is shown in Figure 2.2 (p. 9) , with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32GG380 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 10) , by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 10) , by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 10) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
10) .
Table 3.1. Absolute Maximum Ratings
Symbol Parameter Condition Min Typ Max Unit
TSTG Storage tempera-
ture range -40 1501°C
TSMaximum soldering
temperature Latest IPC/JEDEC J-STD-020
Standard 260 °C
VDDMAX External main sup-
ply voltage 0 3.8 V
VIOPIN Voltage on any I/O
pin -0.3 VDD+0.3 V
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol Parameter Min Typ Max Unit
TAMB Ambient temperature range -40 85 °C
VDDOP Operating supply voltage 1.98 3.8 V
fAPB Internal APB clock frequency 48 MHz
fAHB Internal AHB clock frequency 48 MHz
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3.3.2 Environmental
Table 3.3. Environmental
Symbol Parameter Condition Min Typ Max Unit
VESDHBM ESD (Human Body
Model HBM) TAMB=25°C 2000 V
VESDCDM ESD (Charged De-
vice Model, CDM) TAMB=25°C 750 V
Latch-up sensitivity passed: ±100 mA/1.5 × VSUPPLY(max) according to JEDEC JESD 78 method Class
II, 85°C.
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3.4 Current Consumption
Table 3.4. Current Consumption
Symbol Parameter Condition Min Typ Max Unit
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V 219 240 µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 214 261 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 220 263 µA/
MHz
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 223 270 µA/
MHz
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 225 273 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 230 282 µA/
MHz
IEM0
EM0 current. No
prescaling. Run-
ning prime num-
ber calculation code
from flash. (Produc-
tion test condition =
14MHz)
1.2 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 283 338 µA/
MHz
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V 80 90 µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 80 90 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 81 91 µA/
MHz
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 83 99 µA/
MHz
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 85 100 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 90 102 µA/
MHz
IEM1
EM1 current (Pro-
duction test condi-
tion = 14MHz)
1.2 MHz HFRCO. all peripheral
clocks disabled, VDD= 3.0 V 122 152 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
1.111.81µA
IEM2 EM2 current EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
6.0110.01µA
VDD= 3.0 V, TAMB=25°C 0.811.31µA
IEM3 EM3 current VDD= 3.0 V, TAMB=85°C 5.819.81µA
VDD= 3.0 V, TAMB=25°C 0.02 0.055 µA
IEM4 EM4 current VDD= 3.0 V, TAMB=85°C 0.5 0.9 µA
1Only one RAM block enabled.
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
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Table 3.5. Energy Modes Transitions
Symbol Parameter Min Typ Max Unit
tEM10 Transition time from EM1 to EM0 0 HF-
CORE-
CLK
cycles
tEM20 Transition time from EM2 to EM0 2 µs
tEM30 Transition time from EM3 to EM0 2 µs
tEM40 Transition time from EM4 to EM0 163 µs
3.6 Power Management
The EFM32GG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
Table 3.6. Power Management
Symbol Parameter Condition Min Typ Max Unit
VBODextthr- BOD threshold on
falling external sup-
ply voltage
1.74 1.96 V
VBODintthr- BOD threshold on
falling internally reg-
ulated supply volt-
age
1.57 1.70 V
VBODextthr+ BOD threshold on
rising external sup-
ply voltage
1.85 1.98 V
VPORthr+ Power-on Reset
(POR) threshold on
rising external sup-
ply voltage
1.98 V
tRESET Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset. 163 µs
CDECOUPLE Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1 µF
CUSB_VREGO USB voltage regu-
lator out decoupling
capacitor.
X5R capacitor recommended.
Apply between USB_VREGO
pin and GROUND
1 µF
CUSB_VREGI USB voltage regula-
tor in decoupling ca-
pacitor.
X5R capacitor recommended.
Apply between USB_VREGI
pin and GROUND
4.7 µF
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3.7 Flash
Table 3.7. Flash
Symbol Parameter Condition Min Typ Max Unit
ECFLASH Flash erase cycles
before failure 20000 cycles
TAMB<150°C 10000 h
TAMB<85°C 10 yearsRETFLASH Flash data retention
TAMB<70°C 20 years
tW_PROG Word (32-bit) pro-
gramming time 20 µs
LPERASE == 0 20 20.4 20.8 ms
tPERASE Page erase time LPERASE == 1 40 40.4 40.8 ms
tDERASE Device erase time 161.6 ms
LPERASE == 0 141mA
IERASE Erase current LPERASE == 1 71mA
LPWRITE == 0 141mA
IWRITE Write current LPWRITE == 1 71mA
VFLASH Supply voltage dur-
ing flash erase and
write
1.98 3.8 V
1Measured at 25°C
3.8 General Purpose Input Output
Table 3.8. GPIO
Symbol Parameter Condition Min Typ Max Unit
VIOIL Input low voltage 0.30VDD V
VIOIH Input high voltage 0.70VDD V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.90VDD V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.85VDD V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.90VDD V
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD V
VIOOH
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85VDD V
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Symbol Parameter Condition Min Typ Max Unit
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.60VDD V
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.80VDD V
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.10VDD V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.10VDD V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.05VDD V
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD V
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD V
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.35VDD V
VIOOL
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.20VDD V
IIOLEAK Input leakage cur-
rent High Impedance IO connected
to GROUND or VDD
±0.1 ±100 nA
RPU I/O pin pull-up resis-
tor 40 kOhm
RPD I/O pin pull-down re-
sistor 40 kOhm
RIOESD Internal ESD series
resistor 200 Ohm
tIOGLITCH Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10 50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL 250 ns
tIOOF Output fall time GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
20+0.1CL 250 ns
VIOHYST I/O pin hysteresis
(VIOTHR+ - VIOTHR-)VDD = 1.98 - 3.8 V 0.10VDD V
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Figure 3.1. Typical Low-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0.00
0.05
0.10
0.15
0.20
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0
1
2
3
4
5
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0
5
10
15
20
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
45
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.2. Typical High-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–0.20
–0.15
–0.10
–0.05
0.00
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–20
–15
–10
–5
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.3. Typical Low-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0
2
4
6
8
10
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0
10
20
30
40
50
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.4. Typical High-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–6
–5
–4
–3
–2
–1
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.5. Typical Low-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0
2
4
6
8
10
12
14
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0
10
20
30
40
50
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0
10
20
30
40
50
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.6. Typical High-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.9. LFXO
Symbol Parameter Condition Min Typ Max Unit
fLFXO Supported nominal
crystal frequency 32.768 kHz
ESRLFXO Supported crystal
equivalent series re-
sistance (ESR)
30 120 kOhm
CLFXOL Supported crystal
external load range X1 25 pF
DCLFXO Duty cycle 48 50 53.5 %
ILFXO Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190 nA
tLFXO Start- up time. ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
400 ms
1See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in energyAware Designer in Simplicity Studio
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
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3.9.2 HFXO
Table 3.10. HFXO
Symbol Parameter Condition Min Typ Max Unit
fHFXO Supported nominal
crystal Frequency 4 48 MHz
Crystal frequency 48 MHz 50 Ohm
Crystal frequency 32 MHz 30 60 Ohm
ESRHFXO
Supported crystal
equivalent series re-
sistance (ESR) Crystal frequency 4 MHz 400 1500 Ohm
gmHFXO The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11 20 mS
CHFXOL Supported crystal
external load range 5 25 pF
DCHFXO Duty cycle 46 50 54 %
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85 µA
IHFXO
Current consump-
tion for HFXO after
startup 32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165 µA
tHFXO Startup time 32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
400 µs
3.9.3 LFRCO
Table 3.11. LFRCO
Symbol Parameter Condition Min Typ Max Unit
fLFRCO Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.29 32.768 34.28 kHz
tLFRCO Startup time not in-
cluding software
calibration
150 µs
ILFRCO Current consump-
tion 300 nA
TUNESTEPL-
FRCO
Frequency step
for LSB change in
TUNING value
1.5 %
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Figure 3.7. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
1.8 2.2 2.6 3.0 3.4 3.8
Vdd [V]
30
32
34
36
38
40
42
Frequency [kHz]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85
Temperature [°C]
30
32
34
36
38
40
42
Frequency [kHz]
1.8 V
3 V
3.8 V
3.9.4 HFRCO
Table 3.12. HFRCO
Symbol Parameter Condition Min Typ Max Unit
28 MHz frequency band 27.5 28.0 28.5 MHz
21 MHz frequency band 20.6 21.0 21.4 MHz
14 MHz frequency band 13.7 14.0 14.3 MHz
11 MHz frequency band 10.8 11.0 11.2 MHz
7 MHz frequency band 6.4816.6016.721MHz
fHFRCO
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
1 MHz frequency band 1.1521.2021.252MHz
tHFRCO_settling Settling time after
start-up fHFRCO = 14 MHz 0.6 Cycles
fHFRCO = 28 MHz 165 190 µA
fHFRCO = 21 MHz 134 155 µA
fHFRCO = 14 MHz 106 120 µA
fHFRCO = 11 MHz 94 110 µA
fHFRCO = 6.6 MHz 77 90 µA
IHFRCO
Current consump-
tion (Production test
condition = 14MHz)
fHFRCO = 1.2 MHz 25 32 µA
DCHFRCO Duty cycle fHFRCO = 14 MHz 48.5 50 51 %
TUNESTEPH-
FRCO
Frequency step
for LSB change in
TUNING value
0.33 %
1For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
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Figure 3.8. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.9. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.10. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
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Figure 3.11. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.12. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
20.3
20.4
20.5
20.6
20.7
20.8
20.9
21.0
21.1
21.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
20.3
20.4
20.5
20.6
20.7
20.8
20.9
21.0
21.1
21.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.13. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
27.0
27.2
27.4
27.6
27.8
28.0
28.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
27.0
27.2
27.4
27.6
27.8
28.0
28.2
28.4
Frequency [MHz]
2.0 V
3.0 V
3.8 V
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3.9.5 AUXHFRCO
Table 3.13. AUXHFRCO
Symbol Parameter Condition Min Typ Max Unit
28 MHz frequency band 27.5 28.0 28.5 MHz
21 MHz frequency band 20.6 21.0 21.4 MHz
14 MHz frequency band 13.7 14.0 14.3 MHz
11 MHz frequency band 10.8 11.0 11.2 MHz
7 MHz frequency band 6.4816.6016.721MHz
fAUXHFRCO
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
1 MHz frequency band 1.1521.2021.252MHz
tAUXHFRCO_settlingSettling time after
start-up fAUXHFRCO = 14 MHz 0.6 Cycles
DCAUXHFRCO Duty cycle fAUXHFRCO = 14 MHz 48.5 50 51 %
TUNESTEPAUX-
HFRCO
Frequency step
for LSB change in
TUNING value
0.33 %
1For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough
adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and
temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the
TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz
across operating conditions.
3.9.6 ULFRCO
Table 3.14. ULFRCO
Symbol Parameter Condition Min Typ Max Unit
fULFRCO Oscillation frequen-
cy 25°C, 3V 0.70 1.75 kHz
TCULFRCO Temperature coeffi-
cient 0.05 %/°C
VCULFRCO Supply voltage co-
efficient -18.2 %/V
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol Parameter Condition Min Typ Max Unit
Single ended 0 VREF V
VADCIN Input voltage range Differential -VREF/2 VREF/2 V
VADCREFIN Input range of exter-
nal reference volt-
age, single ended
and differential
1.25 VDD V
VADCREFIN_CH7 Input range of ex-
ternal negative ref-
erence voltage on
channel 7
See VADCREFIN 0 VDD - 1.1 V
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Symbol Parameter Condition Min Typ Max Unit
VADCREFIN_CH6 Input range of ex-
ternal positive ref-
erence voltage on
channel 6
See VADCREFIN 0.625 VDD V
VADCCMIN Common mode in-
put range 0 VDD V
IADCIN Input current 2pF sampling capacitors <100 nA
CMRRADC Analog input com-
mon mode rejection
ratio
65 dB
1 MSamples/s, 12 bit, external
reference 351 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
67 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
63 µA
IADC Average active cur-
rent
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
64 µA
IADCREF Current consump-
tion of internal volt-
age reference
Internal voltage reference 65 µA
CADCIN Input capacitance 2 pF
RADCIN Input ON resistance 1 MOhm
RADCFILT Input RC filter resis-
tance 10 kOhm
CADCFILT Input RC filter/de-
coupling capaci-
tance
250 fF
fADCCLK ADC Clock Fre-
quency 13 MHz
6 bit 7 ADC-
CLK
Cycles
8 bit 11 ADC-
CLK
Cycles
tADCCONV Conversion time
12 bit 13 ADC-
CLK
Cycles
tADCACQ Acquisition time Programmable 1 256 ADC-
CLK
Cycles
tADCACQVDD3 Required acquisi-
tion time for VDD/3
reference
2 µs
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Symbol Parameter Condition Min Typ Max Unit
Startup time of ref-
erence generator
and ADC core in
NORMAL mode
5 µs
tADCSTART Startup time of ref-
erence generator
and ADC core in
KEEPADCWARM
mode
1 µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59 dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference 63 dB
1 MSamples/s, 12 bit, single
ended, VDD reference 65 dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference 60 dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference 65 dB
1 MSamples/s, 12 bit, differen-
tial, 5V reference 54 dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference 67 dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference 69 dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
62 dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference 63 dB
200 kSamples/s, 12 bit, single
ended, VDD reference 67 dB
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 63 dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference 63 66 dB
SNRADC Signal to Noise Ra-
tio (SNR)
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference 70 dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
58 dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference 62 dB
SINADADC
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
1 MSamples/s, 12 bit, single
ended, VDD reference 64 dB
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Symbol Parameter Condition Min Typ Max Unit
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference 60 dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference 64 dB
1 MSamples/s, 12 bit, differen-
tial, 5V reference 54 dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference 66 dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference 68 dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
61 dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference 65 dB
200 kSamples/s, 12 bit, single
ended, VDD reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 63 dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference 62 65 dB
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference 69 dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
64 dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference 76 dBc
1 MSamples/s, 12 bit, single
ended, VDD reference 73 dBc
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference 66 dBc
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference 77 dBc
1 MSamples/s, 12 bit, differen-
tial, VDD reference 76 dBc
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference 75 dBc
1 MSamples/s, 12 bit, differen-
tial, 5V reference 69 dBc
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
75 dBc
SFDRADC
Spurious-Free Dy-
namic Range (SF-
DR)
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference 75 dBc
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Symbol Parameter Condition Min Typ Max Unit
200 kSamples/s, 12 bit, single
ended, VDD reference 76 dBc
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 79 dBc
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 79 dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference 78 dBc
200 kSamples/s, 12 bit, differ-
ential, VDD reference 68 79 dBc
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference 79 dBc
After calibration, single ended 0.3 mV
VADCOFFSET Offset voltage After calibration, differential -3 0.3 3 mV
-1.92 mV/°C
TGRADADCTH Thermometer out-
put gradient -6.3 ADC
Codes/
°C
DNLADC Differential non-lin-
earity (DNL) -1 ±0.7 4 LSB
INLADC Integral non-linear-
ity (INL), End point
method
±1.2 ±3.0 LSB
MCADC No missing codes 11.999112 bits
1.25V reference 0.0120.0333%/°C
GAINED Gain error drift 2.5V reference 0.0120.033%/°C
1.25V reference 0.220.73LSB/°C
OFFSETED Offset error drift 2.5V reference 0.220.623LSB/°C
1On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2Typical numbers given by abs(Mean) / (85 - 25).
3Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.14 (p.
32) and Figure 3.15 (p. 32) , respectively.
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Figure 3.14. Integral Non-Linearity (INL)
Ideal transfer
curve
Digital ouput code
Analog Input
INL=|[(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
0
1
2
3
4092
4093
4094
4095
VOFFSET
Actual ADC
tranfer function
before offset and
gain correction Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Figure 3.15. Differential Non-Linearity (DNL)
Ideal transfer
curve
Digital
ouput
code
Analog Input
DNL=|[(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
0
1
2
3
4092
4093
4094
4095
Actual transfer
function with one
missing code.
4
5
Full Scale Range
0.5
LSB
Ideal Code Center
Ideal 50%
Transition Point
Ideal spacing
between two
adjacent codes
VLSBIDEAL=1 LSB
Code width = 2 LSB
DNL=1 LSB
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Example: Input value
VD corrresponds to
digital output code D
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3.10.1 Typical performance
Figure 3.16. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.17. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.18. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.19. ADC Absolute Offset, Common Mode = Vdd /2
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd (V)
–4
–3
–2
–1
0
1
2
3
4
5
Actual Offset [LSB]
Vref=1V25
Vref=2V5
Vref=2XVDDVSS
Vref=5VDIFF
Vref=VDD
Offset vs Supply Voltage, Temp = 25°C
–40 –15 5 25 45 65 85
Temp (C)
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
Actual Offset [LSB]
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
Offset vs Temperature, Vdd = 3V
Figure 3.20. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
–40 –15 5 25 45 65 85
Temperature [°C]
63
64
65
66
67
68
69
70
71
SNR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Signal to Noise Ratio (SNR)
–40 –15 5 25 45 65 85
Temperature [°C]
78.0
78.2
78.4
78.6
78.8
79.0
79.2
79.4
SFDR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Spurious-Free Dynamic Range (SFDR)
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Figure 3.21. ADC Temperature sensor readout
–40 –25 –15 –5 5 15 25 35 45 55 65 75 85
Temperature [°C]
2100
2200
2300
2400
2500
2600
Sensor readout
Vdd= 1.8
Vdd= 3
Vdd= 3.8
3.11 Digital Analog Converter (DAC)
Table 3.16. DAC
Symbol Parameter Condition Min Typ Max Unit
VDD voltage reference, single
ended 0 VDD V
VDACOUT Output voltage
range VDD voltage reference, differ-
ential -VDD VDD V
VDACCM Output common
mode voltage range 0 VDD V
500 kSamples/s, 12 bit 4001 µA
100 kSamples/s, 12 bit 2001 µAIDAC
Active current in-
cluding references
for 2 channels 1 kSamples/s 12 bit NORMAL 171 µA
SRDAC Sample rate 500 ksam-
ples/s
Continuous Mode 1000 kHz
Sample/Hold Mode 250 kHz
fDAC DAC clock frequen-
cy Sample/Off Mode 250 kHz
CYCDACCONV Clock cyckles per
conversion 2
tDACCONV Conversion time 2 µs
tDACSETTLE Settling time 5 µs
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
58 dB
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference 59 dB
SNRDAC Signal to Noise Ra-
tio (SNR)
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 58 dB
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Symbol Parameter Condition Min Typ Max Unit
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 58 dB
500 kSamples/s, 12 bit, differ-
ential, VDD reference 59 dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
57 dB
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference 54 dB
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 56 dB
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 53 dB
SNDRDAC
Signal to Noise-
pulse Distortion Ra-
tio (SNDR)
500 kSamples/s, 12 bit, differ-
ential, VDD reference 55 dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
62 dBc
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference 56 dBc
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 61 dBc
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 55 dBc
SFDRDAC
Spurious-Free
Dynamic
Range(SFDR)
500 kSamples/s, 12 bit, differ-
ential, VDD reference 60 dBc
After calibration, single ended 2 9 mV
VDACOFFSET Offset voltage After calibration, differential 2 mV
DNLDAC Differential non-lin-
earity ±1 LSB
INLDAC Integral non-lineari-
ty ±5 LSB
MCDAC No missing codes 12 bits
1Measured with a static input code and no loading on the output.
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.17. OPAMP
Symbol Parameter Condition Min Typ Max Unit
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, Unity
Gain
350 405 µA
IOPAMP Active Current (OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity
Gain
95 115 µA
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Symbol Parameter Condition Min Typ Max Unit
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity
Gain
13 17 µA
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0 101 dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1 98 dB
GOL Open Loop Gain
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1 91 dB
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0 6.1 MHz
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1 1.8 MHz
GBWOPAMP Gain Bandwidth
Product
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1 0.25 MHz
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, CL=75
pF
64 °
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, CL=75
pF
58 °
PMOPAMP Phase Margin
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, CL=75
pF
58 °
RINPUT Input Resistance 100 Mohm
RLOAD Load Resistance 200 Ohm
ILOAD_DC DC Load Current 11 mA
OPAxHCMDIS=0 VSS VDD V
VINPUT Input Voltage OPAxHCMDIS=1 VSS VDD-1.2 V
VOUTPUT Output Voltage VSS VDD V
Unity Gain, VSS<Vin<VDD,
OPAxHCMDIS=0 -13 0 11 mV
VOFFSET Input Offset Voltage Unity Gain, VSS<Vin<VDD-1.2,
OPAxHCMDIS=1 1 mV
VOFFSET_DRIFT Input Offset Voltage
Drift 0.02 mV/°C
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0 3.2 V/µs
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1 0.8 V/µs
SROPAMP Slew Rate
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1 0.1 V/µs
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=0
101 µVRMS
NOPAMP Voltage Noise Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=1
141 µVRMS
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Symbol Parameter Condition Min Typ Max Unit
Vout=1V, RESSEL=0, 0.1
Hz<f<1 MHz, OPAxHCMDIS=0 196 µVRMS
Vout=1V, RESSEL=0, 0.1
Hz<f<1 MHz, OPAxHCMDIS=1 229 µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0 1230 µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1 2130 µVRMS
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0 1630 µVRMS
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1 2590 µVRMS
Figure 3.22. OPAMP Common Mode Rejection Ratio
Figure 3.23. OPAMP Positive Power Supply Rejection Ratio
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Figure 3.24. OPAMP Negative Power Supply Rejection Ratio
Figure 3.25. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
Figure 3.26. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
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3.13 Analog Comparator (ACMP)
Table 3.18. ACMP
Symbol Parameter Condition Min Typ Max Unit
VACMPIN Input voltage range 0 VDD V
VACMPCM ACMP Common
Mode voltage range 0 VDD V
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1 0.6 µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
2.87 12 µA
IACMP Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
195 520 µA
Internal voltage reference off.
Using external voltage refer-
ence
0 µA
IACMPREF
Current consump-
tion of internal volt-
age reference Internal voltage reference 5 µA
VACMPOFFSET Offset voltage BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12 0 12 mV
VACMPHYST ACMP hysteresis Programmable 17 mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL 39 kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL 71 kOhm
CSRESSEL=0b10 in
ACMPn_INPUTSEL 104 kOhm
RCSRES Capacitive Sense
Internal Resistance
CSRESSEL=0b11 in
ACMPn_INPUTSEL 136 kOhm
tACMPSTART Startup time 10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 42) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF (3.1)
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Figure 3.27. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
048 12
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
Current [uA]
Current consumption, HYSTSEL = 4
0 2 46 8 10 12 14
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Response Time [us]
HYSTSEL=0.0
HYSTSEL=2.0
HYSTSEL=4.0
HYSTSEL=6.0
Response time
012 3 4 5 67
ACMP_CTRL_HYSTSEL
0
20
40
60
80
100
Hysteresis [mV]
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hysteresis
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3.14 Voltage Comparator (VCMP)
Table 3.19. VCMP
Symbol Parameter Condition Min Typ Max Unit
VVCMPIN Input voltage range VDD V
VVCMPCM VCMP Common
Mode voltage range VDD V
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.3 0.6 µA
IVCMP Active current BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
22 30 µA
tVCMPREF Startup time refer-
ence generator NORMAL 10 µs
Single ended 10 mV
VVCMPOFFSET Offset voltage Differential 10 mV
VVCMPHYST VCMP hysteresis 61 210 mV
tVCMPSTART Startup time 10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL (3.2)
3.15 EBI
Figure 3.28. EBI Write Enable Timing
WRSETUP
(0, 1, 2, ...)
EBI_BL
EBI_BL[N- 1:0] Z
EBI_A
EBI_A[N- 1:0] Z
DATA[15:0]
EBI_AD[15:0] Z
EBI_CSn
EBI_WEn
WRSTRB
(1, 2, 3, ...) WRHOLD
(0, 1, 2, ...)
tOSU_WEn
tOSU_WEn
tOSU_WEn
tOSU_WEn
tWIDTH_WEn
tOH_WEn
tOH_WEn
tOH_WEn
tOH_WEn
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Table 3.20. EBI Write Enable Timing
Symbol Parameter Min Typ Max Unit
tOH_WEn 1 2 3 4Output hold time, from trailing EBI_WEn/
EBI_NANDWEn edge to EBI_AD, EBI_A,
EBI_CSn, EBI_BLn invalid
-6.00 + (WRHOLD *
tHFCORECLK) ns
tOSU_WEn 1 2 3 4 5Output setup time, from EBI_AD, EBI_A,
EBI_CSn, EBI_BLn valid to leading EBI_WEn/
EBI_NANDWEn edge
-14.00 + (WRSETUP
* tHFCORECLK) ns
tWIDTH_WEn 1 2 3 4 5EBI_WEn/EBI_NANDWEn pulse width -7.00 + ((WRSTRB
+1) * tHFCORECLK) ns
1Applies for all addressing modes (figure only shows D16 addressing mode)
2Applies for both EBI_WEn and EBI_NANWEn (figure only shows EBI_WEn)
3Applies for all polarities (figure only shows active low signals)
4Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5 The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge
of EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length
of tOSU_WEn by 1/2 * tHFCLKNODIV.
Figure 3.29. EBI Address Latch Enable Related Output Timing
tOSU_ALEn
ADDRSETUP
(1, 2, 3, ...)
ADDR[16:1]
ADDRHOLD
(0, 1, 2, ...) WRSETUP
(0, 1, 2, ...) WRSTRB
(1, 2, 3, ...) WRHOLD
(0, 1, 2, ...)
Z
DATA[15:0]
tWIDTH_ALEn tWIDTH_ALEn
EBI_AD[15:0]
EBI_ALE
EBI_CSn
EBI_WEn
Table 3.21. EBI Address Latch Enable Related Output Timing
Symbol Parameter Min Typ Max Unit
tOH_ALEn 1 2 3 4Output hold time, from trailing EBI_ALE edge to
EBI_AD invalid -6.00 + (AD-
DRHOLD5 * tHFCORE-
CLK)
ns
tOSU_ALEn 1 2 4Output setup time, from EBI_AD valid to leading
EBI_ALE edge -13.00 + (0 * tHFCORE-
CLK) ns
tWIDTH_ALEn 1 2 3 4EBI_ALEn pulse width -7.00 + (ADDRSET-
UP+1) * tHFCORECLK) ns
1Applies to addressing modes D8A24ALE and D16A16ALE (figure only shows D16A16ALE)
2Applies for all polarities (figure only shows active low signals)
3 The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge
of EBI_ALE can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length
of tOH_ALEn by tHFCORECLK - 1/2 * tHFCLKNODIV.
4Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5Figure only shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state
instead of via the ADDRHOLD state.
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Figure 3.30. EBI Read Enable Related Output Timing
EBI_BL[1:0]
RDSETUP
(0, 1, 2, ...)
EBI_A[27:0]
EBI_BL
EBI_A
EBI_AD[15:8] ADDR[7:0]
EBI_CSn
EBI_AD[7:0]
EBI_REn
RDSTRB
(1, 2, 3, ...) RDHOLD
(0, 1, 2, ...)
tSU_REn
tSU_REn
tSU_REn
tSU_REn
tWIDTH_REn
Z
Z
tH_REn
tH_REn
tH_REn
tH_REn
Z
ZZ
DATA[7:0]
Table 3.22. EBI Read Enable Related Output Timing
Symbol Parameter Min Typ Max Unit
tOH_REn 1 2 3 4Output hold time, from trailing EBI_REn/
EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn,
EBI_BLn invalid
-10.00 + (RDHOLD *
tHFCORECLK) ns
tOSU_REn 1 2 3 4 5Output setup time, from EBI_AD, EBI_A, EBI_CSn,
EBI_BLn valid to leading EBI_REn/EBI_NANDREn
edge
-10.00 + (RDSETUP
* tHFCORECLK) ns
tWIDTH_REn 1 2 3 4 5 6EBI_REn pulse width -9.00 + ((RD-
STRB+1) * tHFCORE-
CLK)
ns
1Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing
modes D8A24ALE and D16A16ALE)
2Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3Applies for all polarities (figure only shows active low signals)
4Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge
of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length
of tOSU_REn by 1/2 * tHFCLKNODIV.
6When page mode is used, RDSTRB is replaced by RDPA for page hits.
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Figure 3.31. EBI Read Enable Related Timing Requirements
EBI_A[N- 1:0]
EBI_AD[15:0]
ADDR[N:1]
RDSETUP
(0, 1, 2, ...)
EBI_CSn
EBI_REn
RDSTRB
(1, 2, 3, ...) RDHOLD
(0, 1, 2, ...)
tSU_REn
tH_REn
Z
Z
DATA[15:0]
Z
Table 3.23. EBI Read Enable Related Timing Requirements
Symbol Parameter Min Typ Max Unit
tSU_REn 1 2 3 4Setup time, from EBI_AD valid to trailing EBI_REn
edge 37 ns
tH_Ren 1 2 3 4Hold time, from trailing EBI_REn edge to EBI_AD
invalid -1 ns
1Applies for all addressing modes (figure only shows D16A8).
2Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3Applies for all polarities (figure only shows active low signals)
4Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
Figure 3.32. EBI Ready/Wait Related Timing Requirements
EBI_RDY
EBI_AD[15:0]
EBI_CSn
EBI_REn
RDSETUP
(0, 1, 2, ...) RDSTRB
(1, 2, 3, ...) SYNC
(3) RDHOLD
(0, 1, 2, ...)
ZDATA[15:0]
tSU_ARDY
tH_ARDY
Table 3.24. EBI Ready/Wait Related Timing Requirements
Symbol Parameter Min Typ Max Unit
tSU_ARDY 1 2 3 4Setup time, from EBI_ARDY valid to trailing
EBI_REn, EBI_WEn edge 37 + (3 * tHFCORECLK) ns
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Symbol Parameter Min Typ Max Unit
tH_ARDY 1 2 3 4Hold time, from trailing EBI_REn, EBI_WEn edge
to EBI_ARDY invalid -1 + (3 * tHFCORECLK) ns
1Applies for all addressing modes (figure only shows D16A8.)
2Applies for EBI_REn, EBI_WEn (figure only shows EBI_REn)
3Applies for all polarities (figure only shows active low signals)
4Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
3.16 I2C
Table 3.25. I2C Standard-mode (Sm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 1001kHz
tLOW SCL clock low time 4.7 µs
tHIGH SCL clock high time 4.0 µs
tSU,DAT SDA set-up time 250 ns
tHD,DAT SDA hold time 8 34502,3 ns
tSU,STA Repeated START condition set-up time 4.7 µs
tHD,STA (Repeated) START condition hold time 4.0 µs
tSU,STO STOP condition set-up time 4.0 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32GG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 3.26. I2C Fast-mode (Fm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 4001kHz
tLOW SCL clock low time 1.3 µs
tHIGH SCL clock high time 0.6 µs
tSU,DAT SDA set-up time 100 ns
tHD,DAT SDA hold time 8 9002,3 ns
tSU,STA Repeated START condition set-up time 0.6 µs
tHD,STA (Repeated) START condition hold time 0.6 µs
tSU,STO STOP condition set-up time 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32GG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
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Table 3.27. I2C Fast-mode Plus (Fm+)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 10001kHz
tLOW SCL clock low time 0.5 µs
tHIGH SCL clock high time 0.26 µs
tSU,DAT SDA set-up time 50 ns
tHD,DAT SDA hold time 8 ns
tSU,STA Repeated START condition set-up time 0.26 µs
tHD,STA (Repeated) START condition hold time 0.26 µs
tSU,STO STOP condition set-up time 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32GG Reference Manual.
3.17 USART SPI
Figure 3.33. SPI Master Timing
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_MO
tH_MI
tSU_MI
tSCKL_MO
tSCLK
SCLK
CLKPOL = 1
Table 3.28. SPI Master Timing
Symbol Parameter Condition Min Typ Max Unit
tSCLK 1 2SCLK period 2 * tHFPER-
CLK
ns
tCS_MO 1 2CS to MOSI -2.00 1.00 ns
tSCLK_MO 1 2SCLK to MOSI -4.00 3.00 ns
IOVDD = 1.98 V 36.00 ns
tSU_MI 1 2MISO setup time IOVDD = 3.0 V 29.00 ns
tH_MI 1 2MISO hold time -4.00 ns
1Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
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Figure 3.34. SPI Slave Timing
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_ACT_MI
tSCLK_HI
tSCLK
tSU_MO tH_MO
tSCLK_MI
tCS_DIS_MI
tSCLK_LO
SCLK
CLKPOL = 1
Table 3.29. SPI Slave Timing
Symbol Parameter Min Typ Max Unit
tSCLK_sl 1 2SCKL period 2 * tHFPER-
CLK
ns
tSCLK_hi 1 2SCLK high period 3 * tHFPER-
CLK
ns
tSCLK_lo 1 2SCLK low period 3 * tHFPER-
CLK
ns
tCS_ACT_MI 1 2CS active to MISO 4.00 30.00 ns
tCS_DIS_MI 1 2CS disable to MISO 4.00 30.00 ns
tSU_MO 1 2MOSI setup time 4.00 ns
tH_MO 1 2MOSI hold time 2 + 2* tHF-
PERCLK
ns
tSCLK_MI 1 2SCLK to MISO 9 + tHFPER-
CLK
36 + 2*tHF-
PERCLK
ns
1Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
3.18 USB
The USB hardware in the EFM32GG380 passes all tests for USB 2.0 Full Speed certification. See the
test-report distributed with application note "AN0046 - USB Hardware Design Guide".
3.19 Digital Peripherals
Table 3.30. Digital Peripherals
Symbol Parameter Condition Min Typ Max Unit
IUSART USART current USART idle current, clock en-
abled 4.9 µA/
MHz
IUART UART current UART idle current, clock en-
abled 3.4 µA/
MHz
ILEUART LEUART current LEUART idle current, clock en-
abled 140 nA
II2C I2C current I2C idle current, clock enabled 6.1 µA/
MHz
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Symbol Parameter Condition Min Typ Max Unit
ITIMER TIMER current TIMER_0 idle current, clock
enabled 6.9 µA/
MHz
ILETIMER LETIMER current LETIMER idle current, clock
enabled 119 nA
IPCNT PCNT current PCNT idle current, clock en-
abled 54 nA
IRTC RTC current RTC idle current, clock enabled 54 nA
IAES AES current AES idle current, clock enabled 3.2 µA/
MHz
IGPIO GPIO current GPIO idle current, clock en-
abled 3.7 µA/
MHz
IEBI EBI current EBI idle current, clock enabled 11.8 µA/
MHz
IPRS PRS current PRS idle current 3.5 µA/
MHz
IDMA DMA current Clock enable 11.0 µA/
MHz
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4 Pinout and Package
Note Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32GG380.
4.1 Pinout
The EFM32GG380 pinout is shown in Figure 4.1 (p. 52) and Table 4.1 (p. 52) . Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32GG380 Pinout (top view, not to scale)
Table 4.1. Device Pinout
LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog EBI Timers Communication Other
1 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 I2C0_SDA #0
LEU0_RX #4 PRS_CH0 #0
GPIO_EM4WU0
2 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
PRS_CH1 #0
3 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 CMU_CLK0 #0
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog EBI Timers Communication Other
ETM_TD0 #3
4 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0
ETM_TD1 #3
5 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0
ETM_TD2 #3
6 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0
ETM_TD3 #3
7 PA6 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3
GPIO_EM4WU1
8 IOVDD_0 Digital IO power supply 0.
9 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2
10 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2
11 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2
12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
14 PB5 EBI_A21 #0/1/2 US2_CLK #1
15 PB6 EBI_A22 #0/1/2 US2_CS #1
16 VSS Ground
17 IOVDD_1 Digital IO power supply 1.
18 PC0 ACMP0_CH0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4
PCNT0_S0IN #2
US0_TX #5
US1_TX #0
I2C0_SDA #4
LES_CH0 #0
PRS_CH2 #0
19 PC1 ACMP0_CH1
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4
PCNT0_S1IN #2
US0_RX #5
US1_RX #0
I2C0_SCL #4
LES_CH1 #0
PRS_CH3 #0
20 PC2 ACMP0_CH2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
21 PC3 ACMP0_CH3
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
22 PC4 ACMP0_CH4
DAC0_P0 /
OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0 LES_CH4 #0
23 PC5 ACMP0_CH5
DAC0_N0 /
OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
I2C1_SCL #0 LES_CH5 #0
24 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4
US1_CLK #0
25 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4
US1_CS #0
26 PA7 EBI_CSTFT #0/1/2
27 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0
28 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0
29 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0
30 PA11 EBI_HSNC #0/1/2
31 IOVDD_2 Digital IO power supply 2.
32 VSS Ground
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog EBI Timers Communication Other
33 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1
34 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1
35 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1
36 RESETn Reset input, active low.
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure
that reset is released.
37 PB9 EBI_A03 #0/1/2 U1_TX #2
38 PB10 EBI_A04 #0/1/2 U1_RX #2
39 PB11 DAC0_OUT0 /
OPAMP_OUT0 LETIM0_OUT0 #1
TIM1_CC2 #3 I2C1_SDA #1
40 PB12 DAC0_OUT1 /
OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1
41 AVDD_1 Analog power supply 1.
42 PB13 HFXTAL_P US0_CLK #4/5
LEU0_TX #1
43 PB14 HFXTAL_N US0_CS #4/5
LEU0_RX #1
44 IOVDD_3 Digital IO power supply 3.
45 AVDD_0 Analog power supply 0.
46 PD0
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0 US1_TX #1
47 PD1 ADC0_CH1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT TIM0_CC0 #3
PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2
48 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 USB_DMPU #0
US1_CLK #1 DBG_SWO #3
49 PD3 ADC0_CH3
OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
50 PD4 ADC0_CH4
OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2
51 PD5 ADC0_CH5
OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2
52 PD6 ADC0_CH6
DAC0_P1 /
OPAMP_P1 LETIM0_OUT0 #0
TIM1_CC0 #4
PCNT0_S0IN #3
US1_RX #2
I2C0_SDA #1
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
53 PD7 ADC0_CH7
DAC0_N1 /
OPAMP_N1 LETIM0_OUT1 #0
TIM1_CC1 #4
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ETM_TCLK #0
54 PD8 BU_VIN CMU_CLK1 #1
55 PC6 ACMP0_CH6 EBI_A05 #0/1/2 I2C0_SDA #2
LEU1_TX #0 LES_CH6 #0
ETM_TCLK #2
56 PC7 ACMP0_CH7 EBI_A06 #0/1/2 I2C0_SCL #2
LEU1_RX #0 LES_CH7 #0
ETM_TD0 #2
57 VDD_DREG Power supply for on-chip voltage regulator.
58 VSS Ground
59 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
60 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1
PCNT0_S0IN #1 U0_TX #1
I2C1_SDA #2
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog EBI Timers Communication Other
61 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1
PCNT0_S1IN #1 U0_RX #1
I2C1_SCL #2
62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1
63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1
64 PE4 EBI_A11 #0/1/2 US0_CS #1
65 PE5 EBI_A12 #0/1/2 US0_CLK #1
66 PE6 EBI_A13 #0/1/2 US0_RX #1
67 PE7 EBI_A14 #0/1/2 US0_TX #1
68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0
69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0
GPIO_EM4WU2
70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0
71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0
72 USB_VREGI USB Input to internal 3.3 V regulator.
73 USB_VREGO USB Decoupling for internal 3.3 V USB regulator and regulator output.
74 PF10 U1_TX #1
USB_DM
75 PF11 U1_RX #1
USB_DP
76 PF0 TIM0_CC0 #5
LETIM0_OUT0 #2
US1_CLK #2
I2C0_SDA #5
LEU0_TX #3 DBG_SWCLK #0/1/2/3
77 PF1 TIM0_CC1 #5
LETIM0_OUT1 #2
US1_CS #2
I2C0_SCL #5
LEU0_RX #3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
78 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
79 USB_VBUS USB 5.0 V VBUS input.
80 PF12 USB_ID
81 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1
82 IOVDD_5 Digital IO power supply 5.
83 VSS Ground
84 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0
85 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0
86 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1
87 PF9 EBI_REn #1 ETM_TD0 #1
88 PD9 EBI_CS0 #0/1/2
89 PD10 EBI_CS1 #0/1/2
90 PD11 EBI_CS2 #0/1/2
91 PD12 EBI_CS3 #0/1/2
92 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1
93 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1
94 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog EBI Timers Communication Other
95 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0
BOOT_RX
96 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
97 PE13 EBI_AD05 #0/1/2 US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
98 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2
99 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2
100 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 56) . The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX
BOOT_TX PE10 Bootloader TX
BU_STAT PE3 Backup Power Domain status, whether or not the system
is in backup mode
BU_VIN PD8 Battery input for Backup Power Domain
BU_VOUT PE2 Power output for Backup Power Domain
CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.
DAC0_N0 /
OPAMP_N0 PC5 Operational Amplifier 0 external negative input.
DAC0_N1 /
OPAMP_N1 PD7 Operational Amplifier 1 external negative input.
OPAMP_N2 PD3 Operational Amplifier 2 external negative input.
DAC0_OUT0 /
OPAMP_OUT0 PB11 Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT PC0 PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
DAC0_OUT1 /
OPAMP_OUT1 PB12 Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
DAC0_OUT1ALT /
OPAMP_OUT1ALT PD1 Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.
DAC0_P0 /
OPAMP_P0 PC4 Operational Amplifier 0 external positive input.
DAC0_P1 /
OPAMP_P1 PD6 Operational Amplifier 1 external positive input.
OPAMP_P2 PD4 Operational Amplifier 2 external positive input.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
DBG_SWO PF2 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must
be enabled by software to be used.
EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.
EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.
EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.
EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.
EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.
EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.
EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.
EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.
EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.
EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.
EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.
EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.
EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.
EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.
EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.
EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.
EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.
EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.
EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.
EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.
EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.
EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.
EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.
EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.
EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.
EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.
EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.
EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / out-
put pin 00.
EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / out-
put pin 01.
EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / out-
put pin 02.
EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / out-
put pin 03.
EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / out-
put pin 04.
EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / out-
put pin 05.
EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / out-
put pin 06.
EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / out-
put pin 07.
EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / out-
put pin 08.
EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / out-
put pin 09.
EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / out-
put pin 10.
EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / out-
put pin 11.
EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / out-
put pin 12.
EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / out-
put pin 13.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / out-
put pin 14.
EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / out-
put pin 15.
EBI_ALE PC11 PC11 External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control in-
put.
EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.
EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.
EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.
EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchroniza-
tion pin.
EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output.
EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.
EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization
pin.
EBI_WEn PF8 External Bus Interface (EBI) Write Enable output.
ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .
ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.
ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.
ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.
ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as exter-
nal optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.
I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.
LES_ALTEX0 PD6 LESENSE alternate exite output 0.
LES_ALTEX1 PD7 LESENSE alternate exite output 1.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
LES_ALTEX2 PA3 LESENSE alternate exite output 2.
LES_ALTEX3 PA4 LESENSE alternate exite output 3.
LES_ALTEX4 PA5 LESENSE alternate exite output 4.
LES_ALTEX5 PE11 LESENSE alternate exite output 5.
LES_ALTEX6 PE12 LESENSE alternate exite output 6.
LES_ALTEX7 PE13 LESENSE alternate exite output 7.
LES_CH0 PC0 LESENSE channel 0.
LES_CH1 PC1 LESENSE channel 1.
LES_CH2 PC2 LESENSE channel 2.
LES_CH3 PC3 LESENSE channel 3.
LES_CH4 PC4 LESENSE channel 4.
LES_CH5 PC5 LESENSE channel 5.
LES_CH6 PC6 LESENSE channel 6.
LES_CH7 PC7 LESENSE channel 7.
LES_CH8 PC8 LESENSE channel 8.
LES_CH9 PC9 LESENSE channel 9.
LES_CH10 PC10 LESENSE channel 10.
LES_CH11 PC11 LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in
half duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.
PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.
PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.
PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.
TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PF5 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.
TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.
TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.
TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.
U0_RX PF7 PE1 PA4 UART0 Receive input.
U0_TX PF6 PE0 PA3 UART0 Transmit output. Also used as receive input in half
duplex communication.
U1_RX PF11 PB10 PE3 UART1 Receive input.
U1_TX PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half
duplex communication.
US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output.
US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output.
US0_RX PE11 PE6 PC10 PE12 PB8 PC1
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 PF0 USART1 clock input / output.
US1_CS PB8 PD3 PF1 USART1 chip select input / output.
US1_RX PC1 PD1 PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
US1_TX PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output
(MISO).
US2_TX PC2 PB3
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM PF10 USB D- pin.
USB_DMPU PD2 USB D- Pullup control.
USB_DP PF11 USB D+ pin.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
USB_ID PF12 USB ID pin. Used in OTG mode.
USB_VBUS USB_VBUS USB 5 V VBUS input.
USB_VBUSEN PF5 USB 5 V VBUS enable.
USB_VREGI USB_VREGI USB Input to internal 3.3 V regulator
USB_VREGO USB_VREGO USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32GG380 is shown in Table 4.3 (p. 62) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port Pin
15 Pin
14 Pin
13 Pin
12 Pin
11 Pin
10 Pin
9Pin
8Pin
7Pin
6Pin
5Pin
4Pin
3Pin
2Pin
1Pin
0
Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B - PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port C - - - - PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D - - - PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Port F - - - PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 - - PF2 PF1 PF0
4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32GG380 is shown in Figure 4.2 (p. 62) .
Figure 4.2. Opamp Pinout
-
+
OPA0
-
+
OPA2
-
+
OPA1
OUT0ALT
OUT0
OUT2
OUT1ALT
OUT1
PC4
PC5
PD4
PD3
PD6
PD7
PB11
PB12
PC0
PC1
PC2
PC3
PC12
PC13
PC14
PC15
PD0
PD1
PD5
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4.5 LQFP100 Package
Figure 4.3. LQFP100
Note:
1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H'.
2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'.
3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Di-
mensions 'D1' and 'E1' do include mold mismatch and are determined at datum plane datum 'H'.
4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the
lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located
on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm
5. Exact shape of each corner is optional.
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Table 4.4. LQFP100 (Dimensions in mm)
SYMBOL MIN NOM MAX
total thickness A -- -- 1.6
stand off A1 0.05 -- 0.15
mold thickness A2 1.35 1.4 1.45
lead width (plating) b 0.17 0.2 0.27
lead width b1 0.17 -- 0.23
L/F thickness (plating) c 0.09 -- 0.2
lead thickness c1 0.09 -- 0.16
x D 16 BSC
y E 16 BSC
x D1 14 BSC
body size y E1 14 BSC
lead pitch e 0.5 BSC
L 0.45 0.6 0.75
footprint L1 1 REF
θ0° 3.5° 7°
θ10° -- --
θ211° 12° 13°
θ311° 12° 13°
R1 0.08 -- --
R1 0.08 -- 0.2
S 0.2 -- --
package edge tolerance aaa 0.2
lead edge tolerance bbb 0.2
coplanarity ccc 0.08
lead offset ddd 0.08
mold flatness eee 0.05
The LQFP100 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. LQFP100 PCB Land Pattern
e
a
d
c
b
p1
p2
p3 p4
p5
p6
p7p8
Table 5.1. QFP100 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin number Symbol Pin number
a 1.45 P1 1 P6 75
b 0.30 P2 25 P7 76
c 0.50 P3 26 P8 100
d 15.40 P4 50 - -
e 15.40 P5 51 - -
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Figure 5.2. LQFP100 PCB Solder Mask
e
a
d
c
b
Table 5.2. QFP100 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.57
b 0.42
c 0.50
d 15.40
e 15.40
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Figure 5.3. LQFP100 PCB Stencil Design
e
a
d
c
b
Table 5.3. QFP100 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.35
b 0.20
c 0.50
d 15.40
e 15.40
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.3 (p. 63) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 68) .
6.3 Errata
Please see the errata document for EFM32GG380 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.30
May 23rd, 2014
Removed "preliminary" markings
Updated HFRCO figures.
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Updated Current Consumption information.
Updated Power Management information.
Updated GPIO information.
Updated LFRCO information.
Updated HFRCO information.
Updated ULFRCO information.
Updated ADC information.
Updated DAC information.
Updated OPAMP information.
Updated ACMP information.
Updated VCMP information.
Added AUXHFRCO information.
7.2 Revision 1.21
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
Re-added missing DAC-data.
7.3 Revision 1.20
September 30th, 2013
Added I2C characterization data.
Added SPI characterization data.
Added EBI characterization data.
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Corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section.
Corrected GPIO operating voltage from 1.8 V to 1.85 V.
Added the USB bootloader information.
Updated that the EM2 current consumption test was carried out with only one RAM block enabled.
Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.4 Revision 1.10
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.5 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.6 Revision 0.98
May 25th, 2012
Corrected EM3 current consumption in the Electrical Characteristics section.
7.7 Revision 0.96
February 28th, 2012
Added reference to errata document.
Corrected LQFP100 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.8 Revision 0.95
September 28th, 2011
Flash configuration for Giant Gecko is now 1024KB or 512KB. For flash sizes below 512KB, see the
Leopard Gecko Family.
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Corrected operating voltage from 1.8 V to 1.85 V.
Added rising POR level to Electrical Characteristics section.
Updated Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup.
Added Gain error drift and Offset error drift to ADC table.
Added Opamp pinout overview.
Added reference to errata document.
Corrected LQFP100 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.9 Revision 0.91
March 21th, 2011
Added new alternative locations for EBI and SWO.
Added new USB Pin to pinout table.
Corrected slew rate data for Opamps.
7.10 Revision 0.90
February 4th, 2011
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 7
2.3. Memory Map ................................................................................................................................. 9
3. Electrical Characteristics ........................................................................................................................... 10
3.1. Test Conditions ............................................................................................................................. 10
3.2. Absolute Maximum Ratings ............................................................................................................. 10
3.3. General Operating Conditions .......................................................................................................... 10
3.4. Current Consumption ..................................................................................................................... 12
3.5. Transition between Energy Modes .................................................................................................... 12
3.6. Power Management ....................................................................................................................... 13
3.7. Flash .......................................................................................................................................... 14
3.8. General Purpose Input Output ......................................................................................................... 14
3.9. Oscillators .................................................................................................................................... 22
3.10. Analog Digital Converter (ADC) ...................................................................................................... 27
3.11. Digital Analog Converter (DAC) ...................................................................................................... 37
3.12. Operational Amplifier (OPAMP) ...................................................................................................... 38
3.13. Analog Comparator (ACMP) .......................................................................................................... 42
3.14. Voltage Comparator (VCMP) ......................................................................................................... 44
3.15. EBI ........................................................................................................................................... 44
3.16. I2C ........................................................................................................................................... 48
3.17. USART SPI ................................................................................................................................ 49
3.18. USB .......................................................................................................................................... 50
3.19. Digital Peripherals ....................................................................................................................... 50
4. Pinout and Package ................................................................................................................................. 52
4.1. Pinout ......................................................................................................................................... 52
4.2. Alternate Functionality Pinout .......................................................................................................... 56
4.3. GPIO Pinout Overview ................................................................................................................... 62
4.4. Opamp Pinout Overview ................................................................................................................. 62
4.5. LQFP100 Package ........................................................................................................................ 63
5. PCB Layout and Soldering ........................................................................................................................ 65
5.1. Recommended PCB Layout ............................................................................................................ 65
5.2. Soldering Information ..................................................................................................................... 67
6. Chip Marking, Revision and Errata .............................................................................................................. 68
6.1. Chip Marking ................................................................................................................................ 68
6.2. Revision ...................................................................................................................................... 68
6.3. Errata ......................................................................................................................................... 68
7. Revision History ...................................................................................................................................... 69
7.1. Revision 1.30 ............................................................................................................................... 69
7.2. Revision 1.21 ............................................................................................................................... 69
7.3. Revision 1.20 ............................................................................................................................... 69
7.4. Revision 1.10 ............................................................................................................................... 70
7.5. Revision 1.00 ............................................................................................................................... 70
7.6. Revision 0.98 ............................................................................................................................... 70
7.7. Revision 0.96 ............................................................................................................................... 70
7.8. Revision 0.95 ............................................................................................................................... 70
7.9. Revision 0.91 ............................................................................................................................... 71
7.10. Revision 0.90 .............................................................................................................................. 71
A. Disclaimer and Trademarks ....................................................................................................................... 72
A.1. Disclaimer ................................................................................................................................... 72
A.2. Trademark Information ................................................................................................................... 72
B. Contact Information ................................................................................................................................. 73
B.1. ................................................................................................................................................. 73
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32GG380 Memory Map with largest RAM and Flash sizes ........................................................................ 9
3.1. Typical Low-Level Output Current, 2V Supply Voltage .................................................................................. 16
3.2. Typical High-Level Output Current, 2V Supply Voltage ................................................................................. 17
3.3. Typical Low-Level Output Current, 3V Supply Voltage .................................................................................. 18
3.4. Typical High-Level Output Current, 3V Supply Voltage ................................................................................. 19
3.5. Typical Low-Level Output Current, 3.8V Supply Voltage ............................................................................... 20
3.6. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................... 21
3.7. Calibrated LFRCO Frequency vs Temperature and Supply Voltage ................................................................ 24
3.8. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature .............................................. 25
3.9. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature .............................................. 25
3.10. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 25
3.11. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 26
3.12. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 26
3.13. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 26
3.14. Integral Non-Linearity (INL) ................................................................................................................... 32
3.15. Differential Non-Linearity (DNL) .............................................................................................................. 32
3.16. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 33
3.17. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 34
3.18. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 35
3.19. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 36
3.20. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 36
3.21. ADC Temperature sensor readout ......................................................................................................... 37
3.22. OPAMP Common Mode Rejection Ratio ................................................................................................. 40
3.23. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 40
3.24. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 41
3.25. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V ..................................................................... 41
3.26. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 41
3.27. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 43
3.28. EBI Write Enable Timing ....................................................................................................................... 44
3.29. EBI Address Latch Enable Related Output Timing ..................................................................................... 45
3.30. EBI Read Enable Related Output Timing ................................................................................................. 46
3.31. EBI Read Enable Related Timing Requirements ........................................................................................ 47
3.32. EBI Ready/Wait Related Timing Requirements .......................................................................................... 47
3.33. SPI Master Timing ............................................................................................................................... 49
3.34. SPI Slave Timing ................................................................................................................................ 50
4.1. EFM32GG380 Pinout (top view, not to scale) ............................................................................................. 52
4.2. Opamp Pinout ...................................................................................................................................... 62
4.3. LQFP100 ............................................................................................................................................. 63
5.1. LQFP100 PCB Land Pattern ................................................................................................................... 65
5.2. LQFP100 PCB Solder Mask .................................................................................................................... 66
5.3. LQFP100 PCB Stencil Design ................................................................................................................. 67
6.1. Example Chip Marking (top view) ............................................................................................................. 68
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 7
3.1. Absolute Maximum Ratings ..................................................................................................................... 10
3.2. General Operating Conditions .................................................................................................................. 10
3.3. Environmental ....................................................................................................................................... 11
3.4. Current Consumption ............................................................................................................................. 12
3.5. Energy Modes Transitions ...................................................................................................................... 13
3.6. Power Management ............................................................................................................................... 13
3.7. Flash .................................................................................................................................................. 14
3.8. GPIO .................................................................................................................................................. 14
3.9. LFXO .................................................................................................................................................. 22
3.10. HFXO ................................................................................................................................................ 23
3.11. LFRCO .............................................................................................................................................. 23
3.12. HFRCO ............................................................................................................................................. 24
3.13. AUXHFRCO ....................................................................................................................................... 27
3.14. ULFRCO ............................................................................................................................................ 27
3.15. ADC .................................................................................................................................................. 27
3.16. DAC .................................................................................................................................................. 37
3.17. OPAMP ............................................................................................................................................. 38
3.18. ACMP ............................................................................................................................................... 42
3.19. VCMP ............................................................................................................................................... 44
3.20. EBI Write Enable Timing ....................................................................................................................... 45
3.21. EBI Address Latch Enable Related Output Timing ..................................................................................... 45
3.22. EBI Read Enable Related Output Timing ................................................................................................. 46
3.23. EBI Read Enable Related Timing Requirements ........................................................................................ 47
3.24. EBI Ready/Wait Related Timing Requirements .......................................................................................... 47
3.25. I2C Standard-mode (Sm) ...................................................................................................................... 48
3.26. I2C Fast-mode (Fm) ............................................................................................................................ 48
3.27. I2C Fast-mode Plus (Fm+) .................................................................................................................... 49
3.28. SPI Master Timing ............................................................................................................................... 49
3.29. SPI Slave Timing ................................................................................................................................ 50
3.30. Digital Peripherals ............................................................................................................................... 50
4.1. Device Pinout ....................................................................................................................................... 52
4.2. Alternate functionality overview ................................................................................................................ 56
4.3. GPIO Pinout ........................................................................................................................................ 62
4.4. LQFP100 (Dimensions in mm) ................................................................................................................. 64
5.1. QFP100 PCB Land Pattern Dimensions (Dimensions in mm) ......................................................................... 65
5.2. QFP100 PCB Solder Mask Dimensions (Dimensions in mm) ......................................................................... 66
5.3. QFP100 PCB Stencil Design Dimensions (Dimensions in mm) ....................................................................... 67
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 42
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 44
