BQ20Z45DBT-R1 - Texas Instruments

FEATURES

DESCRIPTION

APPLICATIONS

bq20z45

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.................................................................................................................................................................................................. SLUS800 – MARCH 2009

SBS 1.1-Compliant Gas Gauge and Protection Enabled With Impedance Track™

•Next Generation Patented Impedance Track™Technology Accurately Measures Available

The bq20z45 SBS-compliant gas gauge andCharge in Li-Ion and Li-Polymer Batteries

protection IC is a single IC solution designed forbattery-pack or in-system installation. The bq20z45– Better Than 1% Error Over the Lifetime of

measures and maintains an accurate record ofthe Battery

available charge in Li-ion or Li-polymer batteries•Supports the Smart Battery Specification

using its integrated high-performance analogSBS V1.1

peripherals, monitors capacity change, battery•Flexible Configuration for 2 to 4 Series Li-Ion

impedance, open-circuit voltage, and other criticalparameters of the battery pack as well and reportsand Li-Polymer Cells

the information to the system host controller over a•Powerful 8-Bit RISC CPU With Ultralow Power

serial-communication bus. Together with theModes

integrated analog front-end (AFE) short-circuit and•Full Array of Programmable Protection

overload protection, the bq20z45 maximizesFeatures

functionality and safety while minimizing externalcomponent count, cost, and size in smart battery– Voltage, Current, and Temperature

circuits.•Satisfies JEITA Guidelines

The implemented Impedance Track™ gas gauging•Added Flexibility to Handle More Complex

technology continuously analyzes the batteryCharging Profiles

impedance, resulting in superior gas-gauging•Lifetime Data Logging

accuracy. This enables remaining capacity to be•Supports SHA-1 Authentication

calculated with discharge rate, temperature, and cellaging all accounted for during each stage of every•Complete Battery Protection and Gas Gauge

cycle with high accuracy.Solution in One Package•Available in a 38-Pin TSSOP (DBT) package

•Notebook PCs•Medical and Test Equipment•Portable Instrumentation

AVAILABLE OPTIONS

PACKAGE

(1)T

38-PIN TSSOP (DBT) Tube 38-PIN TSSOP (DBT) Tape and Reel

– 40 ° C to 85 ° C bq20z45DBT

(2)

bq20z45DBTR

(3)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) A single tube quantity is 50 units.(3) A single reel quantity is 2000 units

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Impedance Track is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

SYSTEM PARTITIONING DIAGRAM

Coloumb

Counter

HWOver

Current &

ShortCircuit

Protection

CellVoltage

Multiplexer

N-ChannelFET

Drive

PreChargeFET

&GPODDrive

PowerMode

Control

SMBD

GSRN

GSRP

ASRN

ASRP

GPOD

ZVCHG

CHG

DSG

VC5

VC4

VC3

VC2

VC1

SMBC

CellBalancing

Temperature

Measurement

DataFlash

Memory

SMB1.1

Impedance

Track ™

GasGauging

SHA-1

Authentication

Over & Under

Voltage

Protection

Voltage

Measurement

OverCurrent

Protection

Oscillator

Charging

Algorithm

FuseBlow

Detectionand

Logic

Over

Temperature

Protection

SAFE

PFIN

TS2

TS1

TOUT

PMS

Watchdog

Regulators

RESET

ALERT

REG33

REG25

VCELL+

BAT

PACK

VCC

VSS

MSRT

RBI

SystemControl AFEHWControl

Pack-

RSNS

5m -20m typ.W W

Pack+

SMBC

SMBD

bq20z45

GND

VC4

VC3

VC2

VC1 VDD

OUT

bq294xx

DSG

PACK

VCC

ALERT

ZVCHG

PRES

PMS

TS2

VSS

PFIN

REG33

SAFE

TOUT

SMBD

VCELL+

SMBC

CHG

BAT

VC1

VSS

VC2

RBI

VC3

REG25

VC4

VSS

VC5

MRST

ASRP

GSRN

ASRN

GSRP

RESET

VSS

GPOD

TS1

bq20z45

SLUS800 – MARCH 2009 ..................................................................................................................................................................................................

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

bq20z45

DBT PACKAGE

(TOP VIEW)

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PIN FUNCTIONS

I/O

(1)

DESCRIPTIONNO. NAME

1 DSG O High side N-chan discharge FET gate driveBattery pack input voltage sense input. It also serves as device wake up when device is in shutdown2 PACK IA, P

mode.

Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to3 VCC P

ensure device supply either from battery stack or battery pack input4 ZVCHG O P-chan pre-charge FET gate driveHigh voltage general purpose open drain output. Can be configured to be used in pre-charge5 GPOD OD

condition

Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET6 PMS I connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected atCHG pin.7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device8 REG33 P 3.3V regulator output. Connect at least a 2.2 µF capacitor to REG33 and VSS9 TOUT P Thermistor bias supply output10 VCELL+ - Internal cell voltage multiplexer and amplifier output. Connect a 0.1 µF capacitor to VCELL+ and VSSAlert output. In case of short circuit condition, overload condition and watchdog time out this pin will11 ALERT I/OD

be triggered.12 PRES I/OD System / Host present input. Pull up to TOUT13 TS1 IA Temperature sensor 1 input14 TS2 IA Temperature sensor 2 input15 PFIN I/OD Fuse blow detection input16 SAFE I/OD blow fuse signal output17 SMBD I/OD SMBus data line18 SMBC I/OD SMBus clock line19 NC - Not connected20, 21, 25,

VSS P Negative device power supply input. Connect all VSS pins together for operation of device28

22 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor23 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor24 MRST I Reset input for internal CPU core. connect to RESET for correct operation of device26 REG25 P 2.5V regulator output. Connect at least a 1 µF capacitor to REG25 and VSSRAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of27 RBI P

short circuit condition29 RESET O Reset output. Connect to MSRT.30 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor31 ASRP IA Short circuit and overload detection differential input. Connect to sense resistorCell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell32 VC5 IA, P

stack.

Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the33 VC4 IA, P

negative voltage of the second lowest cell in cell stack.Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in34 VC3 IA, P

cell stack and the negative voltage of the second highest cell in 4 cell applications.Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell35 VC2 IA, P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stackapplications

Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell36 VC1 IA, P

stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications37 BAT I, P Battery stack voltage sense input38 CHG O High side N-chan charge FET gate drive

(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

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over operating free-air temperature (unless otherwise noted)

(1)

PIN UNIT

BAT, VCC – 0.3 V to 34 VPACK, PMS – 0.3 V to 34 VV

Supply voltage range VC(n)-VC(n+1); n = 1, 2, 3, 4 – 0.3 V to 8.5 VVC1, VC2, VC3, VC4 – 0.3 V to 34 VVC5 – 0.3 V to 1 VPFIN, SMBD, SMBC – 0.3 V to 6 VTS1, TS2, SAFE, VCELL+, PRES; ALERT – 0.3 V to V

(REG25)

+ 0.3 VV

Input voltage range

MRST, GSRN, GSRP, RBI – 0.3 V to V

(REG25)

+ 0.3 VASRN, ASRP – 1 V to 1 VDSG, CHG, GPOD – 0.3 V to 34 VZVCHG – 0.3 V to V

(BAT)

OUT

Output voltage range TOUT, ALERT, REG33 – 0.3 V to 6 VRESET – 0.3 V to 7 VREG25 – 0.3 V to 2.75 VI

Maximum combined sink current for input pins PRES, PFIN, SMBD, SMBC 50 mAT

Operating free-air temperature range – 40 ° C to 85 ° CT

Functional temperature – 40 ° C to 100 ° CT

stg

Storage temperature range – 65 ° C to 150 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

over operating free-air temperature range (unless otherwise noted)

PIN MIN NOM MAX UNIT

Supply voltage VCC, BAT 4.5 25 VV

(STARTUP)

Minimum startup voltage VCC, BAT, PACK 5.5 VVC(n)-VC(n+1); n = 1,2,3,4 0 5 VVC1, VC2, VC3, VC4 0 V

SUP

Input Voltage Range VC5 0 0.5 VASRN, ASRP – 0.5 0.5 VPACK, PMS 0 25 VV

(GPOD)

Output Voltage Range GPOD 0 25 VA

(GPOD)

Drain Current

(1)

GPOD 1 mAC

(REG25)

2.5V LDO Capacitor REG25 1 µ FC

(REG33)

3.3V LDO Capacitor REG33 2.2 µ FC

(VCELL+)

Cell Voltage Output Capacitor VCELL+ 0.1 µ FC

(PACK)

PACK input block resistor

(2)

PACK 1 k Ω

(1) Use an external resistor to limit the current to GPOD to 1mA in high voltage application.(2) Use an external resistor to limit the inrush current PACK pin required.

Product Folder Link(s): bq20z45

ELECTRICAL CHARACTERISTICS

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over operating free-air temperature range (unless otherwise noted), T

= – 40 ° C to 85 ° C, V

(REG25)

= 2.41 V to 2.59 V,V

(BAT)

= 14 V, C

(REG25)

= 1 µ F, C

(REG33)

= 2.2 µ F; typical values at T

= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

(NORMAL)

Firmware running 550 µ A

(SLEEP)

Sleep Mode CHG FET on; DSG FET on 124 µ A

CHG FET off; DSG FET on 90 µ A

CHG FET off; DSG FET off 52 µ A

(SHUTDOWN)

Shutdown Mode 0.1 1 µ A

SHUTDOWN WAKE; T

= 25 ° C (unless otherwise noted)

(PACK)

Shutdown exit at V

STARTUP

threshold 1 µ A

SRx WAKE FROM SLEEP; T

= 25 ° C (unless otherwise noted)

Positive or negative wake thresholdV

(WAKE)

with 1.00 mV, 2.25 mV, 4.5 mV and 9 1.25 10 mVmV programmable options

(WAKE)

= 1 mV;

-0.7 0.7I

(WAKE)

= 0, RSNS1 = 0, RSNS0 = 1;

(WAKE)

= 2.25 mV;I

(WAKE

) = 1, RSNS1 = 0, RSNS0 = 1; -0.8 0.8I

(WAKE)

= 0, RSNS1 = 1, RSNS0 = 0;V

(WAKE_ACR)

Accuracy of V

(WAKE)

mVV

(WAKE)

= 4.5 mV;I

(WAKE)

= 1, RSNS1 = 1, RSNS0 = 1; -1.0 1.0I

(WAKE)

= 0, RSNS1 = 1, RSNS0 = 0;

(WAKE)

= 9 mV;

-1.4 1.4I

(WAKE)

= 1, RSNS1 = 1, RSNS0 = 1;

(WAKE_TCO)

Temperature drift of V

(WAKE)

accuracy 0.5 %/ ° C

Time from application of current andt

(WAKE)

1 10 mswake of bq8040

POWER-ON RESET

IT –

Negative-going voltage input Voltage at REG25 pin 1.70 1.80 1.90 V

hys

Hysteresis V

IT+

– V

IT-

50 150 250 mV

active low time after power up ort

RST

RESET active low time 100 250 560 µ swatchdog reset

WATCHDOG TIMER

WDTINT

Watchdog start up detect time 250 500 1000 ms

WDWT

Watchdog detect time 50 100 150 µ s

2.5V LDO; I

(REG33OUT)

= 0 mA; T

= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25 V;V

(REG25)

Regulator output voltage I

(REG25OUT

)≤16 mA; 2.41 2.5 2.59 VT

= – 40 ° C to 100 ° C

Regulator output change with I

(REG25OUT)

= 2 mA;ΔV

(REG25TEMP)

± 0.2 %temperature T

= – 40 ° C to 100 ° C

5.4 < VCC or BAT < 25 V;ΔV

(REG25LINE)

Line regulation 3 10 mVI

(REG25OUT)

= 2 mA

0.2 mA ≤I

(REG25OUT)

≤2 mA 7 25ΔV

(REG25LOAD)

Load Regulation mV0.2 mA ≤I

(REG25OUT)

≤16 mA 25 50

drawing current untilI

(REG25MAX)

Current Limit 5 40 75 mAREG25 = 2 V to 0 V

3.3V LDO; I

(REG25OUT)

= 0 mA; T

= 25 ° C (unless otherwise noted)

4.5 < VCC or BAT < 25 V;V

(REG33)

Regulator output voltage I

(REG33OUT)

≤25 mA; 3 3.3 3.6 VT

= – 40 ° C to 100 ° C

Regulator output change with I

(REG33OUT)

= 2 mA;ΔV

(REG33TEMP)

± 0.2 %temperature T

= – 40 ° C to 100 ° C

5.4 < VCC or BAT < 25 V;ΔV

(REG33LINE)

Line regulation 3 10 mVI

(REG33OUT)

= 2 mA

0.2 mA ≤I

(REG33OUT)

≤2 mA 7 17ΔV

(REG33LOAD)

Load Regulation mV0.2mA ≤I

(REG33OUT)

≤25 mA 40 100

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ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range (unless otherwise noted), T

= – 40 ° C to 85 ° C, V

(REG25)

= 2.41 V to 2.59 V,V

(BAT)

= 14 V, C

(REG25)

= 1 µ F, C

(REG33)

= 2.2 µ F; typical values at T

= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

drawing current until REG33 = 3 V 25 100 145I

(REG33MAX)

Current Limit mAshort REG33 to VSS, REG33 = 0 V 12 65

THERMISTOR DRIVE

(TOUT)

Output voltage I

(TOUT)

= 0 mA; T

= 25 ° C V

(REG25)

(TOUT)

= 1 mA; R

DS(on)

= (V

(REG25)

-R

DS(on)

TOUT pass element resistance 50 100 ΩV

(TOUT)

)/ 1 mA; T

= – 40 ° C to 100 ° C

VCELL+ HIGH VOLTAGE TRANSLATION

VC(n) - VC(n+1) = 0 V;

0.950 0.975 1T

= – 40 ° C to 100 ° CV

(VCELL+OUT)

VC(n) - VC(n+1) = 4.5 V;

0.275 0.3 0.375T

= – 40 ° C to 100 ° C

internal AFE reference voltage ;V

(VCELL+REF)

Translation output 0.965 0.975 0.985 VT

= – 40 ° C to 100 ° C

Voltage at PACK pin; 0.98 × 1.02 ×V

(VCELL+PACK)

(PACK)

/18T

= – 40 ° C to 100 ° C V

(PACK)

/18 V

(PACK)

/18

Voltage at BAT pin; 0.98 ×V

(VCELL+BAT)

(BAT)

/18 1.02 × V

(BAT)

/18T

= – 40 ° C to 100 ° C V

(BAT)

/18

CMMR Common mode rejection ratio VCELL+ 40 dB

K= {VCELL+ output (VC5=0V;VC4=4.5V) - VCELL+ output (VC5=0V; 0.147 0.150 0.153VC4=0V)}/4.5K Cell scale factor

K= {VCELL+ output (VC2=13.5V;VC1=18V) - VCELL+ output 0.147 0.150 0.153(VC5=13.5V; VC1=13.5V)}/4.5

VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;I

(VCELL+OUT)

Drive Current to VCELL+ capacitor 12 18 µAT

= – 40 ° C to 100 ° C

CELL output (VC2 = VC1 = 18 V) -V

(VCELL+O)

CELL offset error -18 -1 18 mVCELL output (VC2 = VC1 = 0 V)

VCnL

VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V -1 0.01 1 µA

CELL BALANCING

DS(on)

for internal FET switch atR

(BAL)

internal cell balancing FET resistance 200 400 600 ΩV

= 2 V; T

= 25 ° C

HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; T

= 25 ° C (unless otherwise noted)

= 25 mV (min) 15 25 35OL detection threshold voltageV

(OL)

= 100 mV; RSNS = 0, 1 90 100 110 mVaccuracy

= 205 mV (max) 185 205 225

(SCC)

= 50 mV (min) 30 50 70SCC detection threshold voltageV

(SCC)

= 200 mV; RSNS = 0, 1 180 200 220 mVaccuracy

(SCC)

= 475 mV (max) 428 475 523

(SCD)

= – 50 mV (min) – 30 – 50 – 70SCD detection threshold voltageV

(SCD)

= – 200 mV; RSNS = 0, 1 – 180 – 200 – 220 mVaccuracy

(SCD)

= – 475 mV (max) – 428 – 475 – 523

Delay time accuracy ± 15.25 µs

Protection circuit propagation delay 50 µs

FET DRIVE CIRCUIT; T

= 25 ° C (unless otherwise noted)

(DSGON)

= V

(DSG)

- V

(PACK)

(DSGON)

DSG pin output on voltage V

(GS)

= 10 M Ω; DSG and CHG on; 8 12 16 VT

= – 40 ° C to 100 ° C

(CHGON)

= V

(CHG)

- V

(BAT)

(CHGON)

CHG pin output on voltage V

(GS)

= 10 M Ω; DSG and CHG on; 8 12 16 VT

= – 40 ° C to 100 ° C

(DSGOFF)

DSG pin output off voltage V

(DSGOFF)

= V

(DSG)

- V

(PACK)

0.2 V

(CHGOFF)

CHG pin output off voltage V

(CHGOFF)

= V

(CHG)

- V

(BAT)

0.2 V

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ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range (unless otherwise noted), T

= – 40 ° C to 85 ° C, V

(REG25)

= 2.41 V to 2.59 V,V

(BAT)

= 14 V, C

(REG25)

= 1 µ F, C

(REG33)

= 2.2 µ F; typical values at T

= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 4700 pF;

400 1000V

(PACK)

≤DSG ≤V

(PACK)

+ 4Vt

Rise time µsC

= 4700 pF;

400 1000V

(BAT)

≤CHG ≤V

(BAT)

+ 4V

= 4700pF;

(PACK)

+ V

(DSGON)

≤DSG ≤V

(PACK)

+ 40 2001Vt

Fall time µsC

= 4700 pF;

40 200V

(BAT)

+ V

(CHGON)

≤CHG ≤V

(BAT)

+ 1V

(ZVCHG)

ZVCHG clamp voltage BAT = 4.5 V 3.3 3.5 3.7 V

LOGIC; T

= – 40 ° C to 100 ° C (unless otherwise noted)

ALERT 60 100 200R

(PULLUP)

Internal pullup resistance k ΩRESET 1 3 6

ALERT 0.2

RESET; V

(BAT)

= 7V; V

(REG25)

= 1.5 V;V

Logic low output voltage level 0.4 VI

(RESET)

= 200 µA

GPOD; I

(GPOD)

= 50 µA 0.6

LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT

High-level input voltage 2.0 V

Low-level input voltage 0.8 V

Output voltage high

(1)

= – 0.5 mA V

REG25

– 0.5 V

Low-level output voltage PRES, PFIN, ALERT, I

= 7 mA; 0.4 V

Input capacitance 5 pF

(SAFE)

SAFE source currents SAFE active, SAFE = V

(REG25)

– 0.6 V – 3 mA

SAFE leakage current SAFE inactive – 0.2 0.2 µ AI

lkg

Input leakage current 1 µ A

ADC

(2)

Input voltage range TS1, TS2, using Internal V

ref

– 0.2 1 V

Conversion time 31.5 ms

Resolution (no missing codes) 16 bits

Effective resolution 14 15 bits

%FSR

(Integral nonlinearity ± 0.03

Offset error

(4)

140 250 µ V

Offset error drift

(4)

= 25 ° C to 85 ° C 2.5 18 µV/ ° C

Full-scale error

(5)

± 0.1% ± 0.7%

PPM/Full-scale error drift 50

° C

Effective input resistance

(6)

8 M Ω

COULOMB COUNTER

Input voltage range – 0.20 0.20 V

Conversion time Single conversion 250 ms

Effective resolution Single conversion 15 bits

– 0.1 V to 0.20 V ± 0.007 ± 0.034Integral nonlinearity %FSR– 0.20 V to – 0.1 V ± 0.007

(1) RC[0:7] bus(2) Unless otherwise specified, the specification limits are valid at all measurement speed modes(3) Full-scale reference(4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference(5) Uncalibrated performance. This gain error can be eliminated with external calibration.(6) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the averageresistance.

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ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range (unless otherwise noted), T

= – 40 ° C to 85 ° C, V

(REG25)

= 2.41 V to 2.59 V,V

(BAT)

= 14 V, C

(REG25)

= 1 µ F, C

(REG33)

= 2.2 µ F; typical values at T

= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Offset error

(7)

= 25 ° C to 85 ° C 10 µ V

Offset error drift 0.4 0.7 µ V/ ° C

Full-scale error

(8) (9)

± 0.35%

PPM/Full-scale error drift 150

° C

Effective input resistance

(10)

= 25 ° C to 85 ° C 2.5 M Ω

INTERNAL TEMPERATURE SENSOR

(TEMP)

Temperature sensor voltage

(11)

-2.0 mV/ ° C

VOLTAGE REFERENCE

Output voltage 1.215 1.225 1.230 V

PPM/Output voltage drift 65

° C

HIGH FREQUENCY OSCILLATOR

(OSC)

Operating frequency 4.194 MHz

– 3% 0.25% 3%f

(EIO)

Frequency error

(12) (13)

= 20 ° C to 70 ° C – 2% 0.25% 2%

(SXO)

Start-up time

(14)

2.5 5 ms

LOW FREQUENCY OSCILLATOR

(LOSC)

Operating frequency 32.768 kHz

– 2.5% 0.25% 2.5%f

(LEIO)

Frequency error

(13) (15)

= 20 ° C to 70 ° C – 1.5% 0.25% 1.5%

(LSXO)

Start-up time

(14)

500 µ s

(7) Post-calibration performance(8) Reference voltage for the coulomb counter is typically V

ref

/3.969 at V

(REG25)

= 2.5 V, T

= 25 ° C.(9) Uncalibrated performance. This gain error can be eliminated with external calibration.(10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the averageresistance.

(11) – 53.7 LSB/ ° C(12) The frequency error is measured from 4.194 MHz.(13) The frequency drift is included and measured from the trimmed frequency at V

(REG25)

= 2.5V, T

= 25 ° C(14) The startup time is defined as the time it takes for the oscillator output frequency to be ± 3%(15) The frequency error is measured from 32.768 kHz.

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DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND

SMBus TIMING CHARACTERISTICS

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SUPPLY VOLTAGE

Typical Values at T

= 25 ° C and V

(REG25)

= 2.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Data retention 10 YearsFlash programming write-cycles 20k Cyclest

(ROWPROG)

Row programming time See

(1)

2 mst

(MASSERASE)

Mass-erase time 200 mst

(PAGEERASE)

Page-erase time 20 msI

(DDPROG)

Flash-write supply current 5 10 mAI

(DDERASE)

Flash-erase supply current 5 10 mA

RAM BACKUP

(RBI)

> V

(RBI)MIN

, V

REG25

< V

IT –

, T

= 85 ° C 1000 2500I

(RB)

RB data-retention input current nAV

(RBI)

> V

(RBI)MIN

, V

REG25

< V

IT –

, T

= 25 ° C 90 220V

(RB)

RB data-retention input voltage

(1)

1.7 V

(1) Specified by design. Not production tested.

= – 40 ° C to 85 ° C Typical Values at T

= 25 ° C and V

REG25

= 2.5 V (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(SMB)

SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHzMaster mode, No clock low slavef

(MAS)

SMBus master clock frequency 51.2 kHzextendBus free time between start and stopt

(BUF)

4.7 µ s(see Figure 1 )t

(HD:STA)

Hold time after (repeated) start (see Figure 1 ) 4 µ st

(SU:STA)

Repeated start setup time (see Figure 1 ) 4.7 µ st

(SU:STO)

Stop setup time (see Figure 1 ) 4 µ sReceive mode 0 nst

(HD:DAT)

Data hold time (see Figure 1 )

Transmit mode 300t

(SU:DAT)

Data setup time (see Figure 1 ) 250 nst

(TIMEOUT)

Error signal/detect (see Figure 1 ) See

(1)

25 35 µ st

(LOW)

Clock low period (see Figure 1 ) 4.7 µ st

(HIGH)

Clock high period (see Figure 1 ) See

(2)

4 50 µ st

(LOW:SEXT)

Cumulative clock low slave extend time See

(3)

25 msCumulative clock low master extend timet

(LOW:MEXT)

See

(4)

10 ms(see Figure 1 )t

Clock/data fall time See

(5)

300 nst

Clock/data rise time See

(6)

1000 ns

(1) The bq8040 times out when any clock low exceeds t

(TIMEOUT)

.(2) t

(HIGH)

, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq8040 that is inprogress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).(3) t

(LOW:SEXT)

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.(4) t

(LOW:MEXT)

is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.(5) Rise time t

= V

MAX – 0.15) to (V

MIN + 0.15)(6) Fall time t

= 0.9V

to (V

MAX – 0.15)

Product Folder Link(s): bq20z45

TLOW TRTF

THD:STA

TSU:DAT

THD:DAT

THD:STA

TBUF

SCLK

SDATA

TSU:STO

PSSP

SCLK

SDATA

Start Stop

TLOW:SEXT

TLOW:MEXT TLOW:MEXT TLOW:MEXT

SCLKACK†SCLKACK†

TSU:STA

THIGH

bq20z45

www.ti.com

A. SCLKACK is the acknowledge-related clock pulse generated by the master.

Figure 1. SMBus Timing Diagram

Product Folder Link(s): bq20z45

FEATURE SET

Primary (1st Level) Safety Features

Secondary (2nd Level) Safety Features

Charge Control Features

Gas Gauging

bq20z45

www.ti.com

The bq20z45 supports a wide range of battery and system protection features that can easily be configured. Theprimary safety features include:

•Cell over/undervoltage protection•Charge and discharge overcurrent•Short Circuit•Charge and discharge overtemperature with independent alarms and thresholds for each thermistor•AFE Watchdog

The secondary safety features of the bq20z45 can be used to indicate more serious faults via the SAFE (pin 7).This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging ordischarging. The secondary safety protection features include:

•Safety overvoltage

•Safety undervoltage

•Safety overcurrent in charge and discharge•Safety overtemperature in charge and discharge with independent alarms and thresholds for each thermistor•Charge FET and 0 Volt Charge FET fault•Discharge FET fault•Cell imbalance detection (active and at rest)•Open thermistor detection•AFE communication fault

The bq20z45 charge control features include:

•Supports JEITA temperature ranges. Reports charging voltage and charging current according to the activetemperature range.•Handles more complex charging profiles. Allows for splitting the standard temperature range into 2sub-ranges and allows for varying the charging current according to the cell voltage.•Reports the appropriate charging current needed for constant current charging and the appropriate chargingvoltage needed for constant voltage charging to a smart charger using SMBus broadcasts.•Determines the chemical state of charge of each battery cell using Impedance Track™ and can reduce thecharge difference of the battery cells in fully charged state of the battery pack gradually using cell balancingalgorithm during charging. This prevents fully charged cells from overcharging and causing excessivedegradation and also increases the usable pack energy by preventing premature charge termination•Supports pre-charging/zero-volt charging•Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range•Reports charging fault and also indicate charge status via charge and discharge alarms.

The bq20z45 uses the Impedance Track™ Technology to measure and calculate the available charge in batterycells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full chargedischarge learning cycle required.

See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364 )for further details.

Product Folder Link(s): bq20z45

Lifetime Data Logging Features

Authentication

Power Modes

CONFIGURATION

Oscillator Function

System Present Operation

BATTERY PARAMETER MEASUREMENTS

Charge and Discharge Counting

bq20z45

www.ti.com

The bq20z45 offers lifetime data logging, where important measurements are stored for warranty and analysispurposes. The data monitored include:•Lifetime maximum temperature•Lifetime minimum temperature•Lifetime maximum battery cell voltage•Lifetime minimum battery cell voltage•Lifetime maximum battery pack voltage•Lifetime minimum battery pack voltage•Lifetime maximum charge current•Lifetime maximum discharge current•Lifetime maximum charge power•Lifetime maximum discharge power•Lifetime maximum average discharge current•Lifetime maximum average discharge power•Lifetime average temperature

The bq20z45 supports authentication by the host using SHA-1.

The bq20z45 supports 3 different power modes to reduce power consumption:

•In Normal Mode, the bq20z45 performs measurements, calculations, protection decisions and data updates in1 second intervals. Between these intervals, the bq20z45 is in a reduced power stage.•In Sleep Mode, the bq20z45 performs measurements, calculations, protection decisions and data update inadjustable time intervals. Between these intervals, the bq20z45 is in a reduced power stage. The bq20z45has a wake function that enables exit from Sleep mode, when current flow or failure is detected.•In Shutdown Mode the bq20z45 is completely disabled.

The bq20z45 fully integrates the system oscillators. Therefore the bq20z45 requires no external components forthis feature.

The bq20z45 checks the PRES pin periodically (1s). If PRES input is pulled to ground by external system, thebq20z45 detects this as system present.

The bq20z45 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and asecond delta-sigma ADC for individual cell and battery voltage, and temperature measurement.

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltagedrop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolarsignals from -0.25 V to 0.25 V. The bq20z45 detects charge activity when V

= V

(SRP)

- V

(SRN)

is positive anddischarge activity when V

= V

(SRP)

- V

(SRN)

is negative. The bq20z45 continuously integrates the signal overtime, using an internal counter. The fundamental rate of the counter is 0.65 nVh.

Product Folder Link(s): bq20z45

Voltage

Current

Auto Calibration

Temperature

bq20z45

www.ti.com

The bq20z45 updates the individual series cell voltages at one second intervals. The internal ADC of thebq20z45 measures the voltage, scales and calibrates it appropriately. This data is also used to calculate theimpedance of the cell for the Impedance Track™ gas-gauging.

The bq20z45 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge currentusing a 5 m Ωto 20 m Ωtyp. sense resistor.

The bq20z45 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP formaximum charge measurement accuracy. The bq20z45 performs auto-calibration when the SMBus lines staylow continuously for a minimum of 5 s.

The bq20z45 has an internal temperature sensor and inputs for 2 external temperature sensor inputs TS1 andTS2 used in conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the batteryenvironmental temperature. The bq20z45 can be configured to use internal or up to 2 external temperaturesensors.

Product Folder Link(s): bq20z45

COMMUNICATIONS

SMBus On and Off State

SBS Commands

bq20z45

www.ti.com

The bq20z45 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBSspecification.

The bq20z45 detects an SMBus off state when SMBC and SMBD are logic-low for ≥2 seconds. Clearing thisstate requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.

Table 1. SBS COMMANDSSBS Size in Min MaxMode Name Default Value UnitCmd Format Bytes Value Value

0x00 R/W ManufacturerAccess hex 2 0x0000 0xffff — —

0x01 R/W RemainingCapacityAlarm unsigned int 2 0 65535 300 mAh or 10mWh

0x02 R/W RemainingTimeAlarm unsigned int 2 0 65535 10 min

0x03 R/W BatteryMode hex 2 0x0000 0xe383 — —

0x04 R/W AtRate signed int 2 – 32768 32767 — mA or 10mW

0x05 R AtRateTimeToFull unsigned int 2 0 65534 — min

0x06 R AtRateTimeToEmpty unsigned int 2 0 65534 — min

0x07 R AtRateOK unsigned int 2 0 65535 — —

0x08 R Temperature unsigned int 2 0 65535 — 0.1 ° K

0x09 R Voltage unsigned int 2 0 65535 — mV

0x0a R Current signed int 2 – 32768 32767 — mA

0x0b R AverageCurrent signed int 2 – 32768 32767 — mA

0x0c R MaxError unsigned int 1 0 100 — %

0x0d R RelativeStateOfCharge unsigned int 1 0 100 — %

0x0e R AbsoluteStateOfCharge unsigned int 1 0 100+ — %

0x0f R/W RemainingCapacity unsigned int 2 0 65535 — mAh or 10mWh

0x10 R FullChargeCapacity unsigned int 2 0 65535 — mAh or 10mWh

0x11 R RunTimeToEmpty unsigned int 2 0 65534 — min

0x12 R AverageTimeToEmpty unsigned int 2 0 65534 — min

0x13 R AverageTimeToFull unsigned int 2 0 65534 — min

0x14 R ChargingCurrent unsigned int 2 0 65534 — mA

0x15 R ChargingVoltage unsigned int 2 0 65534 — mV

0x16 R BatteryStatus unsigned int 2 0x0000 0xffff — —

0x17 R/W CycleCount unsigned int 2 0 65535 — —

0x18 R/W DesignCapacity unsigned int 2 0 65535 4400 mAh or 10mWh

0x19 R/W DesignVoltage unsigned int 2 7000 16000 14400 mV

0x1a R/W SpecificationInfo unsigned int 2 0x0000 0xffff 0x0031 —

0x1b R/W ManufactureDate unsigned int 2 0 65535 01-Jan-1980 —

0x1c R/W SerialNumber hex 2 0x0000 0xffff 0x0001 —

0x20 R/W ManufacturerName String 20+1 — — Texas Inst. —

0x21 R/W DeviceName String 20+1 — — bq20z45 —

0x22 R/W DeviceChemistry String 4+1 — — LION —

0x23 R ManufacturerData String 14+1 — — — —

0x2f R/W Authenticate String 20+1 — — — —

0x3c R CellVoltage4 unsigned int 2 0 65535 — mV

0x3d R CellVoltage3 unsigned int 2 0 65535 — mV

0x3e R CellVoltage2 unsigned int 2 0 65535 — mV

0x3f R CellVoltage1 unsigned int 2 0 65535 — mV

Product Folder Link(s): bq20z45

bq20z45

www.ti.com

Table 2. EXTENDED SBS COMMANDS

SBS Cmd Size in DefaultMode Name Format Min Value Max Value UnitBytes Value

0x45 R AFEData String 11+1 — — — —0x46 R/W FETControl hex 2 0x00 0xff — —0x4f R StateOfHealth hex 2 0x0000 0xffff — %0x51 R SafetyStatus hex 2 0x0000 0xffff — —0x53 R PFStatus hex 2 0x0000 0xffff — —0x54 R OperationStatus hex 2 0x0000 0xffff — —0x55 R ChargingStatus hex 2 0x0000 0xffff — —0x57 R ResetData hex 2 0x0000 0xffff — —0x58 R WDResetData unsigned int 2 0 65535 — —0x5a R PackVoltage unsigned int 2 0 65535 — mV0x5d R AverageVoltage unsigned int 2 0 65535 — mV0x5e R TS1Temperature integer 2 – 400 1200 — 0.1 ° C0x5f R TS2Temperature integer 2 – 400 1200 — 0.1 ° C0x60 R/W UnSealKey hex 4 0x00000000 0xffffffff — —0x61 R/W FullAccessKey hex 4 0x00000000 0xffffffff — —0x62 R/W PFKey hex 4 0x00000000 0xffffffff — —0x63 R/W AuthenKey3 hex 4 0x00000000 0xffffffff — —0x64 R/W AuthenKey2 hex 4 0x00000000 0xffffffff — —0x65 R/W AuthenKey1 hex 4 0x00000000 0xffffffff — —0x66 R/W AuthenKey0 hex 4 0x00000000 0xffffffff — —0x69 R SafetyStatus2 hex 2 0x0000 0x000f — —0x6b R PFStatus2 hex 2 0x0000 0x000f — —0x6c R/W ManufBlock1 String 20 — — — —0x6d R/W ManufBlock2 String 20 — — — —0x6e R/W ManufBlock3 String 20 — — — —0x6f R/W ManufBlock4 String 20 — — — —0x70 R/W ManufacturerInfo String 31+1 — — — —0x71 R/W SenseResistor unsigned int 2 0 65535 — µΩ

0x72 R TempRange hex 2 0x0000 0xffff — —0x73 R LifetimeData String 32+1 — — — —0x77 R/W DataFlashSubClassID hex 2 0x0000 0xffff — —0x78 R/W DataFlashSubClassPage1 hex 32 — — — —0x79 R/W DataFlashSubClassPage2 hex 32 — — — —0x7a R/W DataFlashSubClassPage3 hex 32 — — — —0x7b R/W DataFlashSubClassPage4 hex 32 — — — —0x7c R/W DataFlashSubClassPage5 hex 32 — — — —0x7d R/W DataFlashSubClassPage6 hex 32 — — — —0x7e R/W DataFlashSubClassPage7 hex 32 — — — —0x7f R/W DataFlashSubClassPage8 hex 32 — — — —

Product Folder Link(s): bq20z45

APPLICATION SCHEMATIC

bq20z45

www.ti.com

Product Folder Link(s): bq20z45

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

BQ20Z45DBT NRND TSSOP DBT 38 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ20Z45DBTR NRND TSSOP DBT 38 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Jan-2010

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ20Z45DBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ20Z45DBTR TSSOP DBT 38 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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