1. General description
The 74HC2G125; 74HCT2G125 is a high-speed, Si-gate CMOS device.
The 74HC2G125; 74HCT2G125 provides two non-inverting buffer/line drivers with 3-state
output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH level
at pin nOE causes the output to assume a high-impedance OFF-state.
The bus driver output currents are equal compared to the 74HC125 and 74HCT125.
2. Features
nWide supply voltage range from 2.0 V to 6.0 V
nSymmetrical output impedance
nHigh noise immunity
nLow power consumption
nBalanced propagation delays
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nMultiple package options
nSpecified from −40 °Cto+85°C and −40 °C to +125 °C
3. Ordering information
74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
Rev. 04 — 4 July 2008 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC2G125DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm SOT505-2
74HCT2G125DP
74HC2G125DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
74HCT2G125DC
74HC2G125GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2
74HCT2G125GD
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 2 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
4. Marking
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 2. Marking
Type number Marking code
74HC2G125DP H25
74HCT2G125DP T25
74HC2G125DC H25
74HCT2G125DC T25
74HC2G125GD H25
74HCT2G125GD T25
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one driver)
mce185
1A 1Y
2
1
6
1OE
2A 2Y
5
7
3
2OE
mce186
11
2
6
2
EN1
73
5
EN2
mna120
AY
OE
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U)
1OE VCC
1A 2OE
2Y 1Y
GND 2A
001aae074
1
2
3
4
6
5
8
7
74HC2G125
74HCT2G125
001aai333
74HC2G125
74HCT2G125
Transparent top view
8
7
6
5
1
2
3
4
1OE
1A
2Y
GND
VCC
2OE
1Y
2A
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 3 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
Table 3. Pin description
Symbol Pin Description
1OE, 2OE 1, 7 output enable input (active LOW)
1A, 2A 2, 5 data input
GND 4 ground (0 V)
1Y, 2Y 6, 3 data output
VCC 8 supply voltage
Table 4. Function table[1]
Control Input Output
nOE nA nY
LLL
LHH
HXZ
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI<−0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±20 mA
IOoutput current VO=−0.5 V to (VCC + 0.5 V) [1] -35mA
ICC supply current - 70 mA
IGND ground current −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[2] - 300 mW
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 4 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74HC2G125 74HCT2G125 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at T
amb
=25
°
C.
Symbol Parameter Conditions Tamb =−40 °C to +85 °C Tamb =−40 °C to +125 °C Unit
Min Typ Max Min Max
74HC2G125
VIH HIGH-level input
voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level input
voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - V
IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - V
IO = −6.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V
IO = −7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
VOL LOW-level output
voltage VI= VIH or VIL
IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 V
IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 V
IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC = 6.0 V - - ±1.0 - ±1.0 µA
IOZ OFF-state output
current VI = VIH or VIL;
VO=V
CC or GND; VCC = 6.0 V --±5.0 - ±10 µA
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 5 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
11. Dynamic characteristics
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 6.0 V - - 10 - 20 µA
CIinput capacitance - 1.0 - - - pF
COoutput
capacitance - 1.5 - - - pF
74HCT2G125
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO = −20 µA 4.4 4.5 - 4.4 - V
IO = −6.0 mA 3.84 4.32 - 3.7 - V
VOL LOW-level output
voltage VI= VIH or VIL; VCC = 4.5 V
IO = 20 µA - 0 0.1 - 0.1 V
IO = 6.0 mA - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 - ±1.0 µA
IOZ OFF-state output
current VI = VIH or VIL; VO =
VCC or GND; VCC = 5.5 V --±5.0 - ±10
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V - - 10 - 20 µA
∆ICC additional supply
current perinput;VCC = 4.5 V to 5.5 V;
VI=V
CC −2.1 V; IO=0A - - 375 - 410 µA
CIinput capacitance - 1.0 - - - pF
COoutput
capacitance - 1.5 - - - pF
Table 7. Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at T
amb
=25
°
C.
Symbol Parameter Conditions Tamb =−40 °C to +85 °C Tamb =−40 °C to +125 °C Unit
Min Typ Max Min Max
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions Tamb =−40 °C to +85 °C Tamb =−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74HC2G125
tpd propagation
delay nA to nY; see Figure 6 [2]
VCC = 2.0 V - 35 115 - 135 ns
VCC = 4.5 V - 11 23 - 27 ns
VCC = 5.0 V; CL=15pF - 10 - - - ns
VCC = 6.0 V - 8 20 - 23 ns
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 6 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of outputs.
ten enable time nOE to nY; see Figure 7 [2]
VCC = 2.0 V - 40 115 - 135 ns
VCC = 4.5 V - 11 23 - 27 ns
VCC = 6.0 V - 8 20 - 23 ns
tdis disable time nOE to nY; see Figure 7 [2]
VCC = 2.0 V - 24 125 - 150 ns
VCC = 4.5 V - 12 25 - 30 ns
VCC = 6.0 V - 10 21 - 26 ns
tttransition
time see Figure 6 [2]
VCC = 2.0 V - 18 75 - 90 ns
VCC = 4.5 V - 6 15 - 18 ns
VCC = 6.0 V - 5 13 - 15 ns
CPD power
dissipation
capacitance
per buffer; VI= GND to VCC [3]
output enabled - 11 - - - pF
output disabled - 1 - - - pF
74HCT2G125
tpd propagation
delay nA to nY; see Figure 6 [2]
VCC = 4.5 V - 15 31 - 38 ns
VCC = 5.0 V; CL=15pF - 12 - - - ns
ten enable time nOE to nY; see Figure 7;
VCC = 4.5 V [2] - 15 35 - 42 ns
tdis disable time nOE to nY; see Figure 7;
VCC = 4.5 V [2] - 15 31 - 38 ns
tttransition
time see Figure 6; VCC = 4.5 V [2] - 6 15 - 18 ns
CPD power
dissipation
capacitance
per buffer;
VI= GND to VCC −1.5 V [3]
output enabled - 11 - - - pF
output disabled - 1 - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions Tamb =−40 °C to +85 °C Tamb =−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 7 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
12. Waveforms
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Propagation delays data input (nA) to output (nY)
001aad982
tPLH
tPHL
VM
VM
90 %
10 %
VMVM
output
nY
input
nA
VI
GND
VOH
VOL
tTLH
tTHL
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
mna362
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 9. Measurement points
Type Input Output
VMVMVXVY
74HC2G125 0.5VCC 0.5VCC VOL + 0.3 V VOH −0.3 V
74HCT2G125 1.3 V 1.3 V VOL + 0.3 V VOH −0.3 V
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 8 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Load circuitry for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Table 10. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC2G125 VCC ≤ 6 ns 15 pF, 50 pF 1 kΩopen GND VCC
74HCT2G125 3 V ≤ 6 ns 15 pF, 50 pF 1 kΩopen GND VCC
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 9 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
13. Package outline
Fig 9. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.95
0.75 0.38
0.22 0.18
0.08 3.1
2.9 3.1
2.9 0.65 4.1
3.9 0.70
0.35 8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
1.1
pin 1 index
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 10 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
Fig 10. Package outline SOT765-1 (VSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.85
0.60 0.27
0.17 0.23
0.08 2.1
1.9 2.4
2.2 0.5 3.2
3.0 0.4
0.1 8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187 02-06-07
wM
bp
D
Z
e
0.12
14
85
θ
A2A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
1
pin 1 index
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 11 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
Fig 11. Package outline SOT996-2 (XSON8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT996-2 - - -- - -
SOT996-2
07-12-18
07-12-21
UNIT A
max
mm 0.5 0.05
0.00 0.35
0.15 3.1
2.9 0.5 1.5 0.5
0.3 0.6
0.4 0.1 0.05
A1
DIMENSIONS (mm are the original dimensions)
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
0 1 2 mm
scale
b D
2.1
1.9
E e e1L L1
0.15
0.05
L2v w
0.05
y y1
0.1
C
y
C
y1
X
b
14
85
e1
eAC B
vMCw M
L2
L1
L
terminal 1
index area
B A
D
E
detail X
AA1
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 12 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT2G125_4 20080704 Product data sheet - 74HC_HCT2G125_3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Section 8: derating factor for TSSOP8, VSSOP8 and XSON8U package added
•Added type numbers 74HC2G125GD and 74HCT2G125GD (XSON8U package)
74HC_HCT2G125_3 20060102 Product data sheet - 74HC_HCT2G125_2
74HC_HCT2G125_2 20030303 Product specification - 74HC_HCT2G125_1
74HC_HCT2G125_1 20030131 Product specification - -
74HC_HCT2G125_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 4 July 2008 13 of 14
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74HC2G125; 74HCT2G125
Dual buffer/line driver; 3-state
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 July 2008
Document identifier: 74HC_HCT2G125_4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
17 Contact information. . . . . . . . . . . . . . . . . . . . . 13
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
